sound/soc/codecs/ab8500-codec.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) ST-Ericsson SA 2012
   4  *
   5  * Author: Ola Lilja <[email protected]>,
   6  *         Kristoffer Karlsson <[email protected]>,
   7  *         Roger Nilsson <[email protected]>,
   8  *         for ST-Ericsson.
   9  *
  10  *         Based on the early work done by:
  11  *         Mikko J. Lehto <[email protected]>,
  12  *         Mikko Sarmanne <[email protected]>,
  13  *         Jarmo K. Kuronen <[email protected]>,
  14  *         for ST-Ericsson.
  15  *
  16  * License terms:
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/slab.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/pm.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mutex.h>
  29 #include <linux/mfd/abx500/ab8500.h>
  30 #include <linux/mfd/abx500.h>
  31 #include <linux/mfd/abx500/ab8500-sysctrl.h>
  32 #include <linux/mfd/abx500/ab8500-codec.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/of.h>
  35
  36 #include <sound/core.h>
  37 #include <sound/pcm.h>
  38 #include <sound/pcm_params.h>
  39 #include <sound/initval.h>
  40 #include <sound/soc.h>
  41 #include <sound/soc-dapm.h>
  42 #include <sound/tlv.h>
  43
  44 #include "ab8500-codec.h"
  45
  46 /* Macrocell value definitions */
  47 #define CLK_32K_OUT2_DISABLE                    0x01
  48 #define INACTIVE_RESET_AUDIO                    0x02
  49 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK           0x10
  50 #define ENABLE_VINTCORE12_SUPPLY                0x04
  51 #define GPIO27_DIR_OUTPUT                       0x04
  52 #define GPIO29_DIR_OUTPUT                       0x10
  53 #define GPIO31_DIR_OUTPUT                       0x40
  54
  55 /* Macrocell register definitions */
  56 #define AB8500_GPIO_DIR4_REG                    0x13 /* Bank AB8500_MISC */
  57
  58 /* Nr of FIR/IIR-coeff banks in ANC-block */
  59 #define AB8500_NR_OF_ANC_COEFF_BANKS            2
  60
  61 /* Minimum duration to keep ANC IIR Init bit high or
  62 low before proceeding with the configuration sequence */
  63 #define AB8500_ANC_SM_DELAY                     2000
  64
  65 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
  66 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  67         .info = filter_control_info, \
  68         .get = filter_control_get, .put = filter_control_put, \
  69         .private_value = (unsigned long)&(struct filter_control) \
  70                 {.count = xcount, .min = xmin, .max = xmax} }
  71
  72 struct filter_control {
  73         long min, max;
  74         unsigned int count;
  75         long value[128];
  76 };
  77
  78 /* Sidetone states */
  79 static const char * const enum_sid_state[] = {
  80         "Unconfigured",
  81         "Apply FIR",
  82         "FIR is configured",
  83 };
  84 enum sid_state {
  85         SID_UNCONFIGURED = 0,
  86         SID_APPLY_FIR = 1,
  87         SID_FIR_CONFIGURED = 2,
  88 };
  89
  90 static const char * const enum_anc_state[] = {
  91         "Unconfigured",
  92         "Apply FIR and IIR",
  93         "FIR and IIR are configured",
  94         "Apply FIR",
  95         "FIR is configured",
  96         "Apply IIR",
  97         "IIR is configured"
  98 };
  99 enum anc_state {
 100         ANC_UNCONFIGURED = 0,
 101         ANC_APPLY_FIR_IIR = 1,
 102         ANC_FIR_IIR_CONFIGURED = 2,
 103         ANC_APPLY_FIR = 3,
 104         ANC_FIR_CONFIGURED = 4,
 105         ANC_APPLY_IIR = 5,
 106         ANC_IIR_CONFIGURED = 6
 107 };
 108
 109 /* Analog microphones */
 110 enum amic_idx {
 111         AMIC_IDX_1A,
 112         AMIC_IDX_1B,
 113         AMIC_IDX_2
 114 };
 115
 116 /* Private data for AB8500 device-driver */
 117 struct ab8500_codec_drvdata {
 118         struct regmap *regmap;
 119         struct mutex ctrl_lock;
 120
 121         /* Sidetone */
 122         long *sid_fir_values;
 123         enum sid_state sid_status;
 124
 125         /* ANC */
 126         long *anc_fir_values;
 127         long *anc_iir_values;
 128         enum anc_state anc_status;
 129 };
 130
 131 static inline const char *amic_micbias_str(enum amic_micbias micbias)
 132 {
 133         switch (micbias) {
 134         case AMIC_MICBIAS_VAMIC1:
 135                 return "VAMIC1";
 136         case AMIC_MICBIAS_VAMIC2:
 137                 return "VAMIC2";
 138         default:
 139                 return "Unknown";
 140         }
 141 }
 142
 143 static inline const char *amic_type_str(enum amic_type type)
 144 {
 145         switch (type) {
 146         case AMIC_TYPE_DIFFERENTIAL:
 147                 return "DIFFERENTIAL";
 148         case AMIC_TYPE_SINGLE_ENDED:
 149                 return "SINGLE ENDED";
 150         default:
 151                 return "Unknown";
 152         }
 153 }
 154
 155 /*
 156  * Read'n'write functions
 157  */
 158
 159 /* Read a register from the audio-bank of AB8500 */
 160 static int ab8500_codec_read_reg(void *context, unsigned int reg,
 161                                  unsigned int *value)
 162 {
 163         struct device *dev = context;
 164         int status;
 165
 166         u8 value8;
 167         status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
 168                                                    reg, &value8);
 169         *value = (unsigned int)value8;
 170
 171         return status;
 172 }
 173
 174 /* Write to a register in the audio-bank of AB8500 */
 175 static int ab8500_codec_write_reg(void *context, unsigned int reg,
 176                                   unsigned int value)
 177 {
 178         struct device *dev = context;
 179
 180         return abx500_set_register_interruptible(dev, AB8500_AUDIO,
 181                                                  reg, value);
 182 }
 183
 184 static const struct regmap_config ab8500_codec_regmap = {
 185         .reg_read = ab8500_codec_read_reg,
 186         .reg_write = ab8500_codec_write_reg,
 187 };
 188
 189 /*
 190  * Controls - DAPM
 191  */
 192
 193 /* Earpiece */
 194
 195 /* Earpiece source selector */
 196 static const char * const enum_ear_lineout_source[] = {"Headset Left",
 197                                                 "Speaker Left"};
 198 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
 199                         AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
 200 static const struct snd_kcontrol_new dapm_ear_lineout_source =
 201         SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
 202                 dapm_enum_ear_lineout_source);
 203
 204 /* LineOut */
 205
 206 /* LineOut source selector */
 207 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
 208 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
 209                         AB8500_ANACONF5_HSLDACTOLOL,
 210                         AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
 211 static const struct snd_kcontrol_new dapm_lineout_source[] = {
 212         SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
 213 };
 214
 215 /* Handsfree */
 216
 217 /* Speaker Left - ANC selector */
 218 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
 219 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
 220                         AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
 221 static const struct snd_kcontrol_new dapm_HFl_select[] = {
 222         SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
 223 };
 224
 225 /* Speaker Right - ANC selector */
 226 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
 227                         AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
 228 static const struct snd_kcontrol_new dapm_HFr_select[] = {
 229         SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
 230 };
 231
 232 /* Mic 1 */
 233
 234 /* Mic 1 - Mic 1a or 1b selector */
 235 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
 236 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
 237                         AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
 238 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
 239         SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
 240 };
 241
 242 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
 243 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
 244 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
 245                         AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
 246 static const struct snd_kcontrol_new dapm_ad3_select[] = {
 247         SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
 248 };
 249
 250 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
 251 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
 252 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
 253                         AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
 254 static const struct snd_kcontrol_new dapm_ad6_select[] = {
 255         SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
 256 };
 257
 258 /* Mic 2 */
 259
 260 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
 261 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
 262 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
 263                         AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
 264 static const struct snd_kcontrol_new dapm_ad5_select[] = {
 265         SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
 266 };
 267
 268 /* LineIn */
 269
 270 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
 271 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
 272 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
 273                         AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
 274 static const struct snd_kcontrol_new dapm_ad1_select[] = {
 275         SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
 276 };
 277
 278 /* LineIn right - Mic 2 or LineIn Right selector */
 279 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
 280 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
 281                         AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
 282 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
 283         SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
 284 };
 285
 286 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
 287 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
 288 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
 289                         AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
 290 static const struct snd_kcontrol_new dapm_ad2_select[] = {
 291         SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
 292 };
 293
 294
 295 /* ANC */
 296
 297 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
 298                                         "Mic 2 / DMic 5"};
 299 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
 300                         AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
 301 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
 302         SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
 303 };
 304
 305 /* ANC - Enable/Disable */
 306 static const struct snd_kcontrol_new dapm_anc_enable[] = {
 307         SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
 308                         AB8500_ANCCONF1_ENANC, 0, 0),
 309 };
 310
 311 /* ANC to Earpiece - Mute */
 312 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
 313         SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
 314                         AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
 315 };
 316
 317
 318
 319 /* Sidetone left */
 320
 321 /* Sidetone left - Input selector */
 322 static const char * const enum_stfir1_in_sel[] = {
 323         "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
 324 };
 325 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
 326                         AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
 327 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
 328         SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
 329 };
 330
 331 /* Sidetone right path */
 332
 333 /* Sidetone right - Input selector */
 334 static const char * const enum_stfir2_in_sel[] = {
 335         "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
 336 };
 337 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
 338                         AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
 339 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
 340         SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
 341 };
 342
 343 /* Vibra */
 344
 345 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
 346
 347 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
 348                         AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
 349
 350 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
 351         SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
 352 };
 353
 354 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
 355                         AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
 356
 357 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
 358         SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
 359 };
 360
 361 /*
 362  * DAPM-widgets
 363  */
 364
 365 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
 366
 367         /* Clocks */
 368         SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
 369
 370         /* Regulators */
 371         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
 372         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
 373         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
 374         SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
 375
 376         /* Power */
 377         SND_SOC_DAPM_SUPPLY("Audio Power",
 378                         AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
 379                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 380         SND_SOC_DAPM_SUPPLY("Audio Analog Power",
 381                         AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
 382                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 383
 384         /* Main supply node */
 385         SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
 386                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 387
 388         /* DA/AD */
 389
 390         SND_SOC_DAPM_INPUT("ADC Input"),
 391         SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
 392
 393         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
 394         SND_SOC_DAPM_OUTPUT("DAC Output"),
 395
 396         SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 397         SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
 398         SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
 399         SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
 400         SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
 401         SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
 402         SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
 403         SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
 404         SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
 405         SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
 406         SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
 407         SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
 408
 409         /* Headset path */
 410
 411         SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
 412                         AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
 413
 414         SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
 415                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
 416         SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
 417                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
 418
 419         SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
 420                         NULL, 0),
 421         SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
 422                         NULL, 0),
 423
 424         SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
 425                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
 426         SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
 427                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
 428         SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
 429                         AB8500_MUTECONF_MUTDACHSL, 1,
 430                         NULL, 0),
 431         SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
 432                         AB8500_MUTECONF_MUTDACHSR, 1,
 433                         NULL, 0),
 434         SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
 435                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
 436         SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
 437                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
 438
 439         SND_SOC_DAPM_MIXER("HSL Mute",
 440                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
 441                         NULL, 0),
 442         SND_SOC_DAPM_MIXER("HSR Mute",
 443                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
 444                         NULL, 0),
 445         SND_SOC_DAPM_MIXER("HSL Enable",
 446                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
 447                         NULL, 0),
 448         SND_SOC_DAPM_MIXER("HSR Enable",
 449                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
 450                         NULL, 0),
 451         SND_SOC_DAPM_PGA("HSL Volume",
 452                         SND_SOC_NOPM, 0, 0,
 453                         NULL, 0),
 454         SND_SOC_DAPM_PGA("HSR Volume",
 455                         SND_SOC_NOPM, 0, 0,
 456                         NULL, 0),
 457
 458         SND_SOC_DAPM_OUTPUT("Headset Left"),
 459         SND_SOC_DAPM_OUTPUT("Headset Right"),
 460
 461         /* LineOut path */
 462
 463         SND_SOC_DAPM_MUX("LineOut Source",
 464                         SND_SOC_NOPM, 0, 0, dapm_lineout_source),
 465
 466         SND_SOC_DAPM_MIXER("LOL Disable HFL",
 467                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
 468                         NULL, 0),
 469         SND_SOC_DAPM_MIXER("LOR Disable HFR",
 470                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
 471                         NULL, 0),
 472
 473         SND_SOC_DAPM_MIXER("LOL Enable",
 474                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
 475                         NULL, 0),
 476         SND_SOC_DAPM_MIXER("LOR Enable",
 477                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
 478                         NULL, 0),
 479
 480         SND_SOC_DAPM_OUTPUT("LineOut Left"),
 481         SND_SOC_DAPM_OUTPUT("LineOut Right"),
 482
 483         /* Earpiece path */
 484
 485         SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
 486                         SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
 487         SND_SOC_DAPM_MIXER("EAR DAC",
 488                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
 489                         NULL, 0),
 490         SND_SOC_DAPM_MIXER("EAR Mute",
 491                         AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
 492                         NULL, 0),
 493         SND_SOC_DAPM_MIXER("EAR Enable",
 494                         AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
 495                         NULL, 0),
 496
 497         SND_SOC_DAPM_OUTPUT("Earpiece"),
 498
 499         /* Handsfree path */
 500
 501         SND_SOC_DAPM_MIXER("DA3 Channel Volume",
 502                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
 503                         NULL, 0),
 504         SND_SOC_DAPM_MIXER("DA4 Channel Volume",
 505                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
 506                         NULL, 0),
 507         SND_SOC_DAPM_MUX("Speaker Left Source",
 508                         SND_SOC_NOPM, 0, 0, dapm_HFl_select),
 509         SND_SOC_DAPM_MUX("Speaker Right Source",
 510                         SND_SOC_NOPM, 0, 0, dapm_HFr_select),
 511         SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
 512                         AB8500_DAPATHCONF_ENDACHFL, 0,
 513                         NULL, 0),
 514         SND_SOC_DAPM_MIXER("HFR DAC",
 515                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
 516                         NULL, 0),
 517         SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
 518                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
 519                         NULL, 0),
 520         SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
 521                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
 522                         NULL, 0),
 523         SND_SOC_DAPM_MIXER("HFL Enable",
 524                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
 525                         NULL, 0),
 526         SND_SOC_DAPM_MIXER("HFR Enable",
 527                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
 528                         NULL, 0),
 529
 530         SND_SOC_DAPM_OUTPUT("Speaker Left"),
 531         SND_SOC_DAPM_OUTPUT("Speaker Right"),
 532
 533         /* Vibrator path */
 534
 535         SND_SOC_DAPM_INPUT("PWMGEN1"),
 536         SND_SOC_DAPM_INPUT("PWMGEN2"),
 537
 538         SND_SOC_DAPM_MIXER("DA5 Channel Volume",
 539                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
 540                         NULL, 0),
 541         SND_SOC_DAPM_MIXER("DA6 Channel Volume",
 542                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
 543                         NULL, 0),
 544         SND_SOC_DAPM_MIXER("VIB1 DAC",
 545                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
 546                         NULL, 0),
 547         SND_SOC_DAPM_MIXER("VIB2 DAC",
 548                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
 549                         NULL, 0),
 550         SND_SOC_DAPM_MUX("Vibra 1 Controller",
 551                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
 552         SND_SOC_DAPM_MUX("Vibra 2 Controller",
 553                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
 554         SND_SOC_DAPM_MIXER("VIB1 Enable",
 555                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
 556                         NULL, 0),
 557         SND_SOC_DAPM_MIXER("VIB2 Enable",
 558                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
 559                         NULL, 0),
 560
 561         SND_SOC_DAPM_OUTPUT("Vibra 1"),
 562         SND_SOC_DAPM_OUTPUT("Vibra 2"),
 563
 564         /* Mic 1 */
 565
 566         SND_SOC_DAPM_INPUT("Mic 1"),
 567
 568         SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
 569                         SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
 570         SND_SOC_DAPM_MIXER("MIC1 Mute",
 571                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
 572                         NULL, 0),
 573         SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
 574                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
 575                         NULL, 0),
 576         SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
 577                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
 578                         NULL, 0),
 579         SND_SOC_DAPM_MIXER("MIC1 ADC",
 580                         AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
 581                         NULL, 0),
 582         SND_SOC_DAPM_MUX("AD3 Source Select",
 583                         SND_SOC_NOPM, 0, 0, dapm_ad3_select),
 584         SND_SOC_DAPM_MIXER("AD3 Channel Volume",
 585                         SND_SOC_NOPM, 0, 0,
 586                         NULL, 0),
 587         SND_SOC_DAPM_MIXER("AD3 Enable",
 588                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
 589                         NULL, 0),
 590
 591         /* Mic 2 */
 592
 593         SND_SOC_DAPM_INPUT("Mic 2"),
 594
 595         SND_SOC_DAPM_MIXER("MIC2 Mute",
 596                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
 597                         NULL, 0),
 598         SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
 599                         AB8500_ANACONF2_ENMIC2, 0,
 600                         NULL, 0),
 601
 602         /* LineIn */
 603
 604         SND_SOC_DAPM_INPUT("LineIn Left"),
 605         SND_SOC_DAPM_INPUT("LineIn Right"),
 606
 607         SND_SOC_DAPM_MIXER("LINL Mute",
 608                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
 609                         NULL, 0),
 610         SND_SOC_DAPM_MIXER("LINR Mute",
 611                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
 612                         NULL, 0),
 613         SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
 614                         AB8500_ANACONF2_ENLINL, 0,
 615                         NULL, 0),
 616         SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
 617                         AB8500_ANACONF2_ENLINR, 0,
 618                         NULL, 0),
 619
 620         /* LineIn Bypass path */
 621         SND_SOC_DAPM_MIXER("LINL to HSL Volume",
 622                         SND_SOC_NOPM, 0, 0,
 623                         NULL, 0),
 624         SND_SOC_DAPM_MIXER("LINR to HSR Volume",
 625                         SND_SOC_NOPM, 0, 0,
 626                         NULL, 0),
 627
 628         /* LineIn, Mic 2 */
 629         SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
 630                         SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
 631         SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
 632                         AB8500_ANACONF3_ENADCLINL, 0,
 633                         NULL, 0),
 634         SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
 635                         AB8500_ANACONF3_ENADCLINR, 0,
 636                         NULL, 0),
 637         SND_SOC_DAPM_MUX("AD1 Source Select",
 638                         SND_SOC_NOPM, 0, 0, dapm_ad1_select),
 639         SND_SOC_DAPM_MUX("AD2 Source Select",
 640                         SND_SOC_NOPM, 0, 0, dapm_ad2_select),
 641         SND_SOC_DAPM_MIXER("AD1 Channel Volume",
 642                         SND_SOC_NOPM, 0, 0,
 643                         NULL, 0),
 644         SND_SOC_DAPM_MIXER("AD2 Channel Volume",
 645                         SND_SOC_NOPM, 0, 0,
 646                         NULL, 0),
 647
 648         SND_SOC_DAPM_MIXER("AD12 Enable",
 649                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
 650                         NULL, 0),
 651
 652         /* HD Capture path */
 653
 654         SND_SOC_DAPM_MUX("AD5 Source Select",
 655                         SND_SOC_NOPM, 0, 0, dapm_ad5_select),
 656         SND_SOC_DAPM_MUX("AD6 Source Select",
 657                         SND_SOC_NOPM, 0, 0, dapm_ad6_select),
 658         SND_SOC_DAPM_MIXER("AD5 Channel Volume",
 659                         SND_SOC_NOPM, 0, 0,
 660                         NULL, 0),
 661         SND_SOC_DAPM_MIXER("AD6 Channel Volume",
 662                         SND_SOC_NOPM, 0, 0,
 663                         NULL, 0),
 664         SND_SOC_DAPM_MIXER("AD57 Enable",
 665                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
 666                         NULL, 0),
 667         SND_SOC_DAPM_MIXER("AD68 Enable",
 668                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
 669                         NULL, 0),
 670
 671         /* Digital Microphone path */
 672
 673         SND_SOC_DAPM_INPUT("DMic 1"),
 674         SND_SOC_DAPM_INPUT("DMic 2"),
 675         SND_SOC_DAPM_INPUT("DMic 3"),
 676         SND_SOC_DAPM_INPUT("DMic 4"),
 677         SND_SOC_DAPM_INPUT("DMic 5"),
 678         SND_SOC_DAPM_INPUT("DMic 6"),
 679
 680         SND_SOC_DAPM_MIXER("DMIC1",
 681                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
 682                         NULL, 0),
 683         SND_SOC_DAPM_MIXER("DMIC2",
 684                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
 685                         NULL, 0),
 686         SND_SOC_DAPM_MIXER("DMIC3",
 687                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
 688                         NULL, 0),
 689         SND_SOC_DAPM_MIXER("DMIC4",
 690                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
 691                         NULL, 0),
 692         SND_SOC_DAPM_MIXER("DMIC5",
 693                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
 694                         NULL, 0),
 695         SND_SOC_DAPM_MIXER("DMIC6",
 696                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
 697                         NULL, 0),
 698         SND_SOC_DAPM_MIXER("AD4 Channel Volume",
 699                         SND_SOC_NOPM, 0, 0,
 700                         NULL, 0),
 701         SND_SOC_DAPM_MIXER("AD4 Enable",
 702                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
 703                         0, NULL, 0),
 704
 705         /* Acoustical Noise Cancellation path */
 706
 707         SND_SOC_DAPM_INPUT("ANC Configure Input"),
 708         SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
 709
 710         SND_SOC_DAPM_MUX("ANC Source",
 711                         SND_SOC_NOPM, 0, 0,
 712                         dapm_anc_in_select),
 713         SND_SOC_DAPM_SWITCH("ANC",
 714                         SND_SOC_NOPM, 0, 0,
 715                         dapm_anc_enable),
 716         SND_SOC_DAPM_SWITCH("ANC to Earpiece",
 717                         SND_SOC_NOPM, 0, 0,
 718                         dapm_anc_ear_mute),
 719
 720         /* Sidetone Filter path */
 721
 722         SND_SOC_DAPM_MUX("Sidetone Left Source",
 723                         SND_SOC_NOPM, 0, 0,
 724                         dapm_stfir1_in_select),
 725         SND_SOC_DAPM_MUX("Sidetone Right Source",
 726                         SND_SOC_NOPM, 0, 0,
 727                         dapm_stfir2_in_select),
 728         SND_SOC_DAPM_MIXER("STFIR1 Control",
 729                         SND_SOC_NOPM, 0, 0,
 730                         NULL, 0),
 731         SND_SOC_DAPM_MIXER("STFIR2 Control",
 732                         SND_SOC_NOPM, 0, 0,
 733                         NULL, 0),
 734         SND_SOC_DAPM_MIXER("STFIR1 Volume",
 735                         SND_SOC_NOPM, 0, 0,
 736                         NULL, 0),
 737         SND_SOC_DAPM_MIXER("STFIR2 Volume",
 738                         SND_SOC_NOPM, 0, 0,
 739                         NULL, 0),
 740 };
 741
 742 /*
 743  * DAPM-routes
 744  */
 745 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
 746         /* Power AB8500 audio-block when AD/DA is active */
 747         {"Main Supply", NULL, "V-AUD"},
 748         {"Main Supply", NULL, "audioclk"},
 749         {"Main Supply", NULL, "Audio Power"},
 750         {"Main Supply", NULL, "Audio Analog Power"},
 751
 752         {"DAC", NULL, "ab8500_0p"},
 753         {"DAC", NULL, "Main Supply"},
 754         {"ADC", NULL, "ab8500_0c"},
 755         {"ADC", NULL, "Main Supply"},
 756
 757         /* ANC Configure */
 758         {"ANC Configure Input", NULL, "Main Supply"},
 759         {"ANC Configure Output", NULL, "ANC Configure Input"},
 760
 761         /* AD/DA */
 762         {"ADC", NULL, "ADC Input"},
 763         {"DAC Output", NULL, "DAC"},
 764
 765         /* Powerup charge pump if DA1/2 is in use */
 766
 767         {"DA_IN1", NULL, "ab8500_0p"},
 768         {"DA_IN1", NULL, "Charge Pump"},
 769         {"DA_IN2", NULL, "ab8500_0p"},
 770         {"DA_IN2", NULL, "Charge Pump"},
 771
 772         /* Headset path */
 773
 774         {"DA1 Enable", NULL, "DA_IN1"},
 775         {"DA2 Enable", NULL, "DA_IN2"},
 776
 777         {"HSL Digital Volume", NULL, "DA1 Enable"},
 778         {"HSR Digital Volume", NULL, "DA2 Enable"},
 779
 780         {"HSL DAC", NULL, "HSL Digital Volume"},
 781         {"HSR DAC", NULL, "HSR Digital Volume"},
 782
 783         {"HSL DAC Mute", NULL, "HSL DAC"},
 784         {"HSR DAC Mute", NULL, "HSR DAC"},
 785
 786         {"HSL DAC Driver", NULL, "HSL DAC Mute"},
 787         {"HSR DAC Driver", NULL, "HSR DAC Mute"},
 788
 789         {"HSL Mute", NULL, "HSL DAC Driver"},
 790         {"HSR Mute", NULL, "HSR DAC Driver"},
 791
 792         {"HSL Enable", NULL, "HSL Mute"},
 793         {"HSR Enable", NULL, "HSR Mute"},
 794
 795         {"HSL Volume", NULL, "HSL Enable"},
 796         {"HSR Volume", NULL, "HSR Enable"},
 797
 798         {"Headset Left", NULL, "HSL Volume"},
 799         {"Headset Right", NULL, "HSR Volume"},
 800
 801         /* HF or LineOut path */
 802
 803         {"DA_IN3", NULL, "ab8500_0p"},
 804         {"DA3 Channel Volume", NULL, "DA_IN3"},
 805         {"DA_IN4", NULL, "ab8500_0p"},
 806         {"DA4 Channel Volume", NULL, "DA_IN4"},
 807
 808         {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
 809         {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
 810
 811         {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
 812         {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
 813
 814         /* HF path */
 815
 816         {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
 817         {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
 818
 819         {"HFL Enable", NULL, "HFL DAC"},
 820         {"HFR Enable", NULL, "HFR DAC"},
 821
 822         {"Speaker Left", NULL, "HFL Enable"},
 823         {"Speaker Right", NULL, "HFR Enable"},
 824
 825         /* Earpiece path */
 826
 827         {"Earpiece or LineOut Mono Source", "Headset Left",
 828                 "HSL Digital Volume"},
 829         {"Earpiece or LineOut Mono Source", "Speaker Left",
 830                 "DA3 or ANC path to HfL"},
 831
 832         {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
 833
 834         {"EAR Mute", NULL, "EAR DAC"},
 835
 836         {"EAR Enable", NULL, "EAR Mute"},
 837
 838         {"Earpiece", NULL, "EAR Enable"},
 839
 840         /* LineOut path stereo */
 841
 842         {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
 843         {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
 844
 845         /* LineOut path mono */
 846
 847         {"LineOut Source", "Mono Path", "EAR DAC"},
 848
 849         /* LineOut path */
 850
 851         {"LOL Disable HFL", NULL, "LineOut Source"},
 852         {"LOR Disable HFR", NULL, "LineOut Source"},
 853
 854         {"LOL Enable", NULL, "LOL Disable HFL"},
 855         {"LOR Enable", NULL, "LOR Disable HFR"},
 856
 857         {"LineOut Left", NULL, "LOL Enable"},
 858         {"LineOut Right", NULL, "LOR Enable"},
 859
 860         /* Vibrator path */
 861
 862         {"DA_IN5", NULL, "ab8500_0p"},
 863         {"DA5 Channel Volume", NULL, "DA_IN5"},
 864         {"DA_IN6", NULL, "ab8500_0p"},
 865         {"DA6 Channel Volume", NULL, "DA_IN6"},
 866
 867         {"VIB1 DAC", NULL, "DA5 Channel Volume"},
 868         {"VIB2 DAC", NULL, "DA6 Channel Volume"},
 869
 870         {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
 871         {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
 872         {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
 873         {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
 874
 875         {"VIB1 Enable", NULL, "Vibra 1 Controller"},
 876         {"VIB2 Enable", NULL, "Vibra 2 Controller"},
 877
 878         {"Vibra 1", NULL, "VIB1 Enable"},
 879         {"Vibra 2", NULL, "VIB2 Enable"},
 880
 881
 882         /* Mic 2 */
 883
 884         {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
 885
 886         /* LineIn */
 887         {"LINL Mute", NULL, "LineIn Left"},
 888         {"LINR Mute", NULL, "LineIn Right"},
 889
 890         {"LINL Enable", NULL, "LINL Mute"},
 891         {"LINR Enable", NULL, "LINR Mute"},
 892
 893         /* LineIn, Mic 2 */
 894         {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
 895         {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
 896
 897         {"LINL ADC", NULL, "LINL Enable"},
 898         {"LINR ADC", NULL, "Mic 2 or LINR Select"},
 899
 900         {"AD1 Source Select", "LineIn Left", "LINL ADC"},
 901         {"AD2 Source Select", "LineIn Right", "LINR ADC"},
 902
 903         {"AD1 Channel Volume", NULL, "AD1 Source Select"},
 904         {"AD2 Channel Volume", NULL, "AD2 Source Select"},
 905
 906         {"AD12 Enable", NULL, "AD1 Channel Volume"},
 907         {"AD12 Enable", NULL, "AD2 Channel Volume"},
 908
 909         {"AD_OUT1", NULL, "ab8500_0c"},
 910         {"AD_OUT1", NULL, "AD12 Enable"},
 911         {"AD_OUT2", NULL, "ab8500_0c"},
 912         {"AD_OUT2", NULL, "AD12 Enable"},
 913
 914         /* Mic 1 */
 915
 916         {"MIC1 Mute", NULL, "Mic 1"},
 917
 918         {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
 919         {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
 920
 921         {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
 922         {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
 923
 924         {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
 925
 926         {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
 927
 928         {"AD3 Channel Volume", NULL, "AD3 Source Select"},
 929
 930         {"AD3 Enable", NULL, "AD3 Channel Volume"},
 931
 932         {"AD_OUT3", NULL, "ab8500_0c"},
 933         {"AD_OUT3", NULL, "AD3 Enable"},
 934
 935         /* HD Capture path */
 936
 937         {"AD5 Source Select", "Mic 2", "LINR ADC"},
 938         {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
 939
 940         {"AD5 Channel Volume", NULL, "AD5 Source Select"},
 941         {"AD6 Channel Volume", NULL, "AD6 Source Select"},
 942
 943         {"AD57 Enable", NULL, "AD5 Channel Volume"},
 944         {"AD68 Enable", NULL, "AD6 Channel Volume"},
 945
 946         {"AD_OUT57", NULL, "ab8500_0c"},
 947         {"AD_OUT57", NULL, "AD57 Enable"},
 948         {"AD_OUT68", NULL, "ab8500_0c"},
 949         {"AD_OUT68", NULL, "AD68 Enable"},
 950
 951         /* Digital Microphone path */
 952
 953         {"DMic 1", NULL, "V-DMIC"},
 954         {"DMic 2", NULL, "V-DMIC"},
 955         {"DMic 3", NULL, "V-DMIC"},
 956         {"DMic 4", NULL, "V-DMIC"},
 957         {"DMic 5", NULL, "V-DMIC"},
 958         {"DMic 6", NULL, "V-DMIC"},
 959
 960         {"AD1 Source Select", NULL, "DMic 1"},
 961         {"AD2 Source Select", NULL, "DMic 2"},
 962         {"AD3 Source Select", NULL, "DMic 3"},
 963         {"AD5 Source Select", NULL, "DMic 5"},
 964         {"AD6 Source Select", NULL, "DMic 6"},
 965
 966         {"AD4 Channel Volume", NULL, "DMic 4"},
 967         {"AD4 Enable", NULL, "AD4 Channel Volume"},
 968
 969         {"AD_OUT4", NULL, "ab8500_0c"},
 970         {"AD_OUT4", NULL, "AD4 Enable"},
 971
 972         /* LineIn Bypass path */
 973
 974         {"LINL to HSL Volume", NULL, "LINL Enable"},
 975         {"LINR to HSR Volume", NULL, "LINR Enable"},
 976
 977         {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
 978         {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
 979
 980         /* ANC path (Acoustic Noise Cancellation) */
 981
 982         {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
 983         {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
 984
 985         {"ANC", "Switch", "ANC Source"},
 986
 987         {"Speaker Left Source", "ANC", "ANC"},
 988         {"Speaker Right Source", "ANC", "ANC"},
 989         {"ANC to Earpiece", "Switch", "ANC"},
 990
 991         {"HSL Digital Volume", NULL, "ANC to Earpiece"},
 992
 993         /* Sidetone Filter path */
 994
 995         {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
 996         {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
 997         {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
 998         {"Sidetone Left Source", "Headset Left", "DA_IN1"},
 999         {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1000         {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1001         {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1002         {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1003
1004         {"STFIR1 Control", NULL, "Sidetone Left Source"},
1005         {"STFIR2 Control", NULL, "Sidetone Right Source"},
1006
1007         {"STFIR1 Volume", NULL, "STFIR1 Control"},
1008         {"STFIR2 Volume", NULL, "STFIR2 Control"},
1009
1010         {"DA1 Enable", NULL, "STFIR1 Volume"},
1011         {"DA2 Enable", NULL, "STFIR2 Volume"},
1012 };
1013
1014 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1015         {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1016         {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1017 };
1018
1019 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1020         {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1021         {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1022 };
1023
1024 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1025         {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1026         {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1027 };
1028
1029 /* ANC FIR-coefficients configuration sequence */
1030 static void anc_fir(struct snd_soc_component *component,
1031                 unsigned int bnk, unsigned int par, unsigned int val)
1032 {
1033         if (par == 0 && bnk == 0)
1034                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1035                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1036                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1037
1038         snd_soc_component_write(component, AB8500_ANCCONF5, val >> 8 & 0xff);
1039         snd_soc_component_write(component, AB8500_ANCCONF6, val &  0xff);
1040
1041         if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1042                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1043                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1044 }
1045
1046 /* ANC IIR-coefficients configuration sequence */
1047 static void anc_iir(struct snd_soc_component *component, unsigned int bnk,
1048                 unsigned int par, unsigned int val)
1049 {
1050         if (par == 0) {
1051                 if (bnk == 0) {
1052                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1053                                         BIT(AB8500_ANCCONF1_ANCIIRINIT),
1054                                         BIT(AB8500_ANCCONF1_ANCIIRINIT));
1055                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1056                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1057                                         BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1058                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY*2);
1059                 } else {
1060                         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1061                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1062                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1063                 }
1064         } else if (par > 3) {
1065                 snd_soc_component_write(component, AB8500_ANCCONF7, 0);
1066                 snd_soc_component_write(component, AB8500_ANCCONF8, val >> 16 & 0xff);
1067         }
1068
1069         snd_soc_component_write(component, AB8500_ANCCONF7, val >> 8 & 0xff);
1070         snd_soc_component_write(component, AB8500_ANCCONF8, val & 0xff);
1071
1072         if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1073                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1074                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1075 }
1076
1077 /* ANC IIR-/FIR-coefficients configuration sequence */
1078 static void anc_configure(struct snd_soc_component *component,
1079                         bool apply_fir, bool apply_iir)
1080 {
1081         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1082         unsigned int bnk, par, val;
1083
1084         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1085
1086         if (apply_fir)
1087                 snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1088                         BIT(AB8500_ANCCONF1_ENANC), 0);
1089
1090         snd_soc_component_update_bits(component, AB8500_ANCCONF1,
1091                 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1092
1093         if (apply_fir)
1094                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1095                         for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1096                                 val = snd_soc_component_read(component,
1097                                                 drvdata->anc_fir_values[par]);
1098                                 anc_fir(component, bnk, par, val);
1099                         }
1100
1101         if (apply_iir)
1102                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1103                         for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1104                                 val = snd_soc_component_read(component,
1105                                                 drvdata->anc_iir_values[par]);
1106                                 anc_iir(component, bnk, par, val);
1107                         }
1108
1109         dev_dbg(component->dev, "%s: Exit.\n", __func__);
1110 }
1111
1112 /*
1113  * Control-events
1114  */
1115
1116 static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1117                 struct snd_ctl_elem_value *ucontrol)
1118 {
1119         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1120         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1121
1122         mutex_lock(&drvdata->ctrl_lock);
1123         ucontrol->value.enumerated.item[0] = drvdata->sid_status;
1124         mutex_unlock(&drvdata->ctrl_lock);
1125
1126         return 0;
1127 }
1128
1129 /* Write sidetone FIR-coefficients configuration sequence */
1130 static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1131                                 struct snd_ctl_elem_value *ucontrol)
1132 {
1133         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1134         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1135         unsigned int param, sidconf, val;
1136         int status = 1;
1137
1138         dev_dbg(component->dev, "%s: Enter\n", __func__);
1139
1140         if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
1141                 dev_err(component->dev,
1142                         "%s: ERROR: This control supports '%s' only!\n",
1143                         __func__, enum_sid_state[SID_APPLY_FIR]);
1144                 return -EIO;
1145         }
1146
1147         mutex_lock(&drvdata->ctrl_lock);
1148
1149         sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF);
1150         if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1151                 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1152                         dev_err(component->dev, "%s: Sidetone busy while off!\n",
1153                                 __func__);
1154                         status = -EPERM;
1155                 } else {
1156                         status = -EBUSY;
1157                 }
1158                 goto out;
1159         }
1160
1161         snd_soc_component_write(component, AB8500_SIDFIRADR, 0);
1162
1163         for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1164                 val = snd_soc_component_read(component, drvdata->sid_fir_values[param]);
1165                 snd_soc_component_write(component, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1166                 snd_soc_component_write(component, AB8500_SIDFIRCOEF2, val & 0xff);
1167         }
1168
1169         snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1170                 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1171                 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1172         snd_soc_component_update_bits(component, AB8500_SIDFIRADR,
1173                 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1174
1175         drvdata->sid_status = SID_FIR_CONFIGURED;
1176
1177 out:
1178         mutex_unlock(&drvdata->ctrl_lock);
1179
1180         dev_dbg(component->dev, "%s: Exit\n", __func__);
1181
1182         return status;
1183 }
1184
1185 static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1186                                 struct snd_ctl_elem_value *ucontrol)
1187 {
1188         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1189         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1190
1191         mutex_lock(&drvdata->ctrl_lock);
1192         ucontrol->value.enumerated.item[0] = drvdata->anc_status;
1193         mutex_unlock(&drvdata->ctrl_lock);
1194
1195         return 0;
1196 }
1197
1198 static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1199                                 struct snd_ctl_elem_value *ucontrol)
1200 {
1201         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1202         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1203         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev);
1204         struct device *dev = component->dev;
1205         bool apply_fir, apply_iir;
1206         unsigned int req;
1207         int status;
1208
1209         dev_dbg(dev, "%s: Enter.\n", __func__);
1210
1211         mutex_lock(&drvdata->ctrl_lock);
1212
1213         req = ucontrol->value.enumerated.item[0];
1214         if (req >= ARRAY_SIZE(enum_anc_state)) {
1215                 status = -EINVAL;
1216                 goto cleanup;
1217         }
1218         if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1219                 req != ANC_APPLY_IIR) {
1220                 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1221                         __func__, enum_anc_state[req]);
1222                 status = -EINVAL;
1223                 goto cleanup;
1224         }
1225         apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1226         apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1227
1228         status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
1229         if (status < 0) {
1230                 dev_err(dev,
1231                         "%s: ERROR: Failed to enable power (status = %d)!\n",
1232                         __func__, status);
1233                 goto cleanup;
1234         }
1235         snd_soc_dapm_sync(dapm);
1236
1237         anc_configure(component, apply_fir, apply_iir);
1238
1239         if (apply_fir) {
1240                 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1241                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1242                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1243                         drvdata->anc_status =  ANC_FIR_CONFIGURED;
1244         }
1245         if (apply_iir) {
1246                 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1247                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1248                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1249                         drvdata->anc_status =  ANC_IIR_CONFIGURED;
1250         }
1251
1252         status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
1253         snd_soc_dapm_sync(dapm);
1254
1255 cleanup:
1256         mutex_unlock(&drvdata->ctrl_lock);
1257
1258         if (status < 0)
1259                 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1260                         __func__, status);
1261
1262         dev_dbg(dev, "%s: Exit.\n", __func__);
1263
1264         return (status < 0) ? status : 1;
1265 }
1266
1267 static int filter_control_info(struct snd_kcontrol *kcontrol,
1268                         struct snd_ctl_elem_info *uinfo)
1269 {
1270         struct filter_control *fc =
1271                         (struct filter_control *)kcontrol->private_value;
1272
1273         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1274         uinfo->count = fc->count;
1275         uinfo->value.integer.min = fc->min;
1276         uinfo->value.integer.max = fc->max;
1277
1278         return 0;
1279 }
1280
1281 static int filter_control_get(struct snd_kcontrol *kcontrol,
1282                         struct snd_ctl_elem_value *ucontrol)
1283 {
1284         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1285         struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1286         struct filter_control *fc =
1287                         (struct filter_control *)kcontrol->private_value;
1288         unsigned int i;
1289
1290         mutex_lock(&drvdata->ctrl_lock);
1291         for (i = 0; i < fc->count; i++)
1292                 ucontrol->value.integer.value[i] = fc->value[i];
1293         mutex_unlock(&drvdata->ctrl_lock);
1294
1295         return 0;
1296 }
1297
1298 static int filter_control_put(struct snd_kcontrol *kcontrol,
1299                 struct snd_ctl_elem_value *ucontrol)
1300 {
1301         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1302         struct ab8500_codec_drvdata *drvdata = snd_soc_component_get_drvdata(component);
1303         struct filter_control *fc =
1304                         (struct filter_control *)kcontrol->private_value;
1305         unsigned int i;
1306
1307         mutex_lock(&drvdata->ctrl_lock);
1308         for (i = 0; i < fc->count; i++)
1309                 fc->value[i] = ucontrol->value.integer.value[i];
1310         mutex_unlock(&drvdata->ctrl_lock);
1311
1312         return 0;
1313 }
1314
1315 /*
1316  * Controls - Non-DAPM ASoC
1317  */
1318
1319 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1320 /* -32dB = Mute */
1321
1322 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1323 /* -63dB = Mute */
1324
1325 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1326 /* -1dB = Mute */
1327
1328 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
1329         0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1330         4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
1331 );
1332
1333 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1334
1335 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1336
1337 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1338 /* -38dB = Mute */
1339
1340 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1341                                         "5ms"};
1342 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1343         AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1344
1345 static const char * const enum_envdetthre[] = {
1346         "250mV", "300mV", "350mV", "400mV",
1347         "450mV", "500mV", "550mV", "600mV",
1348         "650mV", "700mV", "750mV", "800mV",
1349         "850mV", "900mV", "950mV", "1.00V" };
1350 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1351         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1352 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1353         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1354 static const char * const enum_envdettime[] = {
1355         "26.6us", "53.2us", "106us",  "213us",
1356         "426us",  "851us",  "1.70ms", "3.40ms",
1357         "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1358         "109ms",  "218ms",  "436ms",  "872ms" };
1359 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1360         AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1361
1362 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1363 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1364                         AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1365
1366 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1367 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1368                         AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1369
1370 /* Earpiece */
1371
1372 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1373 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1374                         AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1375 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1376                         AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1377
1378 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1379 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1380         AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1381 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1382         AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1383
1384 /* DA */
1385
1386 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1387                         AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1388                         enum_av_mode);
1389 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1390                         AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1391                         enum_av_mode);
1392 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1393                         AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1394                         enum_av_mode);
1395
1396 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1397 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1398                         AB8500_DIGMULTCONF1_DATOHSLEN,
1399                         AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1400
1401 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1402 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1403                         AB8500_DMICFILTCONF_DMIC1SINC3,
1404                         AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1405 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1406                         AB8500_DMICFILTCONF_DMIC3SINC3,
1407                         AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1408 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1409                         AB8500_DMICFILTCONF_DMIC5SINC3,
1410                         AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1411
1412 /* Digital interface - DA from slot mapping */
1413 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1414                                         "SLOT1",
1415                                         "SLOT2",
1416                                         "SLOT3",
1417                                         "SLOT4",
1418                                         "SLOT5",
1419                                         "SLOT6",
1420                                         "SLOT7",
1421                                         "SLOT8",
1422                                         "SLOT9",
1423                                         "SLOT10",
1424                                         "SLOT11",
1425                                         "SLOT12",
1426                                         "SLOT13",
1427                                         "SLOT14",
1428                                         "SLOT15",
1429                                         "SLOT16",
1430                                         "SLOT17",
1431                                         "SLOT18",
1432                                         "SLOT19",
1433                                         "SLOT20",
1434                                         "SLOT21",
1435                                         "SLOT22",
1436                                         "SLOT23",
1437                                         "SLOT24",
1438                                         "SLOT25",
1439                                         "SLOT26",
1440                                         "SLOT27",
1441                                         "SLOT28",
1442                                         "SLOT29",
1443                                         "SLOT30",
1444                                         "SLOT31"};
1445 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1446                         AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1447                         enum_da_from_slot_map);
1448 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1449                         AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1450                         enum_da_from_slot_map);
1451 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1452                         AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1453                         enum_da_from_slot_map);
1454 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1455                         AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1456                         enum_da_from_slot_map);
1457 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1458                         AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1459                         enum_da_from_slot_map);
1460 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1461                         AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1462                         enum_da_from_slot_map);
1463 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1464                         AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1465                         enum_da_from_slot_map);
1466 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1467                         AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1468                         enum_da_from_slot_map);
1469
1470 /* Digital interface - AD to slot mapping */
1471 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1472                                         "AD_OUT2",
1473                                         "AD_OUT3",
1474                                         "AD_OUT4",
1475                                         "AD_OUT5",
1476                                         "AD_OUT6",
1477                                         "AD_OUT7",
1478                                         "AD_OUT8",
1479                                         "zeroes",
1480                                         "zeroes",
1481                                         "zeroes",
1482                                         "zeroes",
1483                                         "tristate",
1484                                         "tristate",
1485                                         "tristate",
1486                                         "tristate"};
1487 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1488                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1489                         enum_ad_to_slot_map);
1490 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1491                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1492                         enum_ad_to_slot_map);
1493 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1494                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1495                         enum_ad_to_slot_map);
1496 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1497                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1498                         enum_ad_to_slot_map);
1499 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1500                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1501                         enum_ad_to_slot_map);
1502 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1503                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1504                         enum_ad_to_slot_map);
1505 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1506                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1507                         enum_ad_to_slot_map);
1508 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1509                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1510                         enum_ad_to_slot_map);
1511 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1512                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1513                         enum_ad_to_slot_map);
1514 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1515                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1516                         enum_ad_to_slot_map);
1517 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1518                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1519                         enum_ad_to_slot_map);
1520 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1521                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1522                         enum_ad_to_slot_map);
1523 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1524                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1525                         enum_ad_to_slot_map);
1526 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1527                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1528                         enum_ad_to_slot_map);
1529 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1530                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1531                         enum_ad_to_slot_map);
1532 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1533                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1534                         enum_ad_to_slot_map);
1535 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1536                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1537                         enum_ad_to_slot_map);
1538 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1539                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1540                         enum_ad_to_slot_map);
1541 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1542                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1543                         enum_ad_to_slot_map);
1544 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1545                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1546                         enum_ad_to_slot_map);
1547 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1548                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1549                         enum_ad_to_slot_map);
1550 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1551                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1552                         enum_ad_to_slot_map);
1553 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1554                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1555                         enum_ad_to_slot_map);
1556 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1557                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1558                         enum_ad_to_slot_map);
1559 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1560                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1561                         enum_ad_to_slot_map);
1562 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1563                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1564                         enum_ad_to_slot_map);
1565 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1566                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1567                         enum_ad_to_slot_map);
1568 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1569                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1570                         enum_ad_to_slot_map);
1571 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1572                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1573                         enum_ad_to_slot_map);
1574 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1575                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1576                         enum_ad_to_slot_map);
1577 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1578                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1579                         enum_ad_to_slot_map);
1580 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1581                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1582                         enum_ad_to_slot_map);
1583
1584 /* Digital interface - Burst mode */
1585 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1586 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1587                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1588                         enum_mask);
1589 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1590 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1591                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1592                         enum_bitclk0);
1593 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1594 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1595                         AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1596                         enum_slavemaster);
1597
1598 /* Sidetone */
1599 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1600
1601 /* ANC */
1602 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1603
1604 static struct snd_kcontrol_new ab8500_ctrls[] = {
1605         /* Charge pump */
1606         SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1607                 soc_enum_envdeththre),
1608         SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1609                 soc_enum_envdetlthre),
1610         SOC_SINGLE("Charge Pump Envelope Detection Switch",
1611                 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1612                 1, 0),
1613         SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1614                 soc_enum_envdettime),
1615
1616         /* Headset */
1617         SOC_ENUM("Headset Mode", soc_enum_da12voice),
1618         SOC_SINGLE("Headset High Pass Switch",
1619                 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1620                 1, 0),
1621         SOC_SINGLE("Headset Low Power Switch",
1622                 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1623                 1, 0),
1624         SOC_SINGLE("Headset DAC Low Power Switch",
1625                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1626                 1, 0),
1627         SOC_SINGLE("Headset DAC Drv Low Power Switch",
1628                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1629                 1, 0),
1630         SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1631         SOC_ENUM("Headset Source", soc_enum_da2hslr),
1632         SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1633         SOC_DOUBLE_R_TLV("Headset Master Volume",
1634                 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1635                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1636         SOC_DOUBLE_R_TLV("Headset Digital Volume",
1637                 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1638                 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1639         SOC_DOUBLE_TLV("Headset Volume",
1640                 AB8500_ANAGAIN3,
1641                 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1642                 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1643
1644         /* Earpiece */
1645         SOC_ENUM("Earpiece DAC Mode",
1646                 soc_enum_eardaclowpow),
1647         SOC_ENUM("Earpiece DAC Drv Mode",
1648                 soc_enum_eardrvlowpow),
1649
1650         /* HandsFree */
1651         SOC_ENUM("HF Mode", soc_enum_da34voice),
1652         SOC_SINGLE("HF and Headset Swap Switch",
1653                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1654                 1, 0),
1655         SOC_DOUBLE("HF Low EMI Mode Switch",
1656                 AB8500_CLASSDCONF1,
1657                 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1658                 1, 0),
1659         SOC_DOUBLE("HF FIR Bypass Switch",
1660                 AB8500_CLASSDCONF2,
1661                 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1662                 1, 0),
1663         SOC_DOUBLE("HF High Volume Switch",
1664                 AB8500_CLASSDCONF2,
1665                 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1666                 1, 0),
1667         SOC_SINGLE("HF L and R Bridge Switch",
1668                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1669                 1, 0),
1670         SOC_DOUBLE_R_TLV("HF Master Volume",
1671                 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1672                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1673
1674         /* Vibra */
1675         SOC_DOUBLE("Vibra High Volume Switch",
1676                 AB8500_CLASSDCONF2,
1677                 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1678                 1, 0),
1679         SOC_DOUBLE("Vibra Low EMI Mode Switch",
1680                 AB8500_CLASSDCONF1,
1681                 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1682                 1, 0),
1683         SOC_DOUBLE("Vibra FIR Bypass Switch",
1684                 AB8500_CLASSDCONF2,
1685                 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1686                 1, 0),
1687         SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1688         SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1689                 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1690                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1691                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1692         SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1693                 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1694                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1695                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1696         SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1697                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1698                 1, 0),
1699         SOC_DOUBLE_R_TLV("Vibra Master Volume",
1700                 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1701                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1702
1703         /* HandsFree, Vibra */
1704         SOC_SINGLE("ClassD High Pass Volume",
1705                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1706                 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1707         SOC_SINGLE("ClassD White Volume",
1708                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1709                 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1710
1711         /* Mic 1, Mic 2, LineIn */
1712         SOC_DOUBLE_R_TLV("Mic Master Volume",
1713                 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1714                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1715
1716         /* Mic 1 */
1717         SOC_SINGLE_TLV("Mic 1",
1718                 AB8500_ANAGAIN1,
1719                 AB8500_ANAGAINX_MICXGAIN,
1720                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1721         SOC_SINGLE("Mic 1 Low Power Switch",
1722                 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1723                 1, 0),
1724
1725         /* Mic 2 */
1726         SOC_DOUBLE("Mic High Pass Switch",
1727                 AB8500_ADFILTCONF,
1728                 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1729                 1, 1),
1730         SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1731         SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1732         SOC_SINGLE_TLV("Mic 2",
1733                 AB8500_ANAGAIN2,
1734                 AB8500_ANAGAINX_MICXGAIN,
1735                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1736         SOC_SINGLE("Mic 2 Low Power Switch",
1737                 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1738                 1, 0),
1739
1740         /* LineIn */
1741         SOC_DOUBLE("LineIn High Pass Switch",
1742                 AB8500_ADFILTCONF,
1743                 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1744                 1, 1),
1745         SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1746         SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1747         SOC_DOUBLE_R_TLV("LineIn Master Volume",
1748                 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1749                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1750         SOC_DOUBLE_TLV("LineIn",
1751                 AB8500_ANAGAIN4,
1752                 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1753                 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1754         SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1755                 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1756                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1757                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1758                 1, lin2hs_gain_tlv),
1759
1760         /* DMic */
1761         SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1762         SOC_DOUBLE_R_TLV("DMic Master Volume",
1763                 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1764                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1765
1766         /* Digital gains */
1767         SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1768
1769         /* Analog loopback */
1770         SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1771                 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1772                 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1773
1774         /* Digital interface - DA from slot mapping */
1775         SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1776         SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1777         SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1778         SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1779         SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1780         SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1781         SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1782         SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1783
1784         /* Digital interface - AD to slot mapping */
1785         SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1786         SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1787         SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1788         SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1789         SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1790         SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1791         SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1792         SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1793         SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1794         SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1795         SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1796         SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1797         SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1798         SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1799         SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1800         SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1801         SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1802         SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1803         SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1804         SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1805         SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1806         SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1807         SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1808         SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1809         SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1810         SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1811         SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1812         SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1813         SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1814         SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1815         SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1816         SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1817
1818         /* Digital interface - Loopback */
1819         SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1820                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1821                 1, 0),
1822         SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1823                 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1824                 1, 0),
1825         SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1826                 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1827                 1, 0),
1828         SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1829                 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1830                 1, 0),
1831         SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1832                 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1833                 1, 0),
1834         SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1835                 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1836                 1, 0),
1837         SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1838                 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1839                 1, 0),
1840         SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1841                 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1842                 1, 0),
1843
1844         /* Digital interface - Burst FIFO */
1845         SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1846                 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1847                 1, 0),
1848         SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1849         SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1850         SOC_SINGLE("Burst FIFO Threshold",
1851                 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1852                 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1853         SOC_SINGLE("Burst FIFO Length",
1854                 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1855                 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1856         SOC_SINGLE("Burst FIFO EOS Extra Slots",
1857                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1858                 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1859         SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1860                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1861                 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1862         SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1863
1864         SOC_SINGLE("Burst FIFO Interface Switch",
1865                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1866                 1, 0),
1867         SOC_SINGLE("Burst FIFO Switch Frame Number",
1868                 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1869                 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1870         SOC_SINGLE("Burst FIFO Wake Up Delay",
1871                 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1872                 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1873         SOC_SINGLE("Burst FIFO Samples In FIFO",
1874                 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1875                 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1876
1877         /* ANC */
1878         SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1879                 anc_status_control_get, anc_status_control_put),
1880         SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1881                 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1882                 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1883         SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1884                 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1885                 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1886         SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1887                 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1888                 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1889         SOC_SINGLE_XR_SX("ANC Warp Delay",
1890                 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1891                 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1892
1893         /* Sidetone */
1894         SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1895                 sid_status_control_get, sid_status_control_put),
1896         SOC_SINGLE_STROBE("Sidetone Reset",
1897                 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1898 };
1899
1900 static struct snd_kcontrol_new ab8500_filter_controls[] = {
1901         AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1902                 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1903         AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1904                 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1905         AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1906                         AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1907                         AB8500_SID_FIR_COEFF_MAX)
1908 };
1909 enum ab8500_filter {
1910         AB8500_FILTER_ANC_FIR = 0,
1911         AB8500_FILTER_ANC_IIR = 1,
1912         AB8500_FILTER_SID_FIR = 2,
1913 };
1914
1915 /*
1916  * Extended interface for codec-driver
1917  */
1918
1919 static int ab8500_audio_init_audioblock(struct snd_soc_component *component)
1920 {
1921         int status;
1922
1923         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1924
1925         /* Reset audio-registers and disable 32kHz-clock output 2 */
1926         status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1927                                 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1928                                         AB8500_STW4500CTRL3_RESETAUDN,
1929                                 AB8500_STW4500CTRL3_RESETAUDN);
1930         if (status < 0)
1931                 return status;
1932
1933         return 0;
1934 }
1935
1936 static int ab8500_audio_setup_mics(struct snd_soc_component *component,
1937                         struct amic_settings *amics)
1938 {
1939         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1940         u8 value8;
1941         unsigned int value;
1942         int status;
1943         const struct snd_soc_dapm_route *route;
1944
1945         dev_dbg(component->dev, "%s: Enter.\n", __func__);
1946
1947         /* Set DMic-clocks to outputs */
1948         status = abx500_get_register_interruptible(component->dev, AB8500_MISC,
1949                                                 AB8500_GPIO_DIR4_REG,
1950                                                 &value8);
1951         if (status < 0)
1952                 return status;
1953         value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1954                 GPIO31_DIR_OUTPUT;
1955         status = abx500_set_register_interruptible(component->dev,
1956                                                 AB8500_MISC,
1957                                                 AB8500_GPIO_DIR4_REG,
1958                                                 value);
1959         if (status < 0)
1960                 return status;
1961
1962         /* Attach regulators to AMic DAPM-paths */
1963         dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__,
1964                 amic_micbias_str(amics->mic1a_micbias));
1965         route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1966         status = snd_soc_dapm_add_routes(dapm, route, 1);
1967         dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__,
1968                 amic_micbias_str(amics->mic1b_micbias));
1969         route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1970         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1971         dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__,
1972                 amic_micbias_str(amics->mic2_micbias));
1973         route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1974         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1975         if (status < 0) {
1976                 dev_err(component->dev,
1977                         "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1978                         __func__, status);
1979                 return status;
1980         }
1981
1982         /* Set AMic-configuration */
1983         dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1984                 amic_type_str(amics->mic1_type));
1985         snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1986                         amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1987                                 0 : AB8500_ANAGAINX_ENSEMICX);
1988         dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__,
1989                 amic_type_str(amics->mic2_type));
1990         snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
1991                         amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
1992                                 0 : AB8500_ANAGAINX_ENSEMICX);
1993
1994         return 0;
1995 }
1996
1997 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
1998                                 enum ear_cm_voltage ear_cmv)
1999 {
2000         char *cmv_str;
2001
2002         switch (ear_cmv) {
2003         case EAR_CMV_0_95V:
2004                 cmv_str = "0.95V";
2005                 break;
2006         case EAR_CMV_1_10V:
2007                 cmv_str = "1.10V";
2008                 break;
2009         case EAR_CMV_1_27V:
2010                 cmv_str = "1.27V";
2011                 break;
2012         case EAR_CMV_1_58V:
2013                 cmv_str = "1.58V";
2014                 break;
2015         default:
2016                 dev_err(component->dev,
2017                         "%s: Unknown earpiece CM-voltage (%d)!\n",
2018                         __func__, (int)ear_cmv);
2019                 return -EINVAL;
2020         }
2021         dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2022                 cmv_str);
2023         snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2024                         ear_cmv);
2025
2026         return 0;
2027 }
2028
2029 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2030                                 unsigned int delay)
2031 {
2032         unsigned int mask, val;
2033         struct snd_soc_component *component = dai->component;
2034
2035         mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2036         val = 0;
2037
2038         switch (delay) {
2039         case 0:
2040                 break;
2041         case 1:
2042                 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2043                 break;
2044         default:
2045                 dev_err(dai->component->dev,
2046                         "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2047                         __func__, delay);
2048                 return -EINVAL;
2049         }
2050
2051         dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
2052                 __func__, delay);
2053         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2054
2055         return 0;
2056 }
2057
2058 /* Gates clocking according format mask */
2059 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
2060                                         unsigned int fmt)
2061 {
2062         unsigned int mask;
2063         unsigned int val;
2064
2065         mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2066                         BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2067
2068         val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2069
2070         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2071         case SND_SOC_DAIFMT_CONT: /* continuous clock */
2072                 dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
2073                         __func__);
2074                 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2075                 break;
2076         case SND_SOC_DAIFMT_GATED: /* clock is gated */
2077                 dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
2078                         __func__);
2079                 break;
2080         default:
2081                 dev_err(component->dev,
2082                         "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2083                         __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2084                 return -EINVAL;
2085         }
2086
2087         snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2088
2089         return 0;
2090 }
2091
2092 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2093 {
2094         unsigned int mask;
2095         unsigned int val;
2096         struct snd_soc_component *component = dai->component;
2097         int status;
2098
2099         dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2100
2101         mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2102                         BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2103                         BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2104                         BIT(AB8500_DIGIFCONF3_IF0MASTER);
2105         val = 0;
2106
2107         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2108         case SND_SOC_DAIFMT_CBP_CFP:
2109                 dev_dbg(dai->component->dev,
2110                         "%s: IF0 Master-mode: AB8500 provider.\n", __func__);
2111                 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2112                 break;
2113         case SND_SOC_DAIFMT_CBC_CFC:
2114                 dev_dbg(dai->component->dev,
2115                         "%s: IF0 Master-mode: AB8500 consumer.\n", __func__);
2116                 break;
2117         case SND_SOC_DAIFMT_CBC_CFP:
2118         case SND_SOC_DAIFMT_CBP_CFC:
2119                 dev_err(dai->component->dev,
2120                         "%s: ERROR: The device is either a provider or a consumer.\n",
2121                         __func__);
2122                 fallthrough;
2123         default:
2124                 dev_err(dai->component->dev,
2125                         "%s: ERROR: Unsupporter clocking mask 0x%x\n",
2126                         __func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
2127                 return -EINVAL;
2128         }
2129
2130         snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
2131
2132         /* Set clock gating */
2133         status = ab8500_codec_set_dai_clock_gate(component, fmt);
2134         if (status) {
2135                 dev_err(dai->component->dev,
2136                         "%s: ERROR: Failed to set clock gate (%d).\n",
2137                         __func__, status);
2138                 return status;
2139         }
2140
2141         /* Setting data transfer format */
2142
2143         mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2144                 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2145                 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2146                 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2147         val = 0;
2148
2149         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2150         case SND_SOC_DAIFMT_I2S: /* I2S mode */
2151                 dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
2152                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2153                 ab8500_audio_set_bit_delay(dai, 0);
2154                 break;
2155
2156         case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2157                 dev_dbg(dai->component->dev,
2158                         "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2159                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2160                 ab8500_audio_set_bit_delay(dai, 1);
2161                 break;
2162
2163         case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2164                 dev_dbg(dai->component->dev,
2165                         "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2166                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2167                 ab8500_audio_set_bit_delay(dai, 0);
2168                 break;
2169
2170         default:
2171                 dev_err(dai->component->dev,
2172                         "%s: ERROR: Unsupported format (0x%x)!\n",
2173                         __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2174                 return -EINVAL;
2175         }
2176
2177         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2178         case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2179                 dev_dbg(dai->component->dev,
2180                         "%s: IF0: Normal bit clock, normal frame\n",
2181                         __func__);
2182                 break;
2183         case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2184                 dev_dbg(dai->component->dev,
2185                         "%s: IF0: Normal bit clock, inverted frame\n",
2186                         __func__);
2187                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2188                 break;
2189         case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2190                 dev_dbg(dai->component->dev,
2191                         "%s: IF0: Inverted bit clock, normal frame\n",
2192                         __func__);
2193                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2194                 break;
2195         case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2196                 dev_dbg(dai->component->dev,
2197                         "%s: IF0: Inverted bit clock, inverted frame\n",
2198                         __func__);
2199                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2200                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2201                 break;
2202         default:
2203                 dev_err(dai->component->dev,
2204                         "%s: ERROR: Unsupported INV mask 0x%x\n",
2205                         __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2206                 return -EINVAL;
2207         }
2208
2209         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2210
2211         return 0;
2212 }
2213
2214 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2215                 unsigned int tx_mask, unsigned int rx_mask,
2216                 int slots, int slot_width)
2217 {
2218         struct snd_soc_component *component = dai->component;
2219         unsigned int val, mask, slot, slots_active;
2220
2221         mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2222                 BIT(AB8500_DIGIFCONF2_IF0WL1);
2223         val = 0;
2224
2225         switch (slot_width) {
2226         case 16:
2227                 break;
2228         case 20:
2229                 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2230                 break;
2231         case 24:
2232                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2233                 break;
2234         case 32:
2235                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2236                         BIT(AB8500_DIGIFCONF2_IF0WL0);
2237                 break;
2238         default:
2239                 dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n",
2240                         __func__, slot_width);
2241                 return -EINVAL;
2242         }
2243
2244         dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n",
2245                 __func__, slot_width);
2246         snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
2247
2248         /* Setup TDM clocking according to slot count */
2249         dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots);
2250         mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2251                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2252         switch (slots) {
2253         case 2:
2254                 val = AB8500_MASK_NONE;
2255                 break;
2256         case 4:
2257                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2258                 break;
2259         case 8:
2260                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2261                 break;
2262         case 16:
2263                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2264                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2265                 break;
2266         default:
2267                 dev_err(dai->component->dev,
2268                         "%s: ERROR: Unsupported number of slots (%d)!\n",
2269                         __func__, slots);
2270                 return -EINVAL;
2271         }
2272         snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
2273
2274         /* Setup TDM DA according to active tx slots */
2275
2276         if (tx_mask & ~0xff)
2277                 return -EINVAL;
2278
2279         mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2280         tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
2281         slots_active = hweight32(tx_mask);
2282
2283         dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__,
2284                 slots_active);
2285
2286         switch (slots_active) {
2287         case 0:
2288                 break;
2289         case 1:
2290                 slot = ffs(tx_mask);
2291                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2292                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2293                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2294                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2295                 break;
2296         case 2:
2297                 slot = ffs(tx_mask);
2298                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot);
2299                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot);
2300                 slot = fls(tx_mask);
2301                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot);
2302                 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot);
2303                 break;
2304         case 8:
2305                 dev_dbg(dai->component->dev,
2306                         "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2307                         __func__);
2308                 break;
2309         default:
2310                 dev_err(dai->component->dev,
2311                         "%s: Unsupported number of active TX-slots (%d)!\n",
2312                         __func__, slots_active);
2313                 return -EINVAL;
2314         }
2315
2316         /* Setup TDM AD according to active RX-slots */
2317
2318         if (rx_mask & ~0xff)
2319                 return -EINVAL;
2320
2321         rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
2322         slots_active = hweight32(rx_mask);
2323
2324         dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__,
2325                 slots_active);
2326
2327         switch (slots_active) {
2328         case 0:
2329                 break;
2330         case 1:
2331                 slot = ffs(rx_mask);
2332                 snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot),
2333                                 AB8500_MASK_SLOT(slot),
2334                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2335                 break;
2336         case 2:
2337                 slot = ffs(rx_mask);
2338                 snd_soc_component_update_bits(component,
2339                                 AB8500_ADSLOTSEL(slot),
2340                                 AB8500_MASK_SLOT(slot),
2341                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2342                 slot = fls(rx_mask);
2343                 snd_soc_component_update_bits(component,
2344                                 AB8500_ADSLOTSEL(slot),
2345                                 AB8500_MASK_SLOT(slot),
2346                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
2347                 break;
2348         case 8:
2349                 dev_dbg(dai->component->dev,
2350                         "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2351                         __func__);
2352                 break;
2353         default:
2354                 dev_err(dai->component->dev,
2355                         "%s: Unsupported number of active RX-slots (%d)!\n",
2356                         __func__, slots_active);
2357                 return -EINVAL;
2358         }
2359
2360         return 0;
2361 }
2362
2363 static const struct snd_soc_dai_ops ab8500_codec_ops = {
2364         .set_fmt = ab8500_codec_set_dai_fmt,
2365         .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2366 };
2367
2368 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
2369         {
2370                 .name = "ab8500-codec-dai.0",
2371                 .id = 0,
2372                 .playback = {
2373                         .stream_name = "ab8500_0p",
2374                         .channels_min = 1,
2375                         .channels_max = 8,
2376                         .rates = AB8500_SUPPORTED_RATE,
2377                         .formats = AB8500_SUPPORTED_FMT,
2378                 },
2379                 .ops = &ab8500_codec_ops,
2380                 .symmetric_rate = 1
2381         },
2382         {
2383                 .name = "ab8500-codec-dai.1",
2384                 .id = 1,
2385                 .capture = {
2386                         .stream_name = "ab8500_0c",
2387                         .channels_min = 1,
2388                         .channels_max = 8,
2389                         .rates = AB8500_SUPPORTED_RATE,
2390                         .formats = AB8500_SUPPORTED_FMT,
2391                 },
2392                 .ops = &ab8500_codec_ops,
2393                 .symmetric_rate = 1
2394         }
2395 };
2396
2397 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2398                                 struct ab8500_codec_platform_data *codec)
2399 {
2400         u32 value;
2401
2402         if (of_property_read_bool(np, "stericsson,amic1-type-single-ended"))
2403                 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2404         else
2405                 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2406
2407         if (of_property_read_bool(np, "stericsson,amic2-type-single-ended"))
2408                 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2409         else
2410                 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2411
2412         /* Has a non-standard Vamic been requested? */
2413         if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2"))
2414                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2415         else
2416                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2417
2418         if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2"))
2419                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2420         else
2421                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2422
2423         if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1"))
2424                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2425         else
2426                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2427
2428         if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2429                 switch (value) {
2430                 case 950 :
2431                         codec->ear_cmv = EAR_CMV_0_95V;
2432                         break;
2433                 case 1100 :
2434                         codec->ear_cmv = EAR_CMV_1_10V;
2435                         break;
2436                 case 1270 :
2437                         codec->ear_cmv = EAR_CMV_1_27V;
2438                         break;
2439                 case 1580 :
2440                         codec->ear_cmv = EAR_CMV_1_58V;
2441                         break;
2442                 default :
2443                         codec->ear_cmv = EAR_CMV_UNKNOWN;
2444                         dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2445                 }
2446         } else {
2447                 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2448                 codec->ear_cmv = EAR_CMV_0_95V;
2449         }
2450 }
2451
2452 static int ab8500_codec_probe(struct snd_soc_component *component)
2453 {
2454         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2455         struct device *dev = component->dev;
2456         struct device_node *np = dev->of_node;
2457         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2458         struct ab8500_codec_platform_data codec_pdata;
2459         struct filter_control *fc;
2460         int status;
2461
2462         dev_dbg(dev, "%s: Enter.\n", __func__);
2463
2464         ab8500_codec_of_probe(dev, np, &codec_pdata);
2465
2466         status = ab8500_audio_setup_mics(component, &codec_pdata.amics);
2467         if (status < 0) {
2468                 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2469                 return status;
2470         }
2471         status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv);
2472         if (status < 0) {
2473                 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2474                         __func__, status);
2475                 return status;
2476         }
2477
2478         status = ab8500_audio_init_audioblock(component);
2479         if (status < 0) {
2480                 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2481                         __func__, status);
2482                 return status;
2483         }
2484
2485         /* Override HW-defaults */
2486         snd_soc_component_write(component, AB8500_ANACONF5,
2487                       BIT(AB8500_ANACONF5_HSAUTOEN));
2488         snd_soc_component_write(component, AB8500_SHORTCIRCONF,
2489                       BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2490
2491         /* Add filter controls */
2492         status = snd_soc_add_component_controls(component, ab8500_filter_controls,
2493                                 ARRAY_SIZE(ab8500_filter_controls));
2494         if (status < 0) {
2495                 dev_err(dev,
2496                         "%s: failed to add ab8500 filter controls (%d).\n",
2497                         __func__, status);
2498                 return status;
2499         }
2500         fc = (struct filter_control *)
2501                 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2502         drvdata->anc_fir_values = (long *)fc->value;
2503         fc = (struct filter_control *)
2504                 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2505         drvdata->anc_iir_values = (long *)fc->value;
2506         fc = (struct filter_control *)
2507                 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2508         drvdata->sid_fir_values = (long *)fc->value;
2509
2510         snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
2511
2512         mutex_init(&drvdata->ctrl_lock);
2513
2514         return status;
2515 }
2516
2517 static const struct snd_soc_component_driver ab8500_component_driver = {
2518         .probe                  = ab8500_codec_probe,
2519         .controls               = ab8500_ctrls,
2520         .num_controls           = ARRAY_SIZE(ab8500_ctrls),
2521         .dapm_widgets           = ab8500_dapm_widgets,
2522         .num_dapm_widgets       = ARRAY_SIZE(ab8500_dapm_widgets),
2523         .dapm_routes            = ab8500_dapm_routes,
2524         .num_dapm_routes        = ARRAY_SIZE(ab8500_dapm_routes),
2525         .idle_bias_on           = 1,
2526         .use_pmdown_time        = 1,
2527         .endianness             = 1,
2528         .non_legacy_dai_naming  = 1,
2529 };
2530
2531 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2532 {
2533         int status;
2534         struct ab8500_codec_drvdata *drvdata;
2535
2536         dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2537
2538         /* Create driver private-data struct */
2539         drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2540                         GFP_KERNEL);
2541         if (!drvdata)
2542                 return -ENOMEM;
2543         drvdata->sid_status = SID_UNCONFIGURED;
2544         drvdata->anc_status = ANC_UNCONFIGURED;
2545         dev_set_drvdata(&pdev->dev, drvdata);
2546
2547         drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2548                                            &ab8500_codec_regmap);
2549         if (IS_ERR(drvdata->regmap)) {
2550                 status = PTR_ERR(drvdata->regmap);
2551                 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2552                         __func__, status);
2553                 return status;
2554         }
2555
2556         dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2557         status = devm_snd_soc_register_component(&pdev->dev,
2558                                 &ab8500_component_driver,
2559                                 ab8500_codec_dai,
2560                                 ARRAY_SIZE(ab8500_codec_dai));
2561         if (status < 0)
2562                 dev_err(&pdev->dev,
2563                         "%s: Error: Failed to register codec (%d).\n",
2564                         __func__, status);
2565
2566         return status;
2567 }
2568
2569 static struct platform_driver ab8500_codec_platform_driver = {
2570         .driver = {
2571                 .name   = "ab8500-codec",
2572         },
2573         .probe          = ab8500_codec_driver_probe,
2574 };
2575 module_platform_driver(ab8500_codec_platform_driver);
2576
2577 MODULE_LICENSE("GPL v2");