drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  34                                       struct drm_amdgpu_cs_chunk_fence *data,
  35                                       uint32_t *offset)
  36 {
  37         struct drm_gem_object *gobj;
  38         unsigned long size;
  39
  40         gobj = drm_gem_object_lookup(p->filp, data->handle);
  41         if (gobj == NULL)
  42                 return -EINVAL;
  43
  44         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  45         p->uf_entry.priority = 0;
  46         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  47         p->uf_entry.tv.shared = true;
  48         p->uf_entry.user_pages = NULL;
  49
  50         size = amdgpu_bo_size(p->uf_entry.robj);
  51         if (size != PAGE_SIZE || (data->offset + 8) > size)
  52                 return -EINVAL;
  53
  54         *offset = data->offset;
  55
  56         drm_gem_object_unreference_unlocked(gobj);
  57
  58         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  59                 amdgpu_bo_unref(&p->uf_entry.robj);
  60                 return -EINVAL;
  61         }
  62
  63         return 0;
  64 }
  65
  66 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  67 {
  68         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  69         struct amdgpu_vm *vm = &fpriv->vm;
  70         union drm_amdgpu_cs *cs = data;
  71         uint64_t *chunk_array_user;
  72         uint64_t *chunk_array;
  73         unsigned size, num_ibs = 0;
  74         uint32_t uf_offset = 0;
  75         int i;
  76         int ret;
  77
  78         if (cs->in.num_chunks == 0)
  79                 return 0;
  80
  81         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  82         if (!chunk_array)
  83                 return -ENOMEM;
  84
  85         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  86         if (!p->ctx) {
  87                 ret = -EINVAL;
  88                 goto free_chunk;
  89         }
  90
  91         /* get chunks */
  92         chunk_array_user = (uint64_t __user *)(uintptr_t)(cs->in.chunks);
  93         if (copy_from_user(chunk_array, chunk_array_user,
  94                            sizeof(uint64_t)*cs->in.num_chunks)) {
  95                 ret = -EFAULT;
  96                 goto put_ctx;
  97         }
  98
  99         p->nchunks = cs->in.num_chunks;
 100         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 101                             GFP_KERNEL);
 102         if (!p->chunks) {
 103                 ret = -ENOMEM;
 104                 goto put_ctx;
 105         }
 106
 107         for (i = 0; i < p->nchunks; i++) {
 108                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 109                 struct drm_amdgpu_cs_chunk user_chunk;
 110                 uint32_t __user *cdata;
 111
 112                 chunk_ptr = (void __user *)(uintptr_t)chunk_array[i];
 113                 if (copy_from_user(&user_chunk, chunk_ptr,
 114                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 115                         ret = -EFAULT;
 116                         i--;
 117                         goto free_partial_kdata;
 118                 }
 119                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 120                 p->chunks[i].length_dw = user_chunk.length_dw;
 121
 122                 size = p->chunks[i].length_dw;
 123                 cdata = (void __user *)(uintptr_t)user_chunk.chunk_data;
 124
 125                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 126                 if (p->chunks[i].kdata == NULL) {
 127                         ret = -ENOMEM;
 128                         i--;
 129                         goto free_partial_kdata;
 130                 }
 131                 size *= sizeof(uint32_t);
 132                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 133                         ret = -EFAULT;
 134                         goto free_partial_kdata;
 135                 }
 136
 137                 switch (p->chunks[i].chunk_id) {
 138                 case AMDGPU_CHUNK_ID_IB:
 139                         ++num_ibs;
 140                         break;
 141
 142                 case AMDGPU_CHUNK_ID_FENCE:
 143                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 144                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 145                                 ret = -EINVAL;
 146                                 goto free_partial_kdata;
 147                         }
 148
 149                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 150                                                          &uf_offset);
 151                         if (ret)
 152                                 goto free_partial_kdata;
 153
 154                         break;
 155
 156                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 157                         break;
 158
 159                 default:
 160                         ret = -EINVAL;
 161                         goto free_partial_kdata;
 162                 }
 163         }
 164
 165         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 166         if (ret)
 167                 goto free_all_kdata;
 168
 169         if (p->uf_entry.robj)
 170                 p->job->uf_addr = uf_offset;
 171         kfree(chunk_array);
 172         return 0;
 173
 174 free_all_kdata:
 175         i = p->nchunks - 1;
 176 free_partial_kdata:
 177         for (; i >= 0; i--)
 178                 kvfree(p->chunks[i].kdata);
 179         kfree(p->chunks);
 180         p->chunks = NULL;
 181         p->nchunks = 0;
 182 put_ctx:
 183         amdgpu_ctx_put(p->ctx);
 184 free_chunk:
 185         kfree(chunk_array);
 186
 187         return ret;
 188 }
 189
 190 /* Convert microseconds to bytes. */
 191 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 192 {
 193         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 194                 return 0;
 195
 196         /* Since accum_us is incremented by a million per second, just
 197          * multiply it by the number of MB/s to get the number of bytes.
 198          */
 199         return us << adev->mm_stats.log2_max_MBps;
 200 }
 201
 202 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 203 {
 204         if (!adev->mm_stats.log2_max_MBps)
 205                 return 0;
 206
 207         return bytes >> adev->mm_stats.log2_max_MBps;
 208 }
 209
 210 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 211  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 212  * which means it can go over the threshold once. If that happens, the driver
 213  * will be in debt and no other buffer migrations can be done until that debt
 214  * is repaid.
 215  *
 216  * This approach allows moving a buffer of any size (it's important to allow
 217  * that).
 218  *
 219  * The currency is simply time in microseconds and it increases as the clock
 220  * ticks. The accumulated microseconds (us) are converted to bytes and
 221  * returned.
 222  */
 223 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 224 {
 225         s64 time_us, increment_us;
 226         u64 max_bytes;
 227         u64 free_vram, total_vram, used_vram;
 228
 229         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 230          * throttling.
 231          *
 232          * It means that in order to get full max MBps, at least 5 IBs per
 233          * second must be submitted and not more than 200ms apart from each
 234          * other.
 235          */
 236         const s64 us_upper_bound = 200000;
 237
 238         if (!adev->mm_stats.log2_max_MBps)
 239                 return 0;
 240
 241         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 242         used_vram = atomic64_read(&adev->vram_usage);
 243         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 244
 245         spin_lock(&adev->mm_stats.lock);
 246
 247         /* Increase the amount of accumulated us. */
 248         time_us = ktime_to_us(ktime_get());
 249         increment_us = time_us - adev->mm_stats.last_update_us;
 250         adev->mm_stats.last_update_us = time_us;
 251         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 252                                       us_upper_bound);
 253
 254         /* This prevents the short period of low performance when the VRAM
 255          * usage is low and the driver is in debt or doesn't have enough
 256          * accumulated us to fill VRAM quickly.
 257          *
 258          * The situation can occur in these cases:
 259          * - a lot of VRAM is freed by userspace
 260          * - the presence of a big buffer causes a lot of evictions
 261          *   (solution: split buffers into smaller ones)
 262          *
 263          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 264          * accum_us to a positive number.
 265          */
 266         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 267                 s64 min_us;
 268
 269                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 270                  * VRAM now.
 271                  */
 272                 if (!(adev->flags & AMD_IS_APU))
 273                         min_us = bytes_to_us(adev, free_vram / 4);
 274                 else
 275                         min_us = 0; /* Reset accum_us on APUs. */
 276
 277                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 278         }
 279
 280         /* This returns 0 if the driver is in debt to disallow (optional)
 281          * buffer moves.
 282          */
 283         max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 284
 285         spin_unlock(&adev->mm_stats.lock);
 286         return max_bytes;
 287 }
 288
 289 /* Report how many bytes have really been moved for the last command
 290  * submission. This can result in a debt that can stop buffer migrations
 291  * temporarily.
 292  */
 293 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes)
 294 {
 295         spin_lock(&adev->mm_stats.lock);
 296         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 297         spin_unlock(&adev->mm_stats.lock);
 298 }
 299
 300 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 301                                  struct amdgpu_bo *bo)
 302 {
 303         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 304         u64 initial_bytes_moved;
 305         uint32_t domain;
 306         int r;
 307
 308         if (bo->pin_count)
 309                 return 0;
 310
 311         /* Don't move this buffer if we have depleted our allowance
 312          * to move it. Don't move anything if the threshold is zero.
 313          */
 314         if (p->bytes_moved < p->bytes_moved_threshold)
 315                 domain = bo->prefered_domains;
 316         else
 317                 domain = bo->allowed_domains;
 318
 319 retry:
 320         amdgpu_ttm_placement_from_domain(bo, domain);
 321         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 322         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 323         p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 324                 initial_bytes_moved;
 325
 326         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 327                 domain = bo->allowed_domains;
 328                 goto retry;
 329         }
 330
 331         return r;
 332 }
 333
 334 /* Last resort, try to evict something from the current working set */
 335 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 336                                 struct amdgpu_bo *validated)
 337 {
 338         uint32_t domain = validated->allowed_domains;
 339         int r;
 340
 341         if (!p->evictable)
 342                 return false;
 343
 344         for (;&p->evictable->tv.head != &p->validated;
 345              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 346
 347                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 348                 struct amdgpu_bo *bo = candidate->robj;
 349                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 350                 u64 initial_bytes_moved;
 351                 uint32_t other;
 352
 353                 /* If we reached our current BO we can forget it */
 354                 if (candidate->robj == validated)
 355                         break;
 356
 357                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 358
 359                 /* Check if this BO is in one of the domains we need space for */
 360                 if (!(other & domain))
 361                         continue;
 362
 363                 /* Check if we can move this BO somewhere else */
 364                 other = bo->allowed_domains & ~domain;
 365                 if (!other)
 366                         continue;
 367
 368                 /* Good we can try to move this BO somewhere else */
 369                 amdgpu_ttm_placement_from_domain(bo, other);
 370                 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 371                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 372                 p->bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 373                         initial_bytes_moved;
 374
 375                 if (unlikely(r))
 376                         break;
 377
 378                 p->evictable = list_prev_entry(p->evictable, tv.head);
 379                 list_move(&candidate->tv.head, &p->validated);
 380
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 388 {
 389         struct amdgpu_cs_parser *p = param;
 390         int r;
 391
 392         do {
 393                 r = amdgpu_cs_bo_validate(p, bo);
 394         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 395         if (r)
 396                 return r;
 397
 398         if (bo->shadow)
 399                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 400
 401         return r;
 402 }
 403
 404 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 405                             struct list_head *validated)
 406 {
 407         struct amdgpu_bo_list_entry *lobj;
 408         int r;
 409
 410         list_for_each_entry(lobj, validated, tv.head) {
 411                 struct amdgpu_bo *bo = lobj->robj;
 412                 bool binding_userptr = false;
 413                 struct mm_struct *usermm;
 414
 415                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 416                 if (usermm && usermm != current->mm)
 417                         return -EPERM;
 418
 419                 /* Check if we have user pages and nobody bound the BO already */
 420                 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
 421                         size_t size = sizeof(struct page *);
 422
 423                         size *= bo->tbo.ttm->num_pages;
 424                         memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
 425                         binding_userptr = true;
 426                 }
 427
 428                 if (p->evictable == lobj)
 429                         p->evictable = NULL;
 430
 431                 r = amdgpu_cs_validate(p, bo);
 432                 if (r)
 433                         return r;
 434
 435                 if (binding_userptr) {
 436                         kvfree(lobj->user_pages);
 437                         lobj->user_pages = NULL;
 438                 }
 439         }
 440         return 0;
 441 }
 442
 443 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 444                                 union drm_amdgpu_cs *cs)
 445 {
 446         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 447         struct amdgpu_bo_list_entry *e;
 448         struct list_head duplicates;
 449         bool need_mmap_lock = false;
 450         unsigned i, tries = 10;
 451         int r;
 452
 453         INIT_LIST_HEAD(&p->validated);
 454
 455         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 456         if (p->bo_list) {
 457                 need_mmap_lock = p->bo_list->first_userptr !=
 458                         p->bo_list->num_entries;
 459                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 460         }
 461
 462         INIT_LIST_HEAD(&duplicates);
 463         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 464
 465         if (p->uf_entry.robj)
 466                 list_add(&p->uf_entry.tv.head, &p->validated);
 467
 468         if (need_mmap_lock)
 469                 down_read(&current->mm->mmap_sem);
 470
 471         while (1) {
 472                 struct list_head need_pages;
 473                 unsigned i;
 474
 475                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 476                                            &duplicates);
 477                 if (unlikely(r != 0)) {
 478                         if (r != -ERESTARTSYS)
 479                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 480                         goto error_free_pages;
 481                 }
 482
 483                 /* Without a BO list we don't have userptr BOs */
 484                 if (!p->bo_list)
 485                         break;
 486
 487                 INIT_LIST_HEAD(&need_pages);
 488                 for (i = p->bo_list->first_userptr;
 489                      i < p->bo_list->num_entries; ++i) {
 490
 491                         e = &p->bo_list->array[i];
 492
 493                         if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
 494                                  &e->user_invalidated) && e->user_pages) {
 495
 496                                 /* We acquired a page array, but somebody
 497                                  * invalidated it. Free it an try again
 498                                  */
 499                                 release_pages(e->user_pages,
 500                                               e->robj->tbo.ttm->num_pages,
 501                                               false);
 502                                 kvfree(e->user_pages);
 503                                 e->user_pages = NULL;
 504                         }
 505
 506                         if (e->robj->tbo.ttm->state != tt_bound &&
 507                             !e->user_pages) {
 508                                 list_del(&e->tv.head);
 509                                 list_add(&e->tv.head, &need_pages);
 510
 511                                 amdgpu_bo_unreserve(e->robj);
 512                         }
 513                 }
 514
 515                 if (list_empty(&need_pages))
 516                         break;
 517
 518                 /* Unreserve everything again. */
 519                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 520
 521                 /* We tried too many times, just abort */
 522                 if (!--tries) {
 523                         r = -EDEADLK;
 524                         DRM_ERROR("deadlock in %s\n", __func__);
 525                         goto error_free_pages;
 526                 }
 527
 528                 /* Fill the page arrays for all userptrs. */
 529                 list_for_each_entry(e, &need_pages, tv.head) {
 530                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 531
 532                         e->user_pages = kvmalloc_array(ttm->num_pages,
 533                                                          sizeof(struct page*),
 534                                                          GFP_KERNEL | __GFP_ZERO);
 535                         if (!e->user_pages) {
 536                                 r = -ENOMEM;
 537                                 DRM_ERROR("calloc failure in %s\n", __func__);
 538                                 goto error_free_pages;
 539                         }
 540
 541                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 542                         if (r) {
 543                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 544                                 kvfree(e->user_pages);
 545                                 e->user_pages = NULL;
 546                                 goto error_free_pages;
 547                         }
 548                 }
 549
 550                 /* And try again. */
 551                 list_splice(&need_pages, &p->validated);
 552         }
 553
 554         p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
 555         p->bytes_moved = 0;
 556         p->evictable = list_last_entry(&p->validated,
 557                                        struct amdgpu_bo_list_entry,
 558                                        tv.head);
 559
 560         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 561                                       amdgpu_cs_validate, p);
 562         if (r) {
 563                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 564                 goto error_validate;
 565         }
 566
 567         r = amdgpu_cs_list_validate(p, &duplicates);
 568         if (r) {
 569                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 570                 goto error_validate;
 571         }
 572
 573         r = amdgpu_cs_list_validate(p, &p->validated);
 574         if (r) {
 575                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 576                 goto error_validate;
 577         }
 578
 579         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved);
 580
 581         fpriv->vm.last_eviction_counter =
 582                 atomic64_read(&p->adev->num_evictions);
 583
 584         if (p->bo_list) {
 585                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 586                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 587                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 588                 struct amdgpu_vm *vm = &fpriv->vm;
 589                 unsigned i;
 590
 591                 for (i = 0; i < p->bo_list->num_entries; i++) {
 592                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 593
 594                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 595                 }
 596
 597                 if (gds) {
 598                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 599                         p->job->gds_size = amdgpu_bo_size(gds);
 600                 }
 601                 if (gws) {
 602                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 603                         p->job->gws_size = amdgpu_bo_size(gws);
 604                 }
 605                 if (oa) {
 606                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 607                         p->job->oa_size = amdgpu_bo_size(oa);
 608                 }
 609         }
 610
 611         if (!r && p->uf_entry.robj) {
 612                 struct amdgpu_bo *uf = p->uf_entry.robj;
 613
 614                 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
 615                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 616         }
 617
 618 error_validate:
 619         if (r) {
 620                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 621                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 622         }
 623
 624 error_free_pages:
 625
 626         if (need_mmap_lock)
 627                 up_read(&current->mm->mmap_sem);
 628
 629         if (p->bo_list) {
 630                 for (i = p->bo_list->first_userptr;
 631                      i < p->bo_list->num_entries; ++i) {
 632                         e = &p->bo_list->array[i];
 633
 634                         if (!e->user_pages)
 635                                 continue;
 636
 637                         release_pages(e->user_pages,
 638                                       e->robj->tbo.ttm->num_pages,
 639                                       false);
 640                         kvfree(e->user_pages);
 641                 }
 642         }
 643
 644         return r;
 645 }
 646
 647 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 648 {
 649         struct amdgpu_bo_list_entry *e;
 650         int r;
 651
 652         list_for_each_entry(e, &p->validated, tv.head) {
 653                 struct reservation_object *resv = e->robj->tbo.resv;
 654                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
 655
 656                 if (r)
 657                         return r;
 658         }
 659         return 0;
 660 }
 661
 662 /**
 663  * cs_parser_fini() - clean parser states
 664  * @parser:     parser structure holding parsing context.
 665  * @error:      error number
 666  *
 667  * If error is set than unvalidate buffer, otherwise just free memory
 668  * used by parsing context.
 669  **/
 670 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 671 {
 672         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 673         unsigned i;
 674
 675         if (!error) {
 676                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 677
 678                 ttm_eu_fence_buffer_objects(&parser->ticket,
 679                                             &parser->validated,
 680                                             parser->fence);
 681         } else if (backoff) {
 682                 ttm_eu_backoff_reservation(&parser->ticket,
 683                                            &parser->validated);
 684         }
 685         dma_fence_put(parser->fence);
 686
 687         if (parser->ctx)
 688                 amdgpu_ctx_put(parser->ctx);
 689         if (parser->bo_list)
 690                 amdgpu_bo_list_put(parser->bo_list);
 691
 692         for (i = 0; i < parser->nchunks; i++)
 693                 kvfree(parser->chunks[i].kdata);
 694         kfree(parser->chunks);
 695         if (parser->job)
 696                 amdgpu_job_free(parser->job);
 697         amdgpu_bo_unref(&parser->uf_entry.robj);
 698 }
 699
 700 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 701 {
 702         struct amdgpu_device *adev = p->adev;
 703         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 704         struct amdgpu_vm *vm = &fpriv->vm;
 705         struct amdgpu_bo_va *bo_va;
 706         struct amdgpu_bo *bo;
 707         int i, r;
 708
 709         r = amdgpu_vm_update_directories(adev, vm);
 710         if (r)
 711                 return r;
 712
 713         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
 714         if (r)
 715                 return r;
 716
 717         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 718         if (r)
 719                 return r;
 720
 721         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 722         if (r)
 723                 return r;
 724
 725         r = amdgpu_sync_fence(adev, &p->job->sync,
 726                               fpriv->prt_va->last_pt_update);
 727         if (r)
 728                 return r;
 729
 730         if (amdgpu_sriov_vf(adev)) {
 731                 struct dma_fence *f;
 732                 bo_va = vm->csa_bo_va;
 733                 BUG_ON(!bo_va);
 734                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 735                 if (r)
 736                         return r;
 737
 738                 f = bo_va->last_pt_update;
 739                 r = amdgpu_sync_fence(adev, &p->job->sync, f);
 740                 if (r)
 741                         return r;
 742         }
 743
 744         if (p->bo_list) {
 745                 for (i = 0; i < p->bo_list->num_entries; i++) {
 746                         struct dma_fence *f;
 747
 748                         /* ignore duplicates */
 749                         bo = p->bo_list->array[i].robj;
 750                         if (!bo)
 751                                 continue;
 752
 753                         bo_va = p->bo_list->array[i].bo_va;
 754                         if (bo_va == NULL)
 755                                 continue;
 756
 757                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 758                         if (r)
 759                                 return r;
 760
 761                         f = bo_va->last_pt_update;
 762                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 763                         if (r)
 764                                 return r;
 765                 }
 766
 767         }
 768
 769         r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
 770
 771         if (amdgpu_vm_debug && p->bo_list) {
 772                 /* Invalidate all BOs to test for userspace bugs */
 773                 for (i = 0; i < p->bo_list->num_entries; i++) {
 774                         /* ignore duplicates */
 775                         bo = p->bo_list->array[i].robj;
 776                         if (!bo)
 777                                 continue;
 778
 779                         amdgpu_vm_bo_invalidate(adev, bo);
 780                 }
 781         }
 782
 783         return r;
 784 }
 785
 786 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 787                                  struct amdgpu_cs_parser *p)
 788 {
 789         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 790         struct amdgpu_vm *vm = &fpriv->vm;
 791         struct amdgpu_ring *ring = p->job->ring;
 792         int i, r;
 793
 794         /* Only for UVD/VCE VM emulation */
 795         if (ring->funcs->parse_cs) {
 796                 for (i = 0; i < p->job->num_ibs; i++) {
 797                         r = amdgpu_ring_parse_cs(ring, p, i);
 798                         if (r)
 799                                 return r;
 800                 }
 801         }
 802
 803         if (p->job->vm) {
 804                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
 805
 806                 r = amdgpu_bo_vm_update_pte(p);
 807                 if (r)
 808                         return r;
 809         }
 810
 811         return amdgpu_cs_sync_rings(p);
 812 }
 813
 814 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 815                              struct amdgpu_cs_parser *parser)
 816 {
 817         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 818         struct amdgpu_vm *vm = &fpriv->vm;
 819         int i, j;
 820         int r, ce_preempt = 0, de_preempt = 0;
 821
 822         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 823                 struct amdgpu_cs_chunk *chunk;
 824                 struct amdgpu_ib *ib;
 825                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 826                 struct amdgpu_ring *ring;
 827
 828                 chunk = &parser->chunks[i];
 829                 ib = &parser->job->ibs[j];
 830                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 831
 832                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 833                         continue;
 834
 835                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 836                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 837                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 838                                         ce_preempt++;
 839                                 else
 840                                         de_preempt++;
 841                         }
 842
 843                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 844                         if (ce_preempt > 1 || de_preempt > 1)
 845                                 return -EINVAL;
 846                 }
 847
 848                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 849                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 850                 if (r)
 851                         return r;
 852
 853                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 854                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 855                         if (!parser->ctx->preamble_presented) {
 856                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 857                                 parser->ctx->preamble_presented = true;
 858                         }
 859                 }
 860
 861                 if (parser->job->ring && parser->job->ring != ring)
 862                         return -EINVAL;
 863
 864                 parser->job->ring = ring;
 865
 866                 if (ring->funcs->parse_cs) {
 867                         struct amdgpu_bo_va_mapping *m;
 868                         struct amdgpu_bo *aobj = NULL;
 869                         uint64_t offset;
 870                         uint8_t *kptr;
 871
 872                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 873                                                    &aobj);
 874                         if (!aobj) {
 875                                 DRM_ERROR("IB va_start is invalid\n");
 876                                 return -EINVAL;
 877                         }
 878
 879                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 880                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 881                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 882                                 return -EINVAL;
 883                         }
 884
 885                         /* the IB should be reserved at this point */
 886                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 887                         if (r) {
 888                                 return r;
 889                         }
 890
 891                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 892                         kptr += chunk_ib->va_start - offset;
 893
 894                         r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
 895                         if (r) {
 896                                 DRM_ERROR("Failed to get ib !\n");
 897                                 return r;
 898                         }
 899
 900                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 901                         amdgpu_bo_kunmap(aobj);
 902                 } else {
 903                         r =  amdgpu_ib_get(adev, vm, 0, ib);
 904                         if (r) {
 905                                 DRM_ERROR("Failed to get ib !\n");
 906                                 return r;
 907                         }
 908
 909                 }
 910
 911                 ib->gpu_addr = chunk_ib->va_start;
 912                 ib->length_dw = chunk_ib->ib_bytes / 4;
 913                 ib->flags = chunk_ib->flags;
 914                 j++;
 915         }
 916
 917         /* UVD & VCE fw doesn't support user fences */
 918         if (parser->job->uf_addr && (
 919             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 920             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
 921                 return -EINVAL;
 922
 923         return 0;
 924 }
 925
 926 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 927                                   struct amdgpu_cs_parser *p)
 928 {
 929         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 930         int i, j, r;
 931
 932         for (i = 0; i < p->nchunks; ++i) {
 933                 struct drm_amdgpu_cs_chunk_dep *deps;
 934                 struct amdgpu_cs_chunk *chunk;
 935                 unsigned num_deps;
 936
 937                 chunk = &p->chunks[i];
 938
 939                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 940                         continue;
 941
 942                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 943                 num_deps = chunk->length_dw * 4 /
 944                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 945
 946                 for (j = 0; j < num_deps; ++j) {
 947                         struct amdgpu_ring *ring;
 948                         struct amdgpu_ctx *ctx;
 949                         struct dma_fence *fence;
 950
 951                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 952                         if (ctx == NULL)
 953                                 return -EINVAL;
 954
 955                         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
 956                                                  deps[j].ip_type,
 957                                                  deps[j].ip_instance,
 958                                                  deps[j].ring, &ring);
 959                         if (r) {
 960                                 amdgpu_ctx_put(ctx);
 961                                 return r;
 962                         }
 963
 964                         fence = amdgpu_ctx_get_fence(ctx, ring,
 965                                                      deps[j].handle);
 966                         if (IS_ERR(fence)) {
 967                                 r = PTR_ERR(fence);
 968                                 amdgpu_ctx_put(ctx);
 969                                 return r;
 970
 971                         } else if (fence) {
 972                                 r = amdgpu_sync_fence(adev, &p->job->sync,
 973                                                       fence);
 974                                 dma_fence_put(fence);
 975                                 amdgpu_ctx_put(ctx);
 976                                 if (r)
 977                                         return r;
 978                         }
 979                 }
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 986                             union drm_amdgpu_cs *cs)
 987 {
 988         struct amdgpu_ring *ring = p->job->ring;
 989         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
 990         struct amdgpu_job *job;
 991         int r;
 992
 993         job = p->job;
 994         p->job = NULL;
 995
 996         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
 997         if (r) {
 998                 amdgpu_job_free(job);
 999                 return r;
1000         }
1001
1002         job->owner = p->filp;
1003         job->fence_ctx = entity->fence_context;
1004         p->fence = dma_fence_get(&job->base.s_fence->finished);
1005         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1006         job->uf_sequence = cs->out.handle;
1007         amdgpu_job_free_resources(job);
1008         amdgpu_cs_parser_fini(p, 0, true);
1009
1010         trace_amdgpu_cs_ioctl(job);
1011         amd_sched_entity_push_job(&job->base);
1012
1013         return 0;
1014 }
1015
1016 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1017 {
1018         struct amdgpu_device *adev = dev->dev_private;
1019         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1020         union drm_amdgpu_cs *cs = data;
1021         struct amdgpu_cs_parser parser = {};
1022         bool reserved_buffers = false;
1023         int i, r;
1024
1025         if (!adev->accel_working)
1026                 return -EBUSY;
1027         if (amdgpu_kms_vram_lost(adev, fpriv))
1028                 return -ENODEV;
1029
1030         parser.adev = adev;
1031         parser.filp = filp;
1032
1033         r = amdgpu_cs_parser_init(&parser, data);
1034         if (r) {
1035                 DRM_ERROR("Failed to initialize parser !\n");
1036                 goto out;
1037         }
1038
1039         r = amdgpu_cs_parser_bos(&parser, data);
1040         if (r) {
1041                 if (r == -ENOMEM)
1042                         DRM_ERROR("Not enough memory for command submission!\n");
1043                 else if (r != -ERESTARTSYS)
1044                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1045                 goto out;
1046         }
1047
1048         reserved_buffers = true;
1049         r = amdgpu_cs_ib_fill(adev, &parser);
1050         if (r)
1051                 goto out;
1052
1053         r = amdgpu_cs_dependencies(adev, &parser);
1054         if (r) {
1055                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1056                 goto out;
1057         }
1058
1059         for (i = 0; i < parser.job->num_ibs; i++)
1060                 trace_amdgpu_cs(&parser, i);
1061
1062         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1063         if (r)
1064                 goto out;
1065
1066         r = amdgpu_cs_submit(&parser, cs);
1067         if (r)
1068                 goto out;
1069
1070         return 0;
1071 out:
1072         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1073         return r;
1074 }
1075
1076 /**
1077  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1078  *
1079  * @dev: drm device
1080  * @data: data from userspace
1081  * @filp: file private
1082  *
1083  * Wait for the command submission identified by handle to finish.
1084  */
1085 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1086                          struct drm_file *filp)
1087 {
1088         union drm_amdgpu_wait_cs *wait = data;
1089         struct amdgpu_device *adev = dev->dev_private;
1090         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1091         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1092         struct amdgpu_ring *ring = NULL;
1093         struct amdgpu_ctx *ctx;
1094         struct dma_fence *fence;
1095         long r;
1096
1097         if (amdgpu_kms_vram_lost(adev, fpriv))
1098                 return -ENODEV;
1099
1100         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1101         if (ctx == NULL)
1102                 return -EINVAL;
1103
1104         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1105                                  wait->in.ip_type, wait->in.ip_instance,
1106                                  wait->in.ring, &ring);
1107         if (r) {
1108                 amdgpu_ctx_put(ctx);
1109                 return r;
1110         }
1111
1112         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1113         if (IS_ERR(fence))
1114                 r = PTR_ERR(fence);
1115         else if (fence) {
1116                 r = dma_fence_wait_timeout(fence, true, timeout);
1117                 dma_fence_put(fence);
1118         } else
1119                 r = 1;
1120
1121         amdgpu_ctx_put(ctx);
1122         if (r < 0)
1123                 return r;
1124
1125         memset(wait, 0, sizeof(*wait));
1126         wait->out.status = (r == 0);
1127
1128         return 0;
1129 }
1130
1131 /**
1132  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1133  *
1134  * @adev: amdgpu device
1135  * @filp: file private
1136  * @user: drm_amdgpu_fence copied from user space
1137  */
1138 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1139                                              struct drm_file *filp,
1140                                              struct drm_amdgpu_fence *user)
1141 {
1142         struct amdgpu_ring *ring;
1143         struct amdgpu_ctx *ctx;
1144         struct dma_fence *fence;
1145         int r;
1146
1147         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1148         if (ctx == NULL)
1149                 return ERR_PTR(-EINVAL);
1150
1151         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1152                                  user->ip_instance, user->ring, &ring);
1153         if (r) {
1154                 amdgpu_ctx_put(ctx);
1155                 return ERR_PTR(r);
1156         }
1157
1158         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1159         amdgpu_ctx_put(ctx);
1160
1161         return fence;
1162 }
1163
1164 /**
1165  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1166  *
1167  * @adev: amdgpu device
1168  * @filp: file private
1169  * @wait: wait parameters
1170  * @fences: array of drm_amdgpu_fence
1171  */
1172 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1173                                      struct drm_file *filp,
1174                                      union drm_amdgpu_wait_fences *wait,
1175                                      struct drm_amdgpu_fence *fences)
1176 {
1177         uint32_t fence_count = wait->in.fence_count;
1178         unsigned int i;
1179         long r = 1;
1180
1181         for (i = 0; i < fence_count; i++) {
1182                 struct dma_fence *fence;
1183                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1184
1185                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1186                 if (IS_ERR(fence))
1187                         return PTR_ERR(fence);
1188                 else if (!fence)
1189                         continue;
1190
1191                 r = dma_fence_wait_timeout(fence, true, timeout);
1192                 dma_fence_put(fence);
1193                 if (r < 0)
1194                         return r;
1195
1196                 if (r == 0)
1197                         break;
1198         }
1199
1200         memset(wait, 0, sizeof(*wait));
1201         wait->out.status = (r > 0);
1202
1203         return 0;
1204 }
1205
1206 /**
1207  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1208  *
1209  * @adev: amdgpu device
1210  * @filp: file private
1211  * @wait: wait parameters
1212  * @fences: array of drm_amdgpu_fence
1213  */
1214 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1215                                     struct drm_file *filp,
1216                                     union drm_amdgpu_wait_fences *wait,
1217                                     struct drm_amdgpu_fence *fences)
1218 {
1219         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1220         uint32_t fence_count = wait->in.fence_count;
1221         uint32_t first = ~0;
1222         struct dma_fence **array;
1223         unsigned int i;
1224         long r;
1225
1226         /* Prepare the fence array */
1227         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1228
1229         if (array == NULL)
1230                 return -ENOMEM;
1231
1232         for (i = 0; i < fence_count; i++) {
1233                 struct dma_fence *fence;
1234
1235                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1236                 if (IS_ERR(fence)) {
1237                         r = PTR_ERR(fence);
1238                         goto err_free_fence_array;
1239                 } else if (fence) {
1240                         array[i] = fence;
1241                 } else { /* NULL, the fence has been already signaled */
1242                         r = 1;
1243                         goto out;
1244                 }
1245         }
1246
1247         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1248                                        &first);
1249         if (r < 0)
1250                 goto err_free_fence_array;
1251
1252 out:
1253         memset(wait, 0, sizeof(*wait));
1254         wait->out.status = (r > 0);
1255         wait->out.first_signaled = first;
1256         /* set return value 0 to indicate success */
1257         r = 0;
1258
1259 err_free_fence_array:
1260         for (i = 0; i < fence_count; i++)
1261                 dma_fence_put(array[i]);
1262         kfree(array);
1263
1264         return r;
1265 }
1266
1267 /**
1268  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1269  *
1270  * @dev: drm device
1271  * @data: data from userspace
1272  * @filp: file private
1273  */
1274 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1275                                 struct drm_file *filp)
1276 {
1277         struct amdgpu_device *adev = dev->dev_private;
1278         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1279         union drm_amdgpu_wait_fences *wait = data;
1280         uint32_t fence_count = wait->in.fence_count;
1281         struct drm_amdgpu_fence *fences_user;
1282         struct drm_amdgpu_fence *fences;
1283         int r;
1284
1285         if (amdgpu_kms_vram_lost(adev, fpriv))
1286                 return -ENODEV;
1287         /* Get the fences from userspace */
1288         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1289                         GFP_KERNEL);
1290         if (fences == NULL)
1291                 return -ENOMEM;
1292
1293         fences_user = (void __user *)(uintptr_t)(wait->in.fences);
1294         if (copy_from_user(fences, fences_user,
1295                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1296                 r = -EFAULT;
1297                 goto err_free_fences;
1298         }
1299
1300         if (wait->in.wait_all)
1301                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1302         else
1303                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1304
1305 err_free_fences:
1306         kfree(fences);
1307
1308         return r;
1309 }
1310
1311 /**
1312  * amdgpu_cs_find_bo_va - find bo_va for VM address
1313  *
1314  * @parser: command submission parser context
1315  * @addr: VM address
1316  * @bo: resulting BO of the mapping found
1317  *
1318  * Search the buffer objects in the command submission context for a certain
1319  * virtual memory address. Returns allocation structure when found, NULL
1320  * otherwise.
1321  */
1322 struct amdgpu_bo_va_mapping *
1323 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1324                        uint64_t addr, struct amdgpu_bo **bo)
1325 {
1326         struct amdgpu_bo_va_mapping *mapping;
1327         unsigned i;
1328
1329         if (!parser->bo_list)
1330                 return NULL;
1331
1332         addr /= AMDGPU_GPU_PAGE_SIZE;
1333
1334         for (i = 0; i < parser->bo_list->num_entries; i++) {
1335                 struct amdgpu_bo_list_entry *lobj;
1336
1337                 lobj = &parser->bo_list->array[i];
1338                 if (!lobj->bo_va)
1339                         continue;
1340
1341                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1342                         if (mapping->start > addr ||
1343                             addr > mapping->last)
1344                                 continue;
1345
1346                         *bo = lobj->bo_va->bo;
1347                         return mapping;
1348                 }
1349
1350                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1351                         if (mapping->start > addr ||
1352                             addr > mapping->last)
1353                                 continue;
1354
1355                         *bo = lobj->bo_va->bo;
1356                         return mapping;
1357                 }
1358         }
1359
1360         return NULL;
1361 }
1362
1363 /**
1364  * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1365  *
1366  * @parser: command submission parser context
1367  *
1368  * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1369  */
1370 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1371 {
1372         unsigned i;
1373         int r;
1374
1375         if (!parser->bo_list)
1376                 return 0;
1377
1378         for (i = 0; i < parser->bo_list->num_entries; i++) {
1379                 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1380
1381                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1382                 if (unlikely(r))
1383                         return r;
1384
1385                 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
1386                         continue;
1387
1388                 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1389                 amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
1390                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
1391                 if (unlikely(r))
1392                         return r;
1393         }
1394
1395         return 0;
1396 }