drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/uaccess.h>
  27
  28 #include "dc.h"
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_debugfs.h"
  32 #include "dm_helpers.h"
  33 #include "dmub/dmub_srv.h"
  34 #include "resource.h"
  35 #include "dsc.h"
  36 #include "dc_link_dp.h"
  37 #include "link_hwss.h"
  38 #include "dc/dc_dmub_srv.h"
  39
  40 struct dmub_debugfs_trace_header {
  41         uint32_t entry_count;
  42         uint32_t reserved[3];
  43 };
  44
  45 struct dmub_debugfs_trace_entry {
  46         uint32_t trace_code;
  47         uint32_t tick_count;
  48         uint32_t param0;
  49         uint32_t param1;
  50 };
  51
  52 static inline const char *yesno(bool v)
  53 {
  54         return v ? "yes" : "no";
  55 }
  56
  57 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  58  *
  59  * Function takes in attributes passed to debugfs write entry
  60  * and writes into param array.
  61  * The user passes max_param_num to identify maximum number of
  62  * parameters that could be parsed.
  63  *
  64  */
  65 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  66                                           long *param, const char __user *buf,
  67                                           int max_param_num,
  68                                           uint8_t *param_nums)
  69 {
  70         char *wr_buf_ptr = NULL;
  71         uint32_t wr_buf_count = 0;
  72         int r;
  73         char *sub_str = NULL;
  74         const char delimiter[3] = {' ', '\n', '\0'};
  75         uint8_t param_index = 0;
  76
  77         *param_nums = 0;
  78
  79         wr_buf_ptr = wr_buf;
  80
  81         r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
  82
  83                 /* r is bytes not be copied */
  84         if (r >= wr_buf_size) {
  85                 DRM_DEBUG_DRIVER("user data not be read\n");
  86                 return -EINVAL;
  87         }
  88
  89         /* check number of parameters. isspace could not differ space and \n */
  90         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  91                 /* skip space*/
  92                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  93                         wr_buf_ptr++;
  94                         wr_buf_count++;
  95                         }
  96
  97                 if (wr_buf_count == wr_buf_size)
  98                         break;
  99
 100                 /* skip non-space*/
 101                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 102                         wr_buf_ptr++;
 103                         wr_buf_count++;
 104                 }
 105
 106                 (*param_nums)++;
 107
 108                 if (wr_buf_count == wr_buf_size)
 109                         break;
 110         }
 111
 112         if (*param_nums > max_param_num)
 113                 *param_nums = max_param_num;
 114
 115         wr_buf_ptr = wr_buf; /* reset buf pointer */
 116         wr_buf_count = 0; /* number of char already checked */
 117
 118         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 119                 wr_buf_ptr++;
 120                 wr_buf_count++;
 121         }
 122
 123         while (param_index < *param_nums) {
 124                 /* after strsep, wr_buf_ptr will be moved to after space */
 125                 sub_str = strsep(&wr_buf_ptr, delimiter);
 126
 127                 r = kstrtol(sub_str, 16, &(param[param_index]));
 128
 129                 if (r)
 130                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 131
 132                 param_index++;
 133         }
 134
 135         return 0;
 136 }
 137
 138 /* function description
 139  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 140  *
 141  * valid lane count value: 1, 2, 4
 142  * valid link rate value:
 143  * 06h = 1.62Gbps per lane
 144  * 0Ah = 2.7Gbps per lane
 145  * 0Ch = 3.24Gbps per lane
 146  * 14h = 5.4Gbps per lane
 147  * 1Eh = 8.1Gbps per lane
 148  *
 149  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 150  *
 151  * --- to get dp configuration
 152  *
 153  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 154  *
 155  * It will list current, verified, reported, preferred dp configuration.
 156  * current -- for current video mode
 157  * verified --- maximum configuration which pass link training
 158  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 159  * preferred --- user force settings
 160  *
 161  * --- set (or force) dp configuration
 162  *
 163  * echo <lane_count>  <link_rate> > link_settings
 164  *
 165  * for example, to force to  2 lane, 2.7GHz,
 166  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 167  *
 168  * spread_spectrum could not be changed dynamically.
 169  *
 170  * in case invalid lane count, link rate are force, no hw programming will be
 171  * done. please check link settings after force operation to see if HW get
 172  * programming.
 173  *
 174  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 175  *
 176  * check current and preferred settings.
 177  *
 178  */
 179 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 180                                  size_t size, loff_t *pos)
 181 {
 182         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 183         struct dc_link *link = connector->dc_link;
 184         char *rd_buf = NULL;
 185         char *rd_buf_ptr = NULL;
 186         const uint32_t rd_buf_size = 100;
 187         uint32_t result = 0;
 188         uint8_t str_len = 0;
 189         int r;
 190
 191         if (*pos & 3 || size & 3)
 192                 return -EINVAL;
 193
 194         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 195         if (!rd_buf)
 196                 return 0;
 197
 198         rd_buf_ptr = rd_buf;
 199
 200         str_len = strlen("Current:  %d  0x%x  %d  ");
 201         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 202                         link->cur_link_settings.lane_count,
 203                         link->cur_link_settings.link_rate,
 204                         link->cur_link_settings.link_spread);
 205         rd_buf_ptr += str_len;
 206
 207         str_len = strlen("Verified:  %d  0x%x  %d  ");
 208         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 209                         link->verified_link_cap.lane_count,
 210                         link->verified_link_cap.link_rate,
 211                         link->verified_link_cap.link_spread);
 212         rd_buf_ptr += str_len;
 213
 214         str_len = strlen("Reported:  %d  0x%x  %d  ");
 215         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 216                         link->reported_link_cap.lane_count,
 217                         link->reported_link_cap.link_rate,
 218                         link->reported_link_cap.link_spread);
 219         rd_buf_ptr += str_len;
 220
 221         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 222         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 223                         link->preferred_link_setting.lane_count,
 224                         link->preferred_link_setting.link_rate,
 225                         link->preferred_link_setting.link_spread);
 226
 227         while (size) {
 228                 if (*pos >= rd_buf_size)
 229                         break;
 230
 231                 r = put_user(*(rd_buf + result), buf);
 232                 if (r)
 233                         return r; /* r = -EFAULT */
 234
 235                 buf += 1;
 236                 size -= 1;
 237                 *pos += 1;
 238                 result += 1;
 239         }
 240
 241         kfree(rd_buf);
 242         return result;
 243 }
 244
 245 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 246                                  size_t size, loff_t *pos)
 247 {
 248         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 249         struct dc_link *link = connector->dc_link;
 250         struct dc *dc = (struct dc *)link->dc;
 251         struct dc_link_settings prefer_link_settings;
 252         char *wr_buf = NULL;
 253         const uint32_t wr_buf_size = 40;
 254         /* 0: lane_count; 1: link_rate */
 255         int max_param_num = 2;
 256         uint8_t param_nums = 0;
 257         long param[2];
 258         bool valid_input = true;
 259
 260         if (size == 0)
 261                 return -EINVAL;
 262
 263         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 264         if (!wr_buf)
 265                 return -ENOSPC;
 266
 267         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 268                                            (long *)param, buf,
 269                                            max_param_num,
 270                                            &param_nums)) {
 271                 kfree(wr_buf);
 272                 return -EINVAL;
 273         }
 274
 275         if (param_nums <= 0) {
 276                 kfree(wr_buf);
 277                 DRM_DEBUG_DRIVER("user data not be read\n");
 278                 return -EINVAL;
 279         }
 280
 281         switch (param[0]) {
 282         case LANE_COUNT_ONE:
 283         case LANE_COUNT_TWO:
 284         case LANE_COUNT_FOUR:
 285                 break;
 286         default:
 287                 valid_input = false;
 288                 break;
 289         }
 290
 291         switch (param[1]) {
 292         case LINK_RATE_LOW:
 293         case LINK_RATE_HIGH:
 294         case LINK_RATE_RBR2:
 295         case LINK_RATE_HIGH2:
 296         case LINK_RATE_HIGH3:
 297 #if defined(CONFIG_DRM_AMD_DC_DCN)
 298         case LINK_RATE_UHBR10:
 299 #endif
 300                 break;
 301         default:
 302                 valid_input = false;
 303                 break;
 304         }
 305
 306         if (!valid_input) {
 307                 kfree(wr_buf);
 308                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 309                 return size;
 310         }
 311
 312         /* save user force lane_count, link_rate to preferred settings
 313          * spread spectrum will not be changed
 314          */
 315         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 316         prefer_link_settings.use_link_rate_set = false;
 317         prefer_link_settings.lane_count = param[0];
 318         prefer_link_settings.link_rate = param[1];
 319
 320         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
 321
 322         kfree(wr_buf);
 323         return size;
 324 }
 325
 326 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 327  * post-cursor2 (defined by VESA DP specification)
 328  *
 329  * valid values
 330  * voltage swing: 0,1,2,3
 331  * pre-emphasis : 0,1,2,3
 332  * post cursor2 : 0,1,2,3
 333  *
 334  *
 335  * how to use this debugfs
 336  *
 337  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 338  *
 339  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 340  *
 341  * To figure out which DP-x is the display for DP to be check,
 342  * cd DP-x
 343  * ls -ll
 344  * There should be debugfs file, like link_settings, phy_settings.
 345  * cat link_settings
 346  * from lane_count, link_rate to figure which DP-x is for display to be worked
 347  * on
 348  *
 349  * To get current DP PHY settings,
 350  * cat phy_settings
 351  *
 352  * To change DP PHY settings,
 353  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 354  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 355  * 0,
 356  * echo 2 3 0 > phy_settings
 357  *
 358  * To check if change be applied, get current phy settings by
 359  * cat phy_settings
 360  *
 361  * In case invalid values are set by user, like
 362  * echo 1 4 0 > phy_settings
 363  *
 364  * HW will NOT be programmed by these settings.
 365  * cat phy_settings will show the previous valid settings.
 366  */
 367 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 368                                  size_t size, loff_t *pos)
 369 {
 370         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 371         struct dc_link *link = connector->dc_link;
 372         char *rd_buf = NULL;
 373         const uint32_t rd_buf_size = 20;
 374         uint32_t result = 0;
 375         int r;
 376
 377         if (*pos & 3 || size & 3)
 378                 return -EINVAL;
 379
 380         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 381         if (!rd_buf)
 382                 return -EINVAL;
 383
 384         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 385                         link->cur_lane_setting[0].VOLTAGE_SWING,
 386                         link->cur_lane_setting[0].PRE_EMPHASIS,
 387                         link->cur_lane_setting[0].POST_CURSOR2);
 388
 389         while (size) {
 390                 if (*pos >= rd_buf_size)
 391                         break;
 392
 393                 r = put_user((*(rd_buf + result)), buf);
 394                 if (r)
 395                         return r; /* r = -EFAULT */
 396
 397                 buf += 1;
 398                 size -= 1;
 399                 *pos += 1;
 400                 result += 1;
 401         }
 402
 403         kfree(rd_buf);
 404         return result;
 405 }
 406
 407 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 408 {
 409         char *data;
 410         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 411         struct dc_link *link = connector->dc_link;
 412         uint32_t read_size = 1;
 413         uint8_t repeater_count = 0;
 414
 415         data = kzalloc(read_size, GFP_KERNEL);
 416         if (!data)
 417                 return 0;
 418
 419         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 420
 421         switch ((uint8_t)*data) {
 422         case 0x80:
 423                 repeater_count = 1;
 424                 break;
 425         case 0x40:
 426                 repeater_count = 2;
 427                 break;
 428         case 0x20:
 429                 repeater_count = 3;
 430                 break;
 431         case 0x10:
 432                 repeater_count = 4;
 433                 break;
 434         case 0x8:
 435                 repeater_count = 5;
 436                 break;
 437         case 0x4:
 438                 repeater_count = 6;
 439                 break;
 440         case 0x2:
 441                 repeater_count = 7;
 442                 break;
 443         case 0x1:
 444                 repeater_count = 8;
 445                 break;
 446         case 0x0:
 447                 repeater_count = 0;
 448                 break;
 449         default:
 450                 repeater_count = (uint8_t)*data;
 451                 break;
 452         }
 453
 454         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 455
 456         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 457
 458         if ((uint8_t)*data == 0x55)
 459                 seq_printf(m, "phy repeater mode: transparent\n");
 460         else if ((uint8_t)*data == 0xAA)
 461                 seq_printf(m, "phy repeater mode: non-transparent\n");
 462         else if ((uint8_t)*data == 0x00)
 463                 seq_printf(m, "phy repeater mode: non lttpr\n");
 464         else
 465                 seq_printf(m, "phy repeater mode: read error\n");
 466
 467         kfree(data);
 468         return 0;
 469 }
 470
 471 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 472                                  size_t size, loff_t *pos)
 473 {
 474         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 475         struct dc_link *link = connector->dc_link;
 476         struct dc *dc = (struct dc *)link->dc;
 477         char *wr_buf = NULL;
 478         uint32_t wr_buf_size = 40;
 479         long param[3];
 480         bool use_prefer_link_setting;
 481         struct link_training_settings link_lane_settings;
 482         int max_param_num = 3;
 483         uint8_t param_nums = 0;
 484         int r = 0;
 485
 486
 487         if (size == 0)
 488                 return -EINVAL;
 489
 490         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 491         if (!wr_buf)
 492                 return -ENOSPC;
 493
 494         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 495                                            (long *)param, buf,
 496                                            max_param_num,
 497                                            &param_nums)) {
 498                 kfree(wr_buf);
 499                 return -EINVAL;
 500         }
 501
 502         if (param_nums <= 0) {
 503                 kfree(wr_buf);
 504                 DRM_DEBUG_DRIVER("user data not be read\n");
 505                 return -EINVAL;
 506         }
 507
 508         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 509                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 510                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 511                 kfree(wr_buf);
 512                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 513                 return size;
 514         }
 515
 516         /* get link settings: lane count, link rate */
 517         use_prefer_link_setting =
 518                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 519                 (link->test_pattern_enabled));
 520
 521         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 522
 523         if (use_prefer_link_setting) {
 524                 link_lane_settings.link_settings.lane_count =
 525                                 link->preferred_link_setting.lane_count;
 526                 link_lane_settings.link_settings.link_rate =
 527                                 link->preferred_link_setting.link_rate;
 528                 link_lane_settings.link_settings.link_spread =
 529                                 link->preferred_link_setting.link_spread;
 530         } else {
 531                 link_lane_settings.link_settings.lane_count =
 532                                 link->cur_link_settings.lane_count;
 533                 link_lane_settings.link_settings.link_rate =
 534                                 link->cur_link_settings.link_rate;
 535                 link_lane_settings.link_settings.link_spread =
 536                                 link->cur_link_settings.link_spread;
 537         }
 538
 539         /* apply phy settings from user */
 540         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 541                 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
 542                                 (enum dc_voltage_swing) (param[0]);
 543                 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
 544                                 (enum dc_pre_emphasis) (param[1]);
 545                 link_lane_settings.lane_settings[r].POST_CURSOR2 =
 546                                 (enum dc_post_cursor2) (param[2]);
 547         }
 548
 549         /* program ASIC registers and DPCD registers */
 550         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 551
 552         kfree(wr_buf);
 553         return size;
 554 }
 555
 556 /* function description
 557  *
 558  * set PHY layer or Link layer test pattern
 559  * PHY test pattern is used for PHY SI check.
 560  * Link layer test will not affect PHY SI.
 561  *
 562  * Reset Test Pattern:
 563  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 564  *
 565  * PHY test pattern supported:
 566  * 1 = DP_TEST_PATTERN_D102
 567  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 568  * 3 = DP_TEST_PATTERN_PRBS7
 569  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 570  * 5 = DP_TEST_PATTERN_CP2520_1
 571  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 572  * 7 = DP_TEST_PATTERN_CP2520_3
 573  *
 574  * DP PHY Link Training Patterns
 575  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 576  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 577  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 578  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 579  *
 580  * DP Link Layer Test pattern
 581  * c = DP_TEST_PATTERN_COLOR_SQUARES
 582  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 583  * e = DP_TEST_PATTERN_VERTICAL_BARS
 584  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 585  * 10= DP_TEST_PATTERN_COLOR_RAMP
 586  *
 587  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 588  *
 589  * --- set test pattern
 590  * echo <test pattern #> > test_pattern
 591  *
 592  * If test pattern # is not supported, NO HW programming will be done.
 593  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 594  * for the user pattern. input 10 bytes data are separated by space
 595  *
 596  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 597  *
 598  * --- reset test pattern
 599  * echo 0 > test_pattern
 600  *
 601  * --- HPD detection is disabled when set PHY test pattern
 602  *
 603  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 604  * is disable. User could unplug DP display from DP connected and plug scope to
 605  * check test pattern PHY SI.
 606  * If there is need unplug scope and plug DP display back, do steps below:
 607  * echo 0 > phy_test_pattern
 608  * unplug scope
 609  * plug DP display.
 610  *
 611  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 612  * driver could detect "unplug scope" and "plug DP display"
 613  */
 614 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 615                                  size_t size, loff_t *pos)
 616 {
 617         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 618         struct dc_link *link = connector->dc_link;
 619         char *wr_buf = NULL;
 620         uint32_t wr_buf_size = 100;
 621         long param[11] = {0x0};
 622         int max_param_num = 11;
 623         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 624         bool disable_hpd = false;
 625         bool valid_test_pattern = false;
 626         uint8_t param_nums = 0;
 627         /* init with default 80bit custom pattern */
 628         uint8_t custom_pattern[10] = {
 629                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 630                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 631                         };
 632         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 633                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 634         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 635                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 636         struct link_training_settings link_training_settings;
 637         int i;
 638
 639         if (size == 0)
 640                 return -EINVAL;
 641
 642         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 643         if (!wr_buf)
 644                 return -ENOSPC;
 645
 646         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 647                                            (long *)param, buf,
 648                                            max_param_num,
 649                                            &param_nums)) {
 650                 kfree(wr_buf);
 651                 return -EINVAL;
 652         }
 653
 654         if (param_nums <= 0) {
 655                 kfree(wr_buf);
 656                 DRM_DEBUG_DRIVER("user data not be read\n");
 657                 return -EINVAL;
 658         }
 659
 660
 661         test_pattern = param[0];
 662
 663         switch (test_pattern) {
 664         case DP_TEST_PATTERN_VIDEO_MODE:
 665         case DP_TEST_PATTERN_COLOR_SQUARES:
 666         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 667         case DP_TEST_PATTERN_VERTICAL_BARS:
 668         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 669         case DP_TEST_PATTERN_COLOR_RAMP:
 670                 valid_test_pattern = true;
 671                 break;
 672
 673         case DP_TEST_PATTERN_D102:
 674         case DP_TEST_PATTERN_SYMBOL_ERROR:
 675         case DP_TEST_PATTERN_PRBS7:
 676         case DP_TEST_PATTERN_80BIT_CUSTOM:
 677         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 678         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 679                 disable_hpd = true;
 680                 valid_test_pattern = true;
 681                 break;
 682
 683         default:
 684                 valid_test_pattern = false;
 685                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 686                 break;
 687         }
 688
 689         if (!valid_test_pattern) {
 690                 kfree(wr_buf);
 691                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 692                 return size;
 693         }
 694
 695         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 696                 for (i = 0; i < 10; i++) {
 697                         if ((uint8_t) param[i + 1] != 0x0)
 698                                 break;
 699                 }
 700
 701                 if (i < 10) {
 702                         /* not use default value */
 703                         for (i = 0; i < 10; i++)
 704                                 custom_pattern[i] = (uint8_t) param[i + 1];
 705                 }
 706         }
 707
 708         /* Usage: set DP physical test pattern using debugfs with normal DP
 709          * panel. Then plug out DP panel and connect a scope to measure
 710          * For normal video mode and test pattern generated from CRCT,
 711          * they are visibile to user. So do not disable HPD.
 712          * Video Mode is also set to clear the test pattern, so enable HPD
 713          * because it might have been disabled after a test pattern was set.
 714          * AUX depends on HPD * sequence dependent, do not move!
 715          */
 716         if (!disable_hpd)
 717                 dc_link_enable_hpd(link);
 718
 719         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 720         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 721         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 722
 723         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 724         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 725         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 726
 727         link_training_settings.link_settings = cur_link_settings;
 728
 729
 730         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 731                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 732                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 733                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 734                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 735                         link_training_settings.link_settings = prefer_link_settings;
 736         }
 737
 738         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 739                 link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
 740
 741         dc_link_set_test_pattern(
 742                 link,
 743                 test_pattern,
 744                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 745                 &link_training_settings,
 746                 custom_pattern,
 747                 10);
 748
 749         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 750          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 751          * Need disable interrupt to avoid SW driver disable DP output. This is
 752          * done after the test pattern is set.
 753          */
 754         if (valid_test_pattern && disable_hpd)
 755                 dc_link_disable_hpd(link);
 756
 757         kfree(wr_buf);
 758
 759         return size;
 760 }
 761
 762 /*
 763  * Returns the DMCUB tracebuffer contents.
 764  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 765  */
 766 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 767 {
 768         struct amdgpu_device *adev = m->private;
 769         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 770         struct dmub_debugfs_trace_entry *entries;
 771         uint8_t *tbuf_base;
 772         uint32_t tbuf_size, max_entries, num_entries, i;
 773
 774         if (!fb_info)
 775                 return 0;
 776
 777         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 778         if (!tbuf_base)
 779                 return 0;
 780
 781         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 782         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 783                       sizeof(struct dmub_debugfs_trace_entry);
 784
 785         num_entries =
 786                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 787
 788         num_entries = min(num_entries, max_entries);
 789
 790         entries = (struct dmub_debugfs_trace_entry
 791                            *)(tbuf_base +
 792                               sizeof(struct dmub_debugfs_trace_header));
 793
 794         for (i = 0; i < num_entries; ++i) {
 795                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 796
 797                 seq_printf(m,
 798                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 799                            entry->trace_code, entry->tick_count, entry->param0,
 800                            entry->param1);
 801         }
 802
 803         return 0;
 804 }
 805
 806 /*
 807  * Returns the DMCUB firmware state contents.
 808  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 809  */
 810 static int dmub_fw_state_show(struct seq_file *m, void *data)
 811 {
 812         struct amdgpu_device *adev = m->private;
 813         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 814         uint8_t *state_base;
 815         uint32_t state_size;
 816
 817         if (!fb_info)
 818                 return 0;
 819
 820         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 821         if (!state_base)
 822                 return 0;
 823
 824         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 825
 826         return seq_write(m, state_base, state_size);
 827 }
 828
 829 /*
 830  * Returns the current and maximum output bpc for the connector.
 831  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
 832  */
 833 static int output_bpc_show(struct seq_file *m, void *data)
 834 {
 835         struct drm_connector *connector = m->private;
 836         struct drm_device *dev = connector->dev;
 837         struct drm_crtc *crtc = NULL;
 838         struct dm_crtc_state *dm_crtc_state = NULL;
 839         int res = -ENODEV;
 840         unsigned int bpc;
 841
 842         mutex_lock(&dev->mode_config.mutex);
 843         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 844
 845         if (connector->state == NULL)
 846                 goto unlock;
 847
 848         crtc = connector->state->crtc;
 849         if (crtc == NULL)
 850                 goto unlock;
 851
 852         drm_modeset_lock(&crtc->mutex, NULL);
 853         if (crtc->state == NULL)
 854                 goto unlock;
 855
 856         dm_crtc_state = to_dm_crtc_state(crtc->state);
 857         if (dm_crtc_state->stream == NULL)
 858                 goto unlock;
 859
 860         switch (dm_crtc_state->stream->timing.display_color_depth) {
 861         case COLOR_DEPTH_666:
 862                 bpc = 6;
 863                 break;
 864         case COLOR_DEPTH_888:
 865                 bpc = 8;
 866                 break;
 867         case COLOR_DEPTH_101010:
 868                 bpc = 10;
 869                 break;
 870         case COLOR_DEPTH_121212:
 871                 bpc = 12;
 872                 break;
 873         case COLOR_DEPTH_161616:
 874                 bpc = 16;
 875                 break;
 876         default:
 877                 goto unlock;
 878         }
 879
 880         seq_printf(m, "Current: %u\n", bpc);
 881         seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 882         res = 0;
 883
 884 unlock:
 885         if (crtc)
 886                 drm_modeset_unlock(&crtc->mutex);
 887
 888         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 889         mutex_unlock(&dev->mode_config.mutex);
 890
 891         return res;
 892 }
 893
 894 /*
 895  * Example usage:
 896  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 897  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 898  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 899  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 900  */
 901 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 902                                  size_t size, loff_t *pos)
 903 {
 904         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 905         char *wr_buf = NULL;
 906         uint32_t wr_buf_size = 42;
 907         int max_param_num = 1;
 908         long param;
 909         uint8_t param_nums = 0;
 910
 911         if (size == 0)
 912                 return -EINVAL;
 913
 914         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 915
 916         if (!wr_buf) {
 917                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 918                 return -ENOSPC;
 919         }
 920
 921         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 922                                            &param, buf,
 923                                            max_param_num,
 924                                            &param_nums)) {
 925                 kfree(wr_buf);
 926                 return -EINVAL;
 927         }
 928
 929         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 930
 931         kfree(wr_buf);
 932         return 0;
 933 }
 934
 935 #ifdef CONFIG_DRM_AMD_DC_HDCP
 936 /*
 937  * Returns the HDCP capability of the Display (1.4 for now).
 938  *
 939  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 940  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 941  *
 942  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 943  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 944  */
 945 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 946 {
 947         struct drm_connector *connector = m->private;
 948         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 949         bool hdcp_cap, hdcp2_cap;
 950
 951         if (connector->status != connector_status_connected)
 952                 return -ENODEV;
 953
 954         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 955
 956         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 957         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 958
 959
 960         if (hdcp_cap)
 961                 seq_printf(m, "%s ", "HDCP1.4");
 962         if (hdcp2_cap)
 963                 seq_printf(m, "%s ", "HDCP2.2");
 964
 965         if (!hdcp_cap && !hdcp2_cap)
 966                 seq_printf(m, "%s ", "None");
 967
 968         seq_puts(m, "\n");
 969
 970         return 0;
 971 }
 972 #endif
 973
 974 /*
 975  * Returns whether the connected display is internal and not hotpluggable.
 976  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
 977  */
 978 static int internal_display_show(struct seq_file *m, void *data)
 979 {
 980         struct drm_connector *connector = m->private;
 981         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 982         struct dc_link *link = aconnector->dc_link;
 983
 984         seq_printf(m, "Internal: %u\n", link->is_internal_display);
 985
 986         return 0;
 987 }
 988
 989 /* function description
 990  *
 991  * generic SDP message access for testing
 992  *
 993  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
 994  *
 995  * SDP header
 996  * Hb0 : Secondary-Data Packet ID
 997  * Hb1 : Secondary-Data Packet type
 998  * Hb2 : Secondary-Data-packet-specific header, Byte 0
 999  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1000  *
1001  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1002  */
1003 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1004                                  size_t size, loff_t *pos)
1005 {
1006         int r;
1007         uint8_t data[36];
1008         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1009         struct dm_crtc_state *acrtc_state;
1010         uint32_t write_size = 36;
1011
1012         if (connector->base.status != connector_status_connected)
1013                 return -ENODEV;
1014
1015         if (size == 0)
1016                 return 0;
1017
1018         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1019
1020         r = copy_from_user(data, buf, write_size);
1021
1022         write_size -= r;
1023
1024         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1025
1026         return write_size;
1027 }
1028
1029 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1030                                  size_t size, loff_t *pos)
1031 {
1032         int r;
1033         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1034
1035         if (size < sizeof(connector->debugfs_dpcd_address))
1036                 return -EINVAL;
1037
1038         r = copy_from_user(&connector->debugfs_dpcd_address,
1039                         buf, sizeof(connector->debugfs_dpcd_address));
1040
1041         return size - r;
1042 }
1043
1044 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1045                                  size_t size, loff_t *pos)
1046 {
1047         int r;
1048         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1049
1050         if (size < sizeof(connector->debugfs_dpcd_size))
1051                 return -EINVAL;
1052
1053         r = copy_from_user(&connector->debugfs_dpcd_size,
1054                         buf, sizeof(connector->debugfs_dpcd_size));
1055
1056         if (connector->debugfs_dpcd_size > 256)
1057                 connector->debugfs_dpcd_size = 0;
1058
1059         return size - r;
1060 }
1061
1062 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1063                                  size_t size, loff_t *pos)
1064 {
1065         int r;
1066         char *data;
1067         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1068         struct dc_link *link = connector->dc_link;
1069         uint32_t write_size = connector->debugfs_dpcd_size;
1070
1071         if (!write_size || size < write_size)
1072                 return -EINVAL;
1073
1074         data = kzalloc(write_size, GFP_KERNEL);
1075         if (!data)
1076                 return 0;
1077
1078         r = copy_from_user(data, buf, write_size);
1079
1080         dm_helpers_dp_write_dpcd(link->ctx, link,
1081                         connector->debugfs_dpcd_address, data, write_size - r);
1082         kfree(data);
1083         return write_size - r;
1084 }
1085
1086 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1087                                  size_t size, loff_t *pos)
1088 {
1089         int r;
1090         char *data;
1091         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1092         struct dc_link *link = connector->dc_link;
1093         uint32_t read_size = connector->debugfs_dpcd_size;
1094
1095         if (!read_size || size < read_size)
1096                 return 0;
1097
1098         data = kzalloc(read_size, GFP_KERNEL);
1099         if (!data)
1100                 return 0;
1101
1102         dm_helpers_dp_read_dpcd(link->ctx, link,
1103                         connector->debugfs_dpcd_address, data, read_size);
1104
1105         r = copy_to_user(buf, data, read_size);
1106
1107         kfree(data);
1108         return read_size - r;
1109 }
1110
1111 /* function: Read link's DSC & FEC capabilities
1112  *
1113  *
1114  * Access it with the following command (you need to specify
1115  * connector like DP-1):
1116  *
1117  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1118  *
1119  */
1120 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1121 {
1122         struct drm_connector *connector = m->private;
1123         struct drm_modeset_acquire_ctx ctx;
1124         struct drm_device *dev = connector->dev;
1125         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1126         int ret = 0;
1127         bool try_again = false;
1128         bool is_fec_supported = false;
1129         bool is_dsc_supported = false;
1130         struct dpcd_caps dpcd_caps;
1131
1132         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1133         do {
1134                 try_again = false;
1135                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1136                 if (ret) {
1137                         if (ret == -EDEADLK) {
1138                                 ret = drm_modeset_backoff(&ctx);
1139                                 if (!ret) {
1140                                         try_again = true;
1141                                         continue;
1142                                 }
1143                         }
1144                         break;
1145                 }
1146                 if (connector->status != connector_status_connected) {
1147                         ret = -ENODEV;
1148                         break;
1149                 }
1150                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1151                 if (aconnector->port) {
1152                         /* aconnector sets dsc_aux during get_modes call
1153                          * if MST connector has it means it can either
1154                          * enable DSC on the sink device or on MST branch
1155                          * its connected to.
1156                          */
1157                         if (aconnector->dsc_aux) {
1158                                 is_fec_supported = true;
1159                                 is_dsc_supported = true;
1160                         }
1161                 } else {
1162                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1163                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1164                 }
1165         } while (try_again);
1166
1167         drm_modeset_drop_locks(&ctx);
1168         drm_modeset_acquire_fini(&ctx);
1169
1170         seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported));
1171         seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported));
1172
1173         return ret;
1174 }
1175
1176 /* function: Trigger virtual HPD redetection on connector
1177  *
1178  * This function will perform link rediscovery, link disable
1179  * and enable, and dm connector state update.
1180  *
1181  * Retrigger HPD on an existing connector by echoing 1 into
1182  * its respectful "trigger_hotplug" debugfs entry:
1183  *
1184  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1185  *
1186  * This function can perform HPD unplug:
1187  *
1188  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1189  *
1190  */
1191 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1192                                                         size_t size, loff_t *pos)
1193 {
1194         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1195         struct drm_connector *connector = &aconnector->base;
1196         struct dc_link *link = NULL;
1197         struct drm_device *dev = connector->dev;
1198         enum dc_connection_type new_connection_type = dc_connection_none;
1199         char *wr_buf = NULL;
1200         uint32_t wr_buf_size = 42;
1201         int max_param_num = 1;
1202         long param[1] = {0};
1203         uint8_t param_nums = 0;
1204
1205         if (!aconnector || !aconnector->dc_link)
1206                 return -EINVAL;
1207
1208         if (size == 0)
1209                 return -EINVAL;
1210
1211         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1212
1213         if (!wr_buf) {
1214                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1215                 return -ENOSPC;
1216         }
1217
1218         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1219                                                 (long *)param, buf,
1220                                                 max_param_num,
1221                                                 &param_nums)) {
1222                 kfree(wr_buf);
1223                 return -EINVAL;
1224         }
1225
1226         if (param_nums <= 0) {
1227                 DRM_DEBUG_DRIVER("user data not be read\n");
1228                 kfree(wr_buf);
1229                 return -EINVAL;
1230         }
1231
1232         if (param[0] == 1) {
1233                 mutex_lock(&aconnector->hpd_lock);
1234
1235                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1236                         new_connection_type != dc_connection_none)
1237                         goto unlock;
1238
1239                 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD))
1240                         goto unlock;
1241
1242                 amdgpu_dm_update_connector_after_detect(aconnector);
1243
1244                 drm_modeset_lock_all(dev);
1245                 dm_restore_drm_connector_state(dev, connector);
1246                 drm_modeset_unlock_all(dev);
1247
1248                 drm_kms_helper_hotplug_event(dev);
1249         } else if (param[0] == 0) {
1250                 if (!aconnector->dc_link)
1251                         goto unlock;
1252
1253                 link = aconnector->dc_link;
1254
1255                 if (link->local_sink) {
1256                         dc_sink_release(link->local_sink);
1257                         link->local_sink = NULL;
1258                 }
1259
1260                 link->dpcd_sink_count = 0;
1261                 link->type = dc_connection_none;
1262                 link->dongle_max_pix_clk = 0;
1263
1264                 amdgpu_dm_update_connector_after_detect(aconnector);
1265
1266                 drm_modeset_lock_all(dev);
1267                 dm_restore_drm_connector_state(dev, connector);
1268                 drm_modeset_unlock_all(dev);
1269
1270                 drm_kms_helper_hotplug_event(dev);
1271         }
1272
1273 unlock:
1274         mutex_unlock(&aconnector->hpd_lock);
1275
1276         kfree(wr_buf);
1277         return size;
1278 }
1279
1280 /* function: read DSC status on the connector
1281  *
1282  * The read function: dp_dsc_clock_en_read
1283  * returns current status of DSC clock on the connector.
1284  * The return is a boolean flag: 1 or 0.
1285  *
1286  * Access it with the following command (you need to specify
1287  * connector like DP-1):
1288  *
1289  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1290  *
1291  * Expected output:
1292  * 1 - means that DSC is currently enabled
1293  * 0 - means that DSC is disabled
1294  */
1295 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1296                                     size_t size, loff_t *pos)
1297 {
1298         char *rd_buf = NULL;
1299         char *rd_buf_ptr = NULL;
1300         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1301         struct display_stream_compressor *dsc;
1302         struct dcn_dsc_state dsc_state = {0};
1303         const uint32_t rd_buf_size = 10;
1304         struct pipe_ctx *pipe_ctx;
1305         ssize_t result = 0;
1306         int i, r, str_len = 30;
1307
1308         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1309
1310         if (!rd_buf)
1311                 return -ENOMEM;
1312
1313         rd_buf_ptr = rd_buf;
1314
1315         for (i = 0; i < MAX_PIPES; i++) {
1316                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1317                         if (pipe_ctx && pipe_ctx->stream &&
1318                             pipe_ctx->stream->link == aconnector->dc_link)
1319                                 break;
1320         }
1321
1322         if (!pipe_ctx)
1323                 return -ENXIO;
1324
1325         dsc = pipe_ctx->stream_res.dsc;
1326         if (dsc)
1327                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1328
1329         snprintf(rd_buf_ptr, str_len,
1330                 "%d\n",
1331                 dsc_state.dsc_clock_en);
1332         rd_buf_ptr += str_len;
1333
1334         while (size) {
1335                 if (*pos >= rd_buf_size)
1336                         break;
1337
1338                 r = put_user(*(rd_buf + result), buf);
1339                 if (r)
1340                         return r; /* r = -EFAULT */
1341
1342                 buf += 1;
1343                 size -= 1;
1344                 *pos += 1;
1345                 result += 1;
1346         }
1347
1348         kfree(rd_buf);
1349         return result;
1350 }
1351
1352 /* function: write force DSC on the connector
1353  *
1354  * The write function: dp_dsc_clock_en_write
1355  * enables to force DSC on the connector.
1356  * User can write to either force enable or force disable DSC
1357  * on the next modeset or set it to driver default
1358  *
1359  * Accepted inputs:
1360  * 0 - default DSC enablement policy
1361  * 1 - force enable DSC on the connector
1362  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1363  *
1364  * Writing DSC settings is done with the following command:
1365  * - To force enable DSC (you need to specify
1366  * connector like DP-1):
1367  *
1368  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1369  *
1370  * - To return to default state set the flag to zero and
1371  * let driver deal with DSC automatically
1372  * (you need to specify connector like DP-1):
1373  *
1374  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1375  *
1376  */
1377 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1378                                      size_t size, loff_t *pos)
1379 {
1380         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1381         struct drm_connector *connector = &aconnector->base;
1382         struct drm_device *dev = connector->dev;
1383         struct drm_crtc *crtc = NULL;
1384         struct dm_crtc_state *dm_crtc_state = NULL;
1385         struct pipe_ctx *pipe_ctx;
1386         int i;
1387         char *wr_buf = NULL;
1388         uint32_t wr_buf_size = 42;
1389         int max_param_num = 1;
1390         long param[1] = {0};
1391         uint8_t param_nums = 0;
1392
1393         if (size == 0)
1394                 return -EINVAL;
1395
1396         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1397
1398         if (!wr_buf) {
1399                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1400                 return -ENOSPC;
1401         }
1402
1403         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1404                                             (long *)param, buf,
1405                                             max_param_num,
1406                                             &param_nums)) {
1407                 kfree(wr_buf);
1408                 return -EINVAL;
1409         }
1410
1411         if (param_nums <= 0) {
1412                 DRM_DEBUG_DRIVER("user data not be read\n");
1413                 kfree(wr_buf);
1414                 return -EINVAL;
1415         }
1416
1417         for (i = 0; i < MAX_PIPES; i++) {
1418                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1419                         if (pipe_ctx && pipe_ctx->stream &&
1420                             pipe_ctx->stream->link == aconnector->dc_link)
1421                                 break;
1422         }
1423
1424         if (!pipe_ctx || !pipe_ctx->stream)
1425                 goto done;
1426
1427         // Get CRTC state
1428         mutex_lock(&dev->mode_config.mutex);
1429         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1430
1431         if (connector->state == NULL)
1432                 goto unlock;
1433
1434         crtc = connector->state->crtc;
1435         if (crtc == NULL)
1436                 goto unlock;
1437
1438         drm_modeset_lock(&crtc->mutex, NULL);
1439         if (crtc->state == NULL)
1440                 goto unlock;
1441
1442         dm_crtc_state = to_dm_crtc_state(crtc->state);
1443         if (dm_crtc_state->stream == NULL)
1444                 goto unlock;
1445
1446         if (param[0] == 1)
1447                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1448         else if (param[0] == 2)
1449                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1450         else
1451                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1452
1453         dm_crtc_state->dsc_force_changed = true;
1454
1455 unlock:
1456         if (crtc)
1457                 drm_modeset_unlock(&crtc->mutex);
1458         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1459         mutex_unlock(&dev->mode_config.mutex);
1460
1461 done:
1462         kfree(wr_buf);
1463         return size;
1464 }
1465
1466 /* function: read DSC slice width parameter on the connector
1467  *
1468  * The read function: dp_dsc_slice_width_read
1469  * returns dsc slice width used in the current configuration
1470  * The return is an integer: 0 or other positive number
1471  *
1472  * Access the status with the following command:
1473  *
1474  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1475  *
1476  * 0 - means that DSC is disabled
1477  *
1478  * Any other number more than zero represents the
1479  * slice width currently used by DSC in pixels
1480  *
1481  */
1482 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1483                                     size_t size, loff_t *pos)
1484 {
1485         char *rd_buf = NULL;
1486         char *rd_buf_ptr = NULL;
1487         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1488         struct display_stream_compressor *dsc;
1489         struct dcn_dsc_state dsc_state = {0};
1490         const uint32_t rd_buf_size = 100;
1491         struct pipe_ctx *pipe_ctx;
1492         ssize_t result = 0;
1493         int i, r, str_len = 30;
1494
1495         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1496
1497         if (!rd_buf)
1498                 return -ENOMEM;
1499
1500         rd_buf_ptr = rd_buf;
1501
1502         for (i = 0; i < MAX_PIPES; i++) {
1503                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1504                         if (pipe_ctx && pipe_ctx->stream &&
1505                             pipe_ctx->stream->link == aconnector->dc_link)
1506                                 break;
1507         }
1508
1509         if (!pipe_ctx)
1510                 return -ENXIO;
1511
1512         dsc = pipe_ctx->stream_res.dsc;
1513         if (dsc)
1514                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1515
1516         snprintf(rd_buf_ptr, str_len,
1517                 "%d\n",
1518                 dsc_state.dsc_slice_width);
1519         rd_buf_ptr += str_len;
1520
1521         while (size) {
1522                 if (*pos >= rd_buf_size)
1523                         break;
1524
1525                 r = put_user(*(rd_buf + result), buf);
1526                 if (r)
1527                         return r; /* r = -EFAULT */
1528
1529                 buf += 1;
1530                 size -= 1;
1531                 *pos += 1;
1532                 result += 1;
1533         }
1534
1535         kfree(rd_buf);
1536         return result;
1537 }
1538
1539 /* function: write DSC slice width parameter
1540  *
1541  * The write function: dp_dsc_slice_width_write
1542  * overwrites automatically generated DSC configuration
1543  * of slice width.
1544  *
1545  * The user has to write the slice width divisible by the
1546  * picture width.
1547  *
1548  * Also the user has to write width in hexidecimal
1549  * rather than in decimal.
1550  *
1551  * Writing DSC settings is done with the following command:
1552  * - To force overwrite slice width: (example sets to 1920 pixels)
1553  *
1554  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1555  *
1556  *  - To stop overwriting and let driver find the optimal size,
1557  * set the width to zero:
1558  *
1559  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1560  *
1561  */
1562 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1563                                      size_t size, loff_t *pos)
1564 {
1565         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1566         struct pipe_ctx *pipe_ctx;
1567         struct drm_connector *connector = &aconnector->base;
1568         struct drm_device *dev = connector->dev;
1569         struct drm_crtc *crtc = NULL;
1570         struct dm_crtc_state *dm_crtc_state = NULL;
1571         int i;
1572         char *wr_buf = NULL;
1573         uint32_t wr_buf_size = 42;
1574         int max_param_num = 1;
1575         long param[1] = {0};
1576         uint8_t param_nums = 0;
1577
1578         if (size == 0)
1579                 return -EINVAL;
1580
1581         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1582
1583         if (!wr_buf) {
1584                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1585                 return -ENOSPC;
1586         }
1587
1588         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1589                                             (long *)param, buf,
1590                                             max_param_num,
1591                                             &param_nums)) {
1592                 kfree(wr_buf);
1593                 return -EINVAL;
1594         }
1595
1596         if (param_nums <= 0) {
1597                 DRM_DEBUG_DRIVER("user data not be read\n");
1598                 kfree(wr_buf);
1599                 return -EINVAL;
1600         }
1601
1602         for (i = 0; i < MAX_PIPES; i++) {
1603                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1604                         if (pipe_ctx && pipe_ctx->stream &&
1605                             pipe_ctx->stream->link == aconnector->dc_link)
1606                                 break;
1607         }
1608
1609         if (!pipe_ctx || !pipe_ctx->stream)
1610                 goto done;
1611
1612         // Safely get CRTC state
1613         mutex_lock(&dev->mode_config.mutex);
1614         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1615
1616         if (connector->state == NULL)
1617                 goto unlock;
1618
1619         crtc = connector->state->crtc;
1620         if (crtc == NULL)
1621                 goto unlock;
1622
1623         drm_modeset_lock(&crtc->mutex, NULL);
1624         if (crtc->state == NULL)
1625                 goto unlock;
1626
1627         dm_crtc_state = to_dm_crtc_state(crtc->state);
1628         if (dm_crtc_state->stream == NULL)
1629                 goto unlock;
1630
1631         if (param[0] > 0)
1632                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1633                                         pipe_ctx->stream->timing.h_addressable,
1634                                         param[0]);
1635         else
1636                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1637
1638         dm_crtc_state->dsc_force_changed = true;
1639
1640 unlock:
1641         if (crtc)
1642                 drm_modeset_unlock(&crtc->mutex);
1643         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1644         mutex_unlock(&dev->mode_config.mutex);
1645
1646 done:
1647         kfree(wr_buf);
1648         return size;
1649 }
1650
1651 /* function: read DSC slice height parameter on the connector
1652  *
1653  * The read function: dp_dsc_slice_height_read
1654  * returns dsc slice height used in the current configuration
1655  * The return is an integer: 0 or other positive number
1656  *
1657  * Access the status with the following command:
1658  *
1659  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1660  *
1661  * 0 - means that DSC is disabled
1662  *
1663  * Any other number more than zero represents the
1664  * slice height currently used by DSC in pixels
1665  *
1666  */
1667 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1668                                     size_t size, loff_t *pos)
1669 {
1670         char *rd_buf = NULL;
1671         char *rd_buf_ptr = NULL;
1672         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1673         struct display_stream_compressor *dsc;
1674         struct dcn_dsc_state dsc_state = {0};
1675         const uint32_t rd_buf_size = 100;
1676         struct pipe_ctx *pipe_ctx;
1677         ssize_t result = 0;
1678         int i, r, str_len = 30;
1679
1680         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1681
1682         if (!rd_buf)
1683                 return -ENOMEM;
1684
1685         rd_buf_ptr = rd_buf;
1686
1687         for (i = 0; i < MAX_PIPES; i++) {
1688                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1689                         if (pipe_ctx && pipe_ctx->stream &&
1690                             pipe_ctx->stream->link == aconnector->dc_link)
1691                                 break;
1692         }
1693
1694         if (!pipe_ctx)
1695                 return -ENXIO;
1696
1697         dsc = pipe_ctx->stream_res.dsc;
1698         if (dsc)
1699                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1700
1701         snprintf(rd_buf_ptr, str_len,
1702                 "%d\n",
1703                 dsc_state.dsc_slice_height);
1704         rd_buf_ptr += str_len;
1705
1706         while (size) {
1707                 if (*pos >= rd_buf_size)
1708                         break;
1709
1710                 r = put_user(*(rd_buf + result), buf);
1711                 if (r)
1712                         return r; /* r = -EFAULT */
1713
1714                 buf += 1;
1715                 size -= 1;
1716                 *pos += 1;
1717                 result += 1;
1718         }
1719
1720         kfree(rd_buf);
1721         return result;
1722 }
1723
1724 /* function: write DSC slice height parameter
1725  *
1726  * The write function: dp_dsc_slice_height_write
1727  * overwrites automatically generated DSC configuration
1728  * of slice height.
1729  *
1730  * The user has to write the slice height divisible by the
1731  * picture height.
1732  *
1733  * Also the user has to write height in hexidecimal
1734  * rather than in decimal.
1735  *
1736  * Writing DSC settings is done with the following command:
1737  * - To force overwrite slice height (example sets to 128 pixels):
1738  *
1739  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1740  *
1741  *  - To stop overwriting and let driver find the optimal size,
1742  * set the height to zero:
1743  *
1744  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1745  *
1746  */
1747 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1748                                      size_t size, loff_t *pos)
1749 {
1750         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1751         struct drm_connector *connector = &aconnector->base;
1752         struct drm_device *dev = connector->dev;
1753         struct drm_crtc *crtc = NULL;
1754         struct dm_crtc_state *dm_crtc_state = NULL;
1755         struct pipe_ctx *pipe_ctx;
1756         int i;
1757         char *wr_buf = NULL;
1758         uint32_t wr_buf_size = 42;
1759         int max_param_num = 1;
1760         uint8_t param_nums = 0;
1761         long param[1] = {0};
1762
1763         if (size == 0)
1764                 return -EINVAL;
1765
1766         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1767
1768         if (!wr_buf) {
1769                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1770                 return -ENOSPC;
1771         }
1772
1773         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1774                                             (long *)param, buf,
1775                                             max_param_num,
1776                                             &param_nums)) {
1777                 kfree(wr_buf);
1778                 return -EINVAL;
1779         }
1780
1781         if (param_nums <= 0) {
1782                 DRM_DEBUG_DRIVER("user data not be read\n");
1783                 kfree(wr_buf);
1784                 return -EINVAL;
1785         }
1786
1787         for (i = 0; i < MAX_PIPES; i++) {
1788                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1789                         if (pipe_ctx && pipe_ctx->stream &&
1790                             pipe_ctx->stream->link == aconnector->dc_link)
1791                                 break;
1792         }
1793
1794         if (!pipe_ctx || !pipe_ctx->stream)
1795                 goto done;
1796
1797         // Get CRTC state
1798         mutex_lock(&dev->mode_config.mutex);
1799         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1800
1801         if (connector->state == NULL)
1802                 goto unlock;
1803
1804         crtc = connector->state->crtc;
1805         if (crtc == NULL)
1806                 goto unlock;
1807
1808         drm_modeset_lock(&crtc->mutex, NULL);
1809         if (crtc->state == NULL)
1810                 goto unlock;
1811
1812         dm_crtc_state = to_dm_crtc_state(crtc->state);
1813         if (dm_crtc_state->stream == NULL)
1814                 goto unlock;
1815
1816         if (param[0] > 0)
1817                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1818                                         pipe_ctx->stream->timing.v_addressable,
1819                                         param[0]);
1820         else
1821                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1822
1823         dm_crtc_state->dsc_force_changed = true;
1824
1825 unlock:
1826         if (crtc)
1827                 drm_modeset_unlock(&crtc->mutex);
1828         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1829         mutex_unlock(&dev->mode_config.mutex);
1830
1831 done:
1832         kfree(wr_buf);
1833         return size;
1834 }
1835
1836 /* function: read DSC target rate on the connector in bits per pixel
1837  *
1838  * The read function: dp_dsc_bits_per_pixel_read
1839  * returns target rate of compression in bits per pixel
1840  * The return is an integer: 0 or other positive integer
1841  *
1842  * Access it with the following command:
1843  *
1844  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1845  *
1846  *  0 - means that DSC is disabled
1847  */
1848 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1849                                     size_t size, loff_t *pos)
1850 {
1851         char *rd_buf = NULL;
1852         char *rd_buf_ptr = NULL;
1853         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1854         struct display_stream_compressor *dsc;
1855         struct dcn_dsc_state dsc_state = {0};
1856         const uint32_t rd_buf_size = 100;
1857         struct pipe_ctx *pipe_ctx;
1858         ssize_t result = 0;
1859         int i, r, str_len = 30;
1860
1861         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1862
1863         if (!rd_buf)
1864                 return -ENOMEM;
1865
1866         rd_buf_ptr = rd_buf;
1867
1868         for (i = 0; i < MAX_PIPES; i++) {
1869                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1870                         if (pipe_ctx && pipe_ctx->stream &&
1871                             pipe_ctx->stream->link == aconnector->dc_link)
1872                                 break;
1873         }
1874
1875         if (!pipe_ctx)
1876                 return -ENXIO;
1877
1878         dsc = pipe_ctx->stream_res.dsc;
1879         if (dsc)
1880                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1881
1882         snprintf(rd_buf_ptr, str_len,
1883                 "%d\n",
1884                 dsc_state.dsc_bits_per_pixel);
1885         rd_buf_ptr += str_len;
1886
1887         while (size) {
1888                 if (*pos >= rd_buf_size)
1889                         break;
1890
1891                 r = put_user(*(rd_buf + result), buf);
1892                 if (r)
1893                         return r; /* r = -EFAULT */
1894
1895                 buf += 1;
1896                 size -= 1;
1897                 *pos += 1;
1898                 result += 1;
1899         }
1900
1901         kfree(rd_buf);
1902         return result;
1903 }
1904
1905 /* function: write DSC target rate in bits per pixel
1906  *
1907  * The write function: dp_dsc_bits_per_pixel_write
1908  * overwrites automatically generated DSC configuration
1909  * of DSC target bit rate.
1910  *
1911  * Also the user has to write bpp in hexidecimal
1912  * rather than in decimal.
1913  *
1914  * Writing DSC settings is done with the following command:
1915  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1916  *
1917  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1918  *
1919  *  - To stop overwriting and let driver find the optimal rate,
1920  * set the rate to zero:
1921  *
1922  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1923  *
1924  */
1925 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1926                                      size_t size, loff_t *pos)
1927 {
1928         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1929         struct drm_connector *connector = &aconnector->base;
1930         struct drm_device *dev = connector->dev;
1931         struct drm_crtc *crtc = NULL;
1932         struct dm_crtc_state *dm_crtc_state = NULL;
1933         struct pipe_ctx *pipe_ctx;
1934         int i;
1935         char *wr_buf = NULL;
1936         uint32_t wr_buf_size = 42;
1937         int max_param_num = 1;
1938         uint8_t param_nums = 0;
1939         long param[1] = {0};
1940
1941         if (size == 0)
1942                 return -EINVAL;
1943
1944         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1945
1946         if (!wr_buf) {
1947                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1948                 return -ENOSPC;
1949         }
1950
1951         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1952                                             (long *)param, buf,
1953                                             max_param_num,
1954                                             &param_nums)) {
1955                 kfree(wr_buf);
1956                 return -EINVAL;
1957         }
1958
1959         if (param_nums <= 0) {
1960                 DRM_DEBUG_DRIVER("user data not be read\n");
1961                 kfree(wr_buf);
1962                 return -EINVAL;
1963         }
1964
1965         for (i = 0; i < MAX_PIPES; i++) {
1966                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1967                         if (pipe_ctx && pipe_ctx->stream &&
1968                             pipe_ctx->stream->link == aconnector->dc_link)
1969                                 break;
1970         }
1971
1972         if (!pipe_ctx || !pipe_ctx->stream)
1973                 goto done;
1974
1975         // Get CRTC state
1976         mutex_lock(&dev->mode_config.mutex);
1977         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1978
1979         if (connector->state == NULL)
1980                 goto unlock;
1981
1982         crtc = connector->state->crtc;
1983         if (crtc == NULL)
1984                 goto unlock;
1985
1986         drm_modeset_lock(&crtc->mutex, NULL);
1987         if (crtc->state == NULL)
1988                 goto unlock;
1989
1990         dm_crtc_state = to_dm_crtc_state(crtc->state);
1991         if (dm_crtc_state->stream == NULL)
1992                 goto unlock;
1993
1994         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
1995
1996         dm_crtc_state->dsc_force_changed = true;
1997
1998 unlock:
1999         if (crtc)
2000                 drm_modeset_unlock(&crtc->mutex);
2001         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2002         mutex_unlock(&dev->mode_config.mutex);
2003
2004 done:
2005         kfree(wr_buf);
2006         return size;
2007 }
2008
2009 /* function: read DSC picture width parameter on the connector
2010  *
2011  * The read function: dp_dsc_pic_width_read
2012  * returns dsc picture width used in the current configuration
2013  * It is the same as h_addressable of the current
2014  * display's timing
2015  * The return is an integer: 0 or other positive integer
2016  * If 0 then DSC is disabled.
2017  *
2018  * Access it with the following command:
2019  *
2020  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2021  *
2022  * 0 - means that DSC is disabled
2023  */
2024 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2025                                     size_t size, loff_t *pos)
2026 {
2027         char *rd_buf = NULL;
2028         char *rd_buf_ptr = NULL;
2029         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2030         struct display_stream_compressor *dsc;
2031         struct dcn_dsc_state dsc_state = {0};
2032         const uint32_t rd_buf_size = 100;
2033         struct pipe_ctx *pipe_ctx;
2034         ssize_t result = 0;
2035         int i, r, str_len = 30;
2036
2037         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2038
2039         if (!rd_buf)
2040                 return -ENOMEM;
2041
2042         rd_buf_ptr = rd_buf;
2043
2044         for (i = 0; i < MAX_PIPES; i++) {
2045                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2046                         if (pipe_ctx && pipe_ctx->stream &&
2047                             pipe_ctx->stream->link == aconnector->dc_link)
2048                                 break;
2049         }
2050
2051         if (!pipe_ctx)
2052                 return -ENXIO;
2053
2054         dsc = pipe_ctx->stream_res.dsc;
2055         if (dsc)
2056                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2057
2058         snprintf(rd_buf_ptr, str_len,
2059                 "%d\n",
2060                 dsc_state.dsc_pic_width);
2061         rd_buf_ptr += str_len;
2062
2063         while (size) {
2064                 if (*pos >= rd_buf_size)
2065                         break;
2066
2067                 r = put_user(*(rd_buf + result), buf);
2068                 if (r)
2069                         return r; /* r = -EFAULT */
2070
2071                 buf += 1;
2072                 size -= 1;
2073                 *pos += 1;
2074                 result += 1;
2075         }
2076
2077         kfree(rd_buf);
2078         return result;
2079 }
2080
2081 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2082                                     size_t size, loff_t *pos)
2083 {
2084         char *rd_buf = NULL;
2085         char *rd_buf_ptr = NULL;
2086         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2087         struct display_stream_compressor *dsc;
2088         struct dcn_dsc_state dsc_state = {0};
2089         const uint32_t rd_buf_size = 100;
2090         struct pipe_ctx *pipe_ctx;
2091         ssize_t result = 0;
2092         int i, r, str_len = 30;
2093
2094         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2095
2096         if (!rd_buf)
2097                 return -ENOMEM;
2098
2099         rd_buf_ptr = rd_buf;
2100
2101         for (i = 0; i < MAX_PIPES; i++) {
2102                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2103                         if (pipe_ctx && pipe_ctx->stream &&
2104                             pipe_ctx->stream->link == aconnector->dc_link)
2105                                 break;
2106         }
2107
2108         if (!pipe_ctx)
2109                 return -ENXIO;
2110
2111         dsc = pipe_ctx->stream_res.dsc;
2112         if (dsc)
2113                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2114
2115         snprintf(rd_buf_ptr, str_len,
2116                 "%d\n",
2117                 dsc_state.dsc_pic_height);
2118         rd_buf_ptr += str_len;
2119
2120         while (size) {
2121                 if (*pos >= rd_buf_size)
2122                         break;
2123
2124                 r = put_user(*(rd_buf + result), buf);
2125                 if (r)
2126                         return r; /* r = -EFAULT */
2127
2128                 buf += 1;
2129                 size -= 1;
2130                 *pos += 1;
2131                 result += 1;
2132         }
2133
2134         kfree(rd_buf);
2135         return result;
2136 }
2137
2138 /* function: read DSC chunk size parameter on the connector
2139  *
2140  * The read function: dp_dsc_chunk_size_read
2141  * returns dsc chunk size set in the current configuration
2142  * The value is calculated automatically by DSC code
2143  * and depends on slice parameters and bpp target rate
2144  * The return is an integer: 0 or other positive integer
2145  * If 0 then DSC is disabled.
2146  *
2147  * Access it with the following command:
2148  *
2149  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2150  *
2151  * 0 - means that DSC is disabled
2152  */
2153 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2154                                     size_t size, loff_t *pos)
2155 {
2156         char *rd_buf = NULL;
2157         char *rd_buf_ptr = NULL;
2158         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2159         struct display_stream_compressor *dsc;
2160         struct dcn_dsc_state dsc_state = {0};
2161         const uint32_t rd_buf_size = 100;
2162         struct pipe_ctx *pipe_ctx;
2163         ssize_t result = 0;
2164         int i, r, str_len = 30;
2165
2166         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2167
2168         if (!rd_buf)
2169                 return -ENOMEM;
2170
2171         rd_buf_ptr = rd_buf;
2172
2173         for (i = 0; i < MAX_PIPES; i++) {
2174                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2175                         if (pipe_ctx && pipe_ctx->stream &&
2176                             pipe_ctx->stream->link == aconnector->dc_link)
2177                                 break;
2178         }
2179
2180         if (!pipe_ctx)
2181                 return -ENXIO;
2182
2183         dsc = pipe_ctx->stream_res.dsc;
2184         if (dsc)
2185                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2186
2187         snprintf(rd_buf_ptr, str_len,
2188                 "%d\n",
2189                 dsc_state.dsc_chunk_size);
2190         rd_buf_ptr += str_len;
2191
2192         while (size) {
2193                 if (*pos >= rd_buf_size)
2194                         break;
2195
2196                 r = put_user(*(rd_buf + result), buf);
2197                 if (r)
2198                         return r; /* r = -EFAULT */
2199
2200                 buf += 1;
2201                 size -= 1;
2202                 *pos += 1;
2203                 result += 1;
2204         }
2205
2206         kfree(rd_buf);
2207         return result;
2208 }
2209
2210 /* function: read DSC slice bpg offset on the connector
2211  *
2212  * The read function: dp_dsc_slice_bpg_offset_read
2213  * returns dsc bpg slice offset set in the current configuration
2214  * The value is calculated automatically by DSC code
2215  * and depends on slice parameters and bpp target rate
2216  * The return is an integer: 0 or other positive integer
2217  * If 0 then DSC is disabled.
2218  *
2219  * Access it with the following command:
2220  *
2221  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2222  *
2223  * 0 - means that DSC is disabled
2224  */
2225 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2226                                     size_t size, loff_t *pos)
2227 {
2228         char *rd_buf = NULL;
2229         char *rd_buf_ptr = NULL;
2230         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2231         struct display_stream_compressor *dsc;
2232         struct dcn_dsc_state dsc_state = {0};
2233         const uint32_t rd_buf_size = 100;
2234         struct pipe_ctx *pipe_ctx;
2235         ssize_t result = 0;
2236         int i, r, str_len = 30;
2237
2238         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2239
2240         if (!rd_buf)
2241                 return -ENOMEM;
2242
2243         rd_buf_ptr = rd_buf;
2244
2245         for (i = 0; i < MAX_PIPES; i++) {
2246                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2247                         if (pipe_ctx && pipe_ctx->stream &&
2248                             pipe_ctx->stream->link == aconnector->dc_link)
2249                                 break;
2250         }
2251
2252         if (!pipe_ctx)
2253                 return -ENXIO;
2254
2255         dsc = pipe_ctx->stream_res.dsc;
2256         if (dsc)
2257                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2258
2259         snprintf(rd_buf_ptr, str_len,
2260                 "%d\n",
2261                 dsc_state.dsc_slice_bpg_offset);
2262         rd_buf_ptr += str_len;
2263
2264         while (size) {
2265                 if (*pos >= rd_buf_size)
2266                         break;
2267
2268                 r = put_user(*(rd_buf + result), buf);
2269                 if (r)
2270                         return r; /* r = -EFAULT */
2271
2272                 buf += 1;
2273                 size -= 1;
2274                 *pos += 1;
2275                 result += 1;
2276         }
2277
2278         kfree(rd_buf);
2279         return result;
2280 }
2281
2282
2283 /*
2284  * function description: Read max_requested_bpc property from the connector
2285  *
2286  * Access it with the following command:
2287  *
2288  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2289  *
2290  */
2291 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2292                 size_t size, loff_t *pos)
2293 {
2294         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2295         struct drm_connector *connector = &aconnector->base;
2296         struct drm_device *dev = connector->dev;
2297         struct dm_connector_state *state;
2298         ssize_t result = 0;
2299         char *rd_buf = NULL;
2300         char *rd_buf_ptr = NULL;
2301         const uint32_t rd_buf_size = 10;
2302         int r;
2303
2304         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2305
2306         if (!rd_buf)
2307                 return -ENOMEM;
2308
2309         mutex_lock(&dev->mode_config.mutex);
2310         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2311
2312         if (connector->state == NULL)
2313                 goto unlock;
2314
2315         state = to_dm_connector_state(connector->state);
2316
2317         rd_buf_ptr = rd_buf;
2318         snprintf(rd_buf_ptr, rd_buf_size,
2319                 "%u\n",
2320                 state->base.max_requested_bpc);
2321
2322         while (size) {
2323                 if (*pos >= rd_buf_size)
2324                         break;
2325
2326                 r = put_user(*(rd_buf + result), buf);
2327                 if (r) {
2328                         result = r; /* r = -EFAULT */
2329                         goto unlock;
2330                 }
2331                 buf += 1;
2332                 size -= 1;
2333                 *pos += 1;
2334                 result += 1;
2335         }
2336 unlock:
2337         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2338         mutex_unlock(&dev->mode_config.mutex);
2339         kfree(rd_buf);
2340         return result;
2341 }
2342
2343
2344 /*
2345  * function description: Set max_requested_bpc property on the connector
2346  *
2347  * This function will not force the input BPC on connector, it will only
2348  * change the max value. This is equivalent to setting max_bpc through
2349  * xrandr.
2350  *
2351  * The BPC value written must be >= 6 and <= 16. Values outside of this
2352  * range will result in errors.
2353  *
2354  * BPC values:
2355  *      0x6 - 6 BPC
2356  *      0x8 - 8 BPC
2357  *      0xa - 10 BPC
2358  *      0xc - 12 BPC
2359  *      0x10 - 16 BPC
2360  *
2361  * Write the max_bpc in the following way:
2362  *
2363  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2364  *
2365  */
2366 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2367                                      size_t size, loff_t *pos)
2368 {
2369         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2370         struct drm_connector *connector = &aconnector->base;
2371         struct dm_connector_state *state;
2372         struct drm_device *dev = connector->dev;
2373         char *wr_buf = NULL;
2374         uint32_t wr_buf_size = 42;
2375         int max_param_num = 1;
2376         long param[1] = {0};
2377         uint8_t param_nums = 0;
2378
2379         if (size == 0)
2380                 return -EINVAL;
2381
2382         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2383
2384         if (!wr_buf) {
2385                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2386                 return -ENOSPC;
2387         }
2388
2389         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2390                                            (long *)param, buf,
2391                                            max_param_num,
2392                                            &param_nums)) {
2393                 kfree(wr_buf);
2394                 return -EINVAL;
2395         }
2396
2397         if (param_nums <= 0) {
2398                 DRM_DEBUG_DRIVER("user data not be read\n");
2399                 kfree(wr_buf);
2400                 return -EINVAL;
2401         }
2402
2403         if (param[0] < 6 || param[0] > 16) {
2404                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2405                 kfree(wr_buf);
2406                 return -EINVAL;
2407         }
2408
2409         mutex_lock(&dev->mode_config.mutex);
2410         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2411
2412         if (connector->state == NULL)
2413                 goto unlock;
2414
2415         state = to_dm_connector_state(connector->state);
2416         state->base.max_requested_bpc = param[0];
2417 unlock:
2418         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2419         mutex_unlock(&dev->mode_config.mutex);
2420
2421         kfree(wr_buf);
2422         return size;
2423 }
2424
2425 /*
2426  * Backlight at this moment.  Read only.
2427  * As written to display, taking ABM and backlight lut into account.
2428  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2429  *
2430  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2431  */
2432 static int current_backlight_show(struct seq_file *m, void *unused)
2433 {
2434         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2435         struct dc_link *link = aconnector->dc_link;
2436         unsigned int backlight;
2437
2438         backlight = dc_link_get_backlight_level(link);
2439         seq_printf(m, "0x%x\n", backlight);
2440
2441         return 0;
2442 }
2443
2444 /*
2445  * Backlight value that is being approached.  Read only.
2446  * As written to display, taking ABM and backlight lut into account.
2447  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2448  *
2449  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2450  */
2451 static int target_backlight_show(struct seq_file *m, void *unused)
2452 {
2453         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2454         struct dc_link *link = aconnector->dc_link;
2455         unsigned int backlight;
2456
2457         backlight = dc_link_get_target_backlight_pwm(link);
2458         seq_printf(m, "0x%x\n", backlight);
2459
2460         return 0;
2461 }
2462
2463 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2464 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2465 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2466 DEFINE_SHOW_ATTRIBUTE(output_bpc);
2467 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2468 #ifdef CONFIG_DRM_AMD_DC_HDCP
2469 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2470 #endif
2471 DEFINE_SHOW_ATTRIBUTE(internal_display);
2472
2473 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2474         .owner = THIS_MODULE,
2475         .read = dp_dsc_clock_en_read,
2476         .write = dp_dsc_clock_en_write,
2477         .llseek = default_llseek
2478 };
2479
2480 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2481         .owner = THIS_MODULE,
2482         .read = dp_dsc_slice_width_read,
2483         .write = dp_dsc_slice_width_write,
2484         .llseek = default_llseek
2485 };
2486
2487 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2488         .owner = THIS_MODULE,
2489         .read = dp_dsc_slice_height_read,
2490         .write = dp_dsc_slice_height_write,
2491         .llseek = default_llseek
2492 };
2493
2494 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2495         .owner = THIS_MODULE,
2496         .read = dp_dsc_bits_per_pixel_read,
2497         .write = dp_dsc_bits_per_pixel_write,
2498         .llseek = default_llseek
2499 };
2500
2501 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2502         .owner = THIS_MODULE,
2503         .read = dp_dsc_pic_width_read,
2504         .llseek = default_llseek
2505 };
2506
2507 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2508         .owner = THIS_MODULE,
2509         .read = dp_dsc_pic_height_read,
2510         .llseek = default_llseek
2511 };
2512
2513 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2514         .owner = THIS_MODULE,
2515         .read = dp_dsc_chunk_size_read,
2516         .llseek = default_llseek
2517 };
2518
2519 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2520         .owner = THIS_MODULE,
2521         .read = dp_dsc_slice_bpg_offset_read,
2522         .llseek = default_llseek
2523 };
2524
2525 static const struct file_operations trigger_hotplug_debugfs_fops = {
2526         .owner = THIS_MODULE,
2527         .write = trigger_hotplug,
2528         .llseek = default_llseek
2529 };
2530
2531 static const struct file_operations dp_link_settings_debugfs_fops = {
2532         .owner = THIS_MODULE,
2533         .read = dp_link_settings_read,
2534         .write = dp_link_settings_write,
2535         .llseek = default_llseek
2536 };
2537
2538 static const struct file_operations dp_phy_settings_debugfs_fop = {
2539         .owner = THIS_MODULE,
2540         .read = dp_phy_settings_read,
2541         .write = dp_phy_settings_write,
2542         .llseek = default_llseek
2543 };
2544
2545 static const struct file_operations dp_phy_test_pattern_fops = {
2546         .owner = THIS_MODULE,
2547         .write = dp_phy_test_pattern_debugfs_write,
2548         .llseek = default_llseek
2549 };
2550
2551 static const struct file_operations sdp_message_fops = {
2552         .owner = THIS_MODULE,
2553         .write = dp_sdp_message_debugfs_write,
2554         .llseek = default_llseek
2555 };
2556
2557 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2558         .owner = THIS_MODULE,
2559         .write = dp_dpcd_address_write,
2560         .llseek = default_llseek
2561 };
2562
2563 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2564         .owner = THIS_MODULE,
2565         .write = dp_dpcd_size_write,
2566         .llseek = default_llseek
2567 };
2568
2569 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2570         .owner = THIS_MODULE,
2571         .read = dp_dpcd_data_read,
2572         .write = dp_dpcd_data_write,
2573         .llseek = default_llseek
2574 };
2575
2576 static const struct file_operations dp_max_bpc_debugfs_fops = {
2577         .owner = THIS_MODULE,
2578         .read = dp_max_bpc_read,
2579         .write = dp_max_bpc_write,
2580         .llseek = default_llseek
2581 };
2582
2583 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2584         .owner = THIS_MODULE,
2585         .write = dp_dsc_passthrough_set,
2586         .llseek = default_llseek
2587 };
2588
2589 static const struct {
2590         char *name;
2591         const struct file_operations *fops;
2592 } dp_debugfs_entries[] = {
2593                 {"link_settings", &dp_link_settings_debugfs_fops},
2594                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2595                 {"lttpr_status", &dp_lttpr_status_fops},
2596                 {"test_pattern", &dp_phy_test_pattern_fops},
2597 #ifdef CONFIG_DRM_AMD_DC_HDCP
2598                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2599 #endif
2600                 {"sdp_message", &sdp_message_fops},
2601                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2602                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2603                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2604                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2605                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2606                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2607                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2608                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2609                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2610                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2611                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2612                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2613                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2614                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2615 };
2616
2617 #ifdef CONFIG_DRM_AMD_DC_HDCP
2618 static const struct {
2619         char *name;
2620         const struct file_operations *fops;
2621 } hdmi_debugfs_entries[] = {
2622                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2623 };
2624 #endif
2625 /*
2626  * Force YUV420 output if available from the given mode
2627  */
2628 static int force_yuv420_output_set(void *data, u64 val)
2629 {
2630         struct amdgpu_dm_connector *connector = data;
2631
2632         connector->force_yuv420_output = (bool)val;
2633
2634         return 0;
2635 }
2636
2637 /*
2638  * Check if YUV420 is forced when available from the given mode
2639  */
2640 static int force_yuv420_output_get(void *data, u64 *val)
2641 {
2642         struct amdgpu_dm_connector *connector = data;
2643
2644         *val = connector->force_yuv420_output;
2645
2646         return 0;
2647 }
2648
2649 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2650                          force_yuv420_output_set, "%llu\n");
2651
2652 /*
2653  *  Read PSR state
2654  */
2655 static int psr_get(void *data, u64 *val)
2656 {
2657         struct amdgpu_dm_connector *connector = data;
2658         struct dc_link *link = connector->dc_link;
2659         enum dc_psr_state state = PSR_STATE0;
2660
2661         dc_link_get_psr_state(link, &state);
2662
2663         *val = state;
2664
2665         return 0;
2666 }
2667
2668 /*
2669  * Set dmcub trace event IRQ enable or disable.
2670  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2671  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2672  */
2673 static int dmcub_trace_event_state_set(void *data, u64 val)
2674 {
2675         struct amdgpu_device *adev = data;
2676
2677         if (val == 1 || val == 0) {
2678                 dc_dmub_trace_event_control(adev->dm.dc, val);
2679                 adev->dm.dmcub_trace_event_en = (bool)val;
2680         } else
2681                 return 0;
2682
2683         return 0;
2684 }
2685
2686 /*
2687  * The interface doesn't need get function, so it will return the
2688  * value of zero
2689  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2690  */
2691 static int dmcub_trace_event_state_get(void *data, u64 *val)
2692 {
2693         struct amdgpu_device *adev = data;
2694
2695         *val = adev->dm.dmcub_trace_event_en;
2696         return 0;
2697 }
2698
2699 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2700                          dmcub_trace_event_state_set, "%llu\n");
2701
2702 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2703
2704 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2705 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2706
2707 static const struct {
2708         char *name;
2709         const struct file_operations *fops;
2710 } connector_debugfs_entries[] = {
2711                 {"force_yuv420_output", &force_yuv420_output_fops},
2712                 {"output_bpc", &output_bpc_fops},
2713                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2714                 {"internal_display", &internal_display_fops}
2715 };
2716
2717 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2718 {
2719         int i;
2720         struct dentry *dir = connector->base.debugfs_entry;
2721
2722         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2723             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2724                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2725                         debugfs_create_file(dp_debugfs_entries[i].name,
2726                                             0644, dir, connector,
2727                                             dp_debugfs_entries[i].fops);
2728                 }
2729         }
2730         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2731                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2732                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
2733                                     &current_backlight_fops);
2734                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
2735                                     &target_backlight_fops);
2736         }
2737
2738         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2739                 debugfs_create_file(connector_debugfs_entries[i].name,
2740                                     0644, dir, connector,
2741                                     connector_debugfs_entries[i].fops);
2742         }
2743
2744         connector->debugfs_dpcd_address = 0;
2745         connector->debugfs_dpcd_size = 0;
2746
2747 #ifdef CONFIG_DRM_AMD_DC_HDCP
2748         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2749                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2750                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2751                                             0644, dir, connector,
2752                                             hdmi_debugfs_entries[i].fops);
2753                 }
2754         }
2755 #endif
2756 }
2757
2758 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2759 /*
2760  * Set crc window coordinate x start
2761  */
2762 static int crc_win_x_start_set(void *data, u64 val)
2763 {
2764         struct drm_crtc *crtc = data;
2765         struct drm_device *drm_dev = crtc->dev;
2766         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2767
2768         spin_lock_irq(&drm_dev->event_lock);
2769         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2770         acrtc->dm_irq_params.crc_window.update_win = false;
2771         spin_unlock_irq(&drm_dev->event_lock);
2772
2773         return 0;
2774 }
2775
2776 /*
2777  * Get crc window coordinate x start
2778  */
2779 static int crc_win_x_start_get(void *data, u64 *val)
2780 {
2781         struct drm_crtc *crtc = data;
2782         struct drm_device *drm_dev = crtc->dev;
2783         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2784
2785         spin_lock_irq(&drm_dev->event_lock);
2786         *val = acrtc->dm_irq_params.crc_window.x_start;
2787         spin_unlock_irq(&drm_dev->event_lock);
2788
2789         return 0;
2790 }
2791
2792 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2793                          crc_win_x_start_set, "%llu\n");
2794
2795
2796 /*
2797  * Set crc window coordinate y start
2798  */
2799 static int crc_win_y_start_set(void *data, u64 val)
2800 {
2801         struct drm_crtc *crtc = data;
2802         struct drm_device *drm_dev = crtc->dev;
2803         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2804
2805         spin_lock_irq(&drm_dev->event_lock);
2806         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
2807         acrtc->dm_irq_params.crc_window.update_win = false;
2808         spin_unlock_irq(&drm_dev->event_lock);
2809
2810         return 0;
2811 }
2812
2813 /*
2814  * Get crc window coordinate y start
2815  */
2816 static int crc_win_y_start_get(void *data, u64 *val)
2817 {
2818         struct drm_crtc *crtc = data;
2819         struct drm_device *drm_dev = crtc->dev;
2820         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2821
2822         spin_lock_irq(&drm_dev->event_lock);
2823         *val = acrtc->dm_irq_params.crc_window.y_start;
2824         spin_unlock_irq(&drm_dev->event_lock);
2825
2826         return 0;
2827 }
2828
2829 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
2830                          crc_win_y_start_set, "%llu\n");
2831
2832 /*
2833  * Set crc window coordinate x end
2834  */
2835 static int crc_win_x_end_set(void *data, u64 val)
2836 {
2837         struct drm_crtc *crtc = data;
2838         struct drm_device *drm_dev = crtc->dev;
2839         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2840
2841         spin_lock_irq(&drm_dev->event_lock);
2842         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
2843         acrtc->dm_irq_params.crc_window.update_win = false;
2844         spin_unlock_irq(&drm_dev->event_lock);
2845
2846         return 0;
2847 }
2848
2849 /*
2850  * Get crc window coordinate x end
2851  */
2852 static int crc_win_x_end_get(void *data, u64 *val)
2853 {
2854         struct drm_crtc *crtc = data;
2855         struct drm_device *drm_dev = crtc->dev;
2856         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2857
2858         spin_lock_irq(&drm_dev->event_lock);
2859         *val = acrtc->dm_irq_params.crc_window.x_end;
2860         spin_unlock_irq(&drm_dev->event_lock);
2861
2862         return 0;
2863 }
2864
2865 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
2866                          crc_win_x_end_set, "%llu\n");
2867
2868 /*
2869  * Set crc window coordinate y end
2870  */
2871 static int crc_win_y_end_set(void *data, u64 val)
2872 {
2873         struct drm_crtc *crtc = data;
2874         struct drm_device *drm_dev = crtc->dev;
2875         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2876
2877         spin_lock_irq(&drm_dev->event_lock);
2878         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
2879         acrtc->dm_irq_params.crc_window.update_win = false;
2880         spin_unlock_irq(&drm_dev->event_lock);
2881
2882         return 0;
2883 }
2884
2885 /*
2886  * Get crc window coordinate y end
2887  */
2888 static int crc_win_y_end_get(void *data, u64 *val)
2889 {
2890         struct drm_crtc *crtc = data;
2891         struct drm_device *drm_dev = crtc->dev;
2892         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2893
2894         spin_lock_irq(&drm_dev->event_lock);
2895         *val = acrtc->dm_irq_params.crc_window.y_end;
2896         spin_unlock_irq(&drm_dev->event_lock);
2897
2898         return 0;
2899 }
2900
2901 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
2902                          crc_win_y_end_set, "%llu\n");
2903 /*
2904  * Trigger to commit crc window
2905  */
2906 static int crc_win_update_set(void *data, u64 val)
2907 {
2908         struct drm_crtc *new_crtc = data;
2909         struct drm_crtc *old_crtc = NULL;
2910         struct amdgpu_crtc *new_acrtc, *old_acrtc;
2911         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
2912         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
2913
2914         if (val) {
2915                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
2916                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
2917                 if (crc_rd_wrk && crc_rd_wrk->crtc) {
2918                         old_crtc = crc_rd_wrk->crtc;
2919                         old_acrtc = to_amdgpu_crtc(old_crtc);
2920                 }
2921                 new_acrtc = to_amdgpu_crtc(new_crtc);
2922
2923                 if (old_crtc && old_crtc != new_crtc) {
2924                         old_acrtc->dm_irq_params.crc_window.activated = false;
2925                         old_acrtc->dm_irq_params.crc_window.update_win = false;
2926                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2927
2928                         new_acrtc->dm_irq_params.crc_window.activated = true;
2929                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2930                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2931                         crc_rd_wrk->crtc = new_crtc;
2932                 } else {
2933                         new_acrtc->dm_irq_params.crc_window.activated = true;
2934                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2935                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2936                         crc_rd_wrk->crtc = new_crtc;
2937                 }
2938                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
2939                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
2940         }
2941
2942         return 0;
2943 }
2944
2945 /*
2946  * Get crc window update flag
2947  */
2948 static int crc_win_update_get(void *data, u64 *val)
2949 {
2950         *val = 0;
2951         return 0;
2952 }
2953
2954 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
2955                          crc_win_update_set, "%llu\n");
2956
2957 void crtc_debugfs_init(struct drm_crtc *crtc)
2958 {
2959         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
2960
2961         if (!dir)
2962                 return;
2963
2964         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
2965                                    &crc_win_x_start_fops);
2966         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
2967                                    &crc_win_y_start_fops);
2968         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
2969                                    &crc_win_x_end_fops);
2970         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
2971                                    &crc_win_y_end_fops);
2972         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
2973                                    &crc_win_update_fops);
2974
2975 }
2976 #endif
2977 /*
2978  * Writes DTN log state to the user supplied buffer.
2979  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2980  */
2981 static ssize_t dtn_log_read(
2982         struct file *f,
2983         char __user *buf,
2984         size_t size,
2985         loff_t *pos)
2986 {
2987         struct amdgpu_device *adev = file_inode(f)->i_private;
2988         struct dc *dc = adev->dm.dc;
2989         struct dc_log_buffer_ctx log_ctx = { 0 };
2990         ssize_t result = 0;
2991
2992         if (!buf || !size)
2993                 return -EINVAL;
2994
2995         if (!dc->hwss.log_hw_state)
2996                 return 0;
2997
2998         dc->hwss.log_hw_state(dc, &log_ctx);
2999
3000         if (*pos < log_ctx.pos) {
3001                 size_t to_copy = log_ctx.pos - *pos;
3002
3003                 to_copy = min(to_copy, size);
3004
3005                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3006                         *pos += to_copy;
3007                         result = to_copy;
3008                 }
3009         }
3010
3011         kfree(log_ctx.buf);
3012
3013         return result;
3014 }
3015
3016 /*
3017  * Writes DTN log state to dmesg when triggered via a write.
3018  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3019  */
3020 static ssize_t dtn_log_write(
3021         struct file *f,
3022         const char __user *buf,
3023         size_t size,
3024         loff_t *pos)
3025 {
3026         struct amdgpu_device *adev = file_inode(f)->i_private;
3027         struct dc *dc = adev->dm.dc;
3028
3029         /* Write triggers log output via dmesg. */
3030         if (size == 0)
3031                 return 0;
3032
3033         if (dc->hwss.log_hw_state)
3034                 dc->hwss.log_hw_state(dc, NULL);
3035
3036         return size;
3037 }
3038
3039 static int mst_topo_show(struct seq_file *m, void *unused)
3040 {
3041         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3042         struct drm_device *dev = adev_to_drm(adev);
3043         struct drm_connector *connector;
3044         struct drm_connector_list_iter conn_iter;
3045         struct amdgpu_dm_connector *aconnector;
3046
3047         drm_connector_list_iter_begin(dev, &conn_iter);
3048         drm_for_each_connector_iter(connector, &conn_iter) {
3049                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3050                         continue;
3051
3052                 aconnector = to_amdgpu_dm_connector(connector);
3053
3054                 /* Ensure we're only dumping the topology of a root mst node */
3055                 if (!aconnector->mst_mgr.mst_state)
3056                         continue;
3057
3058                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3059                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3060         }
3061         drm_connector_list_iter_end(&conn_iter);
3062
3063         return 0;
3064 }
3065
3066 /*
3067  * Sets trigger hpd for MST topologies.
3068  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3069  * All topologies will be disconnected if val of 0 is set .
3070  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3071  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3072  */
3073 static int trigger_hpd_mst_set(void *data, u64 val)
3074 {
3075         struct amdgpu_device *adev = data;
3076         struct drm_device *dev = adev_to_drm(adev);
3077         struct drm_connector_list_iter iter;
3078         struct amdgpu_dm_connector *aconnector;
3079         struct drm_connector *connector;
3080         struct dc_link *link = NULL;
3081
3082         if (val == 1) {
3083                 drm_connector_list_iter_begin(dev, &iter);
3084                 drm_for_each_connector_iter(connector, &iter) {
3085                         aconnector = to_amdgpu_dm_connector(connector);
3086                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3087                             aconnector->mst_mgr.aux) {
3088                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3089                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3090                         }
3091                 }
3092         } else if (val == 0) {
3093                 drm_connector_list_iter_begin(dev, &iter);
3094                 drm_for_each_connector_iter(connector, &iter) {
3095                         aconnector = to_amdgpu_dm_connector(connector);
3096                         if (!aconnector->dc_link)
3097                                 continue;
3098
3099                         if (!aconnector->mst_port)
3100                                 continue;
3101
3102                         link = aconnector->dc_link;
3103                         dp_receiver_power_ctrl(link, false);
3104                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3105                         link->mst_stream_alloc_table.stream_count = 0;
3106                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3107                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3108                 }
3109         } else {
3110                 return 0;
3111         }
3112         drm_kms_helper_hotplug_event(dev);
3113
3114         return 0;
3115 }
3116
3117 /*
3118  * The interface doesn't need get function, so it will return the
3119  * value of zero
3120  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3121  */
3122 static int trigger_hpd_mst_get(void *data, u64 *val)
3123 {
3124         *val = 0;
3125         return 0;
3126 }
3127
3128 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3129                          trigger_hpd_mst_set, "%llu\n");
3130
3131
3132 /*
3133  * Sets the force_timing_sync debug option from the given string.
3134  * All connected displays will be force synchronized immediately.
3135  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3136  */
3137 static int force_timing_sync_set(void *data, u64 val)
3138 {
3139         struct amdgpu_device *adev = data;
3140
3141         adev->dm.force_timing_sync = (bool)val;
3142
3143         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3144
3145         return 0;
3146 }
3147
3148 /*
3149  * Gets the force_timing_sync debug option value into the given buffer.
3150  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3151  */
3152 static int force_timing_sync_get(void *data, u64 *val)
3153 {
3154         struct amdgpu_device *adev = data;
3155
3156         *val = adev->dm.force_timing_sync;
3157
3158         return 0;
3159 }
3160
3161 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3162                          force_timing_sync_set, "%llu\n");
3163
3164
3165 /*
3166  * Disables all HPD and HPD RX interrupt handling in the
3167  * driver when set to 1. Default is 0.
3168  */
3169 static int disable_hpd_set(void *data, u64 val)
3170 {
3171         struct amdgpu_device *adev = data;
3172
3173         adev->dm.disable_hpd_irq = (bool)val;
3174
3175         return 0;
3176 }
3177
3178
3179 /*
3180  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3181  * 0 otherwise.
3182  */
3183 static int disable_hpd_get(void *data, u64 *val)
3184 {
3185         struct amdgpu_device *adev = data;
3186
3187         *val = adev->dm.disable_hpd_irq;
3188
3189         return 0;
3190 }
3191
3192 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3193                          disable_hpd_set, "%llu\n");
3194
3195 /*
3196  * Sets the DC visual confirm debug option from the given string.
3197  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3198  */
3199 static int visual_confirm_set(void *data, u64 val)
3200 {
3201         struct amdgpu_device *adev = data;
3202
3203         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3204
3205         return 0;
3206 }
3207
3208 /*
3209  * Reads the DC visual confirm debug option value into the given buffer.
3210  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3211  */
3212 static int visual_confirm_get(void *data, u64 *val)
3213 {
3214         struct amdgpu_device *adev = data;
3215
3216         *val = adev->dm.dc->debug.visual_confirm;
3217
3218         return 0;
3219 }
3220
3221 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3222 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3223                          visual_confirm_set, "%llu\n");
3224
3225 /*
3226  * Dumps the DCC_EN bit for each pipe.
3227  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3228  */
3229 static ssize_t dcc_en_bits_read(
3230         struct file *f,
3231         char __user *buf,
3232         size_t size,
3233         loff_t *pos)
3234 {
3235         struct amdgpu_device *adev = file_inode(f)->i_private;
3236         struct dc *dc = adev->dm.dc;
3237         char *rd_buf = NULL;
3238         const uint32_t rd_buf_size = 32;
3239         uint32_t result = 0;
3240         int offset = 0;
3241         int num_pipes = dc->res_pool->pipe_count;
3242         int *dcc_en_bits;
3243         int i, r;
3244
3245         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3246         if (!dcc_en_bits)
3247                 return -ENOMEM;
3248
3249         if (!dc->hwss.get_dcc_en_bits) {
3250                 kfree(dcc_en_bits);
3251                 return 0;
3252         }
3253
3254         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3255
3256         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3257         if (!rd_buf)
3258                 return -ENOMEM;
3259
3260         for (i = 0; i < num_pipes; i++)
3261                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3262                                    "%d  ", dcc_en_bits[i]);
3263         rd_buf[strlen(rd_buf)] = '\n';
3264
3265         kfree(dcc_en_bits);
3266
3267         while (size) {
3268                 if (*pos >= rd_buf_size)
3269                         break;
3270                 r = put_user(*(rd_buf + result), buf);
3271                 if (r)
3272                         return r; /* r = -EFAULT */
3273                 buf += 1;
3274                 size -= 1;
3275                 *pos += 1;
3276                 result += 1;
3277         }
3278
3279         kfree(rd_buf);
3280         return result;
3281 }
3282
3283 void dtn_debugfs_init(struct amdgpu_device *adev)
3284 {
3285         static const struct file_operations dtn_log_fops = {
3286                 .owner = THIS_MODULE,
3287                 .read = dtn_log_read,
3288                 .write = dtn_log_write,
3289                 .llseek = default_llseek
3290         };
3291         static const struct file_operations dcc_en_bits_fops = {
3292                 .owner = THIS_MODULE,
3293                 .read = dcc_en_bits_read,
3294                 .llseek = default_llseek
3295         };
3296
3297         struct drm_minor *minor = adev_to_drm(adev)->primary;
3298         struct dentry *root = minor->debugfs_root;
3299
3300         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3301                             adev, &mst_topo_fops);
3302         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3303                             &dtn_log_fops);
3304
3305         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3306                                    &visual_confirm_fops);
3307
3308         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3309                                    adev, &dmub_tracebuffer_fops);
3310
3311         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3312                                    adev, &dmub_fw_state_fops);
3313
3314         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3315                                    adev, &force_timing_sync_ops);
3316
3317         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3318                                    adev, &dmcub_trace_event_state_fops);
3319
3320         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3321                                    adev, &trigger_hpd_mst_ops);
3322
3323         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3324                                    &dcc_en_bits_fops);
3325
3326         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3327                                    &disable_hpd_ops);
3328
3329 }