drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "amdgpu_pm.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "jpeg_v2_0.h"
  30
  31 #include "vcn/vcn_3_0_0_offset.h"
  32 #include "vcn/vcn_3_0_0_sh_mask.h"
  33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  34
  35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET        0x401f
  36
  37 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  38 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  39 static int jpeg_v3_0_set_powergating_state(void *handle,
  40                                 enum amd_powergating_state state);
  41
  42 /**
  43  * jpeg_v3_0_early_init - set function pointers
  44  *
  45  * @handle: amdgpu_device pointer
  46  *
  47  * Set ring and irq function pointers
  48  */
  49 static int jpeg_v3_0_early_init(void *handle)
  50 {
  51         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  52
  53         u32 harvest;
  54
  55         switch (adev->ip_versions[UVD_HWIP][0]) {
  56         case IP_VERSION(3, 1, 1):
  57         case IP_VERSION(3, 1, 2):
  58                 break;
  59         default:
  60                 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
  61                 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  62                         return -ENOENT;
  63                 break;
  64         }
  65
  66         adev->jpeg.num_jpeg_inst = 1;
  67
  68         jpeg_v3_0_set_dec_ring_funcs(adev);
  69         jpeg_v3_0_set_irq_funcs(adev);
  70
  71         return 0;
  72 }
  73
  74 /**
  75  * jpeg_v3_0_sw_init - sw init for JPEG block
  76  *
  77  * @handle: amdgpu_device pointer
  78  *
  79  * Load firmware and sw initialization
  80  */
  81 static int jpeg_v3_0_sw_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84         struct amdgpu_ring *ring;
  85         int r;
  86
  87         /* JPEG TRAP */
  88         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  89                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
  90         if (r)
  91                 return r;
  92
  93         r = amdgpu_jpeg_sw_init(adev);
  94         if (r)
  95                 return r;
  96
  97         r = amdgpu_jpeg_resume(adev);
  98         if (r)
  99                 return r;
 100
 101         ring = &adev->jpeg.inst->ring_dec;
 102         ring->use_doorbell = true;
 103         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
 104         ring->vm_hub = AMDGPU_MMHUB_0;
 105         sprintf(ring->name, "jpeg_dec");
 106         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
 107                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 108         if (r)
 109                 return r;
 110
 111         adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
 112         adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
 113
 114         return 0;
 115 }
 116
 117 /**
 118  * jpeg_v3_0_sw_fini - sw fini for JPEG block
 119  *
 120  * @handle: amdgpu_device pointer
 121  *
 122  * JPEG suspend and free up sw allocation
 123  */
 124 static int jpeg_v3_0_sw_fini(void *handle)
 125 {
 126         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 127         int r;
 128
 129         r = amdgpu_jpeg_suspend(adev);
 130         if (r)
 131                 return r;
 132
 133         r = amdgpu_jpeg_sw_fini(adev);
 134
 135         return r;
 136 }
 137
 138 /**
 139  * jpeg_v3_0_hw_init - start and test JPEG block
 140  *
 141  * @handle: amdgpu_device pointer
 142  *
 143  */
 144 static int jpeg_v3_0_hw_init(void *handle)
 145 {
 146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 147         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 148         int r;
 149
 150         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 151                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 152
 153         r = amdgpu_ring_test_helper(ring);
 154         if (r)
 155                 return r;
 156
 157         DRM_INFO("JPEG decode initialized successfully.\n");
 158
 159         return 0;
 160 }
 161
 162 /**
 163  * jpeg_v3_0_hw_fini - stop the hardware block
 164  *
 165  * @handle: amdgpu_device pointer
 166  *
 167  * Stop the JPEG block, mark ring as not ready any more
 168  */
 169 static int jpeg_v3_0_hw_fini(void *handle)
 170 {
 171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 172
 173         cancel_delayed_work_sync(&adev->vcn.idle_work);
 174
 175         if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 176               RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
 177                 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 178
 179         return 0;
 180 }
 181
 182 /**
 183  * jpeg_v3_0_suspend - suspend JPEG block
 184  *
 185  * @handle: amdgpu_device pointer
 186  *
 187  * HW fini and suspend JPEG block
 188  */
 189 static int jpeg_v3_0_suspend(void *handle)
 190 {
 191         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 192         int r;
 193
 194         r = jpeg_v3_0_hw_fini(adev);
 195         if (r)
 196                 return r;
 197
 198         r = amdgpu_jpeg_suspend(adev);
 199
 200         return r;
 201 }
 202
 203 /**
 204  * jpeg_v3_0_resume - resume JPEG block
 205  *
 206  * @handle: amdgpu_device pointer
 207  *
 208  * Resume firmware and hw init JPEG block
 209  */
 210 static int jpeg_v3_0_resume(void *handle)
 211 {
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213         int r;
 214
 215         r = amdgpu_jpeg_resume(adev);
 216         if (r)
 217                 return r;
 218
 219         r = jpeg_v3_0_hw_init(adev);
 220
 221         return r;
 222 }
 223
 224 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
 225 {
 226         uint32_t data = 0;
 227
 228         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 229         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 230                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 231         else
 232                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 233
 234         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 235         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 236         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 237
 238         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 239         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 240                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 241                 | JPEG_CGC_GATE__JPEG_ENC_MASK
 242                 | JPEG_CGC_GATE__JMCIF_MASK
 243                 | JPEG_CGC_GATE__JRBBM_MASK);
 244         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 245
 246         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 247         data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
 248                 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
 249                 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
 250                 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
 251         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 252 }
 253
 254 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
 255 {
 256         uint32_t data = 0;
 257
 258         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 259         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 260                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 261                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 262                 |JPEG_CGC_GATE__JMCIF_MASK
 263                 |JPEG_CGC_GATE__JRBBM_MASK);
 264         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 265 }
 266
 267 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
 268 {
 269         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 270                 uint32_t data = 0;
 271                 int r = 0;
 272
 273                 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 274                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 275
 276                 r = SOC15_WAIT_ON_RREG(JPEG, 0,
 277                         mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
 278                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 279
 280                 if (r) {
 281                         DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
 282                         return r;
 283                 }
 284         }
 285
 286         /* disable anti hang mechanism */
 287         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
 288                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 289
 290         /* keep the JPEG in static PG mode */
 291         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
 292                 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
 293
 294         return 0;
 295 }
 296
 297 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
 298 {
 299         /* enable anti hang mechanism */
 300         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
 301                 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
 302                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 303
 304         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 305                 uint32_t data = 0;
 306                 int r = 0;
 307
 308                 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 309                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 310
 311                 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
 312                         (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
 313                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 314
 315                 if (r) {
 316                         DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
 317                         return r;
 318                 }
 319         }
 320
 321         return 0;
 322 }
 323
 324 /**
 325  * jpeg_v3_0_start - start JPEG block
 326  *
 327  * @adev: amdgpu_device pointer
 328  *
 329  * Setup and start the JPEG block
 330  */
 331 static int jpeg_v3_0_start(struct amdgpu_device *adev)
 332 {
 333         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 334         int r;
 335
 336         if (adev->pm.dpm_enabled)
 337                 amdgpu_dpm_enable_jpeg(adev, true);
 338
 339         /* disable power gating */
 340         r = jpeg_v3_0_disable_static_power_gating(adev);
 341         if (r)
 342                 return r;
 343
 344         /* JPEG disable CGC */
 345         jpeg_v3_0_disable_clock_gating(adev);
 346
 347         /* MJPEG global tiling registers */
 348         WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
 349                 adev->gfx.config.gb_addr_config);
 350         WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
 351                 adev->gfx.config.gb_addr_config);
 352
 353         /* enable JMI channel */
 354         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
 355                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 356
 357         /* enable System Interrupt for JRBC */
 358         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
 359                 JPEG_SYS_INT_EN__DJRBC_MASK,
 360                 ~JPEG_SYS_INT_EN__DJRBC_MASK);
 361
 362         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 363         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 364         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 365                 lower_32_bits(ring->gpu_addr));
 366         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 367                 upper_32_bits(ring->gpu_addr));
 368         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
 369         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
 370         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 371         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 372         ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 373
 374         return 0;
 375 }
 376
 377 /**
 378  * jpeg_v3_0_stop - stop JPEG block
 379  *
 380  * @adev: amdgpu_device pointer
 381  *
 382  * stop the JPEG block
 383  */
 384 static int jpeg_v3_0_stop(struct amdgpu_device *adev)
 385 {
 386         int r;
 387
 388         /* reset JMI */
 389         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
 390                 UVD_JMI_CNTL__SOFT_RESET_MASK,
 391                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 392
 393         jpeg_v3_0_enable_clock_gating(adev);
 394
 395         /* enable power gating */
 396         r = jpeg_v3_0_enable_static_power_gating(adev);
 397         if (r)
 398                 return r;
 399
 400         if (adev->pm.dpm_enabled)
 401                 amdgpu_dpm_enable_jpeg(adev, false);
 402
 403         return 0;
 404 }
 405
 406 /**
 407  * jpeg_v3_0_dec_ring_get_rptr - get read pointer
 408  *
 409  * @ring: amdgpu_ring pointer
 410  *
 411  * Returns the current hardware read pointer
 412  */
 413 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 414 {
 415         struct amdgpu_device *adev = ring->adev;
 416
 417         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
 418 }
 419
 420 /**
 421  * jpeg_v3_0_dec_ring_get_wptr - get write pointer
 422  *
 423  * @ring: amdgpu_ring pointer
 424  *
 425  * Returns the current hardware write pointer
 426  */
 427 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 428 {
 429         struct amdgpu_device *adev = ring->adev;
 430
 431         if (ring->use_doorbell)
 432                 return *ring->wptr_cpu_addr;
 433         else
 434                 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 435 }
 436
 437 /**
 438  * jpeg_v3_0_dec_ring_set_wptr - set write pointer
 439  *
 440  * @ring: amdgpu_ring pointer
 441  *
 442  * Commits the write pointer to the hardware
 443  */
 444 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 445 {
 446         struct amdgpu_device *adev = ring->adev;
 447
 448         if (ring->use_doorbell) {
 449                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 450                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 451         } else {
 452                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 453         }
 454 }
 455
 456 static bool jpeg_v3_0_is_idle(void *handle)
 457 {
 458         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 459         int ret = 1;
 460
 461         ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
 462                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 463                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
 464
 465         return ret;
 466 }
 467
 468 static int jpeg_v3_0_wait_for_idle(void *handle)
 469 {
 470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 471
 472         return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
 473                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 474                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 475 }
 476
 477 static int jpeg_v3_0_set_clockgating_state(void *handle,
 478                                           enum amd_clockgating_state state)
 479 {
 480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 481         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 482
 483         if (enable) {
 484                 if (!jpeg_v3_0_is_idle(handle))
 485                         return -EBUSY;
 486                 jpeg_v3_0_enable_clock_gating(adev);
 487         } else {
 488                 jpeg_v3_0_disable_clock_gating(adev);
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int jpeg_v3_0_set_powergating_state(void *handle,
 495                                           enum amd_powergating_state state)
 496 {
 497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 498         int ret;
 499
 500         if(state == adev->jpeg.cur_state)
 501                 return 0;
 502
 503         if (state == AMD_PG_STATE_GATE)
 504                 ret = jpeg_v3_0_stop(adev);
 505         else
 506                 ret = jpeg_v3_0_start(adev);
 507
 508         if(!ret)
 509                 adev->jpeg.cur_state = state;
 510
 511         return ret;
 512 }
 513
 514 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
 515                                         struct amdgpu_irq_src *source,
 516                                         unsigned type,
 517                                         enum amdgpu_interrupt_state state)
 518 {
 519         return 0;
 520 }
 521
 522 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
 523                                       struct amdgpu_irq_src *source,
 524                                       struct amdgpu_iv_entry *entry)
 525 {
 526         DRM_DEBUG("IH: JPEG TRAP\n");
 527
 528         switch (entry->src_id) {
 529         case VCN_2_0__SRCID__JPEG_DECODE:
 530                 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
 531                 break;
 532         default:
 533                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 534                           entry->src_id, entry->src_data[0]);
 535                 break;
 536         }
 537
 538         return 0;
 539 }
 540
 541 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
 542         .name = "jpeg_v3_0",
 543         .early_init = jpeg_v3_0_early_init,
 544         .late_init = NULL,
 545         .sw_init = jpeg_v3_0_sw_init,
 546         .sw_fini = jpeg_v3_0_sw_fini,
 547         .hw_init = jpeg_v3_0_hw_init,
 548         .hw_fini = jpeg_v3_0_hw_fini,
 549         .suspend = jpeg_v3_0_suspend,
 550         .resume = jpeg_v3_0_resume,
 551         .is_idle = jpeg_v3_0_is_idle,
 552         .wait_for_idle = jpeg_v3_0_wait_for_idle,
 553         .check_soft_reset = NULL,
 554         .pre_soft_reset = NULL,
 555         .soft_reset = NULL,
 556         .post_soft_reset = NULL,
 557         .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
 558         .set_powergating_state = jpeg_v3_0_set_powergating_state,
 559 };
 560
 561 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
 562         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 563         .align_mask = 0xf,
 564         .get_rptr = jpeg_v3_0_dec_ring_get_rptr,
 565         .get_wptr = jpeg_v3_0_dec_ring_get_wptr,
 566         .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
 567         .emit_frame_size =
 568                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 569                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 570                 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
 571                 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
 572                 8 + 16,
 573         .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
 574         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 575         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 576         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 577         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 578         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 579         .insert_nop = jpeg_v2_0_dec_ring_nop,
 580         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 581         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 582         .pad_ib = amdgpu_ring_generic_pad_ib,
 583         .begin_use = amdgpu_jpeg_ring_begin_use,
 584         .end_use = amdgpu_jpeg_ring_end_use,
 585         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 586         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 587         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 588 };
 589
 590 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 591 {
 592         adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
 593         DRM_INFO("JPEG decode is enabled in VM mode\n");
 594 }
 595
 596 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
 597         .set = jpeg_v3_0_set_interrupt_state,
 598         .process = jpeg_v3_0_process_interrupt,
 599 };
 600
 601 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
 602 {
 603         adev->jpeg.inst->irq.num_types = 1;
 604         adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
 605 }
 606
 607 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
 608 {
 609         .type = AMD_IP_BLOCK_TYPE_JPEG,
 610         .major = 3,
 611         .minor = 0,
 612         .rev = 0,
 613         .funcs = &jpeg_v3_0_ip_funcs,
 614 };