drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "uvd/uvd_7_0_offset.h"
  41 #include "gc/gc_9_0_offset.h"
  42 #include "gc/gc_9_0_sh_mask.h"
  43 #include "sdma0/sdma0_4_0_offset.h"
  44 #include "sdma1/sdma1_4_0_offset.h"
  45 #include "nbio/nbio_7_0_default.h"
  46 #include "nbio/nbio_7_0_offset.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "nbio_v6_1.h"
  60 #include "nbio_v7_0.h"
  61 #include "nbio_v7_4.h"
  62 #include "hdp_v4_0.h"
  63 #include "vega10_ih.h"
  64 #include "vega20_ih.h"
  65 #include "navi10_ih.h"
  66 #include "sdma_v4_0.h"
  67 #include "uvd_v7_0.h"
  68 #include "vce_v4_0.h"
  69 #include "vcn_v1_0.h"
  70 #include "vcn_v2_0.h"
  71 #include "jpeg_v2_0.h"
  72 #include "vcn_v2_5.h"
  73 #include "jpeg_v2_5.h"
  74 #include "smuio_v9_0.h"
  75 #include "smuio_v11_0.h"
  76 #include "smuio_v13_0.h"
  77 #include "amdgpu_vkms.h"
  78 #include "mxgpu_ai.h"
  79 #include "amdgpu_ras.h"
  80 #include "amdgpu_xgmi.h"
  81 #include <uapi/linux/kfd_ioctl.h>
  82
  83 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  87
  88 static const struct amd_ip_funcs soc15_common_ip_funcs;
  89
  90 /* Vega, Raven, Arcturus */
  91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
  92 {
  93         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
  94         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
  95 };
  96
  97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
  98 {
  99         .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
 100         .codec_array = vega_video_codecs_encode_array,
 101 };
 102
 103 /* Vega */
 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
 105 {
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 111         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 112 };
 113
 114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
 115 {
 116         .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
 117         .codec_array = vega_video_codecs_decode_array,
 118 };
 119
 120 /* Raven */
 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
 122 {
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 124         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 125         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 126         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 127         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
 130 };
 131
 132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
 133 {
 134         .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
 135         .codec_array = rv_video_codecs_decode_array,
 136 };
 137
 138 /* Renoir, Arcturus */
 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
 140 {
 141         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 142         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 143         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 148 };
 149
 150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
 151 {
 152         .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
 153         .codec_array = rn_video_codecs_decode_array,
 154 };
 155
 156 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
 157         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 158         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 159         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 160         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 161         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 162 };
 163
 164 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
 165         .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
 166         .codec_array = vcn_4_0_3_video_codecs_decode_array,
 167 };
 168
 169 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
 170         .codec_count = 0,
 171         .codec_array = NULL,
 172 };
 173
 174 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = {
 175         .codec_count = 0,
 176         .codec_array = NULL,
 177 };
 178
 179 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = {
 180         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 181         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 182         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 183         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 184         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 185 };
 186
 187 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = {
 188         .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0),
 189         .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0,
 190 };
 191
 192 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 193                                     const struct amdgpu_video_codecs **codecs)
 194 {
 195         if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
 196                 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
 197                 case IP_VERSION(4, 0, 0):
 198                 case IP_VERSION(4, 1, 0):
 199                         if (encode)
 200                                 *codecs = &vega_video_codecs_encode;
 201                         else
 202                                 *codecs = &vega_video_codecs_decode;
 203                         return 0;
 204                 default:
 205                         return -EINVAL;
 206                 }
 207         } else {
 208                 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
 209                 case IP_VERSION(1, 0, 0):
 210                 case IP_VERSION(1, 0, 1):
 211                         if (encode)
 212                                 *codecs = &vega_video_codecs_encode;
 213                         else
 214                                 *codecs = &rv_video_codecs_decode;
 215                         return 0;
 216                 case IP_VERSION(2, 5, 0):
 217                 case IP_VERSION(2, 6, 0):
 218                 case IP_VERSION(2, 2, 0):
 219                         if (encode)
 220                                 *codecs = &vega_video_codecs_encode;
 221                         else
 222                                 *codecs = &rn_video_codecs_decode;
 223                         return 0;
 224                 case IP_VERSION(4, 0, 3):
 225                         if (encode)
 226                                 *codecs = &vcn_4_0_3_video_codecs_encode;
 227                         else
 228                                 *codecs = &vcn_4_0_3_video_codecs_decode;
 229                         return 0;
 230                 case IP_VERSION(5, 0, 1):
 231                         if (encode)
 232                                 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0;
 233                         else
 234                                 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0;
 235                         return 0;
 236                 default:
 237                         return -EINVAL;
 238                 }
 239         }
 240 }
 241
 242 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 243 {
 244         unsigned long flags, address, data;
 245         u32 r;
 246
 247         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 248         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 249
 250         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 251         WREG32(address, ((reg) & 0x1ff));
 252         r = RREG32(data);
 253         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 254         return r;
 255 }
 256
 257 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 258 {
 259         unsigned long flags, address, data;
 260
 261         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 262         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 263
 264         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 265         WREG32(address, ((reg) & 0x1ff));
 266         WREG32(data, (v));
 267         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 268 }
 269
 270 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 271 {
 272         unsigned long flags, address, data;
 273         u32 r;
 274
 275         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 276         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 277
 278         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 279         WREG32(address, (reg));
 280         r = RREG32(data);
 281         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 282         return r;
 283 }
 284
 285 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 286 {
 287         unsigned long flags, address, data;
 288
 289         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 290         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 291
 292         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 293         WREG32(address, (reg));
 294         WREG32(data, (v));
 295         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 296 }
 297
 298 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 299 {
 300         unsigned long flags;
 301         u32 r;
 302
 303         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 304         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 305         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 306         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 307         return r;
 308 }
 309
 310 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 311 {
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 315         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 316         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 317         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 318 }
 319
 320 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 321 {
 322         unsigned long flags;
 323         u32 r;
 324
 325         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 326         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 327         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 328         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 329         return r;
 330 }
 331
 332 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 333 {
 334         unsigned long flags;
 335
 336         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 337         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 338         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 339         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 340 }
 341
 342 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 343 {
 344         return adev->nbio.funcs->get_memsize(adev);
 345 }
 346
 347 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 348 {
 349         u32 reference_clock = adev->clock.spll.reference_freq;
 350
 351         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||
 352             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||
 353             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||
 354             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) ||
 355             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
 356                 return 10000;
 357         if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||
 358             amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))
 359                 return reference_clock / 4;
 360
 361         return reference_clock;
 362 }
 363
 364
 365 void soc15_grbm_select(struct amdgpu_device *adev,
 366                      u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
 367 {
 368         u32 grbm_gfx_cntl = 0;
 369         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 370         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 371         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 372         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 373
 374         WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 375 }
 376
 377 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 378 {
 379         /* todo */
 380         return false;
 381 }
 382
 383 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 384         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 385         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 386         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 387         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 388         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 389         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 390         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 391         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 392         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 393         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 394         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 395         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 396         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 397         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 398         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 399         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 400         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 401         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 402         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 403         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 404 };
 405
 406 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 407                                          u32 sh_num, u32 reg_offset)
 408 {
 409         uint32_t val;
 410
 411         mutex_lock(&adev->grbm_idx_mutex);
 412         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 413                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
 414
 415         val = RREG32(reg_offset);
 416
 417         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 418                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 419         mutex_unlock(&adev->grbm_idx_mutex);
 420         return val;
 421 }
 422
 423 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 424                                          bool indexed, u32 se_num,
 425                                          u32 sh_num, u32 reg_offset)
 426 {
 427         if (indexed) {
 428                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 429         } else {
 430                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 431                         return adev->gfx.config.gb_addr_config;
 432                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 433                         return adev->gfx.config.db_debug2;
 434                 return RREG32(reg_offset);
 435         }
 436 }
 437
 438 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 439                             u32 sh_num, u32 reg_offset, u32 *value)
 440 {
 441         uint32_t i;
 442         struct soc15_allowed_register_entry  *en;
 443
 444         *value = 0;
 445         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 446                 en = &soc15_allowed_read_registers[i];
 447                 if (!adev->reg_offset[en->hwip][en->inst])
 448                         continue;
 449                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 450                                         + en->reg_offset))
 451                         continue;
 452
 453                 *value = soc15_get_register_value(adev,
 454                                                   soc15_allowed_read_registers[i].grbm_indexed,
 455                                                   se_num, sh_num, reg_offset);
 456                 return 0;
 457         }
 458         return -EINVAL;
 459 }
 460
 461
 462 /**
 463  * soc15_program_register_sequence - program an array of registers.
 464  *
 465  * @adev: amdgpu_device pointer
 466  * @regs: pointer to the register array
 467  * @array_size: size of the register array
 468  *
 469  * Programs an array or registers with and and or masks.
 470  * This is a helper for setting golden registers.
 471  */
 472
 473 void soc15_program_register_sequence(struct amdgpu_device *adev,
 474                                              const struct soc15_reg_golden *regs,
 475                                              const u32 array_size)
 476 {
 477         const struct soc15_reg_golden *entry;
 478         u32 tmp, reg;
 479         int i;
 480
 481         for (i = 0; i < array_size; ++i) {
 482                 entry = &regs[i];
 483                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 484
 485                 if (entry->and_mask == 0xffffffff) {
 486                         tmp = entry->or_mask;
 487                 } else {
 488                         tmp = (entry->hwip == GC_HWIP) ?
 489                                 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
 490
 491                         tmp &= ~(entry->and_mask);
 492                         tmp |= (entry->or_mask & entry->and_mask);
 493                 }
 494
 495                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 496                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 497                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 498                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 499                         WREG32_RLC(reg, tmp);
 500                 else
 501                         (entry->hwip == GC_HWIP) ?
 502                                 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 503
 504         }
 505
 506 }
 507
 508 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 509 {
 510         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 511         int ret = 0;
 512
 513         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 514         if (ras && adev->ras_enabled)
 515                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 516
 517         ret = amdgpu_dpm_baco_reset(adev);
 518         if (ret)
 519                 return ret;
 520
 521         /* re-enable doorbell interrupt after BACO exit */
 522         if (ras && adev->ras_enabled)
 523                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 524
 525         return 0;
 526 }
 527
 528 static enum amd_reset_method
 529 soc15_asic_reset_method(struct amdgpu_device *adev)
 530 {
 531         int baco_reset = 0;
 532         bool connected_to_cpu = false;
 533         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 534
 535         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
 536                 connected_to_cpu = true;
 537
 538         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 539             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 540             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 541             amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
 542                 /* If connected to cpu, driver only support mode2 */
 543                 if (connected_to_cpu)
 544                         return AMD_RESET_METHOD_MODE2;
 545                 return amdgpu_reset_method;
 546         }
 547
 548         if (amdgpu_reset_method != -1)
 549                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 550                                   amdgpu_reset_method);
 551
 552         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 553         case IP_VERSION(10, 0, 0):
 554         case IP_VERSION(10, 0, 1):
 555         case IP_VERSION(12, 0, 0):
 556         case IP_VERSION(12, 0, 1):
 557                 return AMD_RESET_METHOD_MODE2;
 558         case IP_VERSION(9, 0, 0):
 559         case IP_VERSION(11, 0, 2):
 560                 if (adev->asic_type == CHIP_VEGA20) {
 561                         if (adev->psp.sos.fw_version >= 0x80067)
 562                                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 563                         /*
 564                          * 1. PMFW version > 0x284300: all cases use baco
 565                          * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 566                          */
 567                         if (ras && adev->ras_enabled &&
 568                             adev->pm.fw_version <= 0x283400)
 569                                 baco_reset = 0;
 570                 } else {
 571                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 572                 }
 573                 break;
 574         case IP_VERSION(13, 0, 2):
 575                  /*
 576                  * 1.connected to cpu: driver issue mode2 reset
 577                  * 2.discret gpu: driver issue mode1 reset
 578                  */
 579                 if (connected_to_cpu)
 580                         return AMD_RESET_METHOD_MODE2;
 581                 break;
 582         case IP_VERSION(13, 0, 6):
 583         case IP_VERSION(13, 0, 14):
 584         case IP_VERSION(13, 0, 12):
 585                 /* Use gpu_recovery param to target a reset method.
 586                  * Enable triggering of GPU reset only if specified
 587                  * by module parameter.
 588                  */
 589                 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
 590                         return AMD_RESET_METHOD_MODE2;
 591                 else if (!(adev->flags & AMD_IS_APU))
 592                         return AMD_RESET_METHOD_MODE1;
 593                 else
 594                         return AMD_RESET_METHOD_MODE2;
 595         default:
 596                 break;
 597         }
 598
 599         if (baco_reset)
 600                 return AMD_RESET_METHOD_BACO;
 601         else
 602                 return AMD_RESET_METHOD_MODE1;
 603 }
 604
 605 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
 606 {
 607         /* Will reset for the following suspend abort cases.
 608          * 1) Only reset on APU side, dGPU hasn't checked yet.
 609          * 2) S3 suspend aborted in the normal S3 suspend or
 610          *    performing pm core test.
 611          */
 612         if (adev->flags & AMD_IS_APU && adev->in_s3 &&
 613                         !pm_resume_via_firmware())
 614                 return true;
 615         else
 616                 return false;
 617 }
 618
 619 static int soc15_asic_reset(struct amdgpu_device *adev)
 620 {
 621         /* original raven doesn't have full asic reset */
 622         /* On the latest Raven, the GPU reset can be performed
 623          * successfully. So now, temporarily enable it for the
 624          * S3 suspend abort case.
 625          */
 626
 627         if ((adev->apu_flags & AMD_APU_IS_PICASSO ||
 628                         !(adev->apu_flags & AMD_APU_IS_RAVEN)) &&
 629                         soc15_need_reset_on_resume(adev))
 630                 goto asic_reset;
 631
 632         if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
 633                         (adev->apu_flags & AMD_APU_IS_RAVEN2))
 634                 return 0;
 635
 636 asic_reset:
 637         switch (soc15_asic_reset_method(adev)) {
 638         case AMD_RESET_METHOD_PCI:
 639                 dev_info(adev->dev, "PCI reset\n");
 640                 return amdgpu_device_pci_reset(adev);
 641         case AMD_RESET_METHOD_BACO:
 642                 dev_info(adev->dev, "BACO reset\n");
 643                 return soc15_asic_baco_reset(adev);
 644         case AMD_RESET_METHOD_MODE2:
 645                 dev_info(adev->dev, "MODE2 reset\n");
 646                 return amdgpu_dpm_mode2_reset(adev);
 647         default:
 648                 dev_info(adev->dev, "MODE1 reset\n");
 649                 return amdgpu_device_mode1_reset(adev);
 650         }
 651 }
 652
 653 static int soc15_supports_baco(struct amdgpu_device *adev)
 654 {
 655         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 656         case IP_VERSION(9, 0, 0):
 657         case IP_VERSION(11, 0, 2):
 658                 if (adev->asic_type == CHIP_VEGA20) {
 659                         if (adev->psp.sos.fw_version >= 0x80067)
 660                                 return amdgpu_dpm_is_baco_supported(adev);
 661                         return 0;
 662                 } else {
 663                         return amdgpu_dpm_is_baco_supported(adev);
 664                 }
 665                 break;
 666         default:
 667                 return 0;
 668         }
 669 }
 670
 671 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 672                         u32 cntl_reg, u32 status_reg)
 673 {
 674         return 0;
 675 }*/
 676
 677 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 678 {
 679         /*int r;
 680
 681         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 682         if (r)
 683                 return r;
 684
 685         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 686         */
 687         return 0;
 688 }
 689
 690 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 691 {
 692         /* todo */
 693
 694         return 0;
 695 }
 696
 697 static void soc15_program_aspm(struct amdgpu_device *adev)
 698 {
 699         if (!amdgpu_device_should_use_aspm(adev))
 700                 return;
 701
 702         if (adev->nbio.funcs->program_aspm)
 703                 adev->nbio.funcs->program_aspm(adev);
 704 }
 705
 706 const struct amdgpu_ip_block_version vega10_common_ip_block =
 707 {
 708         .type = AMD_IP_BLOCK_TYPE_COMMON,
 709         .major = 2,
 710         .minor = 0,
 711         .rev = 0,
 712         .funcs = &soc15_common_ip_funcs,
 713 };
 714
 715 static void soc15_reg_base_init(struct amdgpu_device *adev)
 716 {
 717         /* Set IP register base before any HW register access */
 718         switch (adev->asic_type) {
 719         case CHIP_VEGA10:
 720         case CHIP_VEGA12:
 721         case CHIP_RAVEN:
 722         case CHIP_RENOIR:
 723                 vega10_reg_base_init(adev);
 724                 break;
 725         case CHIP_VEGA20:
 726                 vega20_reg_base_init(adev);
 727                 break;
 728         case CHIP_ARCTURUS:
 729                 arct_reg_base_init(adev);
 730                 break;
 731         case CHIP_ALDEBARAN:
 732                 aldebaran_reg_base_init(adev);
 733                 break;
 734         default:
 735                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 736                 break;
 737         }
 738 }
 739
 740 void soc15_set_virt_ops(struct amdgpu_device *adev)
 741 {
 742         adev->virt.ops = &xgpu_ai_virt_ops;
 743
 744         /* init soc15 reg base early enough so we can
 745          * request request full access for sriov before
 746          * set_ip_blocks. */
 747         soc15_reg_base_init(adev);
 748 }
 749
 750 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 751 {
 752         /* change this when we implement soft reset */
 753         return true;
 754 }
 755
 756 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 757                                  uint64_t *count1)
 758 {
 759         uint32_t perfctr = 0;
 760         uint64_t cnt0_of, cnt1_of;
 761         int tmp;
 762
 763         /* This reports 0 on APUs, so return to avoid writing/reading registers
 764          * that may or may not be different from their GPU counterparts
 765          */
 766         if (adev->flags & AMD_IS_APU)
 767                 return;
 768
 769         /* Set the 2 events that we wish to watch, defined above */
 770         /* Reg 40 is # received msgs */
 771         /* Reg 104 is # of posted requests sent */
 772         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 773         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 774
 775         /* Write to enable desired perf counters */
 776         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 777         /* Zero out and enable the perf counters
 778          * Write 0x5:
 779          * Bit 0 = Start all counters(1)
 780          * Bit 2 = Global counter reset enable(1)
 781          */
 782         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 783
 784         msleep(1000);
 785
 786         /* Load the shadow and disable the perf counters
 787          * Write 0x2:
 788          * Bit 0 = Stop counters(0)
 789          * Bit 1 = Load the shadow counters(1)
 790          */
 791         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 792
 793         /* Read register values to get any >32bit overflow */
 794         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 795         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 796         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 797
 798         /* Get the values and add the overflow */
 799         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 800         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 801 }
 802
 803 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 804                                  uint64_t *count1)
 805 {
 806         uint32_t perfctr = 0;
 807         uint64_t cnt0_of, cnt1_of;
 808         int tmp;
 809
 810         /* This reports 0 on APUs, so return to avoid writing/reading registers
 811          * that may or may not be different from their GPU counterparts
 812          */
 813         if (adev->flags & AMD_IS_APU)
 814                 return;
 815
 816         /* Set the 2 events that we wish to watch, defined above */
 817         /* Reg 40 is # received msgs */
 818         /* Reg 108 is # of posted requests sent on VG20 */
 819         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 820                                 EVENT0_SEL, 40);
 821         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 822                                 EVENT1_SEL, 108);
 823
 824         /* Write to enable desired perf counters */
 825         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 826         /* Zero out and enable the perf counters
 827          * Write 0x5:
 828          * Bit 0 = Start all counters(1)
 829          * Bit 2 = Global counter reset enable(1)
 830          */
 831         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 832
 833         msleep(1000);
 834
 835         /* Load the shadow and disable the perf counters
 836          * Write 0x2:
 837          * Bit 0 = Stop counters(0)
 838          * Bit 1 = Load the shadow counters(1)
 839          */
 840         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 841
 842         /* Read register values to get any >32bit overflow */
 843         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 844         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 845         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 846
 847         /* Get the values and add the overflow */
 848         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 849         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 850 }
 851
 852 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 853 {
 854         u32 sol_reg;
 855
 856         /* CP hangs in IGT reloading test on RN, reset to WA */
 857         if (adev->asic_type == CHIP_RENOIR)
 858                 return true;
 859
 860         if (amdgpu_gmc_need_reset_on_init(adev))
 861                 return true;
 862         if (amdgpu_psp_tos_reload_needed(adev))
 863                 return true;
 864         /* Just return false for soc15 GPUs.  Reset does not seem to
 865          * be necessary.
 866          */
 867         if (!amdgpu_passthrough(adev))
 868                 return false;
 869
 870         if (adev->flags & AMD_IS_APU)
 871                 return false;
 872
 873         /* Check sOS sign of life register to confirm sys driver and sOS
 874          * are already been loaded.
 875          */
 876         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 877         if (sol_reg)
 878                 return true;
 879
 880         return false;
 881 }
 882
 883 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 884 {
 885         uint64_t nak_r, nak_g;
 886
 887         /* Get the number of NAKs received and generated */
 888         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 889         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 890
 891         /* Add the total number of NAKs, i.e the number of replays */
 892         return (nak_r + nak_g);
 893 }
 894
 895 static void soc15_pre_asic_init(struct amdgpu_device *adev)
 896 {
 897         gmc_v9_0_restore_registers(adev);
 898 }
 899
 900 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 901 {
 902         .read_disabled_bios = &soc15_read_disabled_bios,
 903         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 904         .read_register = &soc15_read_register,
 905         .reset = &soc15_asic_reset,
 906         .reset_method = &soc15_asic_reset_method,
 907         .get_xclk = &soc15_get_xclk,
 908         .set_uvd_clocks = &soc15_set_uvd_clocks,
 909         .set_vce_clocks = &soc15_set_vce_clocks,
 910         .get_config_memsize = &soc15_get_config_memsize,
 911         .need_full_reset = &soc15_need_full_reset,
 912         .init_doorbell_index = &vega10_doorbell_index_init,
 913         .get_pcie_usage = &soc15_get_pcie_usage,
 914         .need_reset_on_init = &soc15_need_reset_on_init,
 915         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 916         .supports_baco = &soc15_supports_baco,
 917         .pre_asic_init = &soc15_pre_asic_init,
 918         .query_video_codecs = &soc15_query_video_codecs,
 919 };
 920
 921 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 922 {
 923         .read_disabled_bios = &soc15_read_disabled_bios,
 924         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 925         .read_register = &soc15_read_register,
 926         .reset = &soc15_asic_reset,
 927         .reset_method = &soc15_asic_reset_method,
 928         .get_xclk = &soc15_get_xclk,
 929         .set_uvd_clocks = &soc15_set_uvd_clocks,
 930         .set_vce_clocks = &soc15_set_vce_clocks,
 931         .get_config_memsize = &soc15_get_config_memsize,
 932         .need_full_reset = &soc15_need_full_reset,
 933         .init_doorbell_index = &vega20_doorbell_index_init,
 934         .get_pcie_usage = &vega20_get_pcie_usage,
 935         .need_reset_on_init = &soc15_need_reset_on_init,
 936         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 937         .supports_baco = &soc15_supports_baco,
 938         .pre_asic_init = &soc15_pre_asic_init,
 939         .query_video_codecs = &soc15_query_video_codecs,
 940 };
 941
 942 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
 943 {
 944         .read_disabled_bios = &soc15_read_disabled_bios,
 945         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 946         .read_register = &soc15_read_register,
 947         .reset = &soc15_asic_reset,
 948         .reset_method = &soc15_asic_reset_method,
 949         .get_xclk = &soc15_get_xclk,
 950         .set_uvd_clocks = &soc15_set_uvd_clocks,
 951         .set_vce_clocks = &soc15_set_vce_clocks,
 952         .get_config_memsize = &soc15_get_config_memsize,
 953         .need_full_reset = &soc15_need_full_reset,
 954         .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
 955         .need_reset_on_init = &soc15_need_reset_on_init,
 956         .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
 957         .supports_baco = &soc15_supports_baco,
 958         .pre_asic_init = &soc15_pre_asic_init,
 959         .query_video_codecs = &soc15_query_video_codecs,
 960         .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
 961         .get_reg_state = &aqua_vanjaram_get_reg_state,
 962 };
 963
 964 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block)
 965 {
 966         struct amdgpu_device *adev = ip_block->adev;
 967
 968         adev->nbio.funcs->set_reg_remap(adev);
 969         adev->smc_rreg = NULL;
 970         adev->smc_wreg = NULL;
 971         adev->pcie_rreg = &amdgpu_device_indirect_rreg;
 972         adev->pcie_wreg = &amdgpu_device_indirect_wreg;
 973         adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
 974         adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
 975         adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
 976         adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
 977         adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
 978         adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
 979         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 980         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 981         adev->didt_rreg = &soc15_didt_rreg;
 982         adev->didt_wreg = &soc15_didt_wreg;
 983         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 984         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 985         adev->se_cac_rreg = &soc15_se_cac_rreg;
 986         adev->se_cac_wreg = &soc15_se_cac_wreg;
 987
 988         adev->rev_id = amdgpu_device_get_rev_id(adev);
 989         adev->external_rev_id = 0xFF;
 990         /* TODO: split the GC and PG flags based on the relevant IP version for which
 991          * they are relevant.
 992          */
 993         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 994         case IP_VERSION(9, 0, 1):
 995                 adev->asic_funcs = &soc15_asic_funcs;
 996                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 997                         AMD_CG_SUPPORT_GFX_MGLS |
 998                         AMD_CG_SUPPORT_GFX_RLC_LS |
 999                         AMD_CG_SUPPORT_GFX_CP_LS |
1000                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1001                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1002                         AMD_CG_SUPPORT_GFX_CGCG |
1003                         AMD_CG_SUPPORT_GFX_CGLS |
1004                         AMD_CG_SUPPORT_BIF_MGCG |
1005                         AMD_CG_SUPPORT_BIF_LS |
1006                         AMD_CG_SUPPORT_HDP_LS |
1007                         AMD_CG_SUPPORT_DRM_MGCG |
1008                         AMD_CG_SUPPORT_DRM_LS |
1009                         AMD_CG_SUPPORT_ROM_MGCG |
1010                         AMD_CG_SUPPORT_DF_MGCG |
1011                         AMD_CG_SUPPORT_SDMA_MGCG |
1012                         AMD_CG_SUPPORT_SDMA_LS |
1013                         AMD_CG_SUPPORT_MC_MGCG |
1014                         AMD_CG_SUPPORT_MC_LS;
1015                 adev->pg_flags = 0;
1016                 adev->external_rev_id = 0x1;
1017                 break;
1018         case IP_VERSION(9, 2, 1):
1019                 adev->asic_funcs = &soc15_asic_funcs;
1020                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1021                         AMD_CG_SUPPORT_GFX_MGLS |
1022                         AMD_CG_SUPPORT_GFX_CGCG |
1023                         AMD_CG_SUPPORT_GFX_CGLS |
1024                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1025                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1026                         AMD_CG_SUPPORT_GFX_CP_LS |
1027                         AMD_CG_SUPPORT_MC_LS |
1028                         AMD_CG_SUPPORT_MC_MGCG |
1029                         AMD_CG_SUPPORT_SDMA_MGCG |
1030                         AMD_CG_SUPPORT_SDMA_LS |
1031                         AMD_CG_SUPPORT_BIF_MGCG |
1032                         AMD_CG_SUPPORT_BIF_LS |
1033                         AMD_CG_SUPPORT_HDP_MGCG |
1034                         AMD_CG_SUPPORT_HDP_LS |
1035                         AMD_CG_SUPPORT_ROM_MGCG |
1036                         AMD_CG_SUPPORT_VCE_MGCG |
1037                         AMD_CG_SUPPORT_UVD_MGCG;
1038                 adev->pg_flags = 0;
1039                 adev->external_rev_id = adev->rev_id + 0x14;
1040                 break;
1041         case IP_VERSION(9, 4, 0):
1042                 adev->asic_funcs = &vega20_asic_funcs;
1043                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1044                         AMD_CG_SUPPORT_GFX_MGLS |
1045                         AMD_CG_SUPPORT_GFX_CGCG |
1046                         AMD_CG_SUPPORT_GFX_CGLS |
1047                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1048                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1049                         AMD_CG_SUPPORT_GFX_CP_LS |
1050                         AMD_CG_SUPPORT_MC_LS |
1051                         AMD_CG_SUPPORT_MC_MGCG |
1052                         AMD_CG_SUPPORT_SDMA_MGCG |
1053                         AMD_CG_SUPPORT_SDMA_LS |
1054                         AMD_CG_SUPPORT_BIF_MGCG |
1055                         AMD_CG_SUPPORT_BIF_LS |
1056                         AMD_CG_SUPPORT_HDP_MGCG |
1057                         AMD_CG_SUPPORT_HDP_LS |
1058                         AMD_CG_SUPPORT_ROM_MGCG |
1059                         AMD_CG_SUPPORT_VCE_MGCG |
1060                         AMD_CG_SUPPORT_UVD_MGCG;
1061                 adev->pg_flags = 0;
1062                 adev->external_rev_id = adev->rev_id + 0x28;
1063                 break;
1064         case IP_VERSION(9, 1, 0):
1065         case IP_VERSION(9, 2, 2):
1066                 adev->asic_funcs = &soc15_asic_funcs;
1067
1068                 if (adev->rev_id >= 0x8)
1069                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
1070
1071                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1072                         adev->external_rev_id = adev->rev_id + 0x79;
1073                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1074                         adev->external_rev_id = adev->rev_id + 0x41;
1075                 else if (adev->rev_id == 1)
1076                         adev->external_rev_id = adev->rev_id + 0x20;
1077                 else
1078                         adev->external_rev_id = adev->rev_id + 0x01;
1079
1080                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1081                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1082                                 AMD_CG_SUPPORT_GFX_MGLS |
1083                                 AMD_CG_SUPPORT_GFX_CP_LS |
1084                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1085                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1086                                 AMD_CG_SUPPORT_GFX_CGCG |
1087                                 AMD_CG_SUPPORT_GFX_CGLS |
1088                                 AMD_CG_SUPPORT_BIF_LS |
1089                                 AMD_CG_SUPPORT_HDP_LS |
1090                                 AMD_CG_SUPPORT_MC_MGCG |
1091                                 AMD_CG_SUPPORT_MC_LS |
1092                                 AMD_CG_SUPPORT_SDMA_MGCG |
1093                                 AMD_CG_SUPPORT_SDMA_LS |
1094                                 AMD_CG_SUPPORT_VCN_MGCG;
1095
1096                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1097                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1098                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1099                                 AMD_CG_SUPPORT_GFX_MGLS |
1100                                 AMD_CG_SUPPORT_GFX_CP_LS |
1101                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1102                                 AMD_CG_SUPPORT_GFX_CGCG |
1103                                 AMD_CG_SUPPORT_GFX_CGLS |
1104                                 AMD_CG_SUPPORT_BIF_LS |
1105                                 AMD_CG_SUPPORT_HDP_LS |
1106                                 AMD_CG_SUPPORT_MC_MGCG |
1107                                 AMD_CG_SUPPORT_MC_LS |
1108                                 AMD_CG_SUPPORT_SDMA_MGCG |
1109                                 AMD_CG_SUPPORT_SDMA_LS |
1110                                 AMD_CG_SUPPORT_VCN_MGCG;
1111
1112                         /*
1113                          * MMHUB PG needs to be disabled for Picasso for
1114                          * stability reasons.
1115                          */
1116                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1117                                 AMD_PG_SUPPORT_VCN;
1118                 } else {
1119                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1120                                 AMD_CG_SUPPORT_GFX_MGLS |
1121                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1122                                 AMD_CG_SUPPORT_GFX_CP_LS |
1123                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1124                                 AMD_CG_SUPPORT_GFX_CGCG |
1125                                 AMD_CG_SUPPORT_GFX_CGLS |
1126                                 AMD_CG_SUPPORT_BIF_MGCG |
1127                                 AMD_CG_SUPPORT_BIF_LS |
1128                                 AMD_CG_SUPPORT_HDP_MGCG |
1129                                 AMD_CG_SUPPORT_HDP_LS |
1130                                 AMD_CG_SUPPORT_DRM_MGCG |
1131                                 AMD_CG_SUPPORT_DRM_LS |
1132                                 AMD_CG_SUPPORT_MC_MGCG |
1133                                 AMD_CG_SUPPORT_MC_LS |
1134                                 AMD_CG_SUPPORT_SDMA_MGCG |
1135                                 AMD_CG_SUPPORT_SDMA_LS |
1136                                 AMD_CG_SUPPORT_VCN_MGCG;
1137
1138                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1139                 }
1140                 break;
1141         case IP_VERSION(9, 4, 1):
1142                 adev->asic_funcs = &vega20_asic_funcs;
1143                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1144                         AMD_CG_SUPPORT_GFX_MGLS |
1145                         AMD_CG_SUPPORT_GFX_CGCG |
1146                         AMD_CG_SUPPORT_GFX_CGLS |
1147                         AMD_CG_SUPPORT_GFX_CP_LS |
1148                         AMD_CG_SUPPORT_HDP_MGCG |
1149                         AMD_CG_SUPPORT_HDP_LS |
1150                         AMD_CG_SUPPORT_SDMA_MGCG |
1151                         AMD_CG_SUPPORT_SDMA_LS |
1152                         AMD_CG_SUPPORT_MC_MGCG |
1153                         AMD_CG_SUPPORT_MC_LS |
1154                         AMD_CG_SUPPORT_IH_CG |
1155                         AMD_CG_SUPPORT_VCN_MGCG |
1156                         AMD_CG_SUPPORT_JPEG_MGCG;
1157                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1158                 adev->external_rev_id = adev->rev_id + 0x32;
1159                 break;
1160         case IP_VERSION(9, 3, 0):
1161                 adev->asic_funcs = &soc15_asic_funcs;
1162
1163                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1164                         adev->external_rev_id = adev->rev_id + 0x91;
1165                 else
1166                         adev->external_rev_id = adev->rev_id + 0xa1;
1167                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1168                                  AMD_CG_SUPPORT_GFX_MGLS |
1169                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1170                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1171                                  AMD_CG_SUPPORT_GFX_CGCG |
1172                                  AMD_CG_SUPPORT_GFX_CGLS |
1173                                  AMD_CG_SUPPORT_GFX_CP_LS |
1174                                  AMD_CG_SUPPORT_MC_MGCG |
1175                                  AMD_CG_SUPPORT_MC_LS |
1176                                  AMD_CG_SUPPORT_SDMA_MGCG |
1177                                  AMD_CG_SUPPORT_SDMA_LS |
1178                                  AMD_CG_SUPPORT_BIF_LS |
1179                                  AMD_CG_SUPPORT_HDP_LS |
1180                                  AMD_CG_SUPPORT_VCN_MGCG |
1181                                  AMD_CG_SUPPORT_JPEG_MGCG |
1182                                  AMD_CG_SUPPORT_IH_CG |
1183                                  AMD_CG_SUPPORT_ATHUB_LS |
1184                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1185                                  AMD_CG_SUPPORT_DF_MGCG;
1186                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1187                                  AMD_PG_SUPPORT_VCN |
1188                                  AMD_PG_SUPPORT_JPEG |
1189                                  AMD_PG_SUPPORT_VCN_DPG;
1190                 break;
1191         case IP_VERSION(9, 4, 2):
1192                 adev->asic_funcs = &vega20_asic_funcs;
1193                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1194                         AMD_CG_SUPPORT_GFX_MGLS |
1195                         AMD_CG_SUPPORT_GFX_CP_LS |
1196                         AMD_CG_SUPPORT_HDP_LS |
1197                         AMD_CG_SUPPORT_SDMA_MGCG |
1198                         AMD_CG_SUPPORT_SDMA_LS |
1199                         AMD_CG_SUPPORT_IH_CG |
1200                         AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1201                 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1202                 adev->external_rev_id = adev->rev_id + 0x3c;
1203                 break;
1204         case IP_VERSION(9, 4, 3):
1205         case IP_VERSION(9, 4, 4):
1206         case IP_VERSION(9, 5, 0):
1207                 adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1208                 adev->cg_flags =
1209                         AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1210                         AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
1211                         AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
1212                         AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
1213                         AMD_CG_SUPPORT_IH_CG;
1214                 adev->pg_flags =
1215                         AMD_PG_SUPPORT_VCN |
1216                         AMD_PG_SUPPORT_VCN_DPG |
1217                         AMD_PG_SUPPORT_JPEG;
1218                 /*TODO: need a new external_rev_id for GC 9.4.4? */
1219                 adev->external_rev_id = adev->rev_id + 0x46;
1220                 break;
1221         default:
1222                 /* FIXME: not supported yet */
1223                 return -EINVAL;
1224         }
1225
1226         if (amdgpu_sriov_vf(adev)) {
1227                 amdgpu_virt_init_setting(adev);
1228                 xgpu_ai_mailbox_set_irq_funcs(adev);
1229         }
1230
1231         return 0;
1232 }
1233
1234 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block)
1235 {
1236         struct amdgpu_device *adev = ip_block->adev;
1237
1238         if (amdgpu_sriov_vf(adev))
1239                 xgpu_ai_mailbox_get_irq(adev);
1240
1241         /* Enable selfring doorbell aperture late because doorbell BAR
1242          * aperture will change if resize BAR successfully in gmc sw_init.
1243          */
1244         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1245
1246         return 0;
1247 }
1248
1249 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block)
1250 {
1251         struct amdgpu_device *adev = ip_block->adev;
1252
1253         if (amdgpu_sriov_vf(adev))
1254                 xgpu_ai_mailbox_add_irq_id(adev);
1255
1256         if (adev->df.funcs &&
1257             adev->df.funcs->sw_init)
1258                 adev->df.funcs->sw_init(adev);
1259
1260         return 0;
1261 }
1262
1263 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block)
1264 {
1265         struct amdgpu_device *adev = ip_block->adev;
1266
1267         if (adev->df.funcs &&
1268             adev->df.funcs->sw_fini)
1269                 adev->df.funcs->sw_fini(adev);
1270         return 0;
1271 }
1272
1273 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1274 {
1275         int i;
1276
1277         /* sdma doorbell range is programed by hypervisor */
1278         if (!amdgpu_sriov_vf(adev)) {
1279                 for (i = 0; i < adev->sdma.num_instances; i++) {
1280                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1281                                 true, adev->doorbell_index.sdma_engine[i] << 1,
1282                                 adev->doorbell_index.sdma_doorbell_range);
1283                 }
1284         }
1285 }
1286
1287 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block)
1288 {
1289         struct amdgpu_device *adev = ip_block->adev;
1290
1291         /* enable aspm */
1292         soc15_program_aspm(adev);
1293         /* setup nbio registers */
1294         adev->nbio.funcs->init_registers(adev);
1295         /* remap HDP registers to a hole in mmio space,
1296          * for the purpose of expose those registers
1297          * to process space
1298          */
1299         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1300                 adev->nbio.funcs->remap_hdp_registers(adev);
1301
1302         /* enable the doorbell aperture */
1303         adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1304
1305         /* HW doorbell routing policy: doorbell writing not
1306          * in SDMA/IH/MM/ACV range will be routed to CP. So
1307          * we need to init SDMA doorbell range prior
1308          * to CP ip block init and ring test.  IH already
1309          * happens before CP.
1310          */
1311         soc15_sdma_doorbell_range_init(adev);
1312
1313         return 0;
1314 }
1315
1316 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block)
1317 {
1318         struct amdgpu_device *adev = ip_block->adev;
1319
1320         /* Disable the doorbell aperture and selfring doorbell aperture
1321          * separately in hw_fini because soc15_enable_doorbell_aperture
1322          * has been removed and there is no need to delay disabling
1323          * selfring doorbell.
1324          */
1325         adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1326         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1327
1328         if (amdgpu_sriov_vf(adev))
1329                 xgpu_ai_mailbox_put_irq(adev);
1330
1331         /*
1332          * For minimal init, late_init is not called, hence RAS irqs are not
1333          * enabled.
1334          */
1335         if ((!amdgpu_sriov_vf(adev)) &&
1336             (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &&
1337             adev->nbio.ras_if &&
1338             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1339                 if (adev->nbio.ras &&
1340                     adev->nbio.ras->init_ras_controller_interrupt)
1341                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1342                 if (adev->nbio.ras &&
1343                     adev->nbio.ras->init_ras_err_event_athub_interrupt)
1344                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block)
1351 {
1352         return soc15_common_hw_fini(ip_block);
1353 }
1354
1355 static int soc15_common_resume(struct amdgpu_ip_block *ip_block)
1356 {
1357         struct amdgpu_device *adev = ip_block->adev;
1358
1359         if (soc15_need_reset_on_resume(adev)) {
1360                 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");
1361                 soc15_asic_reset(adev);
1362         }
1363         return soc15_common_hw_init(ip_block);
1364 }
1365
1366 static bool soc15_common_is_idle(void *handle)
1367 {
1368         return true;
1369 }
1370
1371 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1372 {
1373         uint32_t def, data;
1374
1375         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1376
1377         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1378                 data &= ~(0x01000000 |
1379                           0x02000000 |
1380                           0x04000000 |
1381                           0x08000000 |
1382                           0x10000000 |
1383                           0x20000000 |
1384                           0x40000000 |
1385                           0x80000000);
1386         else
1387                 data |= (0x01000000 |
1388                          0x02000000 |
1389                          0x04000000 |
1390                          0x08000000 |
1391                          0x10000000 |
1392                          0x20000000 |
1393                          0x40000000 |
1394                          0x80000000);
1395
1396         if (def != data)
1397                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1398 }
1399
1400 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1401 {
1402         uint32_t def, data;
1403
1404         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1405
1406         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1407                 data |= 1;
1408         else
1409                 data &= ~1;
1410
1411         if (def != data)
1412                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1413 }
1414
1415 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1416                                             enum amd_clockgating_state state)
1417 {
1418         struct amdgpu_device *adev = ip_block->adev;
1419
1420         if (amdgpu_sriov_vf(adev))
1421                 return 0;
1422
1423         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1424         case IP_VERSION(6, 1, 0):
1425         case IP_VERSION(6, 2, 0):
1426         case IP_VERSION(7, 4, 0):
1427                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1428                                 state == AMD_CG_STATE_GATE);
1429                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1430                                 state == AMD_CG_STATE_GATE);
1431                 adev->hdp.funcs->update_clock_gating(adev,
1432                                 state == AMD_CG_STATE_GATE);
1433                 soc15_update_drm_clock_gating(adev,
1434                                 state == AMD_CG_STATE_GATE);
1435                 soc15_update_drm_light_sleep(adev,
1436                                 state == AMD_CG_STATE_GATE);
1437                 adev->smuio.funcs->update_rom_clock_gating(adev,
1438                                 state == AMD_CG_STATE_GATE);
1439                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1440                                 state == AMD_CG_STATE_GATE);
1441                 break;
1442         case IP_VERSION(7, 0, 0):
1443         case IP_VERSION(7, 0, 1):
1444         case IP_VERSION(2, 5, 0):
1445                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1446                                 state == AMD_CG_STATE_GATE);
1447                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1448                                 state == AMD_CG_STATE_GATE);
1449                 adev->hdp.funcs->update_clock_gating(adev,
1450                                 state == AMD_CG_STATE_GATE);
1451                 soc15_update_drm_clock_gating(adev,
1452                                 state == AMD_CG_STATE_GATE);
1453                 soc15_update_drm_light_sleep(adev,
1454                                 state == AMD_CG_STATE_GATE);
1455                 break;
1456         case IP_VERSION(7, 4, 1):
1457         case IP_VERSION(7, 4, 4):
1458                 adev->hdp.funcs->update_clock_gating(adev,
1459                                 state == AMD_CG_STATE_GATE);
1460                 break;
1461         default:
1462                 break;
1463         }
1464         return 0;
1465 }
1466
1467 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1468 {
1469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1470         int data;
1471
1472         if (amdgpu_sriov_vf(adev))
1473                 *flags = 0;
1474
1475         if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1476                 adev->nbio.funcs->get_clockgating_state(adev, flags);
1477
1478         if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1479                 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1480
1481         if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
1482             (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&
1483             (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) &&
1484             (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {
1485                 /* AMD_CG_SUPPORT_DRM_MGCG */
1486                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1487                 if (!(data & 0x01000000))
1488                         *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1489
1490                 /* AMD_CG_SUPPORT_DRM_LS */
1491                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1492                 if (data & 0x1)
1493                         *flags |= AMD_CG_SUPPORT_DRM_LS;
1494         }
1495
1496         /* AMD_CG_SUPPORT_ROM_MGCG */
1497         if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1498                 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1499
1500         if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1501                 adev->df.funcs->get_clockgating_state(adev, flags);
1502 }
1503
1504 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1505                                             enum amd_powergating_state state)
1506 {
1507         /* todo */
1508         return 0;
1509 }
1510
1511 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1512         .name = "soc15_common",
1513         .early_init = soc15_common_early_init,
1514         .late_init = soc15_common_late_init,
1515         .sw_init = soc15_common_sw_init,
1516         .sw_fini = soc15_common_sw_fini,
1517         .hw_init = soc15_common_hw_init,
1518         .hw_fini = soc15_common_hw_fini,
1519         .suspend = soc15_common_suspend,
1520         .resume = soc15_common_resume,
1521         .is_idle = soc15_common_is_idle,
1522         .set_clockgating_state = soc15_common_set_clockgating_state,
1523         .set_powergating_state = soc15_common_set_powergating_state,
1524         .get_clockgating_state= soc15_common_get_clockgating_state,
1525 };