drivers/gpu/drm/msm/msm_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include "drm/drm_drv.h"
   8
   9 #include "msm_gpu.h"
  10 #include "msm_gem.h"
  11 #include "msm_mmu.h"
  12 #include "msm_fence.h"
  13 #include "msm_gpu_trace.h"
  14 #include "adreno/adreno_gpu.h"
  15
  16 #include <generated/utsrelease.h>
  17 #include <linux/string_helpers.h>
  18 #include <linux/devcoredump.h>
  19 #include <linux/reset.h>
  20 #include <linux/sched/task.h>
  21
  22 /*
  23  * Power Management:
  24  */
  25
  26 static int enable_pwrrail(struct msm_gpu *gpu)
  27 {
  28         struct drm_device *dev = gpu->dev;
  29         int ret = 0;
  30
  31         if (gpu->gpu_reg) {
  32                 ret = regulator_enable(gpu->gpu_reg);
  33                 if (ret) {
  34                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
  35                         return ret;
  36                 }
  37         }
  38
  39         if (gpu->gpu_cx) {
  40                 ret = regulator_enable(gpu->gpu_cx);
  41                 if (ret) {
  42                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
  43                         return ret;
  44                 }
  45         }
  46
  47         return 0;
  48 }
  49
  50 static int disable_pwrrail(struct msm_gpu *gpu)
  51 {
  52         if (gpu->gpu_cx)
  53                 regulator_disable(gpu->gpu_cx);
  54         if (gpu->gpu_reg)
  55                 regulator_disable(gpu->gpu_reg);
  56         return 0;
  57 }
  58
  59 static int enable_clk(struct msm_gpu *gpu)
  60 {
  61         if (gpu->core_clk && gpu->fast_rate)
  62                 clk_set_rate(gpu->core_clk, gpu->fast_rate);
  63
  64         /* Set the RBBM timer rate to 19.2Mhz */
  65         if (gpu->rbbmtimer_clk)
  66                 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
  67
  68         return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
  69 }
  70
  71 static int disable_clk(struct msm_gpu *gpu)
  72 {
  73         clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
  74
  75         /*
  76          * Set the clock to a deliberately low rate. On older targets the clock
  77          * speed had to be non zero to avoid problems. On newer targets this
  78          * will be rounded down to zero anyway so it all works out.
  79          */
  80         if (gpu->core_clk)
  81                 clk_set_rate(gpu->core_clk, 27000000);
  82
  83         if (gpu->rbbmtimer_clk)
  84                 clk_set_rate(gpu->rbbmtimer_clk, 0);
  85
  86         return 0;
  87 }
  88
  89 static int enable_axi(struct msm_gpu *gpu)
  90 {
  91         return clk_prepare_enable(gpu->ebi1_clk);
  92 }
  93
  94 static int disable_axi(struct msm_gpu *gpu)
  95 {
  96         clk_disable_unprepare(gpu->ebi1_clk);
  97         return 0;
  98 }
  99
 100 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 101 {
 102         int ret;
 103
 104         DBG("%s", gpu->name);
 105         trace_msm_gpu_resume(0);
 106
 107         ret = enable_pwrrail(gpu);
 108         if (ret)
 109                 return ret;
 110
 111         ret = enable_clk(gpu);
 112         if (ret)
 113                 return ret;
 114
 115         ret = enable_axi(gpu);
 116         if (ret)
 117                 return ret;
 118
 119         msm_devfreq_resume(gpu);
 120
 121         gpu->needs_hw_init = true;
 122
 123         return 0;
 124 }
 125
 126 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 127 {
 128         int ret;
 129
 130         DBG("%s", gpu->name);
 131         trace_msm_gpu_suspend(0);
 132
 133         msm_devfreq_suspend(gpu);
 134
 135         ret = disable_axi(gpu);
 136         if (ret)
 137                 return ret;
 138
 139         ret = disable_clk(gpu);
 140         if (ret)
 141                 return ret;
 142
 143         ret = disable_pwrrail(gpu);
 144         if (ret)
 145                 return ret;
 146
 147         gpu->suspend_count++;
 148
 149         return 0;
 150 }
 151
 152 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
 153                          struct drm_printer *p)
 154 {
 155         drm_printf(p, "drm-driver:\t%s\n", gpu->dev->driver->name);
 156         drm_printf(p, "drm-client-id:\t%u\n", ctx->seqno);
 157         drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
 158         drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
 159         drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
 160 }
 161
 162 int msm_gpu_hw_init(struct msm_gpu *gpu)
 163 {
 164         int ret;
 165
 166         WARN_ON(!mutex_is_locked(&gpu->lock));
 167
 168         if (!gpu->needs_hw_init)
 169                 return 0;
 170
 171         disable_irq(gpu->irq);
 172         ret = gpu->funcs->hw_init(gpu);
 173         if (!ret)
 174                 gpu->needs_hw_init = false;
 175         enable_irq(gpu->irq);
 176
 177         return ret;
 178 }
 179
 180 #ifdef CONFIG_DEV_COREDUMP
 181 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 182                 size_t count, void *data, size_t datalen)
 183 {
 184         struct msm_gpu *gpu = data;
 185         struct drm_print_iterator iter;
 186         struct drm_printer p;
 187         struct msm_gpu_state *state;
 188
 189         state = msm_gpu_crashstate_get(gpu);
 190         if (!state)
 191                 return 0;
 192
 193         iter.data = buffer;
 194         iter.offset = 0;
 195         iter.start = offset;
 196         iter.remain = count;
 197
 198         p = drm_coredump_printer(&iter);
 199
 200         drm_printf(&p, "---\n");
 201         drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 202         drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 203         drm_printf(&p, "time: %lld.%09ld\n",
 204                 state->time.tv_sec, state->time.tv_nsec);
 205         if (state->comm)
 206                 drm_printf(&p, "comm: %s\n", state->comm);
 207         if (state->cmd)
 208                 drm_printf(&p, "cmdline: %s\n", state->cmd);
 209
 210         gpu->funcs->show(gpu, state, &p);
 211
 212         msm_gpu_crashstate_put(gpu);
 213
 214         return count - iter.remain;
 215 }
 216
 217 static void msm_gpu_devcoredump_free(void *data)
 218 {
 219         struct msm_gpu *gpu = data;
 220
 221         msm_gpu_crashstate_put(gpu);
 222 }
 223
 224 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 225                 struct msm_gem_object *obj, u64 iova, bool full)
 226 {
 227         struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 228
 229         /* Don't record write only objects */
 230         state_bo->size = obj->base.size;
 231         state_bo->iova = iova;
 232
 233         BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name));
 234
 235         memcpy(state_bo->name, obj->name, sizeof(state_bo->name));
 236
 237         if (full) {
 238                 void *ptr;
 239
 240                 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
 241                 if (!state_bo->data)
 242                         goto out;
 243
 244                 msm_gem_lock(&obj->base);
 245                 ptr = msm_gem_get_vaddr_active(&obj->base);
 246                 msm_gem_unlock(&obj->base);
 247                 if (IS_ERR(ptr)) {
 248                         kvfree(state_bo->data);
 249                         state_bo->data = NULL;
 250                         goto out;
 251                 }
 252
 253                 memcpy(state_bo->data, ptr, obj->base.size);
 254                 msm_gem_put_vaddr(&obj->base);
 255         }
 256 out:
 257         state->nr_bos++;
 258 }
 259
 260 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 261                 struct msm_gem_submit *submit, char *comm, char *cmd)
 262 {
 263         struct msm_gpu_state *state;
 264
 265         /* Check if the target supports capturing crash state */
 266         if (!gpu->funcs->gpu_state_get)
 267                 return;
 268
 269         /* Only save one crash state at a time */
 270         if (gpu->crashstate)
 271                 return;
 272
 273         state = gpu->funcs->gpu_state_get(gpu);
 274         if (IS_ERR_OR_NULL(state))
 275                 return;
 276
 277         /* Fill in the additional crash state information */
 278         state->comm = kstrdup(comm, GFP_KERNEL);
 279         state->cmd = kstrdup(cmd, GFP_KERNEL);
 280         state->fault_info = gpu->fault_info;
 281
 282         if (submit) {
 283                 int i;
 284
 285                 state->bos = kcalloc(submit->nr_bos,
 286                         sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 287
 288                 for (i = 0; state->bos && i < submit->nr_bos; i++) {
 289                         msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
 290                                                   submit->bos[i].iova,
 291                                                   should_dump(submit, i));
 292                 }
 293         }
 294
 295         /* Set the active crash state to be dumped on failure */
 296         gpu->crashstate = state;
 297
 298         /* FIXME: Release the crashstate if this errors out? */
 299         dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 300                 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 301 }
 302 #else
 303 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 304                 struct msm_gem_submit *submit, char *comm, char *cmd)
 305 {
 306 }
 307 #endif
 308
 309 /*
 310  * Hangcheck detection for locked gpu:
 311  */
 312
 313 static struct msm_gem_submit *
 314 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 315 {
 316         struct msm_gem_submit *submit;
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&ring->submit_lock, flags);
 320         list_for_each_entry(submit, &ring->submits, node) {
 321                 if (submit->seqno == fence) {
 322                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 323                         return submit;
 324                 }
 325         }
 326         spin_unlock_irqrestore(&ring->submit_lock, flags);
 327
 328         return NULL;
 329 }
 330
 331 static void retire_submits(struct msm_gpu *gpu);
 332
 333 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
 334 {
 335         struct msm_file_private *ctx = submit->queue->ctx;
 336         struct task_struct *task;
 337
 338         /* Note that kstrdup will return NULL if argument is NULL: */
 339         *comm = kstrdup(ctx->comm, GFP_KERNEL);
 340         *cmd  = kstrdup(ctx->cmdline, GFP_KERNEL);
 341
 342         task = get_pid_task(submit->pid, PIDTYPE_PID);
 343         if (!task)
 344                 return;
 345
 346         if (!*comm)
 347                 *comm = kstrdup(task->comm, GFP_KERNEL);
 348
 349         if (!*cmd)
 350                 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
 351
 352         put_task_struct(task);
 353 }
 354
 355 static void recover_worker(struct kthread_work *work)
 356 {
 357         struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 358         struct drm_device *dev = gpu->dev;
 359         struct msm_drm_private *priv = dev->dev_private;
 360         struct msm_gem_submit *submit;
 361         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 362         char *comm = NULL, *cmd = NULL;
 363         int i;
 364
 365         mutex_lock(&gpu->lock);
 366
 367         DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 368
 369         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 370         if (submit) {
 371                 /* Increment the fault counts */
 372                 submit->queue->faults++;
 373                 if (submit->aspace)
 374                         submit->aspace->faults++;
 375
 376                 get_comm_cmdline(submit, &comm, &cmd);
 377
 378                 if (comm && cmd) {
 379                         DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 380                                 gpu->name, comm, cmd);
 381
 382                         msm_rd_dump_submit(priv->hangrd, submit,
 383                                 "offending task: %s (%s)", comm, cmd);
 384                 } else {
 385                         msm_rd_dump_submit(priv->hangrd, submit, NULL);
 386                 }
 387         } else {
 388                 /*
 389                  * We couldn't attribute this fault to any particular context,
 390                  * so increment the global fault count instead.
 391                  */
 392                 gpu->global_faults++;
 393         }
 394
 395         /* Record the crash state */
 396         pm_runtime_get_sync(&gpu->pdev->dev);
 397         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 398
 399         kfree(cmd);
 400         kfree(comm);
 401
 402         /*
 403          * Update all the rings with the latest and greatest fence.. this
 404          * needs to happen after msm_rd_dump_submit() to ensure that the
 405          * bo's referenced by the offending submit are still around.
 406          */
 407         for (i = 0; i < gpu->nr_rings; i++) {
 408                 struct msm_ringbuffer *ring = gpu->rb[i];
 409
 410                 uint32_t fence = ring->memptrs->fence;
 411
 412                 /*
 413                  * For the current (faulting?) ring/submit advance the fence by
 414                  * one more to clear the faulting submit
 415                  */
 416                 if (ring == cur_ring)
 417                         ring->memptrs->fence = ++fence;
 418
 419                 msm_update_fence(ring->fctx, fence);
 420         }
 421
 422         if (msm_gpu_active(gpu)) {
 423                 /* retire completed submits, plus the one that hung: */
 424                 retire_submits(gpu);
 425
 426                 gpu->funcs->recover(gpu);
 427
 428                 /*
 429                  * Replay all remaining submits starting with highest priority
 430                  * ring
 431                  */
 432                 for (i = 0; i < gpu->nr_rings; i++) {
 433                         struct msm_ringbuffer *ring = gpu->rb[i];
 434                         unsigned long flags;
 435
 436                         spin_lock_irqsave(&ring->submit_lock, flags);
 437                         list_for_each_entry(submit, &ring->submits, node)
 438                                 gpu->funcs->submit(gpu, submit);
 439                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 440                 }
 441         }
 442
 443         pm_runtime_put(&gpu->pdev->dev);
 444
 445         mutex_unlock(&gpu->lock);
 446
 447         msm_gpu_retire(gpu);
 448 }
 449
 450 static void fault_worker(struct kthread_work *work)
 451 {
 452         struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
 453         struct msm_gem_submit *submit;
 454         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 455         char *comm = NULL, *cmd = NULL;
 456
 457         mutex_lock(&gpu->lock);
 458
 459         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 460         if (submit && submit->fault_dumped)
 461                 goto resume_smmu;
 462
 463         if (submit) {
 464                 get_comm_cmdline(submit, &comm, &cmd);
 465
 466                 /*
 467                  * When we get GPU iova faults, we can get 1000s of them,
 468                  * but we really only want to log the first one.
 469                  */
 470                 submit->fault_dumped = true;
 471         }
 472
 473         /* Record the crash state */
 474         pm_runtime_get_sync(&gpu->pdev->dev);
 475         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 476         pm_runtime_put_sync(&gpu->pdev->dev);
 477
 478         kfree(cmd);
 479         kfree(comm);
 480
 481 resume_smmu:
 482         memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
 483         gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
 484
 485         mutex_unlock(&gpu->lock);
 486 }
 487
 488 static void hangcheck_timer_reset(struct msm_gpu *gpu)
 489 {
 490         struct msm_drm_private *priv = gpu->dev->dev_private;
 491         mod_timer(&gpu->hangcheck_timer,
 492                         round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
 493 }
 494
 495 static void hangcheck_handler(struct timer_list *t)
 496 {
 497         struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 498         struct drm_device *dev = gpu->dev;
 499         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 500         uint32_t fence = ring->memptrs->fence;
 501
 502         if (fence != ring->hangcheck_fence) {
 503                 /* some progress has been made.. ya! */
 504                 ring->hangcheck_fence = fence;
 505         } else if (fence_before(fence, ring->fctx->last_fence)) {
 506                 /* no progress and not done.. hung! */
 507                 ring->hangcheck_fence = fence;
 508                 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 509                                 gpu->name, ring->id);
 510                 DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 511                                 gpu->name, fence);
 512                 DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 513                                 gpu->name, ring->fctx->last_fence);
 514
 515                 kthread_queue_work(gpu->worker, &gpu->recover_work);
 516         }
 517
 518         /* if still more pending work, reset the hangcheck timer: */
 519         if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
 520                 hangcheck_timer_reset(gpu);
 521
 522         /* workaround for missing irq: */
 523         msm_gpu_retire(gpu);
 524 }
 525
 526 /*
 527  * Performance Counters:
 528  */
 529
 530 /* called under perf_lock */
 531 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 532 {
 533         uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 534         int i, n = min(ncntrs, gpu->num_perfcntrs);
 535
 536         /* read current values: */
 537         for (i = 0; i < gpu->num_perfcntrs; i++)
 538                 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 539
 540         /* update cntrs: */
 541         for (i = 0; i < n; i++)
 542                 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 543
 544         /* save current values: */
 545         for (i = 0; i < gpu->num_perfcntrs; i++)
 546                 gpu->last_cntrs[i] = current_cntrs[i];
 547
 548         return n;
 549 }
 550
 551 static void update_sw_cntrs(struct msm_gpu *gpu)
 552 {
 553         ktime_t time;
 554         uint32_t elapsed;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&gpu->perf_lock, flags);
 558         if (!gpu->perfcntr_active)
 559                 goto out;
 560
 561         time = ktime_get();
 562         elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 563
 564         gpu->totaltime += elapsed;
 565         if (gpu->last_sample.active)
 566                 gpu->activetime += elapsed;
 567
 568         gpu->last_sample.active = msm_gpu_active(gpu);
 569         gpu->last_sample.time = time;
 570
 571 out:
 572         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 573 }
 574
 575 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 576 {
 577         unsigned long flags;
 578
 579         pm_runtime_get_sync(&gpu->pdev->dev);
 580
 581         spin_lock_irqsave(&gpu->perf_lock, flags);
 582         /* we could dynamically enable/disable perfcntr registers too.. */
 583         gpu->last_sample.active = msm_gpu_active(gpu);
 584         gpu->last_sample.time = ktime_get();
 585         gpu->activetime = gpu->totaltime = 0;
 586         gpu->perfcntr_active = true;
 587         update_hw_cntrs(gpu, 0, NULL);
 588         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 589 }
 590
 591 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 592 {
 593         gpu->perfcntr_active = false;
 594         pm_runtime_put_sync(&gpu->pdev->dev);
 595 }
 596
 597 /* returns -errno or # of cntrs sampled */
 598 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 599                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 600 {
 601         unsigned long flags;
 602         int ret;
 603
 604         spin_lock_irqsave(&gpu->perf_lock, flags);
 605
 606         if (!gpu->perfcntr_active) {
 607                 ret = -EINVAL;
 608                 goto out;
 609         }
 610
 611         *activetime = gpu->activetime;
 612         *totaltime = gpu->totaltime;
 613
 614         gpu->activetime = gpu->totaltime = 0;
 615
 616         ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 617
 618 out:
 619         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 620
 621         return ret;
 622 }
 623
 624 /*
 625  * Cmdstream submission/retirement:
 626  */
 627
 628 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 629                 struct msm_gem_submit *submit)
 630 {
 631         int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 632         volatile struct msm_gpu_submit_stats *stats;
 633         u64 elapsed, clock = 0, cycles;
 634         unsigned long flags;
 635
 636         stats = &ring->memptrs->stats[index];
 637         /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 638         elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 639         do_div(elapsed, 192);
 640
 641         cycles = stats->cpcycles_end - stats->cpcycles_start;
 642
 643         /* Calculate the clock frequency from the number of CP cycles */
 644         if (elapsed) {
 645                 clock = cycles * 1000;
 646                 do_div(clock, elapsed);
 647         }
 648
 649         submit->queue->ctx->elapsed_ns += elapsed;
 650         submit->queue->ctx->cycles     += cycles;
 651
 652         trace_msm_gpu_submit_retired(submit, elapsed, clock,
 653                 stats->alwayson_start, stats->alwayson_end);
 654
 655         msm_submit_retire(submit);
 656
 657         pm_runtime_mark_last_busy(&gpu->pdev->dev);
 658
 659         spin_lock_irqsave(&ring->submit_lock, flags);
 660         list_del(&submit->node);
 661         spin_unlock_irqrestore(&ring->submit_lock, flags);
 662
 663         /* Update devfreq on transition from active->idle: */
 664         mutex_lock(&gpu->active_lock);
 665         gpu->active_submits--;
 666         WARN_ON(gpu->active_submits < 0);
 667         if (!gpu->active_submits) {
 668                 msm_devfreq_idle(gpu);
 669                 pm_runtime_put_autosuspend(&gpu->pdev->dev);
 670         }
 671
 672         mutex_unlock(&gpu->active_lock);
 673
 674         msm_gem_submit_put(submit);
 675 }
 676
 677 static void retire_submits(struct msm_gpu *gpu)
 678 {
 679         int i;
 680
 681         /* Retire the commits starting with highest priority */
 682         for (i = 0; i < gpu->nr_rings; i++) {
 683                 struct msm_ringbuffer *ring = gpu->rb[i];
 684
 685                 while (true) {
 686                         struct msm_gem_submit *submit = NULL;
 687                         unsigned long flags;
 688
 689                         spin_lock_irqsave(&ring->submit_lock, flags);
 690                         submit = list_first_entry_or_null(&ring->submits,
 691                                         struct msm_gem_submit, node);
 692                         spin_unlock_irqrestore(&ring->submit_lock, flags);
 693
 694                         /*
 695                          * If no submit, we are done.  If submit->fence hasn't
 696                          * been signalled, then later submits are not signalled
 697                          * either, so we are also done.
 698                          */
 699                         if (submit && dma_fence_is_signaled(submit->hw_fence)) {
 700                                 retire_submit(gpu, ring, submit);
 701                         } else {
 702                                 break;
 703                         }
 704                 }
 705         }
 706
 707         wake_up_all(&gpu->retire_event);
 708 }
 709
 710 static void retire_worker(struct kthread_work *work)
 711 {
 712         struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 713
 714         retire_submits(gpu);
 715 }
 716
 717 /* call from irq handler to schedule work to retire bo's */
 718 void msm_gpu_retire(struct msm_gpu *gpu)
 719 {
 720         int i;
 721
 722         for (i = 0; i < gpu->nr_rings; i++)
 723                 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
 724
 725         kthread_queue_work(gpu->worker, &gpu->retire_work);
 726         update_sw_cntrs(gpu);
 727 }
 728
 729 /* add bo's to gpu's ring, and kick gpu: */
 730 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 731 {
 732         struct drm_device *dev = gpu->dev;
 733         struct msm_drm_private *priv = dev->dev_private;
 734         struct msm_ringbuffer *ring = submit->ring;
 735         unsigned long flags;
 736
 737         WARN_ON(!mutex_is_locked(&gpu->lock));
 738
 739         pm_runtime_get_sync(&gpu->pdev->dev);
 740
 741         msm_gpu_hw_init(gpu);
 742
 743         submit->seqno = submit->hw_fence->seqno;
 744
 745         msm_rd_dump_submit(priv->rd, submit, NULL);
 746
 747         update_sw_cntrs(gpu);
 748
 749         /*
 750          * ring->submits holds a ref to the submit, to deal with the case
 751          * that a submit completes before msm_ioctl_gem_submit() returns.
 752          */
 753         msm_gem_submit_get(submit);
 754
 755         spin_lock_irqsave(&ring->submit_lock, flags);
 756         list_add_tail(&submit->node, &ring->submits);
 757         spin_unlock_irqrestore(&ring->submit_lock, flags);
 758
 759         /* Update devfreq on transition from idle->active: */
 760         mutex_lock(&gpu->active_lock);
 761         if (!gpu->active_submits) {
 762                 pm_runtime_get(&gpu->pdev->dev);
 763                 msm_devfreq_active(gpu);
 764         }
 765         gpu->active_submits++;
 766         mutex_unlock(&gpu->active_lock);
 767
 768         gpu->funcs->submit(gpu, submit);
 769         gpu->cur_ctx_seqno = submit->queue->ctx->seqno;
 770
 771         pm_runtime_put(&gpu->pdev->dev);
 772         hangcheck_timer_reset(gpu);
 773 }
 774
 775 /*
 776  * Init/Cleanup:
 777  */
 778
 779 static irqreturn_t irq_handler(int irq, void *data)
 780 {
 781         struct msm_gpu *gpu = data;
 782         return gpu->funcs->irq(gpu);
 783 }
 784
 785 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 786 {
 787         int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
 788
 789         if (ret < 1) {
 790                 gpu->nr_clocks = 0;
 791                 return ret;
 792         }
 793
 794         gpu->nr_clocks = ret;
 795
 796         gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 797                 gpu->nr_clocks, "core");
 798
 799         gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 800                 gpu->nr_clocks, "rbbmtimer");
 801
 802         return 0;
 803 }
 804
 805 /* Return a new address space for a msm_drm_private instance */
 806 struct msm_gem_address_space *
 807 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
 808 {
 809         struct msm_gem_address_space *aspace = NULL;
 810         if (!gpu)
 811                 return NULL;
 812
 813         /*
 814          * If the target doesn't support private address spaces then return
 815          * the global one
 816          */
 817         if (gpu->funcs->create_private_address_space) {
 818                 aspace = gpu->funcs->create_private_address_space(gpu);
 819                 if (!IS_ERR(aspace))
 820                         aspace->pid = get_pid(task_pid(task));
 821         }
 822
 823         if (IS_ERR_OR_NULL(aspace))
 824                 aspace = msm_gem_address_space_get(gpu->aspace);
 825
 826         return aspace;
 827 }
 828
 829 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 830                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 831                 const char *name, struct msm_gpu_config *config)
 832 {
 833         int i, ret, nr_rings = config->nr_rings;
 834         void *memptrs;
 835         uint64_t memptrs_iova;
 836
 837         if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 838                 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 839
 840         gpu->dev = drm;
 841         gpu->funcs = funcs;
 842         gpu->name = name;
 843
 844         gpu->worker = kthread_create_worker(0, "gpu-worker");
 845         if (IS_ERR(gpu->worker)) {
 846                 ret = PTR_ERR(gpu->worker);
 847                 gpu->worker = NULL;
 848                 goto fail;
 849         }
 850
 851         sched_set_fifo_low(gpu->worker->task);
 852
 853         mutex_init(&gpu->active_lock);
 854         mutex_init(&gpu->lock);
 855         init_waitqueue_head(&gpu->retire_event);
 856         kthread_init_work(&gpu->retire_work, retire_worker);
 857         kthread_init_work(&gpu->recover_work, recover_worker);
 858         kthread_init_work(&gpu->fault_work, fault_worker);
 859
 860         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
 861
 862         spin_lock_init(&gpu->perf_lock);
 863
 864
 865         /* Map registers: */
 866         gpu->mmio = msm_ioremap(pdev, config->ioname);
 867         if (IS_ERR(gpu->mmio)) {
 868                 ret = PTR_ERR(gpu->mmio);
 869                 goto fail;
 870         }
 871
 872         /* Get Interrupt: */
 873         gpu->irq = platform_get_irq(pdev, 0);
 874         if (gpu->irq < 0) {
 875                 ret = gpu->irq;
 876                 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
 877                 goto fail;
 878         }
 879
 880         ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
 881                         IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
 882         if (ret) {
 883                 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
 884                 goto fail;
 885         }
 886
 887         ret = get_clocks(pdev, gpu);
 888         if (ret)
 889                 goto fail;
 890
 891         gpu->ebi1_clk = msm_clk_get(pdev, "bus");
 892         DBG("ebi1_clk: %p", gpu->ebi1_clk);
 893         if (IS_ERR(gpu->ebi1_clk))
 894                 gpu->ebi1_clk = NULL;
 895
 896         /* Acquire regulators: */
 897         gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
 898         DBG("gpu_reg: %p", gpu->gpu_reg);
 899         if (IS_ERR(gpu->gpu_reg))
 900                 gpu->gpu_reg = NULL;
 901
 902         gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
 903         DBG("gpu_cx: %p", gpu->gpu_cx);
 904         if (IS_ERR(gpu->gpu_cx))
 905                 gpu->gpu_cx = NULL;
 906
 907         gpu->cx_collapse = devm_reset_control_get_optional_exclusive(&pdev->dev,
 908                         "cx_collapse");
 909
 910         gpu->pdev = pdev;
 911         platform_set_drvdata(pdev, &gpu->adreno_smmu);
 912
 913         msm_devfreq_init(gpu);
 914
 915
 916         gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
 917
 918         if (gpu->aspace == NULL)
 919                 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
 920         else if (IS_ERR(gpu->aspace)) {
 921                 ret = PTR_ERR(gpu->aspace);
 922                 goto fail;
 923         }
 924
 925         memptrs = msm_gem_kernel_new(drm,
 926                 sizeof(struct msm_rbmemptrs) * nr_rings,
 927                 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
 928                 &memptrs_iova);
 929
 930         if (IS_ERR(memptrs)) {
 931                 ret = PTR_ERR(memptrs);
 932                 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
 933                 goto fail;
 934         }
 935
 936         msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
 937
 938         if (nr_rings > ARRAY_SIZE(gpu->rb)) {
 939                 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
 940                         ARRAY_SIZE(gpu->rb));
 941                 nr_rings = ARRAY_SIZE(gpu->rb);
 942         }
 943
 944         /* Create ringbuffer(s): */
 945         for (i = 0; i < nr_rings; i++) {
 946                 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
 947
 948                 if (IS_ERR(gpu->rb[i])) {
 949                         ret = PTR_ERR(gpu->rb[i]);
 950                         DRM_DEV_ERROR(drm->dev,
 951                                 "could not create ringbuffer %d: %d\n", i, ret);
 952                         goto fail;
 953                 }
 954
 955                 memptrs += sizeof(struct msm_rbmemptrs);
 956                 memptrs_iova += sizeof(struct msm_rbmemptrs);
 957         }
 958
 959         gpu->nr_rings = nr_rings;
 960
 961         refcount_set(&gpu->sysprof_active, 1);
 962
 963         return 0;
 964
 965 fail:
 966         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
 967                 msm_ringbuffer_destroy(gpu->rb[i]);
 968                 gpu->rb[i] = NULL;
 969         }
 970
 971         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
 972
 973         platform_set_drvdata(pdev, NULL);
 974         return ret;
 975 }
 976
 977 void msm_gpu_cleanup(struct msm_gpu *gpu)
 978 {
 979         int i;
 980
 981         DBG("%s", gpu->name);
 982
 983         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
 984                 msm_ringbuffer_destroy(gpu->rb[i]);
 985                 gpu->rb[i] = NULL;
 986         }
 987
 988         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
 989
 990         if (!IS_ERR_OR_NULL(gpu->aspace)) {
 991                 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
 992                 msm_gem_address_space_put(gpu->aspace);
 993         }
 994
 995         if (gpu->worker) {
 996                 kthread_destroy_worker(gpu->worker);
 997         }
 998
 999         msm_devfreq_cleanup(gpu);
1000 }