drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_GFX_H__
  25 #define __AMDGPU_GFX_H__
  26
  27 /*
  28  * GFX stuff
  29  */
  30 #include "clearstate_defs.h"
  31 #include "amdgpu_ring.h"
  32 #include "amdgpu_rlc.h"
  33 #include "amdgpu_imu.h"
  34 #include "soc15.h"
  35 #include "amdgpu_ras.h"
  36 #include "amdgpu_ring_mux.h"
  37 #include "amdgpu_xcp.h"
  38
  39 /* GFX current status */
  40 #define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
  41 #define AMDGPU_GFX_SAFE_MODE                    0x00000001L
  42 #define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
  43 #define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
  44 #define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
  45
  46 #define AMDGPU_MAX_GC_INSTANCES         8
  47 #define AMDGPU_MAX_QUEUES               128
  48
  49 #define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES
  50 #define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES
  51
  52 enum amdgpu_gfx_pipe_priority {
  53         AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
  54         AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
  55 };
  56
  57 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
  58 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
  59
  60 enum amdgpu_gfx_partition {
  61         AMDGPU_SPX_PARTITION_MODE = 0,
  62         AMDGPU_DPX_PARTITION_MODE = 1,
  63         AMDGPU_TPX_PARTITION_MODE = 2,
  64         AMDGPU_QPX_PARTITION_MODE = 3,
  65         AMDGPU_CPX_PARTITION_MODE = 4,
  66         AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1,
  67         /* Automatically choose the right mode */
  68         AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2,
  69 };
  70
  71 #define NUM_XCC(x) hweight16(x)
  72
  73 enum amdgpu_gfx_ras_mem_id_type {
  74         AMDGPU_GFX_CP_MEM = 0,
  75         AMDGPU_GFX_GCEA_MEM,
  76         AMDGPU_GFX_GC_CANE_MEM,
  77         AMDGPU_GFX_GCUTCL2_MEM,
  78         AMDGPU_GFX_GDS_MEM,
  79         AMDGPU_GFX_LDS_MEM,
  80         AMDGPU_GFX_RLC_MEM,
  81         AMDGPU_GFX_SP_MEM,
  82         AMDGPU_GFX_SPI_MEM,
  83         AMDGPU_GFX_SQC_MEM,
  84         AMDGPU_GFX_SQ_MEM,
  85         AMDGPU_GFX_TA_MEM,
  86         AMDGPU_GFX_TCC_MEM,
  87         AMDGPU_GFX_TCA_MEM,
  88         AMDGPU_GFX_TCI_MEM,
  89         AMDGPU_GFX_TCP_MEM,
  90         AMDGPU_GFX_TD_MEM,
  91         AMDGPU_GFX_TCX_MEM,
  92         AMDGPU_GFX_ATC_L2_MEM,
  93         AMDGPU_GFX_UTCL2_MEM,
  94         AMDGPU_GFX_VML2_MEM,
  95         AMDGPU_GFX_VML2_WALKER_MEM,
  96         AMDGPU_GFX_MEM_TYPE_NUM
  97 };
  98
  99 struct amdgpu_mec {
 100         struct amdgpu_bo        *hpd_eop_obj;
 101         u64                     hpd_eop_gpu_addr;
 102         struct amdgpu_bo        *mec_fw_obj;
 103         u64                     mec_fw_gpu_addr;
 104         struct amdgpu_bo        *mec_fw_data_obj;
 105         u64                     mec_fw_data_gpu_addr;
 106
 107         u32 num_mec;
 108         u32 num_pipe_per_mec;
 109         u32 num_queue_per_pipe;
 110         void                    *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
 111 };
 112
 113 struct amdgpu_mec_bitmap {
 114         /* These are the resources for which amdgpu takes ownership */
 115         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 116 };
 117
 118 enum amdgpu_unmap_queues_action {
 119         PREEMPT_QUEUES = 0,
 120         RESET_QUEUES,
 121         DISABLE_PROCESS_QUEUES,
 122         PREEMPT_QUEUES_NO_UNMAP,
 123 };
 124
 125 struct kiq_pm4_funcs {
 126         /* Support ASIC-specific kiq pm4 packets*/
 127         void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
 128                                         uint64_t queue_mask);
 129         void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
 130                                         struct amdgpu_ring *ring);
 131         void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
 132                                  struct amdgpu_ring *ring,
 133                                  enum amdgpu_unmap_queues_action action,
 134                                  u64 gpu_addr, u64 seq);
 135         void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
 136                                         struct amdgpu_ring *ring,
 137                                         u64 addr,
 138                                         u64 seq);
 139         void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
 140                                 uint16_t pasid, uint32_t flush_type,
 141                                 bool all_hub);
 142         void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring,
 143                                    uint32_t queue_type, uint32_t me_id,
 144                                    uint32_t pipe_id, uint32_t queue_id,
 145                                    uint32_t xcc_id, uint32_t vmid);
 146         /* Packet sizes */
 147         int set_resources_size;
 148         int map_queues_size;
 149         int unmap_queues_size;
 150         int query_status_size;
 151         int invalidate_tlbs_size;
 152 };
 153
 154 struct amdgpu_kiq {
 155         u64                     eop_gpu_addr;
 156         struct amdgpu_bo        *eop_obj;
 157         spinlock_t              ring_lock;
 158         struct amdgpu_ring      ring;
 159         struct amdgpu_irq_src   irq;
 160         const struct kiq_pm4_funcs *pmf;
 161         void                    *mqd_backup;
 162 };
 163
 164 /*
 165  * GFX configurations
 166  */
 167 #define AMDGPU_GFX_MAX_SE 4
 168 #define AMDGPU_GFX_MAX_SH_PER_SE 2
 169
 170 struct amdgpu_rb_config {
 171         uint32_t rb_backend_disable;
 172         uint32_t user_rb_backend_disable;
 173         uint32_t raster_config;
 174         uint32_t raster_config_1;
 175 };
 176
 177 struct gb_addr_config {
 178         uint16_t pipe_interleave_size;
 179         uint8_t num_pipes;
 180         uint8_t max_compress_frags;
 181         uint8_t num_banks;
 182         uint8_t num_se;
 183         uint8_t num_rb_per_se;
 184         uint8_t num_pkrs;
 185 };
 186
 187 struct amdgpu_gfx_config {
 188         unsigned max_shader_engines;
 189         unsigned max_tile_pipes;
 190         unsigned max_cu_per_sh;
 191         unsigned max_sh_per_se;
 192         unsigned max_backends_per_se;
 193         unsigned max_texture_channel_caches;
 194         unsigned max_gprs;
 195         unsigned max_gs_threads;
 196         unsigned max_hw_contexts;
 197         unsigned sc_prim_fifo_size_frontend;
 198         unsigned sc_prim_fifo_size_backend;
 199         unsigned sc_hiz_tile_fifo_size;
 200         unsigned sc_earlyz_tile_fifo_size;
 201
 202         unsigned num_tile_pipes;
 203         unsigned backend_enable_mask;
 204         unsigned mem_max_burst_length_bytes;
 205         unsigned mem_row_size_in_kb;
 206         unsigned shader_engine_tile_size;
 207         unsigned num_gpus;
 208         unsigned multi_gpu_tile_size;
 209         unsigned mc_arb_ramcfg;
 210         unsigned num_banks;
 211         unsigned num_ranks;
 212         unsigned gb_addr_config;
 213         unsigned num_rbs;
 214         unsigned gs_vgt_table_depth;
 215         unsigned gs_prim_buffer_depth;
 216
 217         uint32_t tile_mode_array[32];
 218         uint32_t macrotile_mode_array[16];
 219
 220         struct gb_addr_config gb_addr_config_fields;
 221         struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 222
 223         /* gfx configure feature */
 224         uint32_t double_offchip_lds_buf;
 225         /* cached value of DB_DEBUG2 */
 226         uint32_t db_debug2;
 227         /* gfx10 specific config */
 228         uint32_t num_sc_per_sh;
 229         uint32_t num_packer_per_sc;
 230         uint32_t pa_sc_tile_steering_override;
 231         /* Whether texture coordinate truncation is conformant. */
 232         bool ta_cntl2_truncate_coord_mode;
 233         uint64_t tcc_disabled_mask;
 234         uint32_t gc_num_tcp_per_sa;
 235         uint32_t gc_num_sdp_interface;
 236         uint32_t gc_num_tcps;
 237         uint32_t gc_num_tcp_per_wpg;
 238         uint32_t gc_tcp_l1_size;
 239         uint32_t gc_num_sqc_per_wgp;
 240         uint32_t gc_l1_instruction_cache_size_per_sqc;
 241         uint32_t gc_l1_data_cache_size_per_sqc;
 242         uint32_t gc_gl1c_per_sa;
 243         uint32_t gc_gl1c_size_per_instance;
 244         uint32_t gc_gl2c_per_gpu;
 245         uint32_t gc_tcp_size_per_cu;
 246         uint32_t gc_num_cu_per_sqc;
 247         uint32_t gc_tcc_size;
 248         uint32_t gc_tcp_cache_line_size;
 249         uint32_t gc_instruction_cache_size_per_sqc;
 250         uint32_t gc_instruction_cache_line_size;
 251         uint32_t gc_scalar_data_cache_size_per_sqc;
 252         uint32_t gc_scalar_data_cache_line_size;
 253         uint32_t gc_tcc_cache_line_size;
 254 };
 255
 256 struct amdgpu_cu_info {
 257         uint32_t simd_per_cu;
 258         uint32_t max_waves_per_simd;
 259         uint32_t wave_front_size;
 260         uint32_t max_scratch_slots_per_cu;
 261         uint32_t lds_size;
 262
 263         /* total active CU number */
 264         uint32_t number;
 265         uint32_t ao_cu_mask;
 266         uint32_t ao_cu_bitmap[4][4];
 267         uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
 268 };
 269
 270 struct amdgpu_gfx_ras {
 271         struct amdgpu_ras_block_object  ras_block;
 272         void (*enable_watchdog_timer)(struct amdgpu_device *adev);
 273         int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
 274                                 struct amdgpu_irq_src *source,
 275                                 struct amdgpu_iv_entry *entry);
 276         int (*poison_consumption_handler)(struct amdgpu_device *adev,
 277                                                 struct amdgpu_iv_entry *entry);
 278 };
 279
 280 struct amdgpu_gfx_shadow_info {
 281         u32 shadow_size;
 282         u32 shadow_alignment;
 283         u32 csa_size;
 284         u32 csa_alignment;
 285 };
 286
 287 struct amdgpu_gfx_funcs {
 288         /* get the gpu clock counter */
 289         uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
 290         void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
 291                              u32 sh_num, u32 instance, int xcc_id);
 292         void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 293                                uint32_t wave, uint32_t *dst, int *no_fields);
 294         void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 295                                 uint32_t wave, uint32_t thread, uint32_t start,
 296                                 uint32_t size, uint32_t *dst);
 297         void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 298                                 uint32_t wave, uint32_t start, uint32_t size,
 299                                 uint32_t *dst);
 300         void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
 301                                  u32 queue, u32 vmid, u32 xcc_id);
 302         void (*init_spm_golden)(struct amdgpu_device *adev);
 303         void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 304         int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
 305                                    struct amdgpu_gfx_shadow_info *shadow_info);
 306         enum amdgpu_gfx_partition
 307                         (*query_partition_mode)(struct amdgpu_device *adev);
 308         int (*switch_partition_mode)(struct amdgpu_device *adev,
 309                                      int num_xccs_per_xcp);
 310         int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
 311         int (*get_xccs_per_xcp)(struct amdgpu_device *adev);
 312 };
 313
 314 struct sq_work {
 315         struct work_struct      work;
 316         unsigned ih_data;
 317 };
 318
 319 struct amdgpu_pfp {
 320         struct amdgpu_bo                *pfp_fw_obj;
 321         uint64_t                        pfp_fw_gpu_addr;
 322         uint32_t                        *pfp_fw_ptr;
 323
 324         struct amdgpu_bo                *pfp_fw_data_obj;
 325         uint64_t                        pfp_fw_data_gpu_addr;
 326         uint32_t                        *pfp_fw_data_ptr;
 327 };
 328
 329 struct amdgpu_ce {
 330         struct amdgpu_bo                *ce_fw_obj;
 331         uint64_t                        ce_fw_gpu_addr;
 332         uint32_t                        *ce_fw_ptr;
 333 };
 334
 335 struct amdgpu_me {
 336         struct amdgpu_bo                *me_fw_obj;
 337         uint64_t                        me_fw_gpu_addr;
 338         uint32_t                        *me_fw_ptr;
 339
 340         struct amdgpu_bo                *me_fw_data_obj;
 341         uint64_t                        me_fw_data_gpu_addr;
 342         uint32_t                        *me_fw_data_ptr;
 343
 344         uint32_t                        num_me;
 345         uint32_t                        num_pipe_per_me;
 346         uint32_t                        num_queue_per_pipe;
 347         void                            *mqd_backup[AMDGPU_MAX_GFX_RINGS];
 348
 349         /* These are the resources for which amdgpu takes ownership */
 350         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 351 };
 352
 353 struct amdgpu_isolation_work {
 354         struct amdgpu_device            *adev;
 355         u32                             xcp_id;
 356         struct delayed_work             work;
 357 };
 358
 359 struct amdgpu_gfx {
 360         struct mutex                    gpu_clock_mutex;
 361         struct amdgpu_gfx_config        config;
 362         struct amdgpu_rlc               rlc;
 363         struct amdgpu_pfp               pfp;
 364         struct amdgpu_ce                ce;
 365         struct amdgpu_me                me;
 366         struct amdgpu_mec               mec;
 367         struct amdgpu_mec_bitmap        mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
 368         struct amdgpu_kiq               kiq[AMDGPU_MAX_GC_INSTANCES];
 369         struct amdgpu_imu               imu;
 370         bool                            rs64_enable; /* firmware format */
 371         const struct firmware           *me_fw; /* ME firmware */
 372         uint32_t                        me_fw_version;
 373         const struct firmware           *pfp_fw; /* PFP firmware */
 374         uint32_t                        pfp_fw_version;
 375         const struct firmware           *ce_fw; /* CE firmware */
 376         uint32_t                        ce_fw_version;
 377         const struct firmware           *rlc_fw; /* RLC firmware */
 378         uint32_t                        rlc_fw_version;
 379         const struct firmware           *mec_fw; /* MEC firmware */
 380         uint32_t                        mec_fw_version;
 381         const struct firmware           *mec2_fw; /* MEC2 firmware */
 382         uint32_t                        mec2_fw_version;
 383         const struct firmware           *imu_fw; /* IMU firmware */
 384         uint32_t                        imu_fw_version;
 385         uint32_t                        me_feature_version;
 386         uint32_t                        ce_feature_version;
 387         uint32_t                        pfp_feature_version;
 388         uint32_t                        rlc_feature_version;
 389         uint32_t                        rlc_srlc_fw_version;
 390         uint32_t                        rlc_srlc_feature_version;
 391         uint32_t                        rlc_srlg_fw_version;
 392         uint32_t                        rlc_srlg_feature_version;
 393         uint32_t                        rlc_srls_fw_version;
 394         uint32_t                        rlc_srls_feature_version;
 395         uint32_t                        rlcp_ucode_version;
 396         uint32_t                        rlcp_ucode_feature_version;
 397         uint32_t                        rlcv_ucode_version;
 398         uint32_t                        rlcv_ucode_feature_version;
 399         uint32_t                        mec_feature_version;
 400         uint32_t                        mec2_feature_version;
 401         bool                            mec_fw_write_wait;
 402         bool                            me_fw_write_wait;
 403         bool                            cp_fw_write_wait;
 404         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
 405         unsigned                        num_gfx_rings;
 406         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
 407         unsigned                        num_compute_rings;
 408         struct amdgpu_irq_src           eop_irq;
 409         struct amdgpu_irq_src           priv_reg_irq;
 410         struct amdgpu_irq_src           priv_inst_irq;
 411         struct amdgpu_irq_src           bad_op_irq;
 412         struct amdgpu_irq_src           cp_ecc_error_irq;
 413         struct amdgpu_irq_src           sq_irq;
 414         struct amdgpu_irq_src           rlc_gc_fed_irq;
 415         struct sq_work                  sq_work;
 416
 417         /* gfx status */
 418         uint32_t                        gfx_current_status;
 419         /* ce ram size*/
 420         unsigned                        ce_ram_size;
 421         struct amdgpu_cu_info           cu_info;
 422         const struct amdgpu_gfx_funcs   *funcs;
 423
 424         /* reset mask */
 425         uint32_t                        grbm_soft_reset;
 426         uint32_t                        srbm_soft_reset;
 427         uint32_t                        gfx_supported_reset;
 428         uint32_t                        compute_supported_reset;
 429
 430         /* gfx off */
 431         bool                            gfx_off_state;      /* true: enabled, false: disabled */
 432         struct mutex                    gfx_off_mutex;      /* mutex to change gfxoff state */
 433         uint32_t                        gfx_off_req_count;  /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
 434         struct delayed_work             gfx_off_delay_work; /* async work to set gfx block off */
 435         uint32_t                        gfx_off_residency;  /* last logged residency */
 436         uint64_t                        gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
 437
 438         /* pipe reservation */
 439         struct mutex                    pipe_reserve_mutex;
 440         DECLARE_BITMAP                  (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 441
 442         /*ras */
 443         struct ras_common_if            *ras_if;
 444         struct amdgpu_gfx_ras           *ras;
 445
 446         bool                            is_poweron;
 447
 448         struct amdgpu_ring              sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
 449         struct amdgpu_ring_mux          muxer;
 450
 451         bool                            cp_gfx_shadow; /* for gfx11 */
 452
 453         uint16_t                        xcc_mask;
 454         uint32_t                        num_xcc_per_xcp;
 455         struct mutex                    partition_mutex;
 456         bool                            mcbp; /* mid command buffer preemption */
 457
 458         /* IP reg dump */
 459         uint32_t                        *ip_dump_core;
 460         uint32_t                        *ip_dump_compute_queues;
 461         uint32_t                        *ip_dump_gfx_queues;
 462
 463         struct mutex                    reset_sem_mutex;
 464
 465         /* cleaner shader */
 466         struct amdgpu_bo                *cleaner_shader_obj;
 467         unsigned int                    cleaner_shader_size;
 468         u64                             cleaner_shader_gpu_addr;
 469         void                            *cleaner_shader_cpu_ptr;
 470         const void                      *cleaner_shader_ptr;
 471         bool                            enable_cleaner_shader;
 472         struct amdgpu_isolation_work    enforce_isolation[MAX_XCP];
 473         /* Mutex for synchronizing KFD scheduler operations */
 474         struct mutex                    kfd_sch_mutex;
 475         u64                             kfd_sch_req_count[MAX_XCP];
 476         bool                            kfd_sch_inactive[MAX_XCP];
 477         unsigned long                   enforce_isolation_jiffies[MAX_XCP];
 478         unsigned long                   enforce_isolation_time[MAX_XCP];
 479 };
 480
 481 struct amdgpu_gfx_ras_reg_entry {
 482         struct amdgpu_ras_err_status_reg_entry reg_entry;
 483         enum amdgpu_gfx_ras_mem_id_type mem_id_type;
 484         uint32_t se_num;
 485 };
 486
 487 struct amdgpu_gfx_ras_mem_id_entry {
 488         const struct amdgpu_ras_memory_id_entry *mem_id_ent;
 489         uint32_t size;
 490 };
 491
 492 #define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)},
 493
 494 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 495 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
 496 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
 497 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
 498 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
 499
 500 /**
 501  * amdgpu_gfx_create_bitmask - create a bitmask
 502  *
 503  * @bit_width: length of the mask
 504  *
 505  * create a variable length bit mask.
 506  * Returns the bitmask.
 507  */
 508 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 509 {
 510         return (u32)((1ULL << bit_width) - 1);
 511 }
 512
 513 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 514                                  unsigned max_sh);
 515
 516 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
 517
 518 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
 519
 520 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
 521 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 522                         unsigned hpd_size, int xcc_id);
 523
 524 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 525                            unsigned mqd_size, int xcc_id);
 526 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
 527 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
 528 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
 529 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
 530 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
 531
 532 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 533 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
 534
 535 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
 536                                 int pipe, int queue);
 537 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
 538                                  int *mec, int *pipe, int *queue);
 539 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
 540                                      int mec, int pipe, int queue);
 541 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 542                                                struct amdgpu_ring *ring);
 543 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 544                                                 struct amdgpu_ring *ring);
 545 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 546                                int pipe, int queue);
 547 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 548                                     int pipe, int queue);
 549 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 550 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 551 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 552 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
 553 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
 554 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
 555 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
 556 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 557                 void *err_data,
 558                 struct amdgpu_iv_entry *entry);
 559 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 560                                   struct amdgpu_irq_src *source,
 561                                   struct amdgpu_iv_entry *entry);
 562 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);
 563 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
 564 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
 565 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
 566
 567 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
 568 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 569                                                 struct amdgpu_iv_entry *entry);
 570
 571 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
 572 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
 573 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev);
 574 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
 575                 void *ras_error_status,
 576                 void (*func)(struct amdgpu_device *adev, void *ras_error_status,
 577                                 int xcc_id));
 578 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev,
 579                                       unsigned int cleaner_shader_size);
 580 void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev);
 581 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev,
 582                                     unsigned int cleaner_shader_size,
 583                                     const void *cleaner_shader_ptr);
 584 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work);
 585 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring);
 586 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring);
 587 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev);
 588 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);
 589
 590 static inline const char *amdgpu_gfx_compute_mode_desc(int mode)
 591 {
 592         switch (mode) {
 593         case AMDGPU_SPX_PARTITION_MODE:
 594                 return "SPX";
 595         case AMDGPU_DPX_PARTITION_MODE:
 596                 return "DPX";
 597         case AMDGPU_TPX_PARTITION_MODE:
 598                 return "TPX";
 599         case AMDGPU_QPX_PARTITION_MODE:
 600                 return "QPX";
 601         case AMDGPU_CPX_PARTITION_MODE:
 602                 return "CPX";
 603         default:
 604                 return "UNKNOWN";
 605         }
 606 }
 607
 608 #endif