drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/fdtable.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_amdkfd.h"
  29 #include "cikd.h"
  30 #include "cik_sdma.h"
  31 #include "amdgpu_ucode.h"
  32 #include "gfx_v7_0.h"
  33 #include "gca/gfx_7_2_d.h"
  34 #include "gca/gfx_7_2_enum.h"
  35 #include "gca/gfx_7_2_sh_mask.h"
  36 #include "oss/oss_2_0_d.h"
  37 #include "oss/oss_2_0_sh_mask.h"
  38 #include "gmc/gmc_7_1_d.h"
  39 #include "gmc/gmc_7_1_sh_mask.h"
  40 #include "cik_structs.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 enum {
  49         MAX_TRAPID = 8,         /* 3 bits in the bitfield. */
  50         MAX_WATCH_ADDRESSES = 4
  51 };
  52
  53 enum {
  54         ADDRESS_WATCH_REG_ADDR_HI = 0,
  55         ADDRESS_WATCH_REG_ADDR_LO,
  56         ADDRESS_WATCH_REG_CNTL,
  57         ADDRESS_WATCH_REG_MAX
  58 };
  59
  60 /*  not defined in the CI/KV reg file  */
  61 enum {
  62         ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
  63         ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
  64         ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
  65         /* extend the mask to 26 bits to match the low address field */
  66         ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
  67         ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
  68 };
  69
  70 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
  71         mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
  72         mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
  73         mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
  74         mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
  75 };
  76
  77 union TCP_WATCH_CNTL_BITS {
  78         struct {
  79                 uint32_t mask:24;
  80                 uint32_t vmid:4;
  81                 uint32_t atc:1;
  82                 uint32_t mode:2;
  83                 uint32_t valid:1;
  84         } bitfields, bits;
  85         uint32_t u32All;
  86         signed int i32All;
  87         float f32All;
  88 };
  89
  90 /*
  91  * Register access functions
  92  */
  93
  94 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  95                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  96                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  97
  98 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  99                                         unsigned int vmid);
 100
 101 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
 102 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 103                         uint32_t queue_id, uint32_t __user *wptr,
 104                         uint32_t wptr_shift, uint32_t wptr_mask,
 105                         struct mm_struct *mm);
 106 static int kgd_hqd_dump(struct kgd_dev *kgd,
 107                         uint32_t pipe_id, uint32_t queue_id,
 108                         uint32_t (**dump)[2], uint32_t *n_regs);
 109 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 110                              uint32_t __user *wptr, struct mm_struct *mm);
 111 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 112                              uint32_t engine_id, uint32_t queue_id,
 113                              uint32_t (**dump)[2], uint32_t *n_regs);
 114 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 115                                 uint32_t pipe_id, uint32_t queue_id);
 116
 117 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 118                                 enum kfd_preempt_type reset_type,
 119                                 unsigned int utimeout, uint32_t pipe_id,
 120                                 uint32_t queue_id);
 121 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 122 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 123                                 unsigned int utimeout);
 124 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 125 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 126                                         unsigned int watch_point_id,
 127                                         uint32_t cntl_val,
 128                                         uint32_t addr_hi,
 129                                         uint32_t addr_lo);
 130 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 131                                         uint32_t gfx_index_val,
 132                                         uint32_t sq_cmd);
 133 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 134                                         unsigned int watch_point_id,
 135                                         unsigned int reg_offset);
 136
 137 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
 138 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 139                                                         uint8_t vmid);
 140
 141 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 142 static void set_scratch_backing_va(struct kgd_dev *kgd,
 143                                         uint64_t va, uint32_t vmid);
 144 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 145                 uint32_t page_table_base);
 146 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 147 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 148 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
 149
 150 /* Because of REG_GET_FIELD() being used, we put this function in the
 151  * asic specific file.
 152  */
 153 static int get_tile_config(struct kgd_dev *kgd,
 154                 struct tile_config *config)
 155 {
 156         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 157
 158         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 159         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 160                                 MC_ARB_RAMCFG, NOOFBANK);
 161         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 162                                 MC_ARB_RAMCFG, NOOFRANKS);
 163
 164         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 165         config->num_tile_configs =
 166                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 167         config->macro_tile_config_ptr =
 168                         adev->gfx.config.macrotile_mode_array;
 169         config->num_macro_tile_configs =
 170                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 171
 172         return 0;
 173 }
 174
 175 static const struct kfd2kgd_calls kfd2kgd = {
 176         .init_gtt_mem_allocation = alloc_gtt_mem,
 177         .free_gtt_mem = free_gtt_mem,
 178         .get_local_mem_info = get_local_mem_info,
 179         .get_gpu_clock_counter = get_gpu_clock_counter,
 180         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 181         .alloc_pasid = amdgpu_pasid_alloc,
 182         .free_pasid = amdgpu_pasid_free,
 183         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 184         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 185         .init_interrupts = kgd_init_interrupts,
 186         .hqd_load = kgd_hqd_load,
 187         .hqd_sdma_load = kgd_hqd_sdma_load,
 188         .hqd_dump = kgd_hqd_dump,
 189         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 190         .hqd_is_occupied = kgd_hqd_is_occupied,
 191         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 192         .hqd_destroy = kgd_hqd_destroy,
 193         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 194         .address_watch_disable = kgd_address_watch_disable,
 195         .address_watch_execute = kgd_address_watch_execute,
 196         .wave_control_execute = kgd_wave_control_execute,
 197         .address_watch_get_offset = kgd_address_watch_get_offset,
 198         .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
 199         .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
 200         .get_fw_version = get_fw_version,
 201         .set_scratch_backing_va = set_scratch_backing_va,
 202         .get_tile_config = get_tile_config,
 203         .get_cu_info = get_cu_info,
 204         .get_vram_usage = amdgpu_amdkfd_get_vram_usage,
 205         .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
 206         .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
 207         .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
 208         .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
 209         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 210         .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
 211         .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
 212         .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
 213         .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
 214         .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
 215         .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
 216         .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
 217         .invalidate_tlbs = invalidate_tlbs,
 218         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 219         .submit_ib = amdgpu_amdkfd_submit_ib,
 220         .get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
 221         .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
 222         .gpu_recover = amdgpu_amdkfd_gpu_reset,
 223         .set_compute_idle = amdgpu_amdkfd_set_compute_idle
 224 };
 225
 226 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 227 {
 228         return (struct kfd2kgd_calls *)&kfd2kgd;
 229 }
 230
 231 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 232 {
 233         return (struct amdgpu_device *)kgd;
 234 }
 235
 236 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 237                         uint32_t queue, uint32_t vmid)
 238 {
 239         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 240         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 241
 242         mutex_lock(&adev->srbm_mutex);
 243         WREG32(mmSRBM_GFX_CNTL, value);
 244 }
 245
 246 static void unlock_srbm(struct kgd_dev *kgd)
 247 {
 248         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 249
 250         WREG32(mmSRBM_GFX_CNTL, 0);
 251         mutex_unlock(&adev->srbm_mutex);
 252 }
 253
 254 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 255                                 uint32_t queue_id)
 256 {
 257         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 258
 259         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 260         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 261
 262         lock_srbm(kgd, mec, pipe, queue_id, 0);
 263 }
 264
 265 static void release_queue(struct kgd_dev *kgd)
 266 {
 267         unlock_srbm(kgd);
 268 }
 269
 270 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 271                                         uint32_t sh_mem_config,
 272                                         uint32_t sh_mem_ape1_base,
 273                                         uint32_t sh_mem_ape1_limit,
 274                                         uint32_t sh_mem_bases)
 275 {
 276         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 277
 278         lock_srbm(kgd, 0, 0, 0, vmid);
 279
 280         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 281         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 282         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 283         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 284
 285         unlock_srbm(kgd);
 286 }
 287
 288 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 289                                         unsigned int vmid)
 290 {
 291         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 292
 293         /*
 294          * We have to assume that there is no outstanding mapping.
 295          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 296          * a mapping is in progress or because a mapping finished and the
 297          * SW cleared it. So the protocol is to always wait & clear.
 298          */
 299         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 300                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 301
 302         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 303
 304         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 305                 cpu_relax();
 306         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 307
 308         /* Mapping vmid to pasid also for IH block */
 309         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 310
 311         return 0;
 312 }
 313
 314 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 315 {
 316         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 317         uint32_t mec;
 318         uint32_t pipe;
 319
 320         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 321         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 322
 323         lock_srbm(kgd, mec, pipe, 0, 0);
 324
 325         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 326                         CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 327
 328         unlock_srbm(kgd);
 329
 330         return 0;
 331 }
 332
 333 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
 334 {
 335         uint32_t retval;
 336
 337         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 338                         m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 339
 340         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 341
 342         return retval;
 343 }
 344
 345 static inline struct cik_mqd *get_mqd(void *mqd)
 346 {
 347         return (struct cik_mqd *)mqd;
 348 }
 349
 350 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
 351 {
 352         return (struct cik_sdma_rlc_registers *)mqd;
 353 }
 354
 355 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 356                         uint32_t queue_id, uint32_t __user *wptr,
 357                         uint32_t wptr_shift, uint32_t wptr_mask,
 358                         struct mm_struct *mm)
 359 {
 360         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 361         struct cik_mqd *m;
 362         uint32_t *mqd_hqd;
 363         uint32_t reg, wptr_val, data;
 364         bool valid_wptr = false;
 365
 366         m = get_mqd(mqd);
 367
 368         acquire_queue(kgd, pipe_id, queue_id);
 369
 370         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
 371         mqd_hqd = &m->cp_mqd_base_addr_lo;
 372
 373         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 374                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 375
 376         /* Copy userspace write pointer value to register.
 377          * Activate doorbell logic to monitor subsequent changes.
 378          */
 379         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 380                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 381         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 382
 383         /* read_user_ptr may take the mm->mmap_sem.
 384          * release srbm_mutex to avoid circular dependency between
 385          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 386          */
 387         release_queue(kgd);
 388         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 389         acquire_queue(kgd, pipe_id, queue_id);
 390         if (valid_wptr)
 391                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 392
 393         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 394         WREG32(mmCP_HQD_ACTIVE, data);
 395
 396         release_queue(kgd);
 397
 398         return 0;
 399 }
 400
 401 static int kgd_hqd_dump(struct kgd_dev *kgd,
 402                         uint32_t pipe_id, uint32_t queue_id,
 403                         uint32_t (**dump)[2], uint32_t *n_regs)
 404 {
 405         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 406         uint32_t i = 0, reg;
 407 #define HQD_N_REGS (35+4)
 408 #define DUMP_REG(addr) do {                             \
 409                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 410                         break;                          \
 411                 (*dump)[i][0] = (addr) << 2;            \
 412                 (*dump)[i++][1] = RREG32(addr);         \
 413         } while (0)
 414
 415         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 416         if (*dump == NULL)
 417                 return -ENOMEM;
 418
 419         acquire_queue(kgd, pipe_id, queue_id);
 420
 421         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 422         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 423         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 424         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 425
 426         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 427                 DUMP_REG(reg);
 428
 429         release_queue(kgd);
 430
 431         WARN_ON_ONCE(i != HQD_N_REGS);
 432         *n_regs = i;
 433
 434         return 0;
 435 }
 436
 437 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 438                              uint32_t __user *wptr, struct mm_struct *mm)
 439 {
 440         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 441         struct cik_sdma_rlc_registers *m;
 442         unsigned long end_jiffies;
 443         uint32_t sdma_base_addr;
 444         uint32_t data;
 445
 446         m = get_sdma_mqd(mqd);
 447         sdma_base_addr = get_sdma_base_addr(m);
 448
 449         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 450                 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 451
 452         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 453         while (true) {
 454                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 455                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 456                         break;
 457                 if (time_after(jiffies, end_jiffies))
 458                         return -ETIME;
 459                 usleep_range(500, 1000);
 460         }
 461         if (m->sdma_engine_id) {
 462                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 463                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 464                                 RESUME_CTX, 0);
 465                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 466         } else {
 467                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 468                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 469                                 RESUME_CTX, 0);
 470                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 471         }
 472
 473         data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
 474                              ENABLE, 1);
 475         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 476         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
 477
 478         if (read_user_wptr(mm, wptr, data))
 479                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 480         else
 481                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 482                        m->sdma_rlc_rb_rptr);
 483
 484         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 485                                 m->sdma_rlc_virtual_addr);
 486         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
 487         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 488                         m->sdma_rlc_rb_base_hi);
 489         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 490                         m->sdma_rlc_rb_rptr_addr_lo);
 491         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 492                         m->sdma_rlc_rb_rptr_addr_hi);
 493
 494         data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
 495                              RB_ENABLE, 1);
 496         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 497
 498         return 0;
 499 }
 500
 501 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 502                              uint32_t engine_id, uint32_t queue_id,
 503                              uint32_t (**dump)[2], uint32_t *n_regs)
 504 {
 505         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 506         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 507                 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 508         uint32_t i = 0, reg;
 509 #undef HQD_N_REGS
 510 #define HQD_N_REGS (19+4)
 511
 512         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 513         if (*dump == NULL)
 514                 return -ENOMEM;
 515
 516         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 517                 DUMP_REG(sdma_offset + reg);
 518         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 519              reg++)
 520                 DUMP_REG(sdma_offset + reg);
 521
 522         WARN_ON_ONCE(i != HQD_N_REGS);
 523         *n_regs = i;
 524
 525         return 0;
 526 }
 527
 528 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 529                                 uint32_t pipe_id, uint32_t queue_id)
 530 {
 531         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 532         uint32_t act;
 533         bool retval = false;
 534         uint32_t low, high;
 535
 536         acquire_queue(kgd, pipe_id, queue_id);
 537         act = RREG32(mmCP_HQD_ACTIVE);
 538         if (act) {
 539                 low = lower_32_bits(queue_address >> 8);
 540                 high = upper_32_bits(queue_address >> 8);
 541
 542                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 543                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 544                         retval = true;
 545         }
 546         release_queue(kgd);
 547         return retval;
 548 }
 549
 550 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 551 {
 552         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 553         struct cik_sdma_rlc_registers *m;
 554         uint32_t sdma_base_addr;
 555         uint32_t sdma_rlc_rb_cntl;
 556
 557         m = get_sdma_mqd(mqd);
 558         sdma_base_addr = get_sdma_base_addr(m);
 559
 560         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 561
 562         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 563                 return true;
 564
 565         return false;
 566 }
 567
 568 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 569                                 enum kfd_preempt_type reset_type,
 570                                 unsigned int utimeout, uint32_t pipe_id,
 571                                 uint32_t queue_id)
 572 {
 573         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 574         uint32_t temp;
 575         enum hqd_dequeue_request_type type;
 576         unsigned long flags, end_jiffies;
 577         int retry;
 578
 579         if (adev->in_gpu_reset)
 580                 return -EIO;
 581
 582         acquire_queue(kgd, pipe_id, queue_id);
 583         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
 584
 585         switch (reset_type) {
 586         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 587                 type = DRAIN_PIPE;
 588                 break;
 589         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 590                 type = RESET_WAVES;
 591                 break;
 592         default:
 593                 type = DRAIN_PIPE;
 594                 break;
 595         }
 596
 597         /* Workaround: If IQ timer is active and the wait time is close to or
 598          * equal to 0, dequeueing is not safe. Wait until either the wait time
 599          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 600          * cleared before continuing. Also, ensure wait times are set to at
 601          * least 0x3.
 602          */
 603         local_irq_save(flags);
 604         preempt_disable();
 605         retry = 5000; /* wait for 500 usecs at maximum */
 606         while (true) {
 607                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 608                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 609                         pr_debug("HW is processing IQ\n");
 610                         goto loop;
 611                 }
 612                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 613                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 614                                         == 3) /* SEM-rearm is safe */
 615                                 break;
 616                         /* Wait time 3 is safe for CP, but our MMIO read/write
 617                          * time is close to 1 microsecond, so check for 10 to
 618                          * leave more buffer room
 619                          */
 620                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 621                                         >= 10)
 622                                 break;
 623                         pr_debug("IQ timer is active\n");
 624                 } else
 625                         break;
 626 loop:
 627                 if (!retry) {
 628                         pr_err("CP HQD IQ timer status time out\n");
 629                         break;
 630                 }
 631                 ndelay(100);
 632                 --retry;
 633         }
 634         retry = 1000;
 635         while (true) {
 636                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 637                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 638                         break;
 639                 pr_debug("Dequeue request is pending\n");
 640
 641                 if (!retry) {
 642                         pr_err("CP HQD dequeue request time out\n");
 643                         break;
 644                 }
 645                 ndelay(100);
 646                 --retry;
 647         }
 648         local_irq_restore(flags);
 649         preempt_enable();
 650
 651         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 652
 653         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 654         while (true) {
 655                 temp = RREG32(mmCP_HQD_ACTIVE);
 656                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 657                         break;
 658                 if (time_after(jiffies, end_jiffies)) {
 659                         pr_err("cp queue preemption time out\n");
 660                         release_queue(kgd);
 661                         return -ETIME;
 662                 }
 663                 usleep_range(500, 1000);
 664         }
 665
 666         release_queue(kgd);
 667         return 0;
 668 }
 669
 670 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 671                                 unsigned int utimeout)
 672 {
 673         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 674         struct cik_sdma_rlc_registers *m;
 675         uint32_t sdma_base_addr;
 676         uint32_t temp;
 677         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 678
 679         m = get_sdma_mqd(mqd);
 680         sdma_base_addr = get_sdma_base_addr(m);
 681
 682         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 683         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 684         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 685
 686         while (true) {
 687                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 688                 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
 689                         break;
 690                 if (time_after(jiffies, end_jiffies))
 691                         return -ETIME;
 692                 usleep_range(500, 1000);
 693         }
 694
 695         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 696         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 697                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 698                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 699
 700         m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 701
 702         return 0;
 703 }
 704
 705 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 706 {
 707         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 708         union TCP_WATCH_CNTL_BITS cntl;
 709         unsigned int i;
 710
 711         cntl.u32All = 0;
 712
 713         cntl.bitfields.valid = 0;
 714         cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
 715         cntl.bitfields.atc = 1;
 716
 717         /* Turning off this address until we set all the registers */
 718         for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
 719                 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
 720                         ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 721
 722         return 0;
 723 }
 724
 725 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 726                                         unsigned int watch_point_id,
 727                                         uint32_t cntl_val,
 728                                         uint32_t addr_hi,
 729                                         uint32_t addr_lo)
 730 {
 731         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 732         union TCP_WATCH_CNTL_BITS cntl;
 733
 734         cntl.u32All = cntl_val;
 735
 736         /* Turning off this watch point until we set all the registers */
 737         cntl.bitfields.valid = 0;
 738         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 739                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 740
 741         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 742                 ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
 743
 744         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 745                 ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
 746
 747         /* Enable the watch point */
 748         cntl.bitfields.valid = 1;
 749
 750         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 751                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 752
 753         return 0;
 754 }
 755
 756 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 757                                         uint32_t gfx_index_val,
 758                                         uint32_t sq_cmd)
 759 {
 760         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 761         uint32_t data;
 762
 763         mutex_lock(&adev->grbm_idx_mutex);
 764
 765         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 766         WREG32(mmSQ_CMD, sq_cmd);
 767
 768         /*  Restore the GRBM_GFX_INDEX register  */
 769
 770         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
 771                 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
 772                 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
 773
 774         WREG32(mmGRBM_GFX_INDEX, data);
 775
 776         mutex_unlock(&adev->grbm_idx_mutex);
 777
 778         return 0;
 779 }
 780
 781 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 782                                         unsigned int watch_point_id,
 783                                         unsigned int reg_offset)
 784 {
 785         return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
 786 }
 787
 788 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 789                                                         uint8_t vmid)
 790 {
 791         uint32_t reg;
 792         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 793
 794         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 795         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 796 }
 797
 798 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 799                                                                 uint8_t vmid)
 800 {
 801         uint32_t reg;
 802         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 803
 804         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 805         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 806 }
 807
 808 static void set_scratch_backing_va(struct kgd_dev *kgd,
 809                                         uint64_t va, uint32_t vmid)
 810 {
 811         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 812
 813         lock_srbm(kgd, 0, 0, 0, vmid);
 814         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 815         unlock_srbm(kgd);
 816 }
 817
 818 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 819 {
 820         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 821         const union amdgpu_firmware_header *hdr;
 822
 823         switch (type) {
 824         case KGD_ENGINE_PFP:
 825                 hdr = (const union amdgpu_firmware_header *)
 826                                                 adev->gfx.pfp_fw->data;
 827                 break;
 828
 829         case KGD_ENGINE_ME:
 830                 hdr = (const union amdgpu_firmware_header *)
 831                                                 adev->gfx.me_fw->data;
 832                 break;
 833
 834         case KGD_ENGINE_CE:
 835                 hdr = (const union amdgpu_firmware_header *)
 836                                                 adev->gfx.ce_fw->data;
 837                 break;
 838
 839         case KGD_ENGINE_MEC1:
 840                 hdr = (const union amdgpu_firmware_header *)
 841                                                 adev->gfx.mec_fw->data;
 842                 break;
 843
 844         case KGD_ENGINE_MEC2:
 845                 hdr = (const union amdgpu_firmware_header *)
 846                                                 adev->gfx.mec2_fw->data;
 847                 break;
 848
 849         case KGD_ENGINE_RLC:
 850                 hdr = (const union amdgpu_firmware_header *)
 851                                                 adev->gfx.rlc_fw->data;
 852                 break;
 853
 854         case KGD_ENGINE_SDMA1:
 855                 hdr = (const union amdgpu_firmware_header *)
 856                                                 adev->sdma.instance[0].fw->data;
 857                 break;
 858
 859         case KGD_ENGINE_SDMA2:
 860                 hdr = (const union amdgpu_firmware_header *)
 861                                                 adev->sdma.instance[1].fw->data;
 862                 break;
 863
 864         default:
 865                 return 0;
 866         }
 867
 868         if (hdr == NULL)
 869                 return 0;
 870
 871         /* Only 12 bit in use*/
 872         return hdr->common.ucode_version;
 873 }
 874
 875 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 876                         uint32_t page_table_base)
 877 {
 878         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 879
 880         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 881                 pr_err("trying to set page table base for wrong VMID\n");
 882                 return;
 883         }
 884         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
 885 }
 886
 887 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 888 {
 889         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 890         int vmid;
 891         unsigned int tmp;
 892
 893         if (adev->in_gpu_reset)
 894                 return -EIO;
 895
 896         for (vmid = 0; vmid < 16; vmid++) {
 897                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 898                         continue;
 899
 900                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 901                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 902                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 903                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 904                         RREG32(mmVM_INVALIDATE_RESPONSE);
 905                         break;
 906                 }
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 913 {
 914         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 915
 916         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 917                 pr_err("non kfd vmid\n");
 918                 return 0;
 919         }
 920
 921         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 922         RREG32(mmVM_INVALIDATE_RESPONSE);
 923         return 0;
 924 }
 925
 926  /**
 927   * read_vmid_from_vmfault_reg - read vmid from register
 928   *
 929   * adev: amdgpu_device pointer
 930   * @vmid: vmid pointer
 931   * read vmid from register (CIK).
 932   */
 933 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
 934 {
 935         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 936
 937         uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
 938
 939         return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 940 }