drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50
  51 #include <drm/drm_debugfs.h>
  52 #include <drm/amdgpu_drm.h>
  53
  54 #include "amdgpu.h"
  55 #include "amdgpu_object.h"
  56 #include "amdgpu_trace.h"
  57 #include "amdgpu_amdkfd.h"
  58 #include "amdgpu_sdma.h"
  59 #include "amdgpu_ras.h"
  60 #include "amdgpu_atomfirmware.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  66                                    struct ttm_tt *ttm,
  67                                    struct ttm_resource *bo_mem);
  68 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  69                                       struct ttm_tt *ttm);
  70
  71 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  72                                     unsigned int type,
  73                                     uint64_t size_in_page)
  74 {
  75         return ttm_range_man_init(&adev->mman.bdev, type,
  76                                   false, size_in_page);
  77 }
  78
  79 /**
  80  * amdgpu_evict_flags - Compute placement flags
  81  *
  82  * @bo: The buffer object to evict
  83  * @placement: Possible destination(s) for evicted BO
  84  *
  85  * Fill in placement data when ttm_bo_evict() is called
  86  */
  87 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  88                                 struct ttm_placement *placement)
  89 {
  90         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  91         struct amdgpu_bo *abo;
  92         static const struct ttm_place placements = {
  93                 .fpfn = 0,
  94                 .lpfn = 0,
  95                 .mem_type = TTM_PL_SYSTEM,
  96                 .flags = 0
  97         };
  98
  99         /* Don't handle scatter gather BOs */
 100         if (bo->type == ttm_bo_type_sg) {
 101                 placement->num_placement = 0;
 102                 placement->num_busy_placement = 0;
 103                 return;
 104         }
 105
 106         /* Object isn't an AMDGPU object so ignore */
 107         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 108                 placement->placement = &placements;
 109                 placement->busy_placement = &placements;
 110                 placement->num_placement = 1;
 111                 placement->num_busy_placement = 1;
 112                 return;
 113         }
 114
 115         abo = ttm_to_amdgpu_bo(bo);
 116         switch (bo->mem.mem_type) {
 117         case AMDGPU_PL_GDS:
 118         case AMDGPU_PL_GWS:
 119         case AMDGPU_PL_OA:
 120                 placement->num_placement = 0;
 121                 placement->num_busy_placement = 0;
 122                 return;
 123
 124         case TTM_PL_VRAM:
 125                 if (!adev->mman.buffer_funcs_enabled) {
 126                         /* Move to system memory */
 127                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 128                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 129                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 130                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 131
 132                         /* Try evicting to the CPU inaccessible part of VRAM
 133                          * first, but only set GTT as busy placement, so this
 134                          * BO will be evicted to GTT rather than causing other
 135                          * BOs to be evicted from VRAM
 136                          */
 137                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 138                                                          AMDGPU_GEM_DOMAIN_GTT);
 139                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 140                         abo->placements[0].lpfn = 0;
 141                         abo->placement.busy_placement = &abo->placements[1];
 142                         abo->placement.num_busy_placement = 1;
 143                 } else {
 144                         /* Move to GTT memory */
 145                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 146                 }
 147                 break;
 148         case TTM_PL_TT:
 149         default:
 150                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 151                 break;
 152         }
 153         *placement = abo->placement;
 154 }
 155
 156 /**
 157  * amdgpu_verify_access - Verify access for a mmap call
 158  *
 159  * @bo: The buffer object to map
 160  * @filp: The file pointer from the process performing the mmap
 161  *
 162  * This is called by ttm_bo_mmap() to verify whether a process
 163  * has the right to mmap a BO to their process space.
 164  */
 165 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 166 {
 167         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 168
 169         /*
 170          * Don't verify access for KFD BOs. They don't have a GEM
 171          * object associated with them.
 172          */
 173         if (abo->kfd_bo)
 174                 return 0;
 175
 176         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 177                 return -EPERM;
 178         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 179                                           filp->private_data);
 180 }
 181
 182 /**
 183  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 184  *
 185  * @bo: The bo to assign the memory to.
 186  * @mm_node: Memory manager node for drm allocator.
 187  * @mem: The region where the bo resides.
 188  *
 189  */
 190 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 191                                     struct drm_mm_node *mm_node,
 192                                     struct ttm_resource *mem)
 193 {
 194         uint64_t addr = 0;
 195
 196         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 197                 addr = mm_node->start << PAGE_SHIFT;
 198                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 199                                                 mem->mem_type);
 200         }
 201         return addr;
 202 }
 203
 204 /**
 205  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 206  * @offset. It also modifies the offset to be within the drm_mm_node returned
 207  *
 208  * @mem: The region where the bo resides.
 209  * @offset: The offset that drm_mm_node is used for finding.
 210  *
 211  */
 212 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 213                                                uint64_t *offset)
 214 {
 215         struct drm_mm_node *mm_node = mem->mm_node;
 216
 217         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 218                 *offset -= (mm_node->size << PAGE_SHIFT);
 219                 ++mm_node;
 220         }
 221         return mm_node;
 222 }
 223
 224 /**
 225  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 226  * @bo: buffer object to map
 227  * @mem: memory object to map
 228  * @mm_node: drm_mm node object to map
 229  * @num_pages: number of pages to map
 230  * @offset: offset into @mm_node where to start
 231  * @window: which GART window to use
 232  * @ring: DMA ring to use for the copy
 233  * @tmz: if we should setup a TMZ enabled mapping
 234  * @addr: resulting address inside the MC address space
 235  *
 236  * Setup one of the GART windows to access a specific piece of memory or return
 237  * the physical address for local memory.
 238  */
 239 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 240                                  struct ttm_resource *mem,
 241                                  struct drm_mm_node *mm_node,
 242                                  unsigned num_pages, uint64_t offset,
 243                                  unsigned window, struct amdgpu_ring *ring,
 244                                  bool tmz, uint64_t *addr)
 245 {
 246         struct amdgpu_device *adev = ring->adev;
 247         struct amdgpu_job *job;
 248         unsigned num_dw, num_bytes;
 249         struct dma_fence *fence;
 250         uint64_t src_addr, dst_addr;
 251         void *cpu_addr;
 252         uint64_t flags;
 253         unsigned int i;
 254         int r;
 255
 256         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 257                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 258
 259         /* Map only what can't be accessed directly */
 260         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 261                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 262                 return 0;
 263         }
 264
 265         *addr = adev->gmc.gart_start;
 266         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 267                 AMDGPU_GPU_PAGE_SIZE;
 268         *addr += offset & ~PAGE_MASK;
 269
 270         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 271         num_bytes = num_pages * 8;
 272
 273         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 274                                      AMDGPU_IB_POOL_DELAYED, &job);
 275         if (r)
 276                 return r;
 277
 278         src_addr = num_dw * 4;
 279         src_addr += job->ibs[0].gpu_addr;
 280
 281         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 282         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 283         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 284                                 dst_addr, num_bytes, false);
 285
 286         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 287         WARN_ON(job->ibs[0].length_dw > num_dw);
 288
 289         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 290         if (tmz)
 291                 flags |= AMDGPU_PTE_TMZ;
 292
 293         cpu_addr = &job->ibs[0].ptr[num_dw];
 294
 295         if (mem->mem_type == TTM_PL_TT) {
 296                 dma_addr_t *dma_address;
 297
 298                 dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT];
 299                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 300                                     cpu_addr);
 301                 if (r)
 302                         goto error_free;
 303         } else {
 304                 dma_addr_t dma_address;
 305
 306                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 307                 dma_address += adev->vm_manager.vram_base_offset;
 308
 309                 for (i = 0; i < num_pages; ++i) {
 310                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 311                                             &dma_address, flags, cpu_addr);
 312                         if (r)
 313                                 goto error_free;
 314
 315                         dma_address += PAGE_SIZE;
 316                 }
 317         }
 318
 319         r = amdgpu_job_submit(job, &adev->mman.entity,
 320                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 321         if (r)
 322                 goto error_free;
 323
 324         dma_fence_put(fence);
 325
 326         return r;
 327
 328 error_free:
 329         amdgpu_job_free(job);
 330         return r;
 331 }
 332
 333 /**
 334  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 335  * @adev: amdgpu device
 336  * @src: buffer/address where to read from
 337  * @dst: buffer/address where to write to
 338  * @size: number of bytes to copy
 339  * @tmz: if a secure copy should be used
 340  * @resv: resv object to sync to
 341  * @f: Returns the last fence if multiple jobs are submitted.
 342  *
 343  * The function copies @size bytes from {src->mem + src->offset} to
 344  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 345  * move and different for a BO to BO copy.
 346  *
 347  */
 348 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 349                                const struct amdgpu_copy_mem *src,
 350                                const struct amdgpu_copy_mem *dst,
 351                                uint64_t size, bool tmz,
 352                                struct dma_resv *resv,
 353                                struct dma_fence **f)
 354 {
 355         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 356                                         AMDGPU_GPU_PAGE_SIZE);
 357
 358         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 359         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 360         struct drm_mm_node *src_mm, *dst_mm;
 361         struct dma_fence *fence = NULL;
 362         int r = 0;
 363
 364         if (!adev->mman.buffer_funcs_enabled) {
 365                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 366                 return -EINVAL;
 367         }
 368
 369         src_offset = src->offset;
 370         if (src->mem->mm_node) {
 371                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 372                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 373         } else {
 374                 src_mm = NULL;
 375                 src_node_size = ULLONG_MAX;
 376         }
 377
 378         dst_offset = dst->offset;
 379         if (dst->mem->mm_node) {
 380                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 381                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 382         } else {
 383                 dst_mm = NULL;
 384                 dst_node_size = ULLONG_MAX;
 385         }
 386
 387         mutex_lock(&adev->mman.gtt_window_lock);
 388
 389         while (size) {
 390                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 391                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 392                 struct dma_fence *next;
 393                 uint32_t cur_size;
 394                 uint64_t from, to;
 395
 396                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 397                  * begins at an offset, then adjust the size accordingly
 398                  */
 399                 cur_size = max(src_page_offset, dst_page_offset);
 400                 cur_size = min(min3(src_node_size, dst_node_size, size),
 401                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 402
 403                 /* Map src to window 0 and dst to window 1. */
 404                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 405                                           PFN_UP(cur_size + src_page_offset),
 406                                           src_offset, 0, ring, tmz, &from);
 407                 if (r)
 408                         goto error;
 409
 410                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 411                                           PFN_UP(cur_size + dst_page_offset),
 412                                           dst_offset, 1, ring, tmz, &to);
 413                 if (r)
 414                         goto error;
 415
 416                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 417                                        resv, &next, false, true, tmz);
 418                 if (r)
 419                         goto error;
 420
 421                 dma_fence_put(fence);
 422                 fence = next;
 423
 424                 size -= cur_size;
 425                 if (!size)
 426                         break;
 427
 428                 src_node_size -= cur_size;
 429                 if (!src_node_size) {
 430                         ++src_mm;
 431                         src_node_size = src_mm->size << PAGE_SHIFT;
 432                         src_offset = 0;
 433                 } else {
 434                         src_offset += cur_size;
 435                 }
 436
 437                 dst_node_size -= cur_size;
 438                 if (!dst_node_size) {
 439                         ++dst_mm;
 440                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 441                         dst_offset = 0;
 442                 } else {
 443                         dst_offset += cur_size;
 444                 }
 445         }
 446 error:
 447         mutex_unlock(&adev->mman.gtt_window_lock);
 448         if (f)
 449                 *f = dma_fence_get(fence);
 450         dma_fence_put(fence);
 451         return r;
 452 }
 453
 454 /**
 455  * amdgpu_move_blit - Copy an entire buffer to another buffer
 456  *
 457  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 458  * help move buffers to and from VRAM.
 459  */
 460 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 461                             bool evict,
 462                             struct ttm_resource *new_mem,
 463                             struct ttm_resource *old_mem)
 464 {
 465         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 466         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 467         struct amdgpu_copy_mem src, dst;
 468         struct dma_fence *fence = NULL;
 469         int r;
 470
 471         src.bo = bo;
 472         dst.bo = bo;
 473         src.mem = old_mem;
 474         dst.mem = new_mem;
 475         src.offset = 0;
 476         dst.offset = 0;
 477
 478         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 479                                        new_mem->num_pages << PAGE_SHIFT,
 480                                        amdgpu_bo_encrypted(abo),
 481                                        bo->base.resv, &fence);
 482         if (r)
 483                 goto error;
 484
 485         /* clear the space being freed */
 486         if (old_mem->mem_type == TTM_PL_VRAM &&
 487             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 488                 struct dma_fence *wipe_fence = NULL;
 489
 490                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 491                                        NULL, &wipe_fence);
 492                 if (r) {
 493                         goto error;
 494                 } else if (wipe_fence) {
 495                         dma_fence_put(fence);
 496                         fence = wipe_fence;
 497                 }
 498         }
 499
 500         /* Always block for VM page tables before committing the new location */
 501         if (bo->type == ttm_bo_type_kernel)
 502                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 503         else
 504                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 505         dma_fence_put(fence);
 506         return r;
 507
 508 error:
 509         if (fence)
 510                 dma_fence_wait(fence, false);
 511         dma_fence_put(fence);
 512         return r;
 513 }
 514
 515 /**
 516  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 517  *
 518  * Called by amdgpu_bo_move()
 519  */
 520 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 521                                struct ttm_resource *mem)
 522 {
 523         struct drm_mm_node *nodes = mem->mm_node;
 524
 525         if (mem->mem_type == TTM_PL_SYSTEM ||
 526             mem->mem_type == TTM_PL_TT)
 527                 return true;
 528         if (mem->mem_type != TTM_PL_VRAM)
 529                 return false;
 530
 531         /* ttm_resource_ioremap only supports contiguous memory */
 532         if (nodes->size != mem->num_pages)
 533                 return false;
 534
 535         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 536                 <= adev->gmc.visible_vram_size;
 537 }
 538
 539 /**
 540  * amdgpu_bo_move - Move a buffer object to a new memory location
 541  *
 542  * Called by ttm_bo_handle_move_mem()
 543  */
 544 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 545                           struct ttm_operation_ctx *ctx,
 546                           struct ttm_resource *new_mem,
 547                           struct ttm_place *hop)
 548 {
 549         struct amdgpu_device *adev;
 550         struct amdgpu_bo *abo;
 551         struct ttm_resource *old_mem = &bo->mem;
 552         int r;
 553
 554         if ((old_mem->mem_type == TTM_PL_SYSTEM &&
 555              new_mem->mem_type == TTM_PL_VRAM) ||
 556             (old_mem->mem_type == TTM_PL_VRAM &&
 557              new_mem->mem_type == TTM_PL_SYSTEM)) {
 558                 hop->fpfn = 0;
 559                 hop->lpfn = 0;
 560                 hop->mem_type = TTM_PL_TT;
 561                 hop->flags = 0;
 562                 return -EMULTIHOP;
 563         }
 564
 565         if (new_mem->mem_type == TTM_PL_TT) {
 566                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 567                 if (r)
 568                         return r;
 569         }
 570
 571         amdgpu_bo_move_notify(bo, evict, new_mem);
 572
 573         /* Can't move a pinned BO */
 574         abo = ttm_to_amdgpu_bo(bo);
 575         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 576                 return -EINVAL;
 577
 578         adev = amdgpu_ttm_adev(bo->bdev);
 579
 580         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 581                 ttm_bo_move_null(bo, new_mem);
 582                 return 0;
 583         }
 584         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 585             new_mem->mem_type == TTM_PL_TT) {
 586                 ttm_bo_move_null(bo, new_mem);
 587                 return 0;
 588         }
 589
 590         if (old_mem->mem_type == TTM_PL_TT &&
 591             new_mem->mem_type == TTM_PL_SYSTEM) {
 592                 r = ttm_bo_wait_ctx(bo, ctx);
 593                 if (r)
 594                         goto fail;
 595
 596                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 597                 ttm_resource_free(bo, &bo->mem);
 598                 ttm_bo_assign_mem(bo, new_mem);
 599                 return 0;
 600         }
 601
 602         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 603             old_mem->mem_type == AMDGPU_PL_GWS ||
 604             old_mem->mem_type == AMDGPU_PL_OA ||
 605             new_mem->mem_type == AMDGPU_PL_GDS ||
 606             new_mem->mem_type == AMDGPU_PL_GWS ||
 607             new_mem->mem_type == AMDGPU_PL_OA) {
 608                 /* Nothing to save here */
 609                 ttm_bo_move_null(bo, new_mem);
 610                 return 0;
 611         }
 612
 613         if (!adev->mman.buffer_funcs_enabled) {
 614                 r = -ENODEV;
 615                 goto memcpy;
 616         }
 617
 618         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 619         if (r) {
 620 memcpy:
 621                 /* Check that all memory is CPU accessible */
 622                 if (!amdgpu_mem_visible(adev, old_mem) ||
 623                     !amdgpu_mem_visible(adev, new_mem)) {
 624                         pr_err("Move buffer fallback to memcpy unavailable\n");
 625                         goto fail;
 626                 }
 627
 628                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 629                 if (r)
 630                         goto fail;
 631         }
 632
 633         if (bo->type == ttm_bo_type_device &&
 634             new_mem->mem_type == TTM_PL_VRAM &&
 635             old_mem->mem_type != TTM_PL_VRAM) {
 636                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 637                  * accesses the BO after it's moved.
 638                  */
 639                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 640         }
 641
 642         /* update statistics */
 643         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 644         return 0;
 645 fail:
 646         swap(*new_mem, bo->mem);
 647         amdgpu_bo_move_notify(bo, false, new_mem);
 648         swap(*new_mem, bo->mem);
 649         return r;
 650 }
 651
 652 /**
 653  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 654  *
 655  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 656  */
 657 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 658 {
 659         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 660         struct drm_mm_node *mm_node = mem->mm_node;
 661         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 662
 663         switch (mem->mem_type) {
 664         case TTM_PL_SYSTEM:
 665                 /* system memory */
 666                 return 0;
 667         case TTM_PL_TT:
 668                 break;
 669         case TTM_PL_VRAM:
 670                 mem->bus.offset = mem->start << PAGE_SHIFT;
 671                 /* check if it's visible */
 672                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 673                         return -EINVAL;
 674                 /* Only physically contiguous buffers apply. In a contiguous
 675                  * buffer, size of the first mm_node would match the number of
 676                  * pages in ttm_resource.
 677                  */
 678                 if (adev->mman.aper_base_kaddr &&
 679                     (mm_node->size == mem->num_pages))
 680                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 681                                         mem->bus.offset;
 682
 683                 mem->bus.offset += adev->gmc.aper_base;
 684                 mem->bus.is_iomem = true;
 685                 mem->bus.caching = ttm_write_combined;
 686                 break;
 687         default:
 688                 return -EINVAL;
 689         }
 690         return 0;
 691 }
 692
 693 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 694                                            unsigned long page_offset)
 695 {
 696         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 697         uint64_t offset = (page_offset << PAGE_SHIFT);
 698         struct drm_mm_node *mm;
 699
 700         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 701         offset += adev->gmc.aper_base;
 702         return mm->start + (offset >> PAGE_SHIFT);
 703 }
 704
 705 /**
 706  * amdgpu_ttm_domain_start - Returns GPU start address
 707  * @adev: amdgpu device object
 708  * @type: type of the memory
 709  *
 710  * Returns:
 711  * GPU start address of a memory domain
 712  */
 713
 714 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 715 {
 716         switch (type) {
 717         case TTM_PL_TT:
 718                 return adev->gmc.gart_start;
 719         case TTM_PL_VRAM:
 720                 return adev->gmc.vram_start;
 721         }
 722
 723         return 0;
 724 }
 725
 726 /*
 727  * TTM backend functions.
 728  */
 729 struct amdgpu_ttm_tt {
 730         struct ttm_tt   ttm;
 731         struct drm_gem_object   *gobj;
 732         u64                     offset;
 733         uint64_t                userptr;
 734         struct task_struct      *usertask;
 735         uint32_t                userflags;
 736         bool                    bound;
 737 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 738         struct hmm_range        *range;
 739 #endif
 740 };
 741
 742 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 743 /**
 744  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 745  * memory and start HMM tracking CPU page table update
 746  *
 747  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 748  * once afterwards to stop HMM tracking
 749  */
 750 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 751 {
 752         struct ttm_tt *ttm = bo->tbo.ttm;
 753         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 754         unsigned long start = gtt->userptr;
 755         struct vm_area_struct *vma;
 756         struct hmm_range *range;
 757         unsigned long timeout;
 758         struct mm_struct *mm;
 759         unsigned long i;
 760         int r = 0;
 761
 762         mm = bo->notifier.mm;
 763         if (unlikely(!mm)) {
 764                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 765                 return -EFAULT;
 766         }
 767
 768         /* Another get_user_pages is running at the same time?? */
 769         if (WARN_ON(gtt->range))
 770                 return -EFAULT;
 771
 772         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 773                 return -ESRCH;
 774
 775         range = kzalloc(sizeof(*range), GFP_KERNEL);
 776         if (unlikely(!range)) {
 777                 r = -ENOMEM;
 778                 goto out;
 779         }
 780         range->notifier = &bo->notifier;
 781         range->start = bo->notifier.interval_tree.start;
 782         range->end = bo->notifier.interval_tree.last + 1;
 783         range->default_flags = HMM_PFN_REQ_FAULT;
 784         if (!amdgpu_ttm_tt_is_readonly(ttm))
 785                 range->default_flags |= HMM_PFN_REQ_WRITE;
 786
 787         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 788                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 789         if (unlikely(!range->hmm_pfns)) {
 790                 r = -ENOMEM;
 791                 goto out_free_ranges;
 792         }
 793
 794         mmap_read_lock(mm);
 795         vma = find_vma(mm, start);
 796         if (unlikely(!vma || start < vma->vm_start)) {
 797                 r = -EFAULT;
 798                 goto out_unlock;
 799         }
 800         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 801                 vma->vm_file)) {
 802                 r = -EPERM;
 803                 goto out_unlock;
 804         }
 805         mmap_read_unlock(mm);
 806         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 807
 808 retry:
 809         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 810
 811         mmap_read_lock(mm);
 812         r = hmm_range_fault(range);
 813         mmap_read_unlock(mm);
 814         if (unlikely(r)) {
 815                 /*
 816                  * FIXME: This timeout should encompass the retry from
 817                  * mmu_interval_read_retry() as well.
 818                  */
 819                 if (r == -EBUSY && !time_after(jiffies, timeout))
 820                         goto retry;
 821                 goto out_free_pfns;
 822         }
 823
 824         /*
 825          * Due to default_flags, all pages are HMM_PFN_VALID or
 826          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 827          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 828          */
 829         for (i = 0; i < ttm->num_pages; i++)
 830                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 831
 832         gtt->range = range;
 833         mmput(mm);
 834
 835         return 0;
 836
 837 out_unlock:
 838         mmap_read_unlock(mm);
 839 out_free_pfns:
 840         kvfree(range->hmm_pfns);
 841 out_free_ranges:
 842         kfree(range);
 843 out:
 844         mmput(mm);
 845         return r;
 846 }
 847
 848 /**
 849  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 850  * Check if the pages backing this ttm range have been invalidated
 851  *
 852  * Returns: true if pages are still valid
 853  */
 854 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 855 {
 856         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 857         bool r = false;
 858
 859         if (!gtt || !gtt->userptr)
 860                 return false;
 861
 862         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 863                 gtt->userptr, ttm->num_pages);
 864
 865         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 866                 "No user pages to check\n");
 867
 868         if (gtt->range) {
 869                 /*
 870                  * FIXME: Must always hold notifier_lock for this, and must
 871                  * not ignore the return code.
 872                  */
 873                 r = mmu_interval_read_retry(gtt->range->notifier,
 874                                          gtt->range->notifier_seq);
 875                 kvfree(gtt->range->hmm_pfns);
 876                 kfree(gtt->range);
 877                 gtt->range = NULL;
 878         }
 879
 880         return !r;
 881 }
 882 #endif
 883
 884 /**
 885  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 886  *
 887  * Called by amdgpu_cs_list_validate(). This creates the page list
 888  * that backs user memory and will ultimately be mapped into the device
 889  * address space.
 890  */
 891 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 892 {
 893         unsigned long i;
 894
 895         for (i = 0; i < ttm->num_pages; ++i)
 896                 ttm->pages[i] = pages ? pages[i] : NULL;
 897 }
 898
 899 /**
 900  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 901  *
 902  * Called by amdgpu_ttm_backend_bind()
 903  **/
 904 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
 905                                      struct ttm_tt *ttm)
 906 {
 907         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 908         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 909         int r;
 910
 911         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 912         enum dma_data_direction direction = write ?
 913                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 914
 915         /* Allocate an SG array and squash pages into it */
 916         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 917                                       ttm->num_pages << PAGE_SHIFT,
 918                                       GFP_KERNEL);
 919         if (r)
 920                 goto release_sg;
 921
 922         /* Map SG to device */
 923         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 924         if (r)
 925                 goto release_sg;
 926
 927         /* convert SG to linear array of pages and dma addresses */
 928         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 929                                          gtt->ttm.dma_address, ttm->num_pages);
 930
 931         return 0;
 932
 933 release_sg:
 934         kfree(ttm->sg);
 935         ttm->sg = NULL;
 936         return r;
 937 }
 938
 939 /**
 940  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 941  */
 942 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
 943                                         struct ttm_tt *ttm)
 944 {
 945         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 946         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 947
 948         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 949         enum dma_data_direction direction = write ?
 950                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 951
 952         /* double check that we don't free the table twice */
 953         if (!ttm->sg->sgl)
 954                 return;
 955
 956         /* unmap the pages mapped to the device */
 957         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 958         sg_free_table(ttm->sg);
 959
 960 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 961         if (gtt->range) {
 962                 unsigned long i;
 963
 964                 for (i = 0; i < ttm->num_pages; i++) {
 965                         if (ttm->pages[i] !=
 966                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 967                                 break;
 968                 }
 969
 970                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 971         }
 972 #endif
 973 }
 974
 975 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 976                                 struct ttm_buffer_object *tbo,
 977                                 uint64_t flags)
 978 {
 979         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 980         struct ttm_tt *ttm = tbo->ttm;
 981         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 982         int r;
 983
 984         if (amdgpu_bo_encrypted(abo))
 985                 flags |= AMDGPU_PTE_TMZ;
 986
 987         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 988                 uint64_t page_idx = 1;
 989
 990                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 991                                 ttm->pages, gtt->ttm.dma_address, flags);
 992                 if (r)
 993                         goto gart_bind_fail;
 994
 995                 /* The memory type of the first page defaults to UC. Now
 996                  * modify the memory type to NC from the second page of
 997                  * the BO onward.
 998                  */
 999                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1000                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1001
1002                 r = amdgpu_gart_bind(adev,
1003                                 gtt->offset + (page_idx << PAGE_SHIFT),
1004                                 ttm->num_pages - page_idx,
1005                                 &ttm->pages[page_idx],
1006                                 &(gtt->ttm.dma_address[page_idx]), flags);
1007         } else {
1008                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1009                                      ttm->pages, gtt->ttm.dma_address, flags);
1010         }
1011
1012 gart_bind_fail:
1013         if (r)
1014                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1015                           ttm->num_pages, gtt->offset);
1016
1017         return r;
1018 }
1019
1020 /**
1021  * amdgpu_ttm_backend_bind - Bind GTT memory
1022  *
1023  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1024  * This handles binding GTT memory to the device address space.
1025  */
1026 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1027                                    struct ttm_tt *ttm,
1028                                    struct ttm_resource *bo_mem)
1029 {
1030         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1031         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1032         uint64_t flags;
1033         int r = 0;
1034
1035         if (!bo_mem)
1036                 return -EINVAL;
1037
1038         if (gtt->bound)
1039                 return 0;
1040
1041         if (gtt->userptr) {
1042                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1043                 if (r) {
1044                         DRM_ERROR("failed to pin userptr\n");
1045                         return r;
1046                 }
1047         }
1048         if (!ttm->num_pages) {
1049                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1050                      ttm->num_pages, bo_mem, ttm);
1051         }
1052
1053         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1054             bo_mem->mem_type == AMDGPU_PL_GWS ||
1055             bo_mem->mem_type == AMDGPU_PL_OA)
1056                 return -EINVAL;
1057
1058         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1059                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1060                 return 0;
1061         }
1062
1063         /* compute PTE flags relevant to this BO memory */
1064         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1065
1066         /* bind pages into GART page tables */
1067         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1068         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1069                 ttm->pages, gtt->ttm.dma_address, flags);
1070
1071         if (r)
1072                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1073                           ttm->num_pages, gtt->offset);
1074         gtt->bound = true;
1075         return r;
1076 }
1077
1078 /**
1079  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1080  * through AGP or GART aperture.
1081  *
1082  * If bo is accessible through AGP aperture, then use AGP aperture
1083  * to access bo; otherwise allocate logical space in GART aperture
1084  * and map bo to GART aperture.
1085  */
1086 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1087 {
1088         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1089         struct ttm_operation_ctx ctx = { false, false };
1090         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1091         struct ttm_resource tmp;
1092         struct ttm_placement placement;
1093         struct ttm_place placements;
1094         uint64_t addr, flags;
1095         int r;
1096
1097         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1098                 return 0;
1099
1100         addr = amdgpu_gmc_agp_addr(bo);
1101         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1102                 bo->mem.start = addr >> PAGE_SHIFT;
1103         } else {
1104
1105                 /* allocate GART space */
1106                 tmp = bo->mem;
1107                 tmp.mm_node = NULL;
1108                 placement.num_placement = 1;
1109                 placement.placement = &placements;
1110                 placement.num_busy_placement = 1;
1111                 placement.busy_placement = &placements;
1112                 placements.fpfn = 0;
1113                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1114                 placements.mem_type = TTM_PL_TT;
1115                 placements.flags = bo->mem.placement;
1116
1117                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1118                 if (unlikely(r))
1119                         return r;
1120
1121                 /* compute PTE flags for this buffer object */
1122                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1123
1124                 /* Bind pages */
1125                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1126                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1127                 if (unlikely(r)) {
1128                         ttm_resource_free(bo, &tmp);
1129                         return r;
1130                 }
1131
1132                 ttm_resource_free(bo, &bo->mem);
1133                 bo->mem = tmp;
1134         }
1135
1136         return 0;
1137 }
1138
1139 /**
1140  * amdgpu_ttm_recover_gart - Rebind GTT pages
1141  *
1142  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1143  * rebind GTT pages during a GPU reset.
1144  */
1145 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1146 {
1147         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1148         uint64_t flags;
1149         int r;
1150
1151         if (!tbo->ttm)
1152                 return 0;
1153
1154         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1155         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1156
1157         return r;
1158 }
1159
1160 /**
1161  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1162  *
1163  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1164  * ttm_tt_destroy().
1165  */
1166 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1167                                       struct ttm_tt *ttm)
1168 {
1169         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1170         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1171         int r;
1172
1173         if (!gtt->bound)
1174                 return;
1175
1176         /* if the pages have userptr pinning then clear that first */
1177         if (gtt->userptr)
1178                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1179
1180         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1181                 return;
1182
1183         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1184         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1185         if (r)
1186                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1187                           gtt->ttm.num_pages, gtt->offset);
1188         gtt->bound = false;
1189 }
1190
1191 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1192                                        struct ttm_tt *ttm)
1193 {
1194         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1195
1196         amdgpu_ttm_backend_unbind(bdev, ttm);
1197         ttm_tt_destroy_common(bdev, ttm);
1198         if (gtt->usertask)
1199                 put_task_struct(gtt->usertask);
1200
1201         ttm_tt_fini(&gtt->ttm);
1202         kfree(gtt);
1203 }
1204
1205 /**
1206  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1207  *
1208  * @bo: The buffer object to create a GTT ttm_tt object around
1209  *
1210  * Called by ttm_tt_create().
1211  */
1212 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1213                                            uint32_t page_flags)
1214 {
1215         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1216         struct amdgpu_ttm_tt *gtt;
1217         enum ttm_caching caching;
1218
1219         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1220         if (gtt == NULL) {
1221                 return NULL;
1222         }
1223         gtt->gobj = &bo->base;
1224
1225         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1226                 caching = ttm_write_combined;
1227         else
1228                 caching = ttm_cached;
1229
1230         /* allocate space for the uninitialized page entries */
1231         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1232                 kfree(gtt);
1233                 return NULL;
1234         }
1235         return &gtt->ttm;
1236 }
1237
1238 /**
1239  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1240  *
1241  * Map the pages of a ttm_tt object to an address space visible
1242  * to the underlying device.
1243  */
1244 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1245                                   struct ttm_tt *ttm,
1246                                   struct ttm_operation_ctx *ctx)
1247 {
1248         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1249         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250
1251         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1252         if (gtt && gtt->userptr) {
1253                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1254                 if (!ttm->sg)
1255                         return -ENOMEM;
1256
1257                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1258                 return 0;
1259         }
1260
1261         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1262                 if (!ttm->sg) {
1263                         struct dma_buf_attachment *attach;
1264                         struct sg_table *sgt;
1265
1266                         attach = gtt->gobj->import_attach;
1267                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1268                         if (IS_ERR(sgt))
1269                                 return PTR_ERR(sgt);
1270
1271                         ttm->sg = sgt;
1272                 }
1273
1274                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1275                                                  gtt->ttm.dma_address,
1276                                                  ttm->num_pages);
1277                 return 0;
1278         }
1279
1280         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1281 }
1282
1283 /**
1284  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1285  *
1286  * Unmaps pages of a ttm_tt object from the device address space and
1287  * unpopulates the page array backing it.
1288  */
1289 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1290                                      struct ttm_tt *ttm)
1291 {
1292         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1293         struct amdgpu_device *adev;
1294
1295         if (gtt && gtt->userptr) {
1296                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1297                 kfree(ttm->sg);
1298                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1299                 return;
1300         }
1301
1302         if (ttm->sg && gtt->gobj->import_attach) {
1303                 struct dma_buf_attachment *attach;
1304
1305                 attach = gtt->gobj->import_attach;
1306                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1307                 ttm->sg = NULL;
1308                 return;
1309         }
1310
1311         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1312                 return;
1313
1314         adev = amdgpu_ttm_adev(bdev);
1315         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1316 }
1317
1318 /**
1319  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1320  * task
1321  *
1322  * @bo: The ttm_buffer_object to bind this userptr to
1323  * @addr:  The address in the current tasks VM space to use
1324  * @flags: Requirements of userptr object.
1325  *
1326  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1327  * to current task
1328  */
1329 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1330                               uint64_t addr, uint32_t flags)
1331 {
1332         struct amdgpu_ttm_tt *gtt;
1333
1334         if (!bo->ttm) {
1335                 /* TODO: We want a separate TTM object type for userptrs */
1336                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1337                 if (bo->ttm == NULL)
1338                         return -ENOMEM;
1339         }
1340
1341         gtt = (void *)bo->ttm;
1342         gtt->userptr = addr;
1343         gtt->userflags = flags;
1344
1345         if (gtt->usertask)
1346                 put_task_struct(gtt->usertask);
1347         gtt->usertask = current->group_leader;
1348         get_task_struct(gtt->usertask);
1349
1350         return 0;
1351 }
1352
1353 /**
1354  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1355  */
1356 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1357 {
1358         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1359
1360         if (gtt == NULL)
1361                 return NULL;
1362
1363         if (gtt->usertask == NULL)
1364                 return NULL;
1365
1366         return gtt->usertask->mm;
1367 }
1368
1369 /**
1370  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1371  * address range for the current task.
1372  *
1373  */
1374 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1375                                   unsigned long end)
1376 {
1377         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1378         unsigned long size;
1379
1380         if (gtt == NULL || !gtt->userptr)
1381                 return false;
1382
1383         /* Return false if no part of the ttm_tt object lies within
1384          * the range
1385          */
1386         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1387         if (gtt->userptr > end || gtt->userptr + size <= start)
1388                 return false;
1389
1390         return true;
1391 }
1392
1393 /**
1394  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1395  */
1396 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1397 {
1398         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1399
1400         if (gtt == NULL || !gtt->userptr)
1401                 return false;
1402
1403         return true;
1404 }
1405
1406 /**
1407  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1408  */
1409 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1410 {
1411         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1412
1413         if (gtt == NULL)
1414                 return false;
1415
1416         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1417 }
1418
1419 /**
1420  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1421  *
1422  * @ttm: The ttm_tt object to compute the flags for
1423  * @mem: The memory registry backing this ttm_tt object
1424  *
1425  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1426  */
1427 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1428 {
1429         uint64_t flags = 0;
1430
1431         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1432                 flags |= AMDGPU_PTE_VALID;
1433
1434         if (mem && mem->mem_type == TTM_PL_TT) {
1435                 flags |= AMDGPU_PTE_SYSTEM;
1436
1437                 if (ttm->caching == ttm_cached)
1438                         flags |= AMDGPU_PTE_SNOOPED;
1439         }
1440
1441         return flags;
1442 }
1443
1444 /**
1445  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1446  *
1447  * @ttm: The ttm_tt object to compute the flags for
1448  * @mem: The memory registry backing this ttm_tt object
1449
1450  * Figure out the flags to use for a VM PTE (Page Table Entry).
1451  */
1452 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1453                                  struct ttm_resource *mem)
1454 {
1455         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1456
1457         flags |= adev->gart.gart_pte_flags;
1458         flags |= AMDGPU_PTE_READABLE;
1459
1460         if (!amdgpu_ttm_tt_is_readonly(ttm))
1461                 flags |= AMDGPU_PTE_WRITEABLE;
1462
1463         return flags;
1464 }
1465
1466 /**
1467  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1468  * object.
1469  *
1470  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1471  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1472  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1473  * used to clean out a memory space.
1474  */
1475 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1476                                             const struct ttm_place *place)
1477 {
1478         unsigned long num_pages = bo->mem.num_pages;
1479         struct drm_mm_node *node = bo->mem.mm_node;
1480         struct dma_resv_list *flist;
1481         struct dma_fence *f;
1482         int i;
1483
1484         if (bo->type == ttm_bo_type_kernel &&
1485             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1486                 return false;
1487
1488         /* If bo is a KFD BO, check if the bo belongs to the current process.
1489          * If true, then return false as any KFD process needs all its BOs to
1490          * be resident to run successfully
1491          */
1492         flist = dma_resv_get_list(bo->base.resv);
1493         if (flist) {
1494                 for (i = 0; i < flist->shared_count; ++i) {
1495                         f = rcu_dereference_protected(flist->shared[i],
1496                                 dma_resv_held(bo->base.resv));
1497                         if (amdkfd_fence_check_mm(f, current->mm))
1498                                 return false;
1499                 }
1500         }
1501
1502         switch (bo->mem.mem_type) {
1503         case TTM_PL_TT:
1504                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1505                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1506                         return false;
1507                 return true;
1508
1509         case TTM_PL_VRAM:
1510                 /* Check each drm MM node individually */
1511                 while (num_pages) {
1512                         if (place->fpfn < (node->start + node->size) &&
1513                             !(place->lpfn && place->lpfn <= node->start))
1514                                 return true;
1515
1516                         num_pages -= node->size;
1517                         ++node;
1518                 }
1519                 return false;
1520
1521         default:
1522                 break;
1523         }
1524
1525         return ttm_bo_eviction_valuable(bo, place);
1526 }
1527
1528 /**
1529  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1530  *
1531  * @bo:  The buffer object to read/write
1532  * @offset:  Offset into buffer object
1533  * @buf:  Secondary buffer to write/read from
1534  * @len: Length in bytes of access
1535  * @write:  true if writing
1536  *
1537  * This is used to access VRAM that backs a buffer object via MMIO
1538  * access for debugging purposes.
1539  */
1540 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1541                                     unsigned long offset,
1542                                     void *buf, int len, int write)
1543 {
1544         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1545         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1546         struct drm_mm_node *nodes;
1547         uint32_t value = 0;
1548         int ret = 0;
1549         uint64_t pos;
1550         unsigned long flags;
1551
1552         if (bo->mem.mem_type != TTM_PL_VRAM)
1553                 return -EIO;
1554
1555         pos = offset;
1556         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1557         pos += (nodes->start << PAGE_SHIFT);
1558
1559         while (len && pos < adev->gmc.mc_vram_size) {
1560                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1561                 uint64_t bytes = 4 - (pos & 3);
1562                 uint32_t shift = (pos & 3) * 8;
1563                 uint32_t mask = 0xffffffff << shift;
1564
1565                 if (len < bytes) {
1566                         mask &= 0xffffffff >> (bytes - len) * 8;
1567                         bytes = len;
1568                 }
1569
1570                 if (mask != 0xffffffff) {
1571                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1572                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1573                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1574                         if (!write || mask != 0xffffffff)
1575                                 value = RREG32_NO_KIQ(mmMM_DATA);
1576                         if (write) {
1577                                 value &= ~mask;
1578                                 value |= (*(uint32_t *)buf << shift) & mask;
1579                                 WREG32_NO_KIQ(mmMM_DATA, value);
1580                         }
1581                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1582                         if (!write) {
1583                                 value = (value & mask) >> shift;
1584                                 memcpy(buf, &value, bytes);
1585                         }
1586                 } else {
1587                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1588                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1589
1590                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1591                                                   bytes, write);
1592                 }
1593
1594                 ret += bytes;
1595                 buf = (uint8_t *)buf + bytes;
1596                 pos += bytes;
1597                 len -= bytes;
1598                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1599                         ++nodes;
1600                         pos = (nodes->start << PAGE_SHIFT);
1601                 }
1602         }
1603
1604         return ret;
1605 }
1606
1607 static void
1608 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1609 {
1610         amdgpu_bo_move_notify(bo, false, NULL);
1611 }
1612
1613 static struct ttm_bo_driver amdgpu_bo_driver = {
1614         .ttm_tt_create = &amdgpu_ttm_tt_create,
1615         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1616         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1617         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1618         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1619         .evict_flags = &amdgpu_evict_flags,
1620         .move = &amdgpu_bo_move,
1621         .verify_access = &amdgpu_verify_access,
1622         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1623         .release_notify = &amdgpu_bo_release_notify,
1624         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1625         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1626         .access_memory = &amdgpu_ttm_access_memory,
1627         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1628 };
1629
1630 /*
1631  * Firmware Reservation functions
1632  */
1633 /**
1634  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1635  *
1636  * @adev: amdgpu_device pointer
1637  *
1638  * free fw reserved vram if it has been reserved.
1639  */
1640 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1641 {
1642         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1643                 NULL, &adev->mman.fw_vram_usage_va);
1644 }
1645
1646 /**
1647  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1648  *
1649  * @adev: amdgpu_device pointer
1650  *
1651  * create bo vram reservation from fw.
1652  */
1653 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1654 {
1655         uint64_t vram_size = adev->gmc.visible_vram_size;
1656
1657         adev->mman.fw_vram_usage_va = NULL;
1658         adev->mman.fw_vram_usage_reserved_bo = NULL;
1659
1660         if (adev->mman.fw_vram_usage_size == 0 ||
1661             adev->mman.fw_vram_usage_size > vram_size)
1662                 return 0;
1663
1664         return amdgpu_bo_create_kernel_at(adev,
1665                                           adev->mman.fw_vram_usage_start_offset,
1666                                           adev->mman.fw_vram_usage_size,
1667                                           AMDGPU_GEM_DOMAIN_VRAM,
1668                                           &adev->mman.fw_vram_usage_reserved_bo,
1669                                           &adev->mman.fw_vram_usage_va);
1670 }
1671
1672 /*
1673  * Memoy training reservation functions
1674  */
1675
1676 /**
1677  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1678  *
1679  * @adev: amdgpu_device pointer
1680  *
1681  * free memory training reserved vram if it has been reserved.
1682  */
1683 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1684 {
1685         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1686
1687         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1688         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1689         ctx->c2p_bo = NULL;
1690
1691         return 0;
1692 }
1693
1694 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1695 {
1696         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1697
1698         memset(ctx, 0, sizeof(*ctx));
1699
1700         ctx->c2p_train_data_offset =
1701                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1702         ctx->p2c_train_data_offset =
1703                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1704         ctx->train_data_size =
1705                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1706
1707         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1708                         ctx->train_data_size,
1709                         ctx->p2c_train_data_offset,
1710                         ctx->c2p_train_data_offset);
1711 }
1712
1713 /*
1714  * reserve TMR memory at the top of VRAM which holds
1715  * IP Discovery data and is protected by PSP.
1716  */
1717 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1718 {
1719         int ret;
1720         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1721         bool mem_train_support = false;
1722
1723         if (!amdgpu_sriov_vf(adev)) {
1724                 ret = amdgpu_mem_train_support(adev);
1725                 if (ret == 1)
1726                         mem_train_support = true;
1727                 else if (ret == -1)
1728                         return -EINVAL;
1729                 else
1730                         DRM_DEBUG("memory training does not support!\n");
1731         }
1732
1733         /*
1734          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1735          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1736          *
1737          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1738          * discovery data and G6 memory training data respectively
1739          */
1740         adev->mman.discovery_tmr_size =
1741                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1742         if (!adev->mman.discovery_tmr_size)
1743                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1744
1745         if (mem_train_support) {
1746                 /* reserve vram for mem train according to TMR location */
1747                 amdgpu_ttm_training_data_block_init(adev);
1748                 ret = amdgpu_bo_create_kernel_at(adev,
1749                                          ctx->c2p_train_data_offset,
1750                                          ctx->train_data_size,
1751                                          AMDGPU_GEM_DOMAIN_VRAM,
1752                                          &ctx->c2p_bo,
1753                                          NULL);
1754                 if (ret) {
1755                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1756                         amdgpu_ttm_training_reserve_vram_fini(adev);
1757                         return ret;
1758                 }
1759                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1760         }
1761
1762         ret = amdgpu_bo_create_kernel_at(adev,
1763                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1764                                 adev->mman.discovery_tmr_size,
1765                                 AMDGPU_GEM_DOMAIN_VRAM,
1766                                 &adev->mman.discovery_memory,
1767                                 NULL);
1768         if (ret) {
1769                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1770                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1771                 return ret;
1772         }
1773
1774         return 0;
1775 }
1776
1777 /**
1778  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1779  * gtt/vram related fields.
1780  *
1781  * This initializes all of the memory space pools that the TTM layer
1782  * will need such as the GTT space (system memory mapped to the device),
1783  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1784  * can be mapped per VMID.
1785  */
1786 int amdgpu_ttm_init(struct amdgpu_device *adev)
1787 {
1788         uint64_t gtt_size;
1789         int r;
1790         u64 vis_vram_limit;
1791
1792         mutex_init(&adev->mman.gtt_window_lock);
1793
1794         /* No others user of address space so set it to 0 */
1795         r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1796                                adev_to_drm(adev)->anon_inode->i_mapping,
1797                                adev_to_drm(adev)->vma_offset_manager,
1798                                adev->need_swiotlb,
1799                                dma_addressing_limited(adev->dev));
1800         if (r) {
1801                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1802                 return r;
1803         }
1804         adev->mman.initialized = true;
1805
1806         /* Initialize VRAM pool with all of VRAM divided into pages */
1807         r = amdgpu_vram_mgr_init(adev);
1808         if (r) {
1809                 DRM_ERROR("Failed initializing VRAM heap.\n");
1810                 return r;
1811         }
1812
1813         /* Reduce size of CPU-visible VRAM if requested */
1814         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1815         if (amdgpu_vis_vram_limit > 0 &&
1816             vis_vram_limit <= adev->gmc.visible_vram_size)
1817                 adev->gmc.visible_vram_size = vis_vram_limit;
1818
1819         /* Change the size here instead of the init above so only lpfn is affected */
1820         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1821 #ifdef CONFIG_64BIT
1822         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1823                                                 adev->gmc.visible_vram_size);
1824 #endif
1825
1826         /*
1827          *The reserved vram for firmware must be pinned to the specified
1828          *place on the VRAM, so reserve it early.
1829          */
1830         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1831         if (r) {
1832                 return r;
1833         }
1834
1835         /*
1836          * only NAVI10 and onwards ASIC support for IP discovery.
1837          * If IP discovery enabled, a block of memory should be
1838          * reserved for IP discovey.
1839          */
1840         if (adev->mman.discovery_bin) {
1841                 r = amdgpu_ttm_reserve_tmr(adev);
1842                 if (r)
1843                         return r;
1844         }
1845
1846         /* allocate memory as required for VGA
1847          * This is used for VGA emulation and pre-OS scanout buffers to
1848          * avoid display artifacts while transitioning between pre-OS
1849          * and driver.  */
1850         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1851                                        AMDGPU_GEM_DOMAIN_VRAM,
1852                                        &adev->mman.stolen_vga_memory,
1853                                        NULL);
1854         if (r)
1855                 return r;
1856         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1857                                        adev->mman.stolen_extended_size,
1858                                        AMDGPU_GEM_DOMAIN_VRAM,
1859                                        &adev->mman.stolen_extended_memory,
1860                                        NULL);
1861         if (r)
1862                 return r;
1863
1864         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1865                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1866
1867         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1868          * or whatever the user passed on module init */
1869         if (amdgpu_gtt_size == -1) {
1870                 struct sysinfo si;
1871
1872                 si_meminfo(&si);
1873                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1874                                adev->gmc.mc_vram_size),
1875                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1876         }
1877         else
1878                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1879
1880         /* Initialize GTT memory pool */
1881         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1882         if (r) {
1883                 DRM_ERROR("Failed initializing GTT heap.\n");
1884                 return r;
1885         }
1886         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1887                  (unsigned)(gtt_size / (1024 * 1024)));
1888
1889         /* Initialize various on-chip memory pools */
1890         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1891         if (r) {
1892                 DRM_ERROR("Failed initializing GDS heap.\n");
1893                 return r;
1894         }
1895
1896         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1897         if (r) {
1898                 DRM_ERROR("Failed initializing gws heap.\n");
1899                 return r;
1900         }
1901
1902         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1903         if (r) {
1904                 DRM_ERROR("Failed initializing oa heap.\n");
1905                 return r;
1906         }
1907
1908         return 0;
1909 }
1910
1911 /**
1912  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1913  */
1914 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1915 {
1916         /* return the VGA stolen memory (if any) back to VRAM */
1917         if (!adev->mman.keep_stolen_vga_memory)
1918                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1919         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1920 }
1921
1922 /**
1923  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1924  */
1925 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1926 {
1927         if (!adev->mman.initialized)
1928                 return;
1929
1930         amdgpu_ttm_training_reserve_vram_fini(adev);
1931         /* return the stolen vga memory back to VRAM */
1932         if (adev->mman.keep_stolen_vga_memory)
1933                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1934         /* return the IP Discovery TMR memory back to VRAM */
1935         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1936         amdgpu_ttm_fw_reserve_vram_fini(adev);
1937
1938         if (adev->mman.aper_base_kaddr)
1939                 iounmap(adev->mman.aper_base_kaddr);
1940         adev->mman.aper_base_kaddr = NULL;
1941
1942         amdgpu_vram_mgr_fini(adev);
1943         amdgpu_gtt_mgr_fini(adev);
1944         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1945         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1946         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1947         ttm_bo_device_release(&adev->mman.bdev);
1948         adev->mman.initialized = false;
1949         DRM_INFO("amdgpu: ttm finalized\n");
1950 }
1951
1952 /**
1953  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1954  *
1955  * @adev: amdgpu_device pointer
1956  * @enable: true when we can use buffer functions.
1957  *
1958  * Enable/disable use of buffer functions during suspend/resume. This should
1959  * only be called at bootup or when userspace isn't running.
1960  */
1961 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1962 {
1963         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1964         uint64_t size;
1965         int r;
1966
1967         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1968             adev->mman.buffer_funcs_enabled == enable)
1969                 return;
1970
1971         if (enable) {
1972                 struct amdgpu_ring *ring;
1973                 struct drm_gpu_scheduler *sched;
1974
1975                 ring = adev->mman.buffer_funcs_ring;
1976                 sched = &ring->sched;
1977                 r = drm_sched_entity_init(&adev->mman.entity,
1978                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1979                                           1, NULL);
1980                 if (r) {
1981                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1982                                   r);
1983                         return;
1984                 }
1985         } else {
1986                 drm_sched_entity_destroy(&adev->mman.entity);
1987                 dma_fence_put(man->move);
1988                 man->move = NULL;
1989         }
1990
1991         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1992         if (enable)
1993                 size = adev->gmc.real_vram_size;
1994         else
1995                 size = adev->gmc.visible_vram_size;
1996         man->size = size >> PAGE_SHIFT;
1997         adev->mman.buffer_funcs_enabled = enable;
1998 }
1999
2000 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
2001 {
2002         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
2003         vm_fault_t ret;
2004
2005         ret = ttm_bo_vm_reserve(bo, vmf);
2006         if (ret)
2007                 return ret;
2008
2009         ret = amdgpu_bo_fault_reserve_notify(bo);
2010         if (ret)
2011                 goto unlock;
2012
2013         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2014                                        TTM_BO_VM_NUM_PREFAULT, 1);
2015         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2016                 return ret;
2017
2018 unlock:
2019         dma_resv_unlock(bo->base.resv);
2020         return ret;
2021 }
2022
2023 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2024         .fault = amdgpu_ttm_fault,
2025         .open = ttm_bo_vm_open,
2026         .close = ttm_bo_vm_close,
2027         .access = ttm_bo_vm_access
2028 };
2029
2030 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2031 {
2032         struct drm_file *file_priv = filp->private_data;
2033         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2034         int r;
2035
2036         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2037         if (unlikely(r != 0))
2038                 return r;
2039
2040         vma->vm_ops = &amdgpu_ttm_vm_ops;
2041         return 0;
2042 }
2043
2044 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2045                        uint64_t dst_offset, uint32_t byte_count,
2046                        struct dma_resv *resv,
2047                        struct dma_fence **fence, bool direct_submit,
2048                        bool vm_needs_flush, bool tmz)
2049 {
2050         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2051                 AMDGPU_IB_POOL_DELAYED;
2052         struct amdgpu_device *adev = ring->adev;
2053         struct amdgpu_job *job;
2054
2055         uint32_t max_bytes;
2056         unsigned num_loops, num_dw;
2057         unsigned i;
2058         int r;
2059
2060         if (direct_submit && !ring->sched.ready) {
2061                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2062                 return -EINVAL;
2063         }
2064
2065         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2066         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2067         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2068
2069         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2070         if (r)
2071                 return r;
2072
2073         if (vm_needs_flush) {
2074                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2075                 job->vm_needs_flush = true;
2076         }
2077         if (resv) {
2078                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2079                                      AMDGPU_SYNC_ALWAYS,
2080                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2081                 if (r) {
2082                         DRM_ERROR("sync failed (%d).\n", r);
2083                         goto error_free;
2084                 }
2085         }
2086
2087         for (i = 0; i < num_loops; i++) {
2088                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2089
2090                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2091                                         dst_offset, cur_size_in_bytes, tmz);
2092
2093                 src_offset += cur_size_in_bytes;
2094                 dst_offset += cur_size_in_bytes;
2095                 byte_count -= cur_size_in_bytes;
2096         }
2097
2098         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2099         WARN_ON(job->ibs[0].length_dw > num_dw);
2100         if (direct_submit)
2101                 r = amdgpu_job_submit_direct(job, ring, fence);
2102         else
2103                 r = amdgpu_job_submit(job, &adev->mman.entity,
2104                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2105         if (r)
2106                 goto error_free;
2107
2108         return r;
2109
2110 error_free:
2111         amdgpu_job_free(job);
2112         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2113         return r;
2114 }
2115
2116 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2117                        uint32_t src_data,
2118                        struct dma_resv *resv,
2119                        struct dma_fence **fence)
2120 {
2121         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2122         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2123         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2124
2125         struct drm_mm_node *mm_node;
2126         unsigned long num_pages;
2127         unsigned int num_loops, num_dw;
2128
2129         struct amdgpu_job *job;
2130         int r;
2131
2132         if (!adev->mman.buffer_funcs_enabled) {
2133                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2134                 return -EINVAL;
2135         }
2136
2137         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2138                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2139                 if (r)
2140                         return r;
2141         }
2142
2143         num_pages = bo->tbo.num_pages;
2144         mm_node = bo->tbo.mem.mm_node;
2145         num_loops = 0;
2146         while (num_pages) {
2147                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2148
2149                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2150                 num_pages -= mm_node->size;
2151                 ++mm_node;
2152         }
2153         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2154
2155         /* for IB padding */
2156         num_dw += 64;
2157
2158         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2159                                      &job);
2160         if (r)
2161                 return r;
2162
2163         if (resv) {
2164                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2165                                      AMDGPU_SYNC_ALWAYS,
2166                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2167                 if (r) {
2168                         DRM_ERROR("sync failed (%d).\n", r);
2169                         goto error_free;
2170                 }
2171         }
2172
2173         num_pages = bo->tbo.num_pages;
2174         mm_node = bo->tbo.mem.mm_node;
2175
2176         while (num_pages) {
2177                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2178                 uint64_t dst_addr;
2179
2180                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2181                 while (byte_count) {
2182                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2183                                                            max_bytes);
2184
2185                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2186                                                 dst_addr, cur_size_in_bytes);
2187
2188                         dst_addr += cur_size_in_bytes;
2189                         byte_count -= cur_size_in_bytes;
2190                 }
2191
2192                 num_pages -= mm_node->size;
2193                 ++mm_node;
2194         }
2195
2196         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2197         WARN_ON(job->ibs[0].length_dw > num_dw);
2198         r = amdgpu_job_submit(job, &adev->mman.entity,
2199                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2200         if (r)
2201                 goto error_free;
2202
2203         return 0;
2204
2205 error_free:
2206         amdgpu_job_free(job);
2207         return r;
2208 }
2209
2210 #if defined(CONFIG_DEBUG_FS)
2211
2212 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2213 {
2214         struct drm_info_node *node = (struct drm_info_node *)m->private;
2215         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2216         struct drm_device *dev = node->minor->dev;
2217         struct amdgpu_device *adev = drm_to_adev(dev);
2218         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2219         struct drm_printer p = drm_seq_file_printer(m);
2220
2221         man->func->debug(man, &p);
2222         return 0;
2223 }
2224
2225 static int amdgpu_ttm_pool_debugfs(struct seq_file *m, void *data)
2226 {
2227         struct drm_info_node *node = (struct drm_info_node *)m->private;
2228         struct drm_device *dev = node->minor->dev;
2229         struct amdgpu_device *adev = drm_to_adev(dev);
2230
2231         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2232 }
2233
2234 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2235         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2236         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2237         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2238         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2239         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2240         {"ttm_page_pool", amdgpu_ttm_pool_debugfs, 0, NULL},
2241 };
2242
2243 /**
2244  * amdgpu_ttm_vram_read - Linear read access to VRAM
2245  *
2246  * Accesses VRAM via MMIO for debugging purposes.
2247  */
2248 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2249                                     size_t size, loff_t *pos)
2250 {
2251         struct amdgpu_device *adev = file_inode(f)->i_private;
2252         ssize_t result = 0;
2253
2254         if (size & 0x3 || *pos & 0x3)
2255                 return -EINVAL;
2256
2257         if (*pos >= adev->gmc.mc_vram_size)
2258                 return -ENXIO;
2259
2260         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2261         while (size) {
2262                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2263                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2264
2265                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2266                 if (copy_to_user(buf, value, bytes))
2267                         return -EFAULT;
2268
2269                 result += bytes;
2270                 buf += bytes;
2271                 *pos += bytes;
2272                 size -= bytes;
2273         }
2274
2275         return result;
2276 }
2277
2278 /**
2279  * amdgpu_ttm_vram_write - Linear write access to VRAM
2280  *
2281  * Accesses VRAM via MMIO for debugging purposes.
2282  */
2283 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2284                                     size_t size, loff_t *pos)
2285 {
2286         struct amdgpu_device *adev = file_inode(f)->i_private;
2287         ssize_t result = 0;
2288         int r;
2289
2290         if (size & 0x3 || *pos & 0x3)
2291                 return -EINVAL;
2292
2293         if (*pos >= adev->gmc.mc_vram_size)
2294                 return -ENXIO;
2295
2296         while (size) {
2297                 unsigned long flags;
2298                 uint32_t value;
2299
2300                 if (*pos >= adev->gmc.mc_vram_size)
2301                         return result;
2302
2303                 r = get_user(value, (uint32_t *)buf);
2304                 if (r)
2305                         return r;
2306
2307                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2308                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2309                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2310                 WREG32_NO_KIQ(mmMM_DATA, value);
2311                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2312
2313                 result += 4;
2314                 buf += 4;
2315                 *pos += 4;
2316                 size -= 4;
2317         }
2318
2319         return result;
2320 }
2321
2322 static const struct file_operations amdgpu_ttm_vram_fops = {
2323         .owner = THIS_MODULE,
2324         .read = amdgpu_ttm_vram_read,
2325         .write = amdgpu_ttm_vram_write,
2326         .llseek = default_llseek,
2327 };
2328
2329 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2330
2331 /**
2332  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2333  */
2334 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2335                                    size_t size, loff_t *pos)
2336 {
2337         struct amdgpu_device *adev = file_inode(f)->i_private;
2338         ssize_t result = 0;
2339         int r;
2340
2341         while (size) {
2342                 loff_t p = *pos / PAGE_SIZE;
2343                 unsigned off = *pos & ~PAGE_MASK;
2344                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2345                 struct page *page;
2346                 void *ptr;
2347
2348                 if (p >= adev->gart.num_cpu_pages)
2349                         return result;
2350
2351                 page = adev->gart.pages[p];
2352                 if (page) {
2353                         ptr = kmap(page);
2354                         ptr += off;
2355
2356                         r = copy_to_user(buf, ptr, cur_size);
2357                         kunmap(adev->gart.pages[p]);
2358                 } else
2359                         r = clear_user(buf, cur_size);
2360
2361                 if (r)
2362                         return -EFAULT;
2363
2364                 result += cur_size;
2365                 buf += cur_size;
2366                 *pos += cur_size;
2367                 size -= cur_size;
2368         }
2369
2370         return result;
2371 }
2372
2373 static const struct file_operations amdgpu_ttm_gtt_fops = {
2374         .owner = THIS_MODULE,
2375         .read = amdgpu_ttm_gtt_read,
2376         .llseek = default_llseek
2377 };
2378
2379 #endif
2380
2381 /**
2382  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2383  *
2384  * This function is used to read memory that has been mapped to the
2385  * GPU and the known addresses are not physical addresses but instead
2386  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2387  */
2388 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2389                                  size_t size, loff_t *pos)
2390 {
2391         struct amdgpu_device *adev = file_inode(f)->i_private;
2392         struct iommu_domain *dom;
2393         ssize_t result = 0;
2394         int r;
2395
2396         /* retrieve the IOMMU domain if any for this device */
2397         dom = iommu_get_domain_for_dev(adev->dev);
2398
2399         while (size) {
2400                 phys_addr_t addr = *pos & PAGE_MASK;
2401                 loff_t off = *pos & ~PAGE_MASK;
2402                 size_t bytes = PAGE_SIZE - off;
2403                 unsigned long pfn;
2404                 struct page *p;
2405                 void *ptr;
2406
2407                 bytes = bytes < size ? bytes : size;
2408
2409                 /* Translate the bus address to a physical address.  If
2410                  * the domain is NULL it means there is no IOMMU active
2411                  * and the address translation is the identity
2412                  */
2413                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2414
2415                 pfn = addr >> PAGE_SHIFT;
2416                 if (!pfn_valid(pfn))
2417                         return -EPERM;
2418
2419                 p = pfn_to_page(pfn);
2420                 if (p->mapping != adev->mman.bdev.dev_mapping)
2421                         return -EPERM;
2422
2423                 ptr = kmap(p);
2424                 r = copy_to_user(buf, ptr + off, bytes);
2425                 kunmap(p);
2426                 if (r)
2427                         return -EFAULT;
2428
2429                 size -= bytes;
2430                 *pos += bytes;
2431                 result += bytes;
2432         }
2433
2434         return result;
2435 }
2436
2437 /**
2438  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2439  *
2440  * This function is used to write memory that has been mapped to the
2441  * GPU and the known addresses are not physical addresses but instead
2442  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2443  */
2444 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2445                                  size_t size, loff_t *pos)
2446 {
2447         struct amdgpu_device *adev = file_inode(f)->i_private;
2448         struct iommu_domain *dom;
2449         ssize_t result = 0;
2450         int r;
2451
2452         dom = iommu_get_domain_for_dev(adev->dev);
2453
2454         while (size) {
2455                 phys_addr_t addr = *pos & PAGE_MASK;
2456                 loff_t off = *pos & ~PAGE_MASK;
2457                 size_t bytes = PAGE_SIZE - off;
2458                 unsigned long pfn;
2459                 struct page *p;
2460                 void *ptr;
2461
2462                 bytes = bytes < size ? bytes : size;
2463
2464                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2465
2466                 pfn = addr >> PAGE_SHIFT;
2467                 if (!pfn_valid(pfn))
2468                         return -EPERM;
2469
2470                 p = pfn_to_page(pfn);
2471                 if (p->mapping != adev->mman.bdev.dev_mapping)
2472                         return -EPERM;
2473
2474                 ptr = kmap(p);
2475                 r = copy_from_user(ptr + off, buf, bytes);
2476                 kunmap(p);
2477                 if (r)
2478                         return -EFAULT;
2479
2480                 size -= bytes;
2481                 *pos += bytes;
2482                 result += bytes;
2483         }
2484
2485         return result;
2486 }
2487
2488 static const struct file_operations amdgpu_ttm_iomem_fops = {
2489         .owner = THIS_MODULE,
2490         .read = amdgpu_iomem_read,
2491         .write = amdgpu_iomem_write,
2492         .llseek = default_llseek
2493 };
2494
2495 static const struct {
2496         char *name;
2497         const struct file_operations *fops;
2498         int domain;
2499 } ttm_debugfs_entries[] = {
2500         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2501 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2502         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2503 #endif
2504         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2505 };
2506
2507 #endif
2508
2509 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2510 {
2511 #if defined(CONFIG_DEBUG_FS)
2512         unsigned count;
2513
2514         struct drm_minor *minor = adev_to_drm(adev)->primary;
2515         struct dentry *ent, *root = minor->debugfs_root;
2516
2517         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2518                 ent = debugfs_create_file(
2519                                 ttm_debugfs_entries[count].name,
2520                                 S_IFREG | S_IRUGO, root,
2521                                 adev,
2522                                 ttm_debugfs_entries[count].fops);
2523                 if (IS_ERR(ent))
2524                         return PTR_ERR(ent);
2525                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2526                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2527                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2528                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2529                 adev->mman.debugfs_entries[count] = ent;
2530         }
2531
2532         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2533         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2534 #else
2535         return 0;
2536 #endif
2537 }