drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 static const struct hwmon_temp_label {
  39         enum PP_HWMON_TEMP channel;
  40         const char *label;
  41 } temp_label[] = {
  42         {PP_TEMP_EDGE, "edge"},
  43         {PP_TEMP_JUNCTION, "junction"},
  44         {PP_TEMP_MEM, "mem"},
  45 };
  46
  47 const char * const amdgpu_pp_profile_name[] = {
  48         "BOOTUP_DEFAULT",
  49         "3D_FULL_SCREEN",
  50         "POWER_SAVING",
  51         "VIDEO",
  52         "VR",
  53         "COMPUTE",
  54         "CUSTOM",
  55         "WINDOW_3D",
  56         "CAPPED",
  57         "UNCAPPED",
  58 };
  59
  60 /**
  61  * DOC: power_dpm_state
  62  *
  63  * The power_dpm_state file is a legacy interface and is only provided for
  64  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  65  * certain power related parameters.  The file power_dpm_state is used for this.
  66  * It accepts the following arguments:
  67  *
  68  * - battery
  69  *
  70  * - balanced
  71  *
  72  * - performance
  73  *
  74  * battery
  75  *
  76  * On older GPUs, the vbios provided a special power state for battery
  77  * operation.  Selecting battery switched to this state.  This is no
  78  * longer provided on newer GPUs so the option does nothing in that case.
  79  *
  80  * balanced
  81  *
  82  * On older GPUs, the vbios provided a special power state for balanced
  83  * operation.  Selecting balanced switched to this state.  This is no
  84  * longer provided on newer GPUs so the option does nothing in that case.
  85  *
  86  * performance
  87  *
  88  * On older GPUs, the vbios provided a special power state for performance
  89  * operation.  Selecting performance switched to this state.  This is no
  90  * longer provided on newer GPUs so the option does nothing in that case.
  91  *
  92  */
  93
  94 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
  95                                           struct device_attribute *attr,
  96                                           char *buf)
  97 {
  98         struct drm_device *ddev = dev_get_drvdata(dev);
  99         struct amdgpu_device *adev = drm_to_adev(ddev);
 100         enum amd_pm_state_type pm;
 101         int ret;
 102
 103         if (amdgpu_in_reset(adev))
 104                 return -EPERM;
 105         if (adev->in_suspend && !adev->in_runpm)
 106                 return -EPERM;
 107
 108         ret = pm_runtime_get_sync(ddev->dev);
 109         if (ret < 0) {
 110                 pm_runtime_put_autosuspend(ddev->dev);
 111                 return ret;
 112         }
 113
 114         amdgpu_dpm_get_current_power_state(adev, &pm);
 115
 116         pm_runtime_mark_last_busy(ddev->dev);
 117         pm_runtime_put_autosuspend(ddev->dev);
 118
 119         return sysfs_emit(buf, "%s\n",
 120                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 121                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 122 }
 123
 124 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 125                                           struct device_attribute *attr,
 126                                           const char *buf,
 127                                           size_t count)
 128 {
 129         struct drm_device *ddev = dev_get_drvdata(dev);
 130         struct amdgpu_device *adev = drm_to_adev(ddev);
 131         enum amd_pm_state_type  state;
 132         int ret;
 133
 134         if (amdgpu_in_reset(adev))
 135                 return -EPERM;
 136         if (adev->in_suspend && !adev->in_runpm)
 137                 return -EPERM;
 138
 139         if (strncmp("battery", buf, strlen("battery")) == 0)
 140                 state = POWER_STATE_TYPE_BATTERY;
 141         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 142                 state = POWER_STATE_TYPE_BALANCED;
 143         else if (strncmp("performance", buf, strlen("performance")) == 0)
 144                 state = POWER_STATE_TYPE_PERFORMANCE;
 145         else
 146                 return -EINVAL;
 147
 148         ret = pm_runtime_get_sync(ddev->dev);
 149         if (ret < 0) {
 150                 pm_runtime_put_autosuspend(ddev->dev);
 151                 return ret;
 152         }
 153
 154         amdgpu_dpm_set_power_state(adev, state);
 155
 156         pm_runtime_mark_last_busy(ddev->dev);
 157         pm_runtime_put_autosuspend(ddev->dev);
 158
 159         return count;
 160 }
 161
 162
 163 /**
 164  * DOC: power_dpm_force_performance_level
 165  *
 166  * The amdgpu driver provides a sysfs API for adjusting certain power
 167  * related parameters.  The file power_dpm_force_performance_level is
 168  * used for this.  It accepts the following arguments:
 169  *
 170  * - auto
 171  *
 172  * - low
 173  *
 174  * - high
 175  *
 176  * - manual
 177  *
 178  * - profile_standard
 179  *
 180  * - profile_min_sclk
 181  *
 182  * - profile_min_mclk
 183  *
 184  * - profile_peak
 185  *
 186  * auto
 187  *
 188  * When auto is selected, the driver will attempt to dynamically select
 189  * the optimal power profile for current conditions in the driver.
 190  *
 191  * low
 192  *
 193  * When low is selected, the clocks are forced to the lowest power state.
 194  *
 195  * high
 196  *
 197  * When high is selected, the clocks are forced to the highest power state.
 198  *
 199  * manual
 200  *
 201  * When manual is selected, the user can manually adjust which power states
 202  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 203  * and pp_dpm_pcie files and adjust the power state transition heuristics
 204  * via the pp_power_profile_mode sysfs file.
 205  *
 206  * profile_standard
 207  * profile_min_sclk
 208  * profile_min_mclk
 209  * profile_peak
 210  *
 211  * When the profiling modes are selected, clock and power gating are
 212  * disabled and the clocks are set for different profiling cases. This
 213  * mode is recommended for profiling specific work loads where you do
 214  * not want clock or power gating for clock fluctuation to interfere
 215  * with your results. profile_standard sets the clocks to a fixed clock
 216  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 217  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 218  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 219  *
 220  */
 221
 222 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 223                                                             struct device_attribute *attr,
 224                                                             char *buf)
 225 {
 226         struct drm_device *ddev = dev_get_drvdata(dev);
 227         struct amdgpu_device *adev = drm_to_adev(ddev);
 228         enum amd_dpm_forced_level level = 0xff;
 229         int ret;
 230
 231         if (amdgpu_in_reset(adev))
 232                 return -EPERM;
 233         if (adev->in_suspend && !adev->in_runpm)
 234                 return -EPERM;
 235
 236         ret = pm_runtime_get_sync(ddev->dev);
 237         if (ret < 0) {
 238                 pm_runtime_put_autosuspend(ddev->dev);
 239                 return ret;
 240         }
 241
 242         level = amdgpu_dpm_get_performance_level(adev);
 243
 244         pm_runtime_mark_last_busy(ddev->dev);
 245         pm_runtime_put_autosuspend(ddev->dev);
 246
 247         return sysfs_emit(buf, "%s\n",
 248                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 249                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 250                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 251                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 252                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 253                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 254                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 255                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 256                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 257                           "unknown");
 258 }
 259
 260 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             const char *buf,
 263                                                             size_t count)
 264 {
 265         struct drm_device *ddev = dev_get_drvdata(dev);
 266         struct amdgpu_device *adev = drm_to_adev(ddev);
 267         enum amd_dpm_forced_level level;
 268         int ret = 0;
 269
 270         if (amdgpu_in_reset(adev))
 271                 return -EPERM;
 272         if (adev->in_suspend && !adev->in_runpm)
 273                 return -EPERM;
 274
 275         if (strncmp("low", buf, strlen("low")) == 0) {
 276                 level = AMD_DPM_FORCED_LEVEL_LOW;
 277         } else if (strncmp("high", buf, strlen("high")) == 0) {
 278                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 279         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 280                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 281         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 282                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 283         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 284                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 285         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 286                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 287         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 288                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 289         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 290                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 291         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 292                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 293         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 294                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 295         }  else {
 296                 return -EINVAL;
 297         }
 298
 299         ret = pm_runtime_get_sync(ddev->dev);
 300         if (ret < 0) {
 301                 pm_runtime_put_autosuspend(ddev->dev);
 302                 return ret;
 303         }
 304
 305         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 306         if (amdgpu_dpm_force_performance_level(adev, level)) {
 307                 pm_runtime_mark_last_busy(ddev->dev);
 308                 pm_runtime_put_autosuspend(ddev->dev);
 309                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 310                 return -EINVAL;
 311         }
 312         /* override whatever a user ctx may have set */
 313         adev->pm.stable_pstate_ctx = NULL;
 314         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 315
 316         pm_runtime_mark_last_busy(ddev->dev);
 317         pm_runtime_put_autosuspend(ddev->dev);
 318
 319         return count;
 320 }
 321
 322 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 323                 struct device_attribute *attr,
 324                 char *buf)
 325 {
 326         struct drm_device *ddev = dev_get_drvdata(dev);
 327         struct amdgpu_device *adev = drm_to_adev(ddev);
 328         struct pp_states_info data;
 329         uint32_t i;
 330         int buf_len, ret;
 331
 332         if (amdgpu_in_reset(adev))
 333                 return -EPERM;
 334         if (adev->in_suspend && !adev->in_runpm)
 335                 return -EPERM;
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 344                 memset(&data, 0, sizeof(data));
 345
 346         pm_runtime_mark_last_busy(ddev->dev);
 347         pm_runtime_put_autosuspend(ddev->dev);
 348
 349         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 350         for (i = 0; i < data.nums; i++)
 351                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 352                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 353                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 354                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 355                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 356
 357         return buf_len;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data = {0};
 367         enum amd_pm_state_type pm = 0;
 368         int i = 0, ret = 0;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         amdgpu_dpm_get_current_power_state(adev, &pm);
 382
 383         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 384
 385         pm_runtime_mark_last_busy(ddev->dev);
 386         pm_runtime_put_autosuspend(ddev->dev);
 387
 388         if (ret)
 389                 return ret;
 390
 391         for (i = 0; i < data.nums; i++) {
 392                 if (pm == data.states[i])
 393                         break;
 394         }
 395
 396         if (i == data.nums)
 397                 i = -EINVAL;
 398
 399         return sysfs_emit(buf, "%d\n", i);
 400 }
 401
 402 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 403                 struct device_attribute *attr,
 404                 char *buf)
 405 {
 406         struct drm_device *ddev = dev_get_drvdata(dev);
 407         struct amdgpu_device *adev = drm_to_adev(ddev);
 408
 409         if (amdgpu_in_reset(adev))
 410                 return -EPERM;
 411         if (adev->in_suspend && !adev->in_runpm)
 412                 return -EPERM;
 413
 414         if (adev->pm.pp_force_state_enabled)
 415                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 416         else
 417                 return sysfs_emit(buf, "\n");
 418 }
 419
 420 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 421                 struct device_attribute *attr,
 422                 const char *buf,
 423                 size_t count)
 424 {
 425         struct drm_device *ddev = dev_get_drvdata(dev);
 426         struct amdgpu_device *adev = drm_to_adev(ddev);
 427         enum amd_pm_state_type state = 0;
 428         struct pp_states_info data;
 429         unsigned long idx;
 430         int ret;
 431
 432         if (amdgpu_in_reset(adev))
 433                 return -EPERM;
 434         if (adev->in_suspend && !adev->in_runpm)
 435                 return -EPERM;
 436
 437         adev->pm.pp_force_state_enabled = false;
 438
 439         if (strlen(buf) == 1)
 440                 return count;
 441
 442         ret = kstrtoul(buf, 0, &idx);
 443         if (ret || idx >= ARRAY_SIZE(data.states))
 444                 return -EINVAL;
 445
 446         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 447
 448         ret = pm_runtime_get_sync(ddev->dev);
 449         if (ret < 0) {
 450                 pm_runtime_put_autosuspend(ddev->dev);
 451                 return ret;
 452         }
 453
 454         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 455         if (ret)
 456                 goto err_out;
 457
 458         state = data.states[idx];
 459
 460         /* only set user selected power states */
 461         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 462             state != POWER_STATE_TYPE_DEFAULT) {
 463                 ret = amdgpu_dpm_dispatch_task(adev,
 464                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 465                 if (ret)
 466                         goto err_out;
 467
 468                 adev->pm.pp_force_state_enabled = true;
 469         }
 470
 471         pm_runtime_mark_last_busy(ddev->dev);
 472         pm_runtime_put_autosuspend(ddev->dev);
 473
 474         return count;
 475
 476 err_out:
 477         pm_runtime_mark_last_busy(ddev->dev);
 478         pm_runtime_put_autosuspend(ddev->dev);
 479         return ret;
 480 }
 481
 482 /**
 483  * DOC: pp_table
 484  *
 485  * The amdgpu driver provides a sysfs API for uploading new powerplay
 486  * tables.  The file pp_table is used for this.  Reading the file
 487  * will dump the current power play table.  Writing to the file
 488  * will attempt to upload a new powerplay table and re-initialize
 489  * powerplay using that new table.
 490  *
 491  */
 492
 493 static ssize_t amdgpu_get_pp_table(struct device *dev,
 494                 struct device_attribute *attr,
 495                 char *buf)
 496 {
 497         struct drm_device *ddev = dev_get_drvdata(dev);
 498         struct amdgpu_device *adev = drm_to_adev(ddev);
 499         char *table = NULL;
 500         int size, ret;
 501
 502         if (amdgpu_in_reset(adev))
 503                 return -EPERM;
 504         if (adev->in_suspend && !adev->in_runpm)
 505                 return -EPERM;
 506
 507         ret = pm_runtime_get_sync(ddev->dev);
 508         if (ret < 0) {
 509                 pm_runtime_put_autosuspend(ddev->dev);
 510                 return ret;
 511         }
 512
 513         size = amdgpu_dpm_get_pp_table(adev, &table);
 514
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517
 518         if (size <= 0)
 519                 return size;
 520
 521         if (size >= PAGE_SIZE)
 522                 size = PAGE_SIZE - 1;
 523
 524         memcpy(buf, table, size);
 525
 526         return size;
 527 }
 528
 529 static ssize_t amdgpu_set_pp_table(struct device *dev,
 530                 struct device_attribute *attr,
 531                 const char *buf,
 532                 size_t count)
 533 {
 534         struct drm_device *ddev = dev_get_drvdata(dev);
 535         struct amdgpu_device *adev = drm_to_adev(ddev);
 536         int ret = 0;
 537
 538         if (amdgpu_in_reset(adev))
 539                 return -EPERM;
 540         if (adev->in_suspend && !adev->in_runpm)
 541                 return -EPERM;
 542
 543         ret = pm_runtime_get_sync(ddev->dev);
 544         if (ret < 0) {
 545                 pm_runtime_put_autosuspend(ddev->dev);
 546                 return ret;
 547         }
 548
 549         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 550
 551         pm_runtime_mark_last_busy(ddev->dev);
 552         pm_runtime_put_autosuspend(ddev->dev);
 553
 554         if (ret)
 555                 return ret;
 556
 557         return count;
 558 }
 559
 560 /**
 561  * DOC: pp_od_clk_voltage
 562  *
 563  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 564  * in each power level within a power state.  The pp_od_clk_voltage is used for
 565  * this.
 566  *
 567  * Note that the actual memory controller clock rate are exposed, not
 568  * the effective memory clock of the DRAMs. To translate it, use the
 569  * following formula:
 570  *
 571  * Clock conversion (Mhz):
 572  *
 573  * HBM: effective_memory_clock = memory_controller_clock * 1
 574  *
 575  * G5: effective_memory_clock = memory_controller_clock * 1
 576  *
 577  * G6: effective_memory_clock = memory_controller_clock * 2
 578  *
 579  * DRAM data rate (MT/s):
 580  *
 581  * HBM: effective_memory_clock * 2 = data_rate
 582  *
 583  * G5: effective_memory_clock * 4 = data_rate
 584  *
 585  * G6: effective_memory_clock * 8 = data_rate
 586  *
 587  * Bandwidth (MB/s):
 588  *
 589  * data_rate * vram_bit_width / 8 = memory_bandwidth
 590  *
 591  * Some examples:
 592  *
 593  * G5 on RX460:
 594  *
 595  * memory_controller_clock = 1750 Mhz
 596  *
 597  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 598  *
 599  * data rate = 1750 * 4 = 7000 MT/s
 600  *
 601  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 602  *
 603  * G6 on RX5700:
 604  *
 605  * memory_controller_clock = 875 Mhz
 606  *
 607  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 608  *
 609  * data rate = 1750 * 8 = 14000 MT/s
 610  *
 611  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 612  *
 613  * < For Vega10 and previous ASICs >
 614  *
 615  * Reading the file will display:
 616  *
 617  * - a list of engine clock levels and voltages labeled OD_SCLK
 618  *
 619  * - a list of memory clock levels and voltages labeled OD_MCLK
 620  *
 621  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 622  *
 623  * To manually adjust these settings, first select manual using
 624  * power_dpm_force_performance_level. Enter a new value for each
 625  * level by writing a string that contains "s/m level clock voltage" to
 626  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 627  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 628  * 810 mV.  When you have edited all of the states as needed, write
 629  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 630  * default power levels, write "r" (reset) to the file to reset them.
 631  *
 632  *
 633  * < For Vega20 and newer ASICs >
 634  *
 635  * Reading the file will display:
 636  *
 637  * - minimum and maximum engine clock labeled OD_SCLK
 638  *
 639  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 640  *   clock labeled OD_MCLK
 641  *
 642  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 643  *   They can be used to calibrate the sclk voltage curve. This is
 644  *   available for Vega20 and NV1X.
 645  *
 646  * - voltage offset for the six anchor points of the v/f curve labeled
 647  *   OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This
 648  *   is only availabe for some SMU13 ASICs.
 649  *
 650  * - voltage offset(in mV) applied on target voltage calculation.
 651  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 652  *   Cavefish. For these ASICs, the target voltage calculation can be
 653  *   illustrated by "voltage = voltage calculated from v/f curve +
 654  *   overdrive vddgfx offset"
 655  *
 656  * - a list of valid ranges for sclk, mclk, and voltage curve points
 657  *   labeled OD_RANGE
 658  *
 659  * < For APUs >
 660  *
 661  * Reading the file will display:
 662  *
 663  * - minimum and maximum engine clock labeled OD_SCLK
 664  *
 665  * - a list of valid ranges for sclk labeled OD_RANGE
 666  *
 667  * < For VanGogh >
 668  *
 669  * Reading the file will display:
 670  *
 671  * - minimum and maximum engine clock labeled OD_SCLK
 672  * - minimum and maximum core clocks labeled OD_CCLK
 673  *
 674  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 675  *
 676  * To manually adjust these settings:
 677  *
 678  * - First select manual using power_dpm_force_performance_level
 679  *
 680  * - For clock frequency setting, enter a new value by writing a
 681  *   string that contains "s/m index clock" to the file. The index
 682  *   should be 0 if to set minimum clock. And 1 if to set maximum
 683  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 684  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 685  *   clocks on VanGogh, the string contains "p core index clock".
 686  *   E.g., "p 2 0 800" would set the minimum core clock on core
 687  *   2 to 800Mhz.
 688  *
 689  *   For sclk voltage curve,
 690  *     - For NV1X, enter the new values by writing a string that
 691  *       contains "vc point clock voltage" to the file. The points
 692  *       are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update
 693  *       point1 with clock set as 300Mhz and voltage as 600mV. "vc 2
 694  *       1000 1000" will update point3 with clock set as 1000Mhz and
 695  *       voltage 1000mV.
 696  *     - For SMU13 ASICs, enter the new values by writing a string that
 697  *       contains "vc anchor_point_index voltage_offset" to the file.
 698  *       There are total six anchor points defined on the v/f curve with
 699  *       index as 0 - 5.
 700  *       - "vc 0 10" will update the voltage offset for point1 as 10mv.
 701  *       - "vc 5 -10" will update the voltage offset for point6 as -10mv.
 702  *
 703  *   To update the voltage offset applied for gfxclk/voltage calculation,
 704  *   enter the new value by writing a string that contains "vo offset".
 705  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 706  *   And the offset can be a positive or negative value.
 707  *
 708  * - When you have edited all of the states as needed, write "c" (commit)
 709  *   to the file to commit your changes
 710  *
 711  * - If you want to reset to the default power levels, write "r" (reset)
 712  *   to the file to reset them
 713  *
 714  */
 715
 716 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 717                 struct device_attribute *attr,
 718                 const char *buf,
 719                 size_t count)
 720 {
 721         struct drm_device *ddev = dev_get_drvdata(dev);
 722         struct amdgpu_device *adev = drm_to_adev(ddev);
 723         int ret;
 724         uint32_t parameter_size = 0;
 725         long parameter[64];
 726         char buf_cpy[128];
 727         char *tmp_str;
 728         char *sub_str;
 729         const char delimiter[3] = {' ', '\n', '\0'};
 730         uint32_t type;
 731
 732         if (amdgpu_in_reset(adev))
 733                 return -EPERM;
 734         if (adev->in_suspend && !adev->in_runpm)
 735                 return -EPERM;
 736
 737         if (count > 127)
 738                 return -EINVAL;
 739
 740         if (*buf == 's')
 741                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 742         else if (*buf == 'p')
 743                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 744         else if (*buf == 'm')
 745                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 746         else if(*buf == 'r')
 747                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 748         else if (*buf == 'c')
 749                 type = PP_OD_COMMIT_DPM_TABLE;
 750         else if (!strncmp(buf, "vc", 2))
 751                 type = PP_OD_EDIT_VDDC_CURVE;
 752         else if (!strncmp(buf, "vo", 2))
 753                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 754         else
 755                 return -EINVAL;
 756
 757         memcpy(buf_cpy, buf, count+1);
 758
 759         tmp_str = buf_cpy;
 760
 761         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 762              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 763                 tmp_str++;
 764         while (isspace(*++tmp_str));
 765
 766         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 767                 if (strlen(sub_str) == 0)
 768                         continue;
 769                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 770                 if (ret)
 771                         return -EINVAL;
 772                 parameter_size++;
 773
 774                 while (isspace(*tmp_str))
 775                         tmp_str++;
 776         }
 777
 778         ret = pm_runtime_get_sync(ddev->dev);
 779         if (ret < 0) {
 780                 pm_runtime_put_autosuspend(ddev->dev);
 781                 return ret;
 782         }
 783
 784         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 785                                               type,
 786                                               parameter,
 787                                               parameter_size))
 788                 goto err_out;
 789
 790         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 791                                           parameter, parameter_size))
 792                 goto err_out;
 793
 794         if (type == PP_OD_COMMIT_DPM_TABLE) {
 795                 if (amdgpu_dpm_dispatch_task(adev,
 796                                              AMD_PP_TASK_READJUST_POWER_STATE,
 797                                              NULL))
 798                         goto err_out;
 799         }
 800
 801         pm_runtime_mark_last_busy(ddev->dev);
 802         pm_runtime_put_autosuspend(ddev->dev);
 803
 804         return count;
 805
 806 err_out:
 807         pm_runtime_mark_last_busy(ddev->dev);
 808         pm_runtime_put_autosuspend(ddev->dev);
 809         return -EINVAL;
 810 }
 811
 812 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 813                 struct device_attribute *attr,
 814                 char *buf)
 815 {
 816         struct drm_device *ddev = dev_get_drvdata(dev);
 817         struct amdgpu_device *adev = drm_to_adev(ddev);
 818         int size = 0;
 819         int ret;
 820         enum pp_clock_type od_clocks[6] = {
 821                 OD_SCLK,
 822                 OD_MCLK,
 823                 OD_VDDC_CURVE,
 824                 OD_RANGE,
 825                 OD_VDDGFX_OFFSET,
 826                 OD_CCLK,
 827         };
 828         uint clk_index;
 829
 830         if (amdgpu_in_reset(adev))
 831                 return -EPERM;
 832         if (adev->in_suspend && !adev->in_runpm)
 833                 return -EPERM;
 834
 835         ret = pm_runtime_get_sync(ddev->dev);
 836         if (ret < 0) {
 837                 pm_runtime_put_autosuspend(ddev->dev);
 838                 return ret;
 839         }
 840
 841         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 842                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 843                 if (ret)
 844                         break;
 845         }
 846         if (ret == -ENOENT) {
 847                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 848                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 849                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 850                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 851                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 852                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 853         }
 854
 855         if (size == 0)
 856                 size = sysfs_emit(buf, "\n");
 857
 858         pm_runtime_mark_last_busy(ddev->dev);
 859         pm_runtime_put_autosuspend(ddev->dev);
 860
 861         return size;
 862 }
 863
 864 /**
 865  * DOC: pp_features
 866  *
 867  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 868  * features to be enabled. The file pp_features is used for this. And
 869  * this is only available for Vega10 and later dGPUs.
 870  *
 871  * Reading back the file will show you the followings:
 872  * - Current ppfeature masks
 873  * - List of the all supported powerplay features with their naming,
 874  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 875  *
 876  * To manually enable or disable a specific feature, just set or clear
 877  * the corresponding bit from original ppfeature masks and input the
 878  * new ppfeature masks.
 879  */
 880 static ssize_t amdgpu_set_pp_features(struct device *dev,
 881                                       struct device_attribute *attr,
 882                                       const char *buf,
 883                                       size_t count)
 884 {
 885         struct drm_device *ddev = dev_get_drvdata(dev);
 886         struct amdgpu_device *adev = drm_to_adev(ddev);
 887         uint64_t featuremask;
 888         int ret;
 889
 890         if (amdgpu_in_reset(adev))
 891                 return -EPERM;
 892         if (adev->in_suspend && !adev->in_runpm)
 893                 return -EPERM;
 894
 895         ret = kstrtou64(buf, 0, &featuremask);
 896         if (ret)
 897                 return -EINVAL;
 898
 899         ret = pm_runtime_get_sync(ddev->dev);
 900         if (ret < 0) {
 901                 pm_runtime_put_autosuspend(ddev->dev);
 902                 return ret;
 903         }
 904
 905         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 906
 907         pm_runtime_mark_last_busy(ddev->dev);
 908         pm_runtime_put_autosuspend(ddev->dev);
 909
 910         if (ret)
 911                 return -EINVAL;
 912
 913         return count;
 914 }
 915
 916 static ssize_t amdgpu_get_pp_features(struct device *dev,
 917                                       struct device_attribute *attr,
 918                                       char *buf)
 919 {
 920         struct drm_device *ddev = dev_get_drvdata(dev);
 921         struct amdgpu_device *adev = drm_to_adev(ddev);
 922         ssize_t size;
 923         int ret;
 924
 925         if (amdgpu_in_reset(adev))
 926                 return -EPERM;
 927         if (adev->in_suspend && !adev->in_runpm)
 928                 return -EPERM;
 929
 930         ret = pm_runtime_get_sync(ddev->dev);
 931         if (ret < 0) {
 932                 pm_runtime_put_autosuspend(ddev->dev);
 933                 return ret;
 934         }
 935
 936         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 937         if (size <= 0)
 938                 size = sysfs_emit(buf, "\n");
 939
 940         pm_runtime_mark_last_busy(ddev->dev);
 941         pm_runtime_put_autosuspend(ddev->dev);
 942
 943         return size;
 944 }
 945
 946 /**
 947  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 948  *
 949  * The amdgpu driver provides a sysfs API for adjusting what power levels
 950  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 951  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 952  * this.
 953  *
 954  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 955  * Vega10 and later ASICs.
 956  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 957  *
 958  * Reading back the files will show you the available power levels within
 959  * the power state and the clock information for those levels.
 960  *
 961  * To manually adjust these states, first select manual using
 962  * power_dpm_force_performance_level.
 963  * Secondly, enter a new value for each level by inputing a string that
 964  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 965  * E.g.,
 966  *
 967  * .. code-block:: bash
 968  *
 969  *      echo "4 5 6" > pp_dpm_sclk
 970  *
 971  * will enable sclk levels 4, 5, and 6.
 972  *
 973  * NOTE: change to the dcefclk max dpm level is not supported now
 974  */
 975
 976 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
 977                 enum pp_clock_type type,
 978                 char *buf)
 979 {
 980         struct drm_device *ddev = dev_get_drvdata(dev);
 981         struct amdgpu_device *adev = drm_to_adev(ddev);
 982         int size = 0;
 983         int ret = 0;
 984
 985         if (amdgpu_in_reset(adev))
 986                 return -EPERM;
 987         if (adev->in_suspend && !adev->in_runpm)
 988                 return -EPERM;
 989
 990         ret = pm_runtime_get_sync(ddev->dev);
 991         if (ret < 0) {
 992                 pm_runtime_put_autosuspend(ddev->dev);
 993                 return ret;
 994         }
 995
 996         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
 997         if (ret == -ENOENT)
 998                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
 999
1000         if (size == 0)
1001                 size = sysfs_emit(buf, "\n");
1002
1003         pm_runtime_mark_last_busy(ddev->dev);
1004         pm_runtime_put_autosuspend(ddev->dev);
1005
1006         return size;
1007 }
1008
1009 /*
1010  * Worst case: 32 bits individually specified, in octal at 12 characters
1011  * per line (+1 for \n).
1012  */
1013 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1014
1015 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1016 {
1017         int ret;
1018         unsigned long level;
1019         char *sub_str = NULL;
1020         char *tmp;
1021         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1022         const char delimiter[3] = {' ', '\n', '\0'};
1023         size_t bytes;
1024
1025         *mask = 0;
1026
1027         bytes = min(count, sizeof(buf_cpy) - 1);
1028         memcpy(buf_cpy, buf, bytes);
1029         buf_cpy[bytes] = '\0';
1030         tmp = buf_cpy;
1031         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1032                 if (strlen(sub_str)) {
1033                         ret = kstrtoul(sub_str, 0, &level);
1034                         if (ret || level > 31)
1035                                 return -EINVAL;
1036                         *mask |= 1 << level;
1037                 } else
1038                         break;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1045                 enum pp_clock_type type,
1046                 const char *buf,
1047                 size_t count)
1048 {
1049         struct drm_device *ddev = dev_get_drvdata(dev);
1050         struct amdgpu_device *adev = drm_to_adev(ddev);
1051         int ret;
1052         uint32_t mask = 0;
1053
1054         if (amdgpu_in_reset(adev))
1055                 return -EPERM;
1056         if (adev->in_suspend && !adev->in_runpm)
1057                 return -EPERM;
1058
1059         ret = amdgpu_read_mask(buf, count, &mask);
1060         if (ret)
1061                 return ret;
1062
1063         ret = pm_runtime_get_sync(ddev->dev);
1064         if (ret < 0) {
1065                 pm_runtime_put_autosuspend(ddev->dev);
1066                 return ret;
1067         }
1068
1069         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1070
1071         pm_runtime_mark_last_busy(ddev->dev);
1072         pm_runtime_put_autosuspend(ddev->dev);
1073
1074         if (ret)
1075                 return -EINVAL;
1076
1077         return count;
1078 }
1079
1080 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1081                 struct device_attribute *attr,
1082                 char *buf)
1083 {
1084         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1085 }
1086
1087 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1088                 struct device_attribute *attr,
1089                 const char *buf,
1090                 size_t count)
1091 {
1092         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1093 }
1094
1095 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1096                 struct device_attribute *attr,
1097                 char *buf)
1098 {
1099         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1100 }
1101
1102 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1103                 struct device_attribute *attr,
1104                 const char *buf,
1105                 size_t count)
1106 {
1107         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1108 }
1109
1110 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1111                 struct device_attribute *attr,
1112                 char *buf)
1113 {
1114         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1115 }
1116
1117 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1118                 struct device_attribute *attr,
1119                 const char *buf,
1120                 size_t count)
1121 {
1122         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1123 }
1124
1125 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1126                 struct device_attribute *attr,
1127                 char *buf)
1128 {
1129         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1130 }
1131
1132 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1133                 struct device_attribute *attr,
1134                 const char *buf,
1135                 size_t count)
1136 {
1137         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1138 }
1139
1140 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1141                 struct device_attribute *attr,
1142                 char *buf)
1143 {
1144         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1145 }
1146
1147 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1148                 struct device_attribute *attr,
1149                 const char *buf,
1150                 size_t count)
1151 {
1152         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1153 }
1154
1155 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1156                 struct device_attribute *attr,
1157                 char *buf)
1158 {
1159         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1160 }
1161
1162 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1163                 struct device_attribute *attr,
1164                 const char *buf,
1165                 size_t count)
1166 {
1167         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1168 }
1169
1170 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1171                 struct device_attribute *attr,
1172                 char *buf)
1173 {
1174         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1175 }
1176
1177 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1178                 struct device_attribute *attr,
1179                 const char *buf,
1180                 size_t count)
1181 {
1182         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1183 }
1184
1185 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1186                 struct device_attribute *attr,
1187                 char *buf)
1188 {
1189         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1190 }
1191
1192 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1193                 struct device_attribute *attr,
1194                 const char *buf,
1195                 size_t count)
1196 {
1197         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1198 }
1199
1200 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1201                 struct device_attribute *attr,
1202                 char *buf)
1203 {
1204         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1205 }
1206
1207 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1208                 struct device_attribute *attr,
1209                 const char *buf,
1210                 size_t count)
1211 {
1212         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1213 }
1214
1215 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1216                 struct device_attribute *attr,
1217                 char *buf)
1218 {
1219         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1220 }
1221
1222 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1223                 struct device_attribute *attr,
1224                 const char *buf,
1225                 size_t count)
1226 {
1227         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1228 }
1229
1230 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1231                 struct device_attribute *attr,
1232                 char *buf)
1233 {
1234         struct drm_device *ddev = dev_get_drvdata(dev);
1235         struct amdgpu_device *adev = drm_to_adev(ddev);
1236         uint32_t value = 0;
1237         int ret;
1238
1239         if (amdgpu_in_reset(adev))
1240                 return -EPERM;
1241         if (adev->in_suspend && !adev->in_runpm)
1242                 return -EPERM;
1243
1244         ret = pm_runtime_get_sync(ddev->dev);
1245         if (ret < 0) {
1246                 pm_runtime_put_autosuspend(ddev->dev);
1247                 return ret;
1248         }
1249
1250         value = amdgpu_dpm_get_sclk_od(adev);
1251
1252         pm_runtime_mark_last_busy(ddev->dev);
1253         pm_runtime_put_autosuspend(ddev->dev);
1254
1255         return sysfs_emit(buf, "%d\n", value);
1256 }
1257
1258 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1259                 struct device_attribute *attr,
1260                 const char *buf,
1261                 size_t count)
1262 {
1263         struct drm_device *ddev = dev_get_drvdata(dev);
1264         struct amdgpu_device *adev = drm_to_adev(ddev);
1265         int ret;
1266         long int value;
1267
1268         if (amdgpu_in_reset(adev))
1269                 return -EPERM;
1270         if (adev->in_suspend && !adev->in_runpm)
1271                 return -EPERM;
1272
1273         ret = kstrtol(buf, 0, &value);
1274
1275         if (ret)
1276                 return -EINVAL;
1277
1278         ret = pm_runtime_get_sync(ddev->dev);
1279         if (ret < 0) {
1280                 pm_runtime_put_autosuspend(ddev->dev);
1281                 return ret;
1282         }
1283
1284         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1285
1286         pm_runtime_mark_last_busy(ddev->dev);
1287         pm_runtime_put_autosuspend(ddev->dev);
1288
1289         return count;
1290 }
1291
1292 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1293                 struct device_attribute *attr,
1294                 char *buf)
1295 {
1296         struct drm_device *ddev = dev_get_drvdata(dev);
1297         struct amdgpu_device *adev = drm_to_adev(ddev);
1298         uint32_t value = 0;
1299         int ret;
1300
1301         if (amdgpu_in_reset(adev))
1302                 return -EPERM;
1303         if (adev->in_suspend && !adev->in_runpm)
1304                 return -EPERM;
1305
1306         ret = pm_runtime_get_sync(ddev->dev);
1307         if (ret < 0) {
1308                 pm_runtime_put_autosuspend(ddev->dev);
1309                 return ret;
1310         }
1311
1312         value = amdgpu_dpm_get_mclk_od(adev);
1313
1314         pm_runtime_mark_last_busy(ddev->dev);
1315         pm_runtime_put_autosuspend(ddev->dev);
1316
1317         return sysfs_emit(buf, "%d\n", value);
1318 }
1319
1320 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1321                 struct device_attribute *attr,
1322                 const char *buf,
1323                 size_t count)
1324 {
1325         struct drm_device *ddev = dev_get_drvdata(dev);
1326         struct amdgpu_device *adev = drm_to_adev(ddev);
1327         int ret;
1328         long int value;
1329
1330         if (amdgpu_in_reset(adev))
1331                 return -EPERM;
1332         if (adev->in_suspend && !adev->in_runpm)
1333                 return -EPERM;
1334
1335         ret = kstrtol(buf, 0, &value);
1336
1337         if (ret)
1338                 return -EINVAL;
1339
1340         ret = pm_runtime_get_sync(ddev->dev);
1341         if (ret < 0) {
1342                 pm_runtime_put_autosuspend(ddev->dev);
1343                 return ret;
1344         }
1345
1346         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1347
1348         pm_runtime_mark_last_busy(ddev->dev);
1349         pm_runtime_put_autosuspend(ddev->dev);
1350
1351         return count;
1352 }
1353
1354 /**
1355  * DOC: pp_power_profile_mode
1356  *
1357  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1358  * related to switching between power levels in a power state.  The file
1359  * pp_power_profile_mode is used for this.
1360  *
1361  * Reading this file outputs a list of all of the predefined power profiles
1362  * and the relevant heuristics settings for that profile.
1363  *
1364  * To select a profile or create a custom profile, first select manual using
1365  * power_dpm_force_performance_level.  Writing the number of a predefined
1366  * profile to pp_power_profile_mode will enable those heuristics.  To
1367  * create a custom set of heuristics, write a string of numbers to the file
1368  * starting with the number of the custom profile along with a setting
1369  * for each heuristic parameter.  Due to differences across asic families
1370  * the heuristic parameters vary from family to family.
1371  *
1372  */
1373
1374 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1375                 struct device_attribute *attr,
1376                 char *buf)
1377 {
1378         struct drm_device *ddev = dev_get_drvdata(dev);
1379         struct amdgpu_device *adev = drm_to_adev(ddev);
1380         ssize_t size;
1381         int ret;
1382
1383         if (amdgpu_in_reset(adev))
1384                 return -EPERM;
1385         if (adev->in_suspend && !adev->in_runpm)
1386                 return -EPERM;
1387
1388         ret = pm_runtime_get_sync(ddev->dev);
1389         if (ret < 0) {
1390                 pm_runtime_put_autosuspend(ddev->dev);
1391                 return ret;
1392         }
1393
1394         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1395         if (size <= 0)
1396                 size = sysfs_emit(buf, "\n");
1397
1398         pm_runtime_mark_last_busy(ddev->dev);
1399         pm_runtime_put_autosuspend(ddev->dev);
1400
1401         return size;
1402 }
1403
1404
1405 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1406                 struct device_attribute *attr,
1407                 const char *buf,
1408                 size_t count)
1409 {
1410         int ret;
1411         struct drm_device *ddev = dev_get_drvdata(dev);
1412         struct amdgpu_device *adev = drm_to_adev(ddev);
1413         uint32_t parameter_size = 0;
1414         long parameter[64];
1415         char *sub_str, buf_cpy[128];
1416         char *tmp_str;
1417         uint32_t i = 0;
1418         char tmp[2];
1419         long int profile_mode = 0;
1420         const char delimiter[3] = {' ', '\n', '\0'};
1421
1422         if (amdgpu_in_reset(adev))
1423                 return -EPERM;
1424         if (adev->in_suspend && !adev->in_runpm)
1425                 return -EPERM;
1426
1427         tmp[0] = *(buf);
1428         tmp[1] = '\0';
1429         ret = kstrtol(tmp, 0, &profile_mode);
1430         if (ret)
1431                 return -EINVAL;
1432
1433         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1434                 if (count < 2 || count > 127)
1435                         return -EINVAL;
1436                 while (isspace(*++buf))
1437                         i++;
1438                 memcpy(buf_cpy, buf, count-i);
1439                 tmp_str = buf_cpy;
1440                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1441                         if (strlen(sub_str) == 0)
1442                                 continue;
1443                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1444                         if (ret)
1445                                 return -EINVAL;
1446                         parameter_size++;
1447                         while (isspace(*tmp_str))
1448                                 tmp_str++;
1449                 }
1450         }
1451         parameter[parameter_size] = profile_mode;
1452
1453         ret = pm_runtime_get_sync(ddev->dev);
1454         if (ret < 0) {
1455                 pm_runtime_put_autosuspend(ddev->dev);
1456                 return ret;
1457         }
1458
1459         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1460
1461         pm_runtime_mark_last_busy(ddev->dev);
1462         pm_runtime_put_autosuspend(ddev->dev);
1463
1464         if (!ret)
1465                 return count;
1466
1467         return -EINVAL;
1468 }
1469
1470 /**
1471  * DOC: gpu_busy_percent
1472  *
1473  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1474  * is as a percentage.  The file gpu_busy_percent is used for this.
1475  * The SMU firmware computes a percentage of load based on the
1476  * aggregate activity level in the IP cores.
1477  */
1478 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1479                                            struct device_attribute *attr,
1480                                            char *buf)
1481 {
1482         struct drm_device *ddev = dev_get_drvdata(dev);
1483         struct amdgpu_device *adev = drm_to_adev(ddev);
1484         int r, value, size = sizeof(value);
1485
1486         if (amdgpu_in_reset(adev))
1487                 return -EPERM;
1488         if (adev->in_suspend && !adev->in_runpm)
1489                 return -EPERM;
1490
1491         r = pm_runtime_get_sync(ddev->dev);
1492         if (r < 0) {
1493                 pm_runtime_put_autosuspend(ddev->dev);
1494                 return r;
1495         }
1496
1497         /* read the IP busy sensor */
1498         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1499                                    (void *)&value, &size);
1500
1501         pm_runtime_mark_last_busy(ddev->dev);
1502         pm_runtime_put_autosuspend(ddev->dev);
1503
1504         if (r)
1505                 return r;
1506
1507         return sysfs_emit(buf, "%d\n", value);
1508 }
1509
1510 /**
1511  * DOC: mem_busy_percent
1512  *
1513  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1514  * is as a percentage.  The file mem_busy_percent is used for this.
1515  * The SMU firmware computes a percentage of load based on the
1516  * aggregate activity level in the IP cores.
1517  */
1518 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1519                                            struct device_attribute *attr,
1520                                            char *buf)
1521 {
1522         struct drm_device *ddev = dev_get_drvdata(dev);
1523         struct amdgpu_device *adev = drm_to_adev(ddev);
1524         int r, value, size = sizeof(value);
1525
1526         if (amdgpu_in_reset(adev))
1527                 return -EPERM;
1528         if (adev->in_suspend && !adev->in_runpm)
1529                 return -EPERM;
1530
1531         r = pm_runtime_get_sync(ddev->dev);
1532         if (r < 0) {
1533                 pm_runtime_put_autosuspend(ddev->dev);
1534                 return r;
1535         }
1536
1537         /* read the IP busy sensor */
1538         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1539                                    (void *)&value, &size);
1540
1541         pm_runtime_mark_last_busy(ddev->dev);
1542         pm_runtime_put_autosuspend(ddev->dev);
1543
1544         if (r)
1545                 return r;
1546
1547         return sysfs_emit(buf, "%d\n", value);
1548 }
1549
1550 /**
1551  * DOC: pcie_bw
1552  *
1553  * The amdgpu driver provides a sysfs API for estimating how much data
1554  * has been received and sent by the GPU in the last second through PCIe.
1555  * The file pcie_bw is used for this.
1556  * The Perf counters count the number of received and sent messages and return
1557  * those values, as well as the maximum payload size of a PCIe packet (mps).
1558  * Note that it is not possible to easily and quickly obtain the size of each
1559  * packet transmitted, so we output the max payload size (mps) to allow for
1560  * quick estimation of the PCIe bandwidth usage
1561  */
1562 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1563                 struct device_attribute *attr,
1564                 char *buf)
1565 {
1566         struct drm_device *ddev = dev_get_drvdata(dev);
1567         struct amdgpu_device *adev = drm_to_adev(ddev);
1568         uint64_t count0 = 0, count1 = 0;
1569         int ret;
1570
1571         if (amdgpu_in_reset(adev))
1572                 return -EPERM;
1573         if (adev->in_suspend && !adev->in_runpm)
1574                 return -EPERM;
1575
1576         if (adev->flags & AMD_IS_APU)
1577                 return -ENODATA;
1578
1579         if (!adev->asic_funcs->get_pcie_usage)
1580                 return -ENODATA;
1581
1582         ret = pm_runtime_get_sync(ddev->dev);
1583         if (ret < 0) {
1584                 pm_runtime_put_autosuspend(ddev->dev);
1585                 return ret;
1586         }
1587
1588         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1589
1590         pm_runtime_mark_last_busy(ddev->dev);
1591         pm_runtime_put_autosuspend(ddev->dev);
1592
1593         return sysfs_emit(buf, "%llu %llu %i\n",
1594                           count0, count1, pcie_get_mps(adev->pdev));
1595 }
1596
1597 /**
1598  * DOC: unique_id
1599  *
1600  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1601  * The file unique_id is used for this.
1602  * This will provide a Unique ID that will persist from machine to machine
1603  *
1604  * NOTE: This will only work for GFX9 and newer. This file will be absent
1605  * on unsupported ASICs (GFX8 and older)
1606  */
1607 static ssize_t amdgpu_get_unique_id(struct device *dev,
1608                 struct device_attribute *attr,
1609                 char *buf)
1610 {
1611         struct drm_device *ddev = dev_get_drvdata(dev);
1612         struct amdgpu_device *adev = drm_to_adev(ddev);
1613
1614         if (amdgpu_in_reset(adev))
1615                 return -EPERM;
1616         if (adev->in_suspend && !adev->in_runpm)
1617                 return -EPERM;
1618
1619         if (adev->unique_id)
1620                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1621
1622         return 0;
1623 }
1624
1625 /**
1626  * DOC: thermal_throttling_logging
1627  *
1628  * Thermal throttling pulls down the clock frequency and thus the performance.
1629  * It's an useful mechanism to protect the chip from overheating. Since it
1630  * impacts performance, the user controls whether it is enabled and if so,
1631  * the log frequency.
1632  *
1633  * Reading back the file shows you the status(enabled or disabled) and
1634  * the interval(in seconds) between each thermal logging.
1635  *
1636  * Writing an integer to the file, sets a new logging interval, in seconds.
1637  * The value should be between 1 and 3600. If the value is less than 1,
1638  * thermal logging is disabled. Values greater than 3600 are ignored.
1639  */
1640 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1641                                                      struct device_attribute *attr,
1642                                                      char *buf)
1643 {
1644         struct drm_device *ddev = dev_get_drvdata(dev);
1645         struct amdgpu_device *adev = drm_to_adev(ddev);
1646
1647         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1648                           adev_to_drm(adev)->unique,
1649                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1650                           adev->throttling_logging_rs.interval / HZ + 1);
1651 }
1652
1653 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1654                                                      struct device_attribute *attr,
1655                                                      const char *buf,
1656                                                      size_t count)
1657 {
1658         struct drm_device *ddev = dev_get_drvdata(dev);
1659         struct amdgpu_device *adev = drm_to_adev(ddev);
1660         long throttling_logging_interval;
1661         unsigned long flags;
1662         int ret = 0;
1663
1664         ret = kstrtol(buf, 0, &throttling_logging_interval);
1665         if (ret)
1666                 return ret;
1667
1668         if (throttling_logging_interval > 3600)
1669                 return -EINVAL;
1670
1671         if (throttling_logging_interval > 0) {
1672                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1673                 /*
1674                  * Reset the ratelimit timer internals.
1675                  * This can effectively restart the timer.
1676                  */
1677                 adev->throttling_logging_rs.interval =
1678                         (throttling_logging_interval - 1) * HZ;
1679                 adev->throttling_logging_rs.begin = 0;
1680                 adev->throttling_logging_rs.printed = 0;
1681                 adev->throttling_logging_rs.missed = 0;
1682                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1683
1684                 atomic_set(&adev->throttling_logging_enabled, 1);
1685         } else {
1686                 atomic_set(&adev->throttling_logging_enabled, 0);
1687         }
1688
1689         return count;
1690 }
1691
1692 /**
1693  * DOC: apu_thermal_cap
1694  *
1695  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1696  * limit temperature in millidegrees Celsius
1697  *
1698  * Reading back the file shows you core limit value
1699  *
1700  * Writing an integer to the file, sets a new thermal limit. The value
1701  * should be between 0 and 100. If the value is less than 0 or greater
1702  * than 100, then the write request will be ignored.
1703  */
1704 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1705                                          struct device_attribute *attr,
1706                                          char *buf)
1707 {
1708         int ret, size;
1709         u32 limit;
1710         struct drm_device *ddev = dev_get_drvdata(dev);
1711         struct amdgpu_device *adev = drm_to_adev(ddev);
1712
1713         ret = pm_runtime_get_sync(ddev->dev);
1714         if (ret < 0) {
1715                 pm_runtime_put_autosuspend(ddev->dev);
1716                 return ret;
1717         }
1718
1719         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1720         if (!ret)
1721                 size = sysfs_emit(buf, "%u\n", limit);
1722         else
1723                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1724
1725         pm_runtime_mark_last_busy(ddev->dev);
1726         pm_runtime_put_autosuspend(ddev->dev);
1727
1728         return size;
1729 }
1730
1731 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1732                                          struct device_attribute *attr,
1733                                          const char *buf,
1734                                          size_t count)
1735 {
1736         int ret;
1737         u32 value;
1738         struct drm_device *ddev = dev_get_drvdata(dev);
1739         struct amdgpu_device *adev = drm_to_adev(ddev);
1740
1741         ret = kstrtou32(buf, 10, &value);
1742         if (ret)
1743                 return ret;
1744
1745         if (value > 100) {
1746                 dev_err(dev, "Invalid argument !\n");
1747                 return -EINVAL;
1748         }
1749
1750         ret = pm_runtime_get_sync(ddev->dev);
1751         if (ret < 0) {
1752                 pm_runtime_put_autosuspend(ddev->dev);
1753                 return ret;
1754         }
1755
1756         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1757         if (ret) {
1758                 dev_err(dev, "failed to update thermal limit\n");
1759                 return ret;
1760         }
1761
1762         pm_runtime_mark_last_busy(ddev->dev);
1763         pm_runtime_put_autosuspend(ddev->dev);
1764
1765         return count;
1766 }
1767
1768 /**
1769  * DOC: gpu_metrics
1770  *
1771  * The amdgpu driver provides a sysfs API for retrieving current gpu
1772  * metrics data. The file gpu_metrics is used for this. Reading the
1773  * file will dump all the current gpu metrics data.
1774  *
1775  * These data include temperature, frequency, engines utilization,
1776  * power consume, throttler status, fan speed and cpu core statistics(
1777  * available for APU only). That's it will give a snapshot of all sensors
1778  * at the same time.
1779  */
1780 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1781                                       struct device_attribute *attr,
1782                                       char *buf)
1783 {
1784         struct drm_device *ddev = dev_get_drvdata(dev);
1785         struct amdgpu_device *adev = drm_to_adev(ddev);
1786         void *gpu_metrics;
1787         ssize_t size = 0;
1788         int ret;
1789
1790         if (amdgpu_in_reset(adev))
1791                 return -EPERM;
1792         if (adev->in_suspend && !adev->in_runpm)
1793                 return -EPERM;
1794
1795         ret = pm_runtime_get_sync(ddev->dev);
1796         if (ret < 0) {
1797                 pm_runtime_put_autosuspend(ddev->dev);
1798                 return ret;
1799         }
1800
1801         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1802         if (size <= 0)
1803                 goto out;
1804
1805         if (size >= PAGE_SIZE)
1806                 size = PAGE_SIZE - 1;
1807
1808         memcpy(buf, gpu_metrics, size);
1809
1810 out:
1811         pm_runtime_mark_last_busy(ddev->dev);
1812         pm_runtime_put_autosuspend(ddev->dev);
1813
1814         return size;
1815 }
1816
1817 static int amdgpu_device_read_powershift(struct amdgpu_device *adev,
1818                                                 uint32_t *ss_power, bool dgpu_share)
1819 {
1820         struct drm_device *ddev = adev_to_drm(adev);
1821         uint32_t size;
1822         int r = 0;
1823
1824         if (amdgpu_in_reset(adev))
1825                 return -EPERM;
1826         if (adev->in_suspend && !adev->in_runpm)
1827                 return -EPERM;
1828
1829         r = pm_runtime_get_sync(ddev->dev);
1830         if (r < 0) {
1831                 pm_runtime_put_autosuspend(ddev->dev);
1832                 return r;
1833         }
1834
1835         if (dgpu_share)
1836                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1837                                    (void *)ss_power, &size);
1838         else
1839                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1840                                    (void *)ss_power, &size);
1841
1842         pm_runtime_mark_last_busy(ddev->dev);
1843         pm_runtime_put_autosuspend(ddev->dev);
1844         return r;
1845 }
1846
1847 static int amdgpu_show_powershift_percent(struct device *dev,
1848                                         char *buf, bool dgpu_share)
1849 {
1850         struct drm_device *ddev = dev_get_drvdata(dev);
1851         struct amdgpu_device *adev = drm_to_adev(ddev);
1852         uint32_t ss_power;
1853         int r = 0, i;
1854
1855         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1856         if (r == -EOPNOTSUPP) {
1857                 /* sensor not available on dGPU, try to read from APU */
1858                 adev = NULL;
1859                 mutex_lock(&mgpu_info.mutex);
1860                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1861                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1862                                 adev = mgpu_info.gpu_ins[i].adev;
1863                                 break;
1864                         }
1865                 }
1866                 mutex_unlock(&mgpu_info.mutex);
1867                 if (adev)
1868                         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1869         }
1870
1871         if (!r)
1872                 r = sysfs_emit(buf, "%u%%\n", ss_power);
1873
1874         return r;
1875 }
1876 /**
1877  * DOC: smartshift_apu_power
1878  *
1879  * The amdgpu driver provides a sysfs API for reporting APU power
1880  * shift in percentage if platform supports smartshift. Value 0 means that
1881  * there is no powershift and values between [1-100] means that the power
1882  * is shifted to APU, the percentage of boost is with respect to APU power
1883  * limit on the platform.
1884  */
1885
1886 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1887                                                char *buf)
1888 {
1889         return amdgpu_show_powershift_percent(dev, buf, false);
1890 }
1891
1892 /**
1893  * DOC: smartshift_dgpu_power
1894  *
1895  * The amdgpu driver provides a sysfs API for reporting dGPU power
1896  * shift in percentage if platform supports smartshift. Value 0 means that
1897  * there is no powershift and values between [1-100] means that the power is
1898  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1899  * limit on the platform.
1900  */
1901
1902 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1903                                                 char *buf)
1904 {
1905         return amdgpu_show_powershift_percent(dev, buf, true);
1906 }
1907
1908 /**
1909  * DOC: smartshift_bias
1910  *
1911  * The amdgpu driver provides a sysfs API for reporting the
1912  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1913  * and the default is 0. -100 sets maximum preference to APU
1914  * and 100 sets max perference to dGPU.
1915  */
1916
1917 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1918                                           struct device_attribute *attr,
1919                                           char *buf)
1920 {
1921         int r = 0;
1922
1923         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1924
1925         return r;
1926 }
1927
1928 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1929                                           struct device_attribute *attr,
1930                                           const char *buf, size_t count)
1931 {
1932         struct drm_device *ddev = dev_get_drvdata(dev);
1933         struct amdgpu_device *adev = drm_to_adev(ddev);
1934         int r = 0;
1935         int bias = 0;
1936
1937         if (amdgpu_in_reset(adev))
1938                 return -EPERM;
1939         if (adev->in_suspend && !adev->in_runpm)
1940                 return -EPERM;
1941
1942         r = pm_runtime_get_sync(ddev->dev);
1943         if (r < 0) {
1944                 pm_runtime_put_autosuspend(ddev->dev);
1945                 return r;
1946         }
1947
1948         r = kstrtoint(buf, 10, &bias);
1949         if (r)
1950                 goto out;
1951
1952         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1953                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1954         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1955                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1956
1957         amdgpu_smartshift_bias = bias;
1958         r = count;
1959
1960         /* TODO: update bias level with SMU message */
1961
1962 out:
1963         pm_runtime_mark_last_busy(ddev->dev);
1964         pm_runtime_put_autosuspend(ddev->dev);
1965         return r;
1966 }
1967
1968
1969 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1970                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1971 {
1972         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1973                 *states = ATTR_STATE_UNSUPPORTED;
1974
1975         return 0;
1976 }
1977
1978 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1979                                uint32_t mask, enum amdgpu_device_attr_states *states)
1980 {
1981         uint32_t ss_power, size;
1982
1983         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1984                 *states = ATTR_STATE_UNSUPPORTED;
1985         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1986                  (void *)&ss_power, &size))
1987                 *states = ATTR_STATE_UNSUPPORTED;
1988         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1989                  (void *)&ss_power, &size))
1990                 *states = ATTR_STATE_UNSUPPORTED;
1991
1992         return 0;
1993 }
1994
1995 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1996         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1997         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1998         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1999         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2000         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2001         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2002         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2003         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2004         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2005         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2006         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2007         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2008         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2009         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2010         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2011         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2012         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2013         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2014         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2015         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2016         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2017         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2018         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2019         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2020         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2021         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2022         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2023         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2024         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2025                               .attr_update = ss_power_attr_update),
2026         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2027                               .attr_update = ss_power_attr_update),
2028         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2029                               .attr_update = ss_bias_attr_update),
2030 };
2031
2032 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2033                                uint32_t mask, enum amdgpu_device_attr_states *states)
2034 {
2035         struct device_attribute *dev_attr = &attr->dev_attr;
2036         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
2037         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2038         const char *attr_name = dev_attr->attr.name;
2039
2040         if (!(attr->flags & mask)) {
2041                 *states = ATTR_STATE_UNSUPPORTED;
2042                 return 0;
2043         }
2044
2045 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2046
2047         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2048                 if (gc_ver < IP_VERSION(9, 0, 0))
2049                         *states = ATTR_STATE_UNSUPPORTED;
2050         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2051                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2052                     gc_ver == IP_VERSION(9, 4, 1) ||
2053                     gc_ver == IP_VERSION(9, 4, 2))
2054                         *states = ATTR_STATE_UNSUPPORTED;
2055         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2056                 if (mp1_ver < IP_VERSION(10, 0, 0))
2057                         *states = ATTR_STATE_UNSUPPORTED;
2058         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2059                 *states = ATTR_STATE_UNSUPPORTED;
2060                 if (amdgpu_dpm_is_overdrive_supported(adev))
2061                         *states = ATTR_STATE_SUPPORTED;
2062         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2063                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2064                         *states = ATTR_STATE_UNSUPPORTED;
2065         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2066                 /* PCIe Perf counters won't work on APU nodes */
2067                 if (adev->flags & AMD_IS_APU)
2068                         *states = ATTR_STATE_UNSUPPORTED;
2069         } else if (DEVICE_ATTR_IS(unique_id)) {
2070                 switch (gc_ver) {
2071                 case IP_VERSION(9, 0, 1):
2072                 case IP_VERSION(9, 4, 0):
2073                 case IP_VERSION(9, 4, 1):
2074                 case IP_VERSION(9, 4, 2):
2075                 case IP_VERSION(9, 4, 3):
2076                 case IP_VERSION(10, 3, 0):
2077                 case IP_VERSION(11, 0, 0):
2078                 case IP_VERSION(11, 0, 1):
2079                 case IP_VERSION(11, 0, 2):
2080                         *states = ATTR_STATE_SUPPORTED;
2081                         break;
2082                 default:
2083                         *states = ATTR_STATE_UNSUPPORTED;
2084                 }
2085         } else if (DEVICE_ATTR_IS(pp_features)) {
2086                 if ((adev->flags & AMD_IS_APU &&
2087                      gc_ver != IP_VERSION(9, 4, 3)) ||
2088                     gc_ver < IP_VERSION(9, 0, 0))
2089                         *states = ATTR_STATE_UNSUPPORTED;
2090         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2091                 if (gc_ver < IP_VERSION(9, 1, 0))
2092                         *states = ATTR_STATE_UNSUPPORTED;
2093         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2094                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2095                       gc_ver == IP_VERSION(10, 3, 0) ||
2096                       gc_ver == IP_VERSION(10, 1, 2) ||
2097                       gc_ver == IP_VERSION(11, 0, 0) ||
2098                       gc_ver == IP_VERSION(11, 0, 2) ||
2099                       gc_ver == IP_VERSION(11, 0, 3)))
2100                         *states = ATTR_STATE_UNSUPPORTED;
2101         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2102                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2103                            gc_ver == IP_VERSION(10, 3, 0) ||
2104                            gc_ver == IP_VERSION(11, 0, 2) ||
2105                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2106                         *states = ATTR_STATE_UNSUPPORTED;
2107         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2108                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2109                       gc_ver == IP_VERSION(10, 3, 0) ||
2110                       gc_ver == IP_VERSION(10, 1, 2) ||
2111                       gc_ver == IP_VERSION(11, 0, 0) ||
2112                       gc_ver == IP_VERSION(11, 0, 2) ||
2113                       gc_ver == IP_VERSION(11, 0, 3)))
2114                         *states = ATTR_STATE_UNSUPPORTED;
2115         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2116                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2117                            gc_ver == IP_VERSION(10, 3, 0) ||
2118                            gc_ver == IP_VERSION(11, 0, 2) ||
2119                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2120                         *states = ATTR_STATE_UNSUPPORTED;
2121         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2122                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2123                         *states = ATTR_STATE_UNSUPPORTED;
2124                 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2125                         *states = ATTR_STATE_UNSUPPORTED;
2126         }
2127
2128         switch (gc_ver) {
2129         case IP_VERSION(9, 4, 1):
2130         case IP_VERSION(9, 4, 2):
2131                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2132                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2133                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2134                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2135                         dev_attr->attr.mode &= ~S_IWUGO;
2136                         dev_attr->store = NULL;
2137                 }
2138                 break;
2139         case IP_VERSION(10, 3, 0):
2140                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2141                     amdgpu_sriov_vf(adev)) {
2142                         dev_attr->attr.mode &= ~0222;
2143                         dev_attr->store = NULL;
2144                 }
2145                 break;
2146         default:
2147                 break;
2148         }
2149
2150         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2151                 /* SMU MP1 does not support dcefclk level setting */
2152                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2153                         dev_attr->attr.mode &= ~S_IWUGO;
2154                         dev_attr->store = NULL;
2155                 }
2156         }
2157
2158         /* setting should not be allowed from VF if not in one VF mode */
2159         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2160                 dev_attr->attr.mode &= ~S_IWUGO;
2161                 dev_attr->store = NULL;
2162         }
2163
2164 #undef DEVICE_ATTR_IS
2165
2166         return 0;
2167 }
2168
2169
2170 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2171                                      struct amdgpu_device_attr *attr,
2172                                      uint32_t mask, struct list_head *attr_list)
2173 {
2174         int ret = 0;
2175         struct device_attribute *dev_attr = &attr->dev_attr;
2176         const char *name = dev_attr->attr.name;
2177         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2178         struct amdgpu_device_attr_entry *attr_entry;
2179
2180         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2181                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2182
2183         BUG_ON(!attr);
2184
2185         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2186
2187         ret = attr_update(adev, attr, mask, &attr_states);
2188         if (ret) {
2189                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2190                         name, ret);
2191                 return ret;
2192         }
2193
2194         if (attr_states == ATTR_STATE_UNSUPPORTED)
2195                 return 0;
2196
2197         ret = device_create_file(adev->dev, dev_attr);
2198         if (ret) {
2199                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2200                         name, ret);
2201         }
2202
2203         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2204         if (!attr_entry)
2205                 return -ENOMEM;
2206
2207         attr_entry->attr = attr;
2208         INIT_LIST_HEAD(&attr_entry->entry);
2209
2210         list_add_tail(&attr_entry->entry, attr_list);
2211
2212         return ret;
2213 }
2214
2215 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2216 {
2217         struct device_attribute *dev_attr = &attr->dev_attr;
2218
2219         device_remove_file(adev->dev, dev_attr);
2220 }
2221
2222 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2223                                              struct list_head *attr_list);
2224
2225 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2226                                             struct amdgpu_device_attr *attrs,
2227                                             uint32_t counts,
2228                                             uint32_t mask,
2229                                             struct list_head *attr_list)
2230 {
2231         int ret = 0;
2232         uint32_t i = 0;
2233
2234         for (i = 0; i < counts; i++) {
2235                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2236                 if (ret)
2237                         goto failed;
2238         }
2239
2240         return 0;
2241
2242 failed:
2243         amdgpu_device_attr_remove_groups(adev, attr_list);
2244
2245         return ret;
2246 }
2247
2248 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2249                                              struct list_head *attr_list)
2250 {
2251         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2252
2253         if (list_empty(attr_list))
2254                 return ;
2255
2256         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2257                 amdgpu_device_attr_remove(adev, entry->attr);
2258                 list_del(&entry->entry);
2259                 kfree(entry);
2260         }
2261 }
2262
2263 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2264                                       struct device_attribute *attr,
2265                                       char *buf)
2266 {
2267         struct amdgpu_device *adev = dev_get_drvdata(dev);
2268         int channel = to_sensor_dev_attr(attr)->index;
2269         int r, temp = 0, size = sizeof(temp);
2270
2271         if (amdgpu_in_reset(adev))
2272                 return -EPERM;
2273         if (adev->in_suspend && !adev->in_runpm)
2274                 return -EPERM;
2275
2276         if (channel >= PP_TEMP_MAX)
2277                 return -EINVAL;
2278
2279         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2280         if (r < 0) {
2281                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2282                 return r;
2283         }
2284
2285         switch (channel) {
2286         case PP_TEMP_JUNCTION:
2287                 /* get current junction temperature */
2288                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2289                                            (void *)&temp, &size);
2290                 break;
2291         case PP_TEMP_EDGE:
2292                 /* get current edge temperature */
2293                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2294                                            (void *)&temp, &size);
2295                 break;
2296         case PP_TEMP_MEM:
2297                 /* get current memory temperature */
2298                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2299                                            (void *)&temp, &size);
2300                 break;
2301         default:
2302                 r = -EINVAL;
2303                 break;
2304         }
2305
2306         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2307         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2308
2309         if (r)
2310                 return r;
2311
2312         return sysfs_emit(buf, "%d\n", temp);
2313 }
2314
2315 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2316                                              struct device_attribute *attr,
2317                                              char *buf)
2318 {
2319         struct amdgpu_device *adev = dev_get_drvdata(dev);
2320         int hyst = to_sensor_dev_attr(attr)->index;
2321         int temp;
2322
2323         if (hyst)
2324                 temp = adev->pm.dpm.thermal.min_temp;
2325         else
2326                 temp = adev->pm.dpm.thermal.max_temp;
2327
2328         return sysfs_emit(buf, "%d\n", temp);
2329 }
2330
2331 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2332                                              struct device_attribute *attr,
2333                                              char *buf)
2334 {
2335         struct amdgpu_device *adev = dev_get_drvdata(dev);
2336         int hyst = to_sensor_dev_attr(attr)->index;
2337         int temp;
2338
2339         if (hyst)
2340                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2341         else
2342                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2343
2344         return sysfs_emit(buf, "%d\n", temp);
2345 }
2346
2347 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2348                                              struct device_attribute *attr,
2349                                              char *buf)
2350 {
2351         struct amdgpu_device *adev = dev_get_drvdata(dev);
2352         int hyst = to_sensor_dev_attr(attr)->index;
2353         int temp;
2354
2355         if (hyst)
2356                 temp = adev->pm.dpm.thermal.min_mem_temp;
2357         else
2358                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2359
2360         return sysfs_emit(buf, "%d\n", temp);
2361 }
2362
2363 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2364                                              struct device_attribute *attr,
2365                                              char *buf)
2366 {
2367         int channel = to_sensor_dev_attr(attr)->index;
2368
2369         if (channel >= PP_TEMP_MAX)
2370                 return -EINVAL;
2371
2372         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2373 }
2374
2375 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2376                                              struct device_attribute *attr,
2377                                              char *buf)
2378 {
2379         struct amdgpu_device *adev = dev_get_drvdata(dev);
2380         int channel = to_sensor_dev_attr(attr)->index;
2381         int temp = 0;
2382
2383         if (channel >= PP_TEMP_MAX)
2384                 return -EINVAL;
2385
2386         switch (channel) {
2387         case PP_TEMP_JUNCTION:
2388                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2389                 break;
2390         case PP_TEMP_EDGE:
2391                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2392                 break;
2393         case PP_TEMP_MEM:
2394                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2395                 break;
2396         }
2397
2398         return sysfs_emit(buf, "%d\n", temp);
2399 }
2400
2401 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2402                                             struct device_attribute *attr,
2403                                             char *buf)
2404 {
2405         struct amdgpu_device *adev = dev_get_drvdata(dev);
2406         u32 pwm_mode = 0;
2407         int ret;
2408
2409         if (amdgpu_in_reset(adev))
2410                 return -EPERM;
2411         if (adev->in_suspend && !adev->in_runpm)
2412                 return -EPERM;
2413
2414         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2415         if (ret < 0) {
2416                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2417                 return ret;
2418         }
2419
2420         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2421
2422         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2423         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2424
2425         if (ret)
2426                 return -EINVAL;
2427
2428         return sysfs_emit(buf, "%u\n", pwm_mode);
2429 }
2430
2431 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2432                                             struct device_attribute *attr,
2433                                             const char *buf,
2434                                             size_t count)
2435 {
2436         struct amdgpu_device *adev = dev_get_drvdata(dev);
2437         int err, ret;
2438         int value;
2439
2440         if (amdgpu_in_reset(adev))
2441                 return -EPERM;
2442         if (adev->in_suspend && !adev->in_runpm)
2443                 return -EPERM;
2444
2445         err = kstrtoint(buf, 10, &value);
2446         if (err)
2447                 return err;
2448
2449         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2450         if (ret < 0) {
2451                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2452                 return ret;
2453         }
2454
2455         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2456
2457         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2458         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2459
2460         if (ret)
2461                 return -EINVAL;
2462
2463         return count;
2464 }
2465
2466 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2467                                          struct device_attribute *attr,
2468                                          char *buf)
2469 {
2470         return sysfs_emit(buf, "%i\n", 0);
2471 }
2472
2473 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2474                                          struct device_attribute *attr,
2475                                          char *buf)
2476 {
2477         return sysfs_emit(buf, "%i\n", 255);
2478 }
2479
2480 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2481                                      struct device_attribute *attr,
2482                                      const char *buf, size_t count)
2483 {
2484         struct amdgpu_device *adev = dev_get_drvdata(dev);
2485         int err;
2486         u32 value;
2487         u32 pwm_mode;
2488
2489         if (amdgpu_in_reset(adev))
2490                 return -EPERM;
2491         if (adev->in_suspend && !adev->in_runpm)
2492                 return -EPERM;
2493
2494         err = kstrtou32(buf, 10, &value);
2495         if (err)
2496                 return err;
2497
2498         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2499         if (err < 0) {
2500                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2501                 return err;
2502         }
2503
2504         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2505         if (err)
2506                 goto out;
2507
2508         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2509                 pr_info("manual fan speed control should be enabled first\n");
2510                 err = -EINVAL;
2511                 goto out;
2512         }
2513
2514         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2515
2516 out:
2517         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2518         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2519
2520         if (err)
2521                 return err;
2522
2523         return count;
2524 }
2525
2526 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2527                                      struct device_attribute *attr,
2528                                      char *buf)
2529 {
2530         struct amdgpu_device *adev = dev_get_drvdata(dev);
2531         int err;
2532         u32 speed = 0;
2533
2534         if (amdgpu_in_reset(adev))
2535                 return -EPERM;
2536         if (adev->in_suspend && !adev->in_runpm)
2537                 return -EPERM;
2538
2539         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2540         if (err < 0) {
2541                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2542                 return err;
2543         }
2544
2545         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2546
2547         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2548         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2549
2550         if (err)
2551                 return err;
2552
2553         return sysfs_emit(buf, "%i\n", speed);
2554 }
2555
2556 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2557                                            struct device_attribute *attr,
2558                                            char *buf)
2559 {
2560         struct amdgpu_device *adev = dev_get_drvdata(dev);
2561         int err;
2562         u32 speed = 0;
2563
2564         if (amdgpu_in_reset(adev))
2565                 return -EPERM;
2566         if (adev->in_suspend && !adev->in_runpm)
2567                 return -EPERM;
2568
2569         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2570         if (err < 0) {
2571                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2572                 return err;
2573         }
2574
2575         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2576
2577         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2578         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2579
2580         if (err)
2581                 return err;
2582
2583         return sysfs_emit(buf, "%i\n", speed);
2584 }
2585
2586 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2587                                          struct device_attribute *attr,
2588                                          char *buf)
2589 {
2590         struct amdgpu_device *adev = dev_get_drvdata(dev);
2591         u32 min_rpm = 0;
2592         u32 size = sizeof(min_rpm);
2593         int r;
2594
2595         if (amdgpu_in_reset(adev))
2596                 return -EPERM;
2597         if (adev->in_suspend && !adev->in_runpm)
2598                 return -EPERM;
2599
2600         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2601         if (r < 0) {
2602                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2603                 return r;
2604         }
2605
2606         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2607                                    (void *)&min_rpm, &size);
2608
2609         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2610         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2611
2612         if (r)
2613                 return r;
2614
2615         return sysfs_emit(buf, "%d\n", min_rpm);
2616 }
2617
2618 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2619                                          struct device_attribute *attr,
2620                                          char *buf)
2621 {
2622         struct amdgpu_device *adev = dev_get_drvdata(dev);
2623         u32 max_rpm = 0;
2624         u32 size = sizeof(max_rpm);
2625         int r;
2626
2627         if (amdgpu_in_reset(adev))
2628                 return -EPERM;
2629         if (adev->in_suspend && !adev->in_runpm)
2630                 return -EPERM;
2631
2632         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2633         if (r < 0) {
2634                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2635                 return r;
2636         }
2637
2638         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2639                                    (void *)&max_rpm, &size);
2640
2641         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2642         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2643
2644         if (r)
2645                 return r;
2646
2647         return sysfs_emit(buf, "%d\n", max_rpm);
2648 }
2649
2650 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2651                                            struct device_attribute *attr,
2652                                            char *buf)
2653 {
2654         struct amdgpu_device *adev = dev_get_drvdata(dev);
2655         int err;
2656         u32 rpm = 0;
2657
2658         if (amdgpu_in_reset(adev))
2659                 return -EPERM;
2660         if (adev->in_suspend && !adev->in_runpm)
2661                 return -EPERM;
2662
2663         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2664         if (err < 0) {
2665                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2666                 return err;
2667         }
2668
2669         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2670
2671         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2672         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2673
2674         if (err)
2675                 return err;
2676
2677         return sysfs_emit(buf, "%i\n", rpm);
2678 }
2679
2680 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2681                                      struct device_attribute *attr,
2682                                      const char *buf, size_t count)
2683 {
2684         struct amdgpu_device *adev = dev_get_drvdata(dev);
2685         int err;
2686         u32 value;
2687         u32 pwm_mode;
2688
2689         if (amdgpu_in_reset(adev))
2690                 return -EPERM;
2691         if (adev->in_suspend && !adev->in_runpm)
2692                 return -EPERM;
2693
2694         err = kstrtou32(buf, 10, &value);
2695         if (err)
2696                 return err;
2697
2698         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2699         if (err < 0) {
2700                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2701                 return err;
2702         }
2703
2704         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2705         if (err)
2706                 goto out;
2707
2708         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2709                 err = -ENODATA;
2710                 goto out;
2711         }
2712
2713         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2714
2715 out:
2716         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2717         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2718
2719         if (err)
2720                 return err;
2721
2722         return count;
2723 }
2724
2725 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2726                                             struct device_attribute *attr,
2727                                             char *buf)
2728 {
2729         struct amdgpu_device *adev = dev_get_drvdata(dev);
2730         u32 pwm_mode = 0;
2731         int ret;
2732
2733         if (amdgpu_in_reset(adev))
2734                 return -EPERM;
2735         if (adev->in_suspend && !adev->in_runpm)
2736                 return -EPERM;
2737
2738         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2739         if (ret < 0) {
2740                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2741                 return ret;
2742         }
2743
2744         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2745
2746         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2747         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2748
2749         if (ret)
2750                 return -EINVAL;
2751
2752         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2753 }
2754
2755 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2756                                             struct device_attribute *attr,
2757                                             const char *buf,
2758                                             size_t count)
2759 {
2760         struct amdgpu_device *adev = dev_get_drvdata(dev);
2761         int err;
2762         int value;
2763         u32 pwm_mode;
2764
2765         if (amdgpu_in_reset(adev))
2766                 return -EPERM;
2767         if (adev->in_suspend && !adev->in_runpm)
2768                 return -EPERM;
2769
2770         err = kstrtoint(buf, 10, &value);
2771         if (err)
2772                 return err;
2773
2774         if (value == 0)
2775                 pwm_mode = AMD_FAN_CTRL_AUTO;
2776         else if (value == 1)
2777                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2778         else
2779                 return -EINVAL;
2780
2781         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2782         if (err < 0) {
2783                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2784                 return err;
2785         }
2786
2787         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2788
2789         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2790         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2791
2792         if (err)
2793                 return -EINVAL;
2794
2795         return count;
2796 }
2797
2798 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2799                                         struct device_attribute *attr,
2800                                         char *buf)
2801 {
2802         struct amdgpu_device *adev = dev_get_drvdata(dev);
2803         u32 vddgfx;
2804         int r, size = sizeof(vddgfx);
2805
2806         if (amdgpu_in_reset(adev))
2807                 return -EPERM;
2808         if (adev->in_suspend && !adev->in_runpm)
2809                 return -EPERM;
2810
2811         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2812         if (r < 0) {
2813                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2814                 return r;
2815         }
2816
2817         /* get the voltage */
2818         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2819                                    (void *)&vddgfx, &size);
2820
2821         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2822         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2823
2824         if (r)
2825                 return r;
2826
2827         return sysfs_emit(buf, "%d\n", vddgfx);
2828 }
2829
2830 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2831                                               struct device_attribute *attr,
2832                                               char *buf)
2833 {
2834         return sysfs_emit(buf, "vddgfx\n");
2835 }
2836
2837 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2838                                        struct device_attribute *attr,
2839                                        char *buf)
2840 {
2841         struct amdgpu_device *adev = dev_get_drvdata(dev);
2842         u32 vddnb;
2843         int r, size = sizeof(vddnb);
2844
2845         if (amdgpu_in_reset(adev))
2846                 return -EPERM;
2847         if (adev->in_suspend && !adev->in_runpm)
2848                 return -EPERM;
2849
2850         /* only APUs have vddnb */
2851         if  (!(adev->flags & AMD_IS_APU))
2852                 return -EINVAL;
2853
2854         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2855         if (r < 0) {
2856                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2857                 return r;
2858         }
2859
2860         /* get the voltage */
2861         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2862                                    (void *)&vddnb, &size);
2863
2864         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2865         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2866
2867         if (r)
2868                 return r;
2869
2870         return sysfs_emit(buf, "%d\n", vddnb);
2871 }
2872
2873 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2874                                               struct device_attribute *attr,
2875                                               char *buf)
2876 {
2877         return sysfs_emit(buf, "vddnb\n");
2878 }
2879
2880 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2881                                            struct device_attribute *attr,
2882                                            char *buf)
2883 {
2884         struct amdgpu_device *adev = dev_get_drvdata(dev);
2885         u32 query = 0;
2886         int r, size = sizeof(u32);
2887         unsigned uw;
2888
2889         if (amdgpu_in_reset(adev))
2890                 return -EPERM;
2891         if (adev->in_suspend && !adev->in_runpm)
2892                 return -EPERM;
2893
2894         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2895         if (r < 0) {
2896                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2897                 return r;
2898         }
2899
2900         /* get the voltage */
2901         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2902                                    (void *)&query, &size);
2903
2904         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2905         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2906
2907         if (r)
2908                 return r;
2909
2910         /* convert to microwatts */
2911         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2912
2913         return sysfs_emit(buf, "%u\n", uw);
2914 }
2915
2916 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2917                                          struct device_attribute *attr,
2918                                          char *buf)
2919 {
2920         return sysfs_emit(buf, "%i\n", 0);
2921 }
2922
2923
2924 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2925                                         struct device_attribute *attr,
2926                                         char *buf,
2927                                         enum pp_power_limit_level pp_limit_level)
2928 {
2929         struct amdgpu_device *adev = dev_get_drvdata(dev);
2930         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2931         uint32_t limit;
2932         ssize_t size;
2933         int r;
2934
2935         if (amdgpu_in_reset(adev))
2936                 return -EPERM;
2937         if (adev->in_suspend && !adev->in_runpm)
2938                 return -EPERM;
2939
2940         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2941         if (r < 0) {
2942                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2943                 return r;
2944         }
2945
2946         r = amdgpu_dpm_get_power_limit(adev, &limit,
2947                                       pp_limit_level, power_type);
2948
2949         if (!r)
2950                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2951         else
2952                 size = sysfs_emit(buf, "\n");
2953
2954         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2955         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2956
2957         return size;
2958 }
2959
2960
2961 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2962                                          struct device_attribute *attr,
2963                                          char *buf)
2964 {
2965         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2966
2967 }
2968
2969 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2970                                          struct device_attribute *attr,
2971                                          char *buf)
2972 {
2973         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2974
2975 }
2976
2977 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2978                                          struct device_attribute *attr,
2979                                          char *buf)
2980 {
2981         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2982
2983 }
2984
2985 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2986                                          struct device_attribute *attr,
2987                                          char *buf)
2988 {
2989         struct amdgpu_device *adev = dev_get_drvdata(dev);
2990         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2991
2992         if (gc_ver == IP_VERSION(10, 3, 1))
2993                 return sysfs_emit(buf, "%s\n",
2994                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
2995                                   "fastPPT" : "slowPPT");
2996         else
2997                 return sysfs_emit(buf, "PPT\n");
2998 }
2999
3000 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3001                 struct device_attribute *attr,
3002                 const char *buf,
3003                 size_t count)
3004 {
3005         struct amdgpu_device *adev = dev_get_drvdata(dev);
3006         int limit_type = to_sensor_dev_attr(attr)->index;
3007         int err;
3008         u32 value;
3009
3010         if (amdgpu_in_reset(adev))
3011                 return -EPERM;
3012         if (adev->in_suspend && !adev->in_runpm)
3013                 return -EPERM;
3014
3015         if (amdgpu_sriov_vf(adev))
3016                 return -EINVAL;
3017
3018         err = kstrtou32(buf, 10, &value);
3019         if (err)
3020                 return err;
3021
3022         value = value / 1000000; /* convert to Watt */
3023         value |= limit_type << 24;
3024
3025         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3026         if (err < 0) {
3027                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3028                 return err;
3029         }
3030
3031         err = amdgpu_dpm_set_power_limit(adev, value);
3032
3033         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3034         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3035
3036         if (err)
3037                 return err;
3038
3039         return count;
3040 }
3041
3042 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3043                                       struct device_attribute *attr,
3044                                       char *buf)
3045 {
3046         struct amdgpu_device *adev = dev_get_drvdata(dev);
3047         uint32_t sclk;
3048         int r, size = sizeof(sclk);
3049
3050         if (amdgpu_in_reset(adev))
3051                 return -EPERM;
3052         if (adev->in_suspend && !adev->in_runpm)
3053                 return -EPERM;
3054
3055         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3056         if (r < 0) {
3057                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3058                 return r;
3059         }
3060
3061         /* get the sclk */
3062         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3063                                    (void *)&sclk, &size);
3064
3065         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3066         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3067
3068         if (r)
3069                 return r;
3070
3071         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3072 }
3073
3074 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3075                                             struct device_attribute *attr,
3076                                             char *buf)
3077 {
3078         return sysfs_emit(buf, "sclk\n");
3079 }
3080
3081 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3082                                       struct device_attribute *attr,
3083                                       char *buf)
3084 {
3085         struct amdgpu_device *adev = dev_get_drvdata(dev);
3086         uint32_t mclk;
3087         int r, size = sizeof(mclk);
3088
3089         if (amdgpu_in_reset(adev))
3090                 return -EPERM;
3091         if (adev->in_suspend && !adev->in_runpm)
3092                 return -EPERM;
3093
3094         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3095         if (r < 0) {
3096                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3097                 return r;
3098         }
3099
3100         /* get the sclk */
3101         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3102                                    (void *)&mclk, &size);
3103
3104         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3105         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3106
3107         if (r)
3108                 return r;
3109
3110         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3111 }
3112
3113 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3114                                             struct device_attribute *attr,
3115                                             char *buf)
3116 {
3117         return sysfs_emit(buf, "mclk\n");
3118 }
3119
3120 /**
3121  * DOC: hwmon
3122  *
3123  * The amdgpu driver exposes the following sensor interfaces:
3124  *
3125  * - GPU temperature (via the on-die sensor)
3126  *
3127  * - GPU voltage
3128  *
3129  * - Northbridge voltage (APUs only)
3130  *
3131  * - GPU power
3132  *
3133  * - GPU fan
3134  *
3135  * - GPU gfx/compute engine clock
3136  *
3137  * - GPU memory clock (dGPU only)
3138  *
3139  * hwmon interfaces for GPU temperature:
3140  *
3141  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3142  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3143  *
3144  * - temp[1-3]_label: temperature channel label
3145  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3146  *
3147  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3148  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3149  *
3150  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3151  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3152  *
3153  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3154  *   - these are supported on SOC15 dGPUs only
3155  *
3156  * hwmon interfaces for GPU voltage:
3157  *
3158  * - in0_input: the voltage on the GPU in millivolts
3159  *
3160  * - in1_input: the voltage on the Northbridge in millivolts
3161  *
3162  * hwmon interfaces for GPU power:
3163  *
3164  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3165  *
3166  * - power1_cap_min: minimum cap supported in microWatts
3167  *
3168  * - power1_cap_max: maximum cap supported in microWatts
3169  *
3170  * - power1_cap: selected power cap in microWatts
3171  *
3172  * hwmon interfaces for GPU fan:
3173  *
3174  * - pwm1: pulse width modulation fan level (0-255)
3175  *
3176  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3177  *
3178  * - pwm1_min: pulse width modulation fan control minimum level (0)
3179  *
3180  * - pwm1_max: pulse width modulation fan control maximum level (255)
3181  *
3182  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3183  *
3184  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3185  *
3186  * - fan1_input: fan speed in RPM
3187  *
3188  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3189  *
3190  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3191  *
3192  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3193  *       That will get the former one overridden.
3194  *
3195  * hwmon interfaces for GPU clocks:
3196  *
3197  * - freq1_input: the gfx/compute clock in hertz
3198  *
3199  * - freq2_input: the memory clock in hertz
3200  *
3201  * You can use hwmon tools like sensors to view this information on your system.
3202  *
3203  */
3204
3205 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3206 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3207 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3208 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3209 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3210 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3211 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3212 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3213 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3214 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3215 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3216 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3217 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3218 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3219 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3220 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3221 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3222 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3223 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3224 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3225 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3226 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3227 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3228 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3229 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3230 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3231 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3232 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3233 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3234 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3235 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3236 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3237 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3238 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3239 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3240 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3241 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3242 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3243 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3244 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3245 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3246 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3247 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3248 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3249
3250 static struct attribute *hwmon_attributes[] = {
3251         &sensor_dev_attr_temp1_input.dev_attr.attr,
3252         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3253         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3254         &sensor_dev_attr_temp2_input.dev_attr.attr,
3255         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3256         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3257         &sensor_dev_attr_temp3_input.dev_attr.attr,
3258         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3259         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3260         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3261         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3262         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3263         &sensor_dev_attr_temp1_label.dev_attr.attr,
3264         &sensor_dev_attr_temp2_label.dev_attr.attr,
3265         &sensor_dev_attr_temp3_label.dev_attr.attr,
3266         &sensor_dev_attr_pwm1.dev_attr.attr,
3267         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3268         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3269         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3270         &sensor_dev_attr_fan1_input.dev_attr.attr,
3271         &sensor_dev_attr_fan1_min.dev_attr.attr,
3272         &sensor_dev_attr_fan1_max.dev_attr.attr,
3273         &sensor_dev_attr_fan1_target.dev_attr.attr,
3274         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3275         &sensor_dev_attr_in0_input.dev_attr.attr,
3276         &sensor_dev_attr_in0_label.dev_attr.attr,
3277         &sensor_dev_attr_in1_input.dev_attr.attr,
3278         &sensor_dev_attr_in1_label.dev_attr.attr,
3279         &sensor_dev_attr_power1_average.dev_attr.attr,
3280         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3281         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3282         &sensor_dev_attr_power1_cap.dev_attr.attr,
3283         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3284         &sensor_dev_attr_power1_label.dev_attr.attr,
3285         &sensor_dev_attr_power2_average.dev_attr.attr,
3286         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3287         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3288         &sensor_dev_attr_power2_cap.dev_attr.attr,
3289         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3290         &sensor_dev_attr_power2_label.dev_attr.attr,
3291         &sensor_dev_attr_freq1_input.dev_attr.attr,
3292         &sensor_dev_attr_freq1_label.dev_attr.attr,
3293         &sensor_dev_attr_freq2_input.dev_attr.attr,
3294         &sensor_dev_attr_freq2_label.dev_attr.attr,
3295         NULL
3296 };
3297
3298 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3299                                         struct attribute *attr, int index)
3300 {
3301         struct device *dev = kobj_to_dev(kobj);
3302         struct amdgpu_device *adev = dev_get_drvdata(dev);
3303         umode_t effective_mode = attr->mode;
3304         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3305
3306         /* under multi-vf mode, the hwmon attributes are all not supported */
3307         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3308                 return 0;
3309
3310         /* under pp one vf mode manage of hwmon attributes is not supported */
3311         if (amdgpu_sriov_is_pp_one_vf(adev))
3312                 effective_mode &= ~S_IWUSR;
3313
3314         /* Skip fan attributes if fan is not present */
3315         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3316             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3317             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3318             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3319             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3320             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3321             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3322             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3323             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3324                 return 0;
3325
3326         /* Skip fan attributes on APU */
3327         if ((adev->flags & AMD_IS_APU) &&
3328             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3329              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3330              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3331              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3332              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3333              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3334              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3335              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3336              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3337                 return 0;
3338
3339         /* Skip crit temp on APU */
3340         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3341             (gc_ver == IP_VERSION(9, 4, 3))) &&
3342             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3343              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3344                 return 0;
3345
3346         /* Skip limit attributes if DPM is not enabled */
3347         if (!adev->pm.dpm_enabled &&
3348             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3349              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3350              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3351              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3352              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3353              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3354              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3355              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3356              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3357              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3358              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3359                 return 0;
3360
3361         /* mask fan attributes if we have no bindings for this asic to expose */
3362         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3363               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3364             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3365              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3366                 effective_mode &= ~S_IRUGO;
3367
3368         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3369               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3370               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3371               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3372                 effective_mode &= ~S_IWUSR;
3373
3374         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3375         if (((adev->family == AMDGPU_FAMILY_SI) ||
3376              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3377               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3378             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3379              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3380              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3381              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3382                 return 0;
3383
3384         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3385         if (((adev->family == AMDGPU_FAMILY_SI) ||
3386              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3387             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3388                 return 0;
3389
3390         /* hide max/min values if we can't both query and manage the fan */
3391         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3392               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3393               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3394               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3395             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3396              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3397                 return 0;
3398
3399         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3400              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3401              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3402              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3403                 return 0;
3404
3405         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3406              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3407              (gc_ver == IP_VERSION(9, 4, 3))) &&
3408             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3409              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3410                 return 0;
3411
3412         /* only APUs other than gc 9,4,3 have vddnb */
3413         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3414             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3415              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3416                 return 0;
3417
3418         /* no mclk on APUs other than gc 9,4,3*/
3419         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3420             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3421              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3422                 return 0;
3423
3424         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3425             (gc_ver != IP_VERSION(9, 4, 3)) &&
3426             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3427              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3428              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3429              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3430                 return 0;
3431
3432         /* hotspot temperature for gc 9,4,3*/
3433         if ((gc_ver == IP_VERSION(9, 4, 3)) &&
3434             (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3435              attr == &sensor_dev_attr_temp1_label.dev_attr.attr))
3436                 return 0;
3437
3438         /* only SOC15 dGPUs support hotspot and mem temperatures */
3439         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) ||
3440             (gc_ver == IP_VERSION(9, 4, 3))) &&
3441             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3442              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3443              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3444              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3445              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3446              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3447              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3448                 return 0;
3449
3450         /* only Vangogh has fast PPT limit and power labels */
3451         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3452             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3453              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3454              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3455              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3456              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3457              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3458                 return 0;
3459
3460         return effective_mode;
3461 }
3462
3463 static const struct attribute_group hwmon_attrgroup = {
3464         .attrs = hwmon_attributes,
3465         .is_visible = hwmon_attributes_visible,
3466 };
3467
3468 static const struct attribute_group *hwmon_groups[] = {
3469         &hwmon_attrgroup,
3470         NULL
3471 };
3472
3473 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3474 {
3475         int ret;
3476         uint32_t mask = 0;
3477
3478         if (adev->pm.sysfs_initialized)
3479                 return 0;
3480
3481         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3482
3483         if (adev->pm.dpm_enabled == 0)
3484                 return 0;
3485
3486         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3487                                                                    DRIVER_NAME, adev,
3488                                                                    hwmon_groups);
3489         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3490                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3491                 dev_err(adev->dev,
3492                         "Unable to register hwmon device: %d\n", ret);
3493                 return ret;
3494         }
3495
3496         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3497         case SRIOV_VF_MODE_ONE_VF:
3498                 mask = ATTR_FLAG_ONEVF;
3499                 break;
3500         case SRIOV_VF_MODE_MULTI_VF:
3501                 mask = 0;
3502                 break;
3503         case SRIOV_VF_MODE_BARE_METAL:
3504         default:
3505                 mask = ATTR_FLAG_MASK_ALL;
3506                 break;
3507         }
3508
3509         ret = amdgpu_device_attr_create_groups(adev,
3510                                                amdgpu_device_attrs,
3511                                                ARRAY_SIZE(amdgpu_device_attrs),
3512                                                mask,
3513                                                &adev->pm.pm_attr_list);
3514         if (ret)
3515                 return ret;
3516
3517         adev->pm.sysfs_initialized = true;
3518
3519         return 0;
3520 }
3521
3522 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3523 {
3524         if (adev->pm.int_hwmon_dev)
3525                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3526
3527         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3528 }
3529
3530 /*
3531  * Debugfs info
3532  */
3533 #if defined(CONFIG_DEBUG_FS)
3534
3535 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3536                                            struct amdgpu_device *adev) {
3537         uint16_t *p_val;
3538         uint32_t size;
3539         int i;
3540         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3541
3542         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3543                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3544                                 GFP_KERNEL);
3545
3546                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3547                                             (void *)p_val, &size)) {
3548                         for (i = 0; i < num_cpu_cores; i++)
3549                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3550                                            *(p_val + i), i);
3551                 }
3552
3553                 kfree(p_val);
3554         }
3555 }
3556
3557 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3558 {
3559         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3560         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3561         uint32_t value;
3562         uint64_t value64 = 0;
3563         uint32_t query = 0;
3564         int size;
3565
3566         /* GPU Clocks */
3567         size = sizeof(value);
3568         seq_printf(m, "GFX Clocks and Power:\n");
3569
3570         amdgpu_debugfs_prints_cpu_info(m, adev);
3571
3572         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3573                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3574         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3575                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3576         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3577                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3578         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3579                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3580         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3581                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3582         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3583                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3584         size = sizeof(uint32_t);
3585         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3586                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3587         size = sizeof(value);
3588         seq_printf(m, "\n");
3589
3590         /* GPU Temp */
3591         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3592                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3593
3594         /* GPU Load */
3595         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3596                 seq_printf(m, "GPU Load: %u %%\n", value);
3597         /* MEM Load */
3598         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3599                 seq_printf(m, "MEM Load: %u %%\n", value);
3600
3601         seq_printf(m, "\n");
3602
3603         /* SMC feature mask */
3604         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3605                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3606
3607         /* ASICs greater than CHIP_VEGA20 supports these sensors */
3608         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3609                 /* VCN clocks */
3610                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3611                         if (!value) {
3612                                 seq_printf(m, "VCN: Disabled\n");
3613                         } else {
3614                                 seq_printf(m, "VCN: Enabled\n");
3615                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3616                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3617                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3618                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3619                         }
3620                 }
3621                 seq_printf(m, "\n");
3622         } else {
3623                 /* UVD clocks */
3624                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3625                         if (!value) {
3626                                 seq_printf(m, "UVD: Disabled\n");
3627                         } else {
3628                                 seq_printf(m, "UVD: Enabled\n");
3629                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3630                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3631                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3632                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3633                         }
3634                 }
3635                 seq_printf(m, "\n");
3636
3637                 /* VCE clocks */
3638                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3639                         if (!value) {
3640                                 seq_printf(m, "VCE: Disabled\n");
3641                         } else {
3642                                 seq_printf(m, "VCE: Enabled\n");
3643                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3644                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3645                         }
3646                 }
3647         }
3648
3649         return 0;
3650 }
3651
3652 static const struct cg_flag_name clocks[] = {
3653         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
3654         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
3655         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
3656         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
3657         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
3658         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
3659         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
3660         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
3661         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
3662         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
3663         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
3664         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
3665         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
3666         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
3667         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
3668         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
3669         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
3670         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
3671         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
3672         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
3673         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
3674         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
3675         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
3676         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
3677         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
3678         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
3679         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
3680         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
3681         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
3682         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
3683         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
3684         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
3685         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
3686         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
3687         {0, NULL},
3688 };
3689
3690 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3691 {
3692         int i;
3693
3694         for (i = 0; clocks[i].flag; i++)
3695                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3696                            (flags & clocks[i].flag) ? "On" : "Off");
3697 }
3698
3699 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3700 {
3701         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3702         struct drm_device *dev = adev_to_drm(adev);
3703         u64 flags = 0;
3704         int r;
3705
3706         if (amdgpu_in_reset(adev))
3707                 return -EPERM;
3708         if (adev->in_suspend && !adev->in_runpm)
3709                 return -EPERM;
3710
3711         r = pm_runtime_get_sync(dev->dev);
3712         if (r < 0) {
3713                 pm_runtime_put_autosuspend(dev->dev);
3714                 return r;
3715         }
3716
3717         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3718                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3719                 if (r)
3720                         goto out;
3721         }
3722
3723         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3724
3725         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3726         amdgpu_parse_cg_state(m, flags);
3727         seq_printf(m, "\n");
3728
3729 out:
3730         pm_runtime_mark_last_busy(dev->dev);
3731         pm_runtime_put_autosuspend(dev->dev);
3732
3733         return r;
3734 }
3735
3736 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3737
3738 /*
3739  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3740  *
3741  * Reads debug memory region allocated to PMFW
3742  */
3743 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3744                                          size_t size, loff_t *pos)
3745 {
3746         struct amdgpu_device *adev = file_inode(f)->i_private;
3747         size_t smu_prv_buf_size;
3748         void *smu_prv_buf;
3749         int ret = 0;
3750
3751         if (amdgpu_in_reset(adev))
3752                 return -EPERM;
3753         if (adev->in_suspend && !adev->in_runpm)
3754                 return -EPERM;
3755
3756         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3757         if (ret)
3758                 return ret;
3759
3760         if (!smu_prv_buf || !smu_prv_buf_size)
3761                 return -EINVAL;
3762
3763         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3764                                        smu_prv_buf_size);
3765 }
3766
3767 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3768         .owner = THIS_MODULE,
3769         .open = simple_open,
3770         .read = amdgpu_pm_prv_buffer_read,
3771         .llseek = default_llseek,
3772 };
3773
3774 #endif
3775
3776 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3777 {
3778 #if defined(CONFIG_DEBUG_FS)
3779         struct drm_minor *minor = adev_to_drm(adev)->primary;
3780         struct dentry *root = minor->debugfs_root;
3781
3782         if (!adev->pm.dpm_enabled)
3783                 return;
3784
3785         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3786                             &amdgpu_debugfs_pm_info_fops);
3787
3788         if (adev->pm.smu_prv_buffer_size > 0)
3789                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3790                                          adev,
3791                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3792                                          adev->pm.smu_prv_buffer_size);
3793
3794         amdgpu_dpm_stb_debug_fs_init(adev);
3795 #endif
3796 }