drivers/misc/cardreader/rts5227.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <[email protected]>
  20  *   Roger Tseng <[email protected]>
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/rtsx_pci.h>
  26
  27 #include "rtsx_pcr.h"
  28
  29 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  30 {
  31         u8 val;
  32
  33         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  34         return val & 0x0F;
  35 }
  36
  37 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  38 {
  39         u8 driving_3v3[4][3] = {
  40                 {0x13, 0x13, 0x13},
  41                 {0x96, 0x96, 0x96},
  42                 {0x7F, 0x7F, 0x7F},
  43                 {0x96, 0x96, 0x96},
  44         };
  45         u8 driving_1v8[4][3] = {
  46                 {0x99, 0x99, 0x99},
  47                 {0xAA, 0xAA, 0xAA},
  48                 {0xFE, 0xFE, 0xFE},
  49                 {0xB3, 0xB3, 0xB3},
  50         };
  51         u8 (*driving)[3], drive_sel;
  52
  53         if (voltage == OUTPUT_3V3) {
  54                 driving = driving_3v3;
  55                 drive_sel = pcr->sd30_drive_sel_3v3;
  56         } else {
  57                 driving = driving_1v8;
  58                 drive_sel = pcr->sd30_drive_sel_1v8;
  59         }
  60
  61         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  62                         0xFF, driving[drive_sel][0]);
  63         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  64                         0xFF, driving[drive_sel][1]);
  65         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  66                         0xFF, driving[drive_sel][2]);
  67 }
  68
  69 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  70 {
  71         u32 reg;
  72
  73         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  74         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  75
  76         if (!rtsx_vendor_setting_valid(reg))
  77                 return;
  78
  79         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  80         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  81         pcr->card_drive_sel &= 0x3F;
  82         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  83
  84         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  85         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  86         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  87         if (rtsx_reg_check_reverse_socket(reg))
  88                 pcr->flags |= PCR_REVERSE_SOCKET;
  89 }
  90
  91 static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  92 {
  93         /* Set relink_time to 0 */
  94         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  95         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  96         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  97
  98         if (pm_state == HOST_ENTER_S3)
  99                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
 100
 101         rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
 102 }
 103
 104 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
 105 {
 106         u16 cap;
 107
 108         rtsx_pci_init_cmd(pcr);
 109
 110         /* Configure GPIO as output */
 111         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 112         /* Reset ASPM state to default value */
 113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 114         /* Switch LDO3318 source from DV33 to card_3v3 */
 115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 117         /* LED shine disabled, set initial shine cycle period */
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 119         /* Configure LTR */
 120         pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
 121         if (cap & PCI_EXP_DEVCTL2_LTR_EN)
 122                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
 123         /* Configure OBFF */
 124         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
 125         /* Configure driving */
 126         rts5227_fill_driving(pcr, OUTPUT_3V3);
 127         /* Configure force_clock_req */
 128         if (pcr->flags & PCR_REVERSE_SOCKET)
 129                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
 130         else
 131                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
 132         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
 133
 134         return rtsx_pci_send_cmd(pcr, 100);
 135 }
 136
 137 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
 138 {
 139         int err;
 140
 141         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 142         if (err < 0)
 143                 return err;
 144
 145         /* Optimize RX sensitivity */
 146         return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
 147 }
 148
 149 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
 150 {
 151         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 152 }
 153
 154 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
 155 {
 156         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 157 }
 158
 159 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
 160 {
 161         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 162 }
 163
 164 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
 165 {
 166         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 167 }
 168
 169 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
 170 {
 171         int err;
 172
 173         if (pcr->option.ocp_en)
 174                 rtsx_pci_enable_ocp(pcr);
 175
 176         rtsx_pci_init_cmd(pcr);
 177         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 178                         SD_POWER_MASK, SD_PARTIAL_POWER_ON);
 179
 180         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 181                         LDO3318_PWR_MASK, 0x02);
 182
 183         err = rtsx_pci_send_cmd(pcr, 100);
 184         if (err < 0)
 185                 return err;
 186
 187         /* To avoid too large in-rush current */
 188         msleep(20);
 189         rtsx_pci_init_cmd(pcr);
 190         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 191                         SD_POWER_MASK, SD_POWER_ON);
 192
 193         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 194                         LDO3318_PWR_MASK, 0x06);
 195
 196         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 197                         SD_OUTPUT_EN, SD_OUTPUT_EN);
 198         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 199                         MS_OUTPUT_EN, MS_OUTPUT_EN);
 200         return rtsx_pci_send_cmd(pcr, 100);
 201 }
 202
 203 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
 204 {
 205         if (pcr->option.ocp_en)
 206                 rtsx_pci_disable_ocp(pcr);
 207
 208         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
 209                         PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
 210         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
 211
 212         return 0;
 213 }
 214
 215 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 216 {
 217         int err;
 218
 219         if (voltage == OUTPUT_3V3) {
 220                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
 221                 if (err < 0)
 222                         return err;
 223         } else if (voltage == OUTPUT_1V8) {
 224                 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 225                 if (err < 0)
 226                         return err;
 227                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
 228                 if (err < 0)
 229                         return err;
 230         } else {
 231                 return -EINVAL;
 232         }
 233
 234         /* set pad drive */
 235         rtsx_pci_init_cmd(pcr);
 236         rts5227_fill_driving(pcr, voltage);
 237         return rtsx_pci_send_cmd(pcr, 100);
 238 }
 239
 240 static const struct pcr_ops rts5227_pcr_ops = {
 241         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 242         .extra_init_hw = rts5227_extra_init_hw,
 243         .optimize_phy = rts5227_optimize_phy,
 244         .turn_on_led = rts5227_turn_on_led,
 245         .turn_off_led = rts5227_turn_off_led,
 246         .enable_auto_blink = rts5227_enable_auto_blink,
 247         .disable_auto_blink = rts5227_disable_auto_blink,
 248         .card_power_on = rts5227_card_power_on,
 249         .card_power_off = rts5227_card_power_off,
 250         .switch_output_voltage = rts5227_switch_output_voltage,
 251         .cd_deglitch = NULL,
 252         .conv_clk_and_div_n = NULL,
 253         .force_power_down = rts5227_force_power_down,
 254 };
 255
 256 /* SD Pull Control Enable:
 257  *     SD_DAT[3:0] ==> pull up
 258  *     SD_CD       ==> pull up
 259  *     SD_WP       ==> pull up
 260  *     SD_CMD      ==> pull up
 261  *     SD_CLK      ==> pull down
 262  */
 263 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
 264         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 265         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 266         0,
 267 };
 268
 269 /* SD Pull Control Disable:
 270  *     SD_DAT[3:0] ==> pull down
 271  *     SD_CD       ==> pull up
 272  *     SD_WP       ==> pull down
 273  *     SD_CMD      ==> pull down
 274  *     SD_CLK      ==> pull down
 275  */
 276 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
 277         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 278         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 279         0,
 280 };
 281
 282 /* MS Pull Control Enable:
 283  *     MS CD       ==> pull up
 284  *     others      ==> pull down
 285  */
 286 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
 287         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 288         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 289         0,
 290 };
 291
 292 /* MS Pull Control Disable:
 293  *     MS CD       ==> pull up
 294  *     others      ==> pull down
 295  */
 296 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
 297         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 298         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 299         0,
 300 };
 301
 302 void rts5227_init_params(struct rtsx_pcr *pcr)
 303 {
 304         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 305         pcr->num_slots = 2;
 306         pcr->ops = &rts5227_pcr_ops;
 307
 308         pcr->flags = 0;
 309         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 310         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 311         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 312         pcr->aspm_en = ASPM_L1_EN;
 313         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
 314         pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
 315
 316         pcr->ic_version = rts5227_get_ic_version(pcr);
 317         pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
 318         pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
 319         pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
 320         pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
 321
 322         pcr->reg_pm_ctrl3 = PM_CTRL3;
 323 }
 324
 325 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
 326 {
 327         int err;
 328
 329         err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
 330                 0x00);
 331         if (err < 0)
 332                 return err;
 333
 334         if (is_version(pcr, 0x522A, IC_VER_A)) {
 335                 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 336                         PHY_RCR2_INIT_27S);
 337                 if (err)
 338                         return err;
 339
 340                 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
 341                 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
 342                 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
 343                 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
 350 {
 351         rts5227_extra_init_hw(pcr);
 352
 353         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
 354                 FUNC_FORCE_UPME_XMT_DBG);
 355         rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
 356         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 357         rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
 358
 359         return 0;
 360 }
 361
 362 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 363 {
 364         int err;
 365
 366         if (voltage == OUTPUT_3V3) {
 367                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
 368                 if (err < 0)
 369                         return err;
 370         } else if (voltage == OUTPUT_1V8) {
 371                 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 372                 if (err < 0)
 373                         return err;
 374                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
 375                 if (err < 0)
 376                         return err;
 377         } else {
 378                 return -EINVAL;
 379         }
 380
 381         /* set pad drive */
 382         rtsx_pci_init_cmd(pcr);
 383         rts5227_fill_driving(pcr, voltage);
 384         return rtsx_pci_send_cmd(pcr, 100);
 385 }
 386
 387
 388 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
 389  */
 390 static const struct pcr_ops rts522a_pcr_ops = {
 391         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 392         .extra_init_hw = rts522a_extra_init_hw,
 393         .optimize_phy = rts522a_optimize_phy,
 394         .turn_on_led = rts5227_turn_on_led,
 395         .turn_off_led = rts5227_turn_off_led,
 396         .enable_auto_blink = rts5227_enable_auto_blink,
 397         .disable_auto_blink = rts5227_disable_auto_blink,
 398         .card_power_on = rts5227_card_power_on,
 399         .card_power_off = rts5227_card_power_off,
 400         .switch_output_voltage = rts522a_switch_output_voltage,
 401         .cd_deglitch = NULL,
 402         .conv_clk_and_div_n = NULL,
 403         .force_power_down = rts5227_force_power_down,
 404 };
 405
 406 void rts522a_init_params(struct rtsx_pcr *pcr)
 407 {
 408         rts5227_init_params(pcr);
 409
 410         pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
 411
 412         pcr->option.ocp_en = 1;
 413         if (pcr->option.ocp_en)
 414                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 415         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 416         pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
 417
 418 }