drivers/memory/tegra/mc.c

   1 /*
   2  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/sort.h>
  19
  20 #include <soc/tegra/fuse.h>
  21
  22 #include "mc.h"
  23
  24 #define MC_INTSTATUS 0x000
  25
  26 #define MC_INTMASK 0x004
  27
  28 #define MC_ERR_STATUS 0x08
  29 #define  MC_ERR_STATUS_TYPE_SHIFT 28
  30 #define  MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
  31 #define  MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
  32 #define  MC_ERR_STATUS_READABLE (1 << 27)
  33 #define  MC_ERR_STATUS_WRITABLE (1 << 26)
  34 #define  MC_ERR_STATUS_NONSECURE (1 << 25)
  35 #define  MC_ERR_STATUS_ADR_HI_SHIFT 20
  36 #define  MC_ERR_STATUS_ADR_HI_MASK 0x3
  37 #define  MC_ERR_STATUS_SECURITY (1 << 17)
  38 #define  MC_ERR_STATUS_RW (1 << 16)
  39
  40 #define MC_ERR_ADR 0x0c
  41
  42 #define MC_GART_ERROR_REQ               0x30
  43 #define MC_DECERR_EMEM_OTHERS_STATUS    0x58
  44 #define MC_SECURITY_VIOLATION_STATUS    0x74
  45
  46 #define MC_EMEM_ARB_CFG 0x90
  47 #define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)   (((x) & 0x1ff) << 0)
  48 #define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
  49 #define MC_EMEM_ARB_MISC0 0xd8
  50
  51 #define MC_EMEM_ADR_CFG 0x54
  52 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
  53
  54 #define MC_TIMING_CONTROL               0xfc
  55 #define MC_TIMING_UPDATE                BIT(0)
  56
  57 static const struct of_device_id tegra_mc_of_match[] = {
  58 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  59         { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
  60 #endif
  61 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  62         { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
  63 #endif
  64 #ifdef CONFIG_ARCH_TEGRA_114_SOC
  65         { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
  66 #endif
  67 #ifdef CONFIG_ARCH_TEGRA_124_SOC
  68         { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
  69 #endif
  70 #ifdef CONFIG_ARCH_TEGRA_132_SOC
  71         { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
  72 #endif
  73 #ifdef CONFIG_ARCH_TEGRA_210_SOC
  74         { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
  75 #endif
  76         { }
  77 };
  78 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
  79
  80 static int tegra_mc_block_dma_common(struct tegra_mc *mc,
  81                                      const struct tegra_mc_reset *rst)
  82 {
  83         unsigned long flags;
  84         u32 value;
  85
  86         spin_lock_irqsave(&mc->lock, flags);
  87
  88         value = mc_readl(mc, rst->control) | BIT(rst->bit);
  89         mc_writel(mc, value, rst->control);
  90
  91         spin_unlock_irqrestore(&mc->lock, flags);
  92
  93         return 0;
  94 }
  95
  96 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
  97                                        const struct tegra_mc_reset *rst)
  98 {
  99         return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
 100 }
 101
 102 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
 103                                        const struct tegra_mc_reset *rst)
 104 {
 105         unsigned long flags;
 106         u32 value;
 107
 108         spin_lock_irqsave(&mc->lock, flags);
 109
 110         value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
 111         mc_writel(mc, value, rst->control);
 112
 113         spin_unlock_irqrestore(&mc->lock, flags);
 114
 115         return 0;
 116 }
 117
 118 static int tegra_mc_reset_status_common(struct tegra_mc *mc,
 119                                         const struct tegra_mc_reset *rst)
 120 {
 121         return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
 122 }
 123
 124 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
 125         .block_dma = tegra_mc_block_dma_common,
 126         .dma_idling = tegra_mc_dma_idling_common,
 127         .unblock_dma = tegra_mc_unblock_dma_common,
 128         .reset_status = tegra_mc_reset_status_common,
 129 };
 130
 131 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
 132 {
 133         return container_of(rcdev, struct tegra_mc, reset);
 134 }
 135
 136 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
 137                                                         unsigned long id)
 138 {
 139         unsigned int i;
 140
 141         for (i = 0; i < mc->soc->num_resets; i++)
 142                 if (mc->soc->resets[i].id == id)
 143                         return &mc->soc->resets[i];
 144
 145         return NULL;
 146 }
 147
 148 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
 149                                     unsigned long id)
 150 {
 151         struct tegra_mc *mc = reset_to_mc(rcdev);
 152         const struct tegra_mc_reset_ops *rst_ops;
 153         const struct tegra_mc_reset *rst;
 154         int retries = 500;
 155         int err;
 156
 157         rst = tegra_mc_reset_find(mc, id);
 158         if (!rst)
 159                 return -ENODEV;
 160
 161         rst_ops = mc->soc->reset_ops;
 162         if (!rst_ops)
 163                 return -ENODEV;
 164
 165         if (rst_ops->block_dma) {
 166                 /* block clients DMA requests */
 167                 err = rst_ops->block_dma(mc, rst);
 168                 if (err) {
 169                         dev_err(mc->dev, "failed to block %s DMA: %d\n",
 170                                 rst->name, err);
 171                         return err;
 172                 }
 173         }
 174
 175         if (rst_ops->dma_idling) {
 176                 /* wait for completion of the outstanding DMA requests */
 177                 while (!rst_ops->dma_idling(mc, rst)) {
 178                         if (!retries--) {
 179                                 dev_err(mc->dev, "failed to flush %s DMA\n",
 180                                         rst->name);
 181                                 return -EBUSY;
 182                         }
 183
 184                         usleep_range(10, 100);
 185                 }
 186         }
 187
 188         if (rst_ops->hotreset_assert) {
 189                 /* clear clients DMA requests sitting before arbitration */
 190                 err = rst_ops->hotreset_assert(mc, rst);
 191                 if (err) {
 192                         dev_err(mc->dev, "failed to hot reset %s: %d\n",
 193                                 rst->name, err);
 194                         return err;
 195                 }
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
 202                                       unsigned long id)
 203 {
 204         struct tegra_mc *mc = reset_to_mc(rcdev);
 205         const struct tegra_mc_reset_ops *rst_ops;
 206         const struct tegra_mc_reset *rst;
 207         int err;
 208
 209         rst = tegra_mc_reset_find(mc, id);
 210         if (!rst)
 211                 return -ENODEV;
 212
 213         rst_ops = mc->soc->reset_ops;
 214         if (!rst_ops)
 215                 return -ENODEV;
 216
 217         if (rst_ops->hotreset_deassert) {
 218                 /* take out client from hot reset */
 219                 err = rst_ops->hotreset_deassert(mc, rst);
 220                 if (err) {
 221                         dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
 222                                 rst->name, err);
 223                         return err;
 224                 }
 225         }
 226
 227         if (rst_ops->unblock_dma) {
 228                 /* allow new DMA requests to proceed to arbitration */
 229                 err = rst_ops->unblock_dma(mc, rst);
 230                 if (err) {
 231                         dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
 232                                 rst->name, err);
 233                         return err;
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
 241                                     unsigned long id)
 242 {
 243         struct tegra_mc *mc = reset_to_mc(rcdev);
 244         const struct tegra_mc_reset_ops *rst_ops;
 245         const struct tegra_mc_reset *rst;
 246
 247         rst = tegra_mc_reset_find(mc, id);
 248         if (!rst)
 249                 return -ENODEV;
 250
 251         rst_ops = mc->soc->reset_ops;
 252         if (!rst_ops)
 253                 return -ENODEV;
 254
 255         return rst_ops->reset_status(mc, rst);
 256 }
 257
 258 static const struct reset_control_ops tegra_mc_reset_ops = {
 259         .assert = tegra_mc_hotreset_assert,
 260         .deassert = tegra_mc_hotreset_deassert,
 261         .status = tegra_mc_hotreset_status,
 262 };
 263
 264 static int tegra_mc_reset_setup(struct tegra_mc *mc)
 265 {
 266         int err;
 267
 268         mc->reset.ops = &tegra_mc_reset_ops;
 269         mc->reset.owner = THIS_MODULE;
 270         mc->reset.of_node = mc->dev->of_node;
 271         mc->reset.of_reset_n_cells = 1;
 272         mc->reset.nr_resets = mc->soc->num_resets;
 273
 274         err = reset_controller_register(&mc->reset);
 275         if (err < 0)
 276                 return err;
 277
 278         return 0;
 279 }
 280
 281 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
 282 {
 283         unsigned long long tick;
 284         unsigned int i;
 285         u32 value;
 286
 287         /* compute the number of MC clock cycles per tick */
 288         tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
 289         do_div(tick, NSEC_PER_SEC);
 290
 291         value = mc_readl(mc, MC_EMEM_ARB_CFG);
 292         value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
 293         value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
 294         mc_writel(mc, value, MC_EMEM_ARB_CFG);
 295
 296         /* write latency allowance defaults */
 297         for (i = 0; i < mc->soc->num_clients; i++) {
 298                 const struct tegra_mc_la *la = &mc->soc->clients[i].la;
 299                 u32 value;
 300
 301                 value = mc_readl(mc, la->reg);
 302                 value &= ~(la->mask << la->shift);
 303                 value |= (la->def & la->mask) << la->shift;
 304                 mc_writel(mc, value, la->reg);
 305         }
 306
 307         /* latch new values */
 308         mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
 309
 310         return 0;
 311 }
 312
 313 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
 314 {
 315         unsigned int i;
 316         struct tegra_mc_timing *timing = NULL;
 317
 318         for (i = 0; i < mc->num_timings; i++) {
 319                 if (mc->timings[i].rate == rate) {
 320                         timing = &mc->timings[i];
 321                         break;
 322                 }
 323         }
 324
 325         if (!timing) {
 326                 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
 327                         rate);
 328                 return;
 329         }
 330
 331         for (i = 0; i < mc->soc->num_emem_regs; ++i)
 332                 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
 333 }
 334
 335 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
 336 {
 337         u8 dram_count;
 338
 339         dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
 340         dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
 341         dram_count++;
 342
 343         return dram_count;
 344 }
 345
 346 static int load_one_timing(struct tegra_mc *mc,
 347                            struct tegra_mc_timing *timing,
 348                            struct device_node *node)
 349 {
 350         int err;
 351         u32 tmp;
 352
 353         err = of_property_read_u32(node, "clock-frequency", &tmp);
 354         if (err) {
 355                 dev_err(mc->dev,
 356                         "timing %pOFn: failed to read rate\n", node);
 357                 return err;
 358         }
 359
 360         timing->rate = tmp;
 361         timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
 362                                          sizeof(u32), GFP_KERNEL);
 363         if (!timing->emem_data)
 364                 return -ENOMEM;
 365
 366         err = of_property_read_u32_array(node, "nvidia,emem-configuration",
 367                                          timing->emem_data,
 368                                          mc->soc->num_emem_regs);
 369         if (err) {
 370                 dev_err(mc->dev,
 371                         "timing %pOFn: failed to read EMEM configuration\n",
 372                         node);
 373                 return err;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int load_timings(struct tegra_mc *mc, struct device_node *node)
 380 {
 381         struct device_node *child;
 382         struct tegra_mc_timing *timing;
 383         int child_count = of_get_child_count(node);
 384         int i = 0, err;
 385
 386         mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
 387                                    GFP_KERNEL);
 388         if (!mc->timings)
 389                 return -ENOMEM;
 390
 391         mc->num_timings = child_count;
 392
 393         for_each_child_of_node(node, child) {
 394                 timing = &mc->timings[i++];
 395
 396                 err = load_one_timing(mc, timing, child);
 397                 if (err) {
 398                         of_node_put(child);
 399                         return err;
 400                 }
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int tegra_mc_setup_timings(struct tegra_mc *mc)
 407 {
 408         struct device_node *node;
 409         u32 ram_code, node_ram_code;
 410         int err;
 411
 412         ram_code = tegra_read_ram_code();
 413
 414         mc->num_timings = 0;
 415
 416         for_each_child_of_node(mc->dev->of_node, node) {
 417                 err = of_property_read_u32(node, "nvidia,ram-code",
 418                                            &node_ram_code);
 419                 if (err || (node_ram_code != ram_code))
 420                         continue;
 421
 422                 err = load_timings(mc, node);
 423                 of_node_put(node);
 424                 if (err)
 425                         return err;
 426                 break;
 427         }
 428
 429         if (mc->num_timings == 0)
 430                 dev_warn(mc->dev,
 431                          "no memory timings for RAM code %u registered\n",
 432                          ram_code);
 433
 434         return 0;
 435 }
 436
 437 static const char *const status_names[32] = {
 438         [ 1] = "External interrupt",
 439         [ 6] = "EMEM address decode error",
 440         [ 7] = "GART page fault",
 441         [ 8] = "Security violation",
 442         [ 9] = "EMEM arbitration error",
 443         [10] = "Page fault",
 444         [11] = "Invalid APB ASID update",
 445         [12] = "VPR violation",
 446         [13] = "Secure carveout violation",
 447         [16] = "MTS carveout violation",
 448 };
 449
 450 static const char *const error_names[8] = {
 451         [2] = "EMEM decode error",
 452         [3] = "TrustZone violation",
 453         [4] = "Carveout violation",
 454         [6] = "SMMU translation error",
 455 };
 456
 457 static irqreturn_t tegra_mc_irq(int irq, void *data)
 458 {
 459         struct tegra_mc *mc = data;
 460         unsigned long status;
 461         unsigned int bit;
 462
 463         /* mask all interrupts to avoid flooding */
 464         status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
 465         if (!status)
 466                 return IRQ_NONE;
 467
 468         for_each_set_bit(bit, &status, 32) {
 469                 const char *error = status_names[bit] ?: "unknown";
 470                 const char *client = "unknown", *desc;
 471                 const char *direction, *secure;
 472                 phys_addr_t addr = 0;
 473                 unsigned int i;
 474                 char perm[7];
 475                 u8 id, type;
 476                 u32 value;
 477
 478                 value = mc_readl(mc, MC_ERR_STATUS);
 479
 480 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 481                 if (mc->soc->num_address_bits > 32) {
 482                         addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
 483                                 MC_ERR_STATUS_ADR_HI_MASK);
 484                         addr <<= 32;
 485                 }
 486 #endif
 487
 488                 if (value & MC_ERR_STATUS_RW)
 489                         direction = "write";
 490                 else
 491                         direction = "read";
 492
 493                 if (value & MC_ERR_STATUS_SECURITY)
 494                         secure = "secure ";
 495                 else
 496                         secure = "";
 497
 498                 id = value & mc->soc->client_id_mask;
 499
 500                 for (i = 0; i < mc->soc->num_clients; i++) {
 501                         if (mc->soc->clients[i].id == id) {
 502                                 client = mc->soc->clients[i].name;
 503                                 break;
 504                         }
 505                 }
 506
 507                 type = (value & MC_ERR_STATUS_TYPE_MASK) >>
 508                        MC_ERR_STATUS_TYPE_SHIFT;
 509                 desc = error_names[type];
 510
 511                 switch (value & MC_ERR_STATUS_TYPE_MASK) {
 512                 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
 513                         perm[0] = ' ';
 514                         perm[1] = '[';
 515
 516                         if (value & MC_ERR_STATUS_READABLE)
 517                                 perm[2] = 'R';
 518                         else
 519                                 perm[2] = '-';
 520
 521                         if (value & MC_ERR_STATUS_WRITABLE)
 522                                 perm[3] = 'W';
 523                         else
 524                                 perm[3] = '-';
 525
 526                         if (value & MC_ERR_STATUS_NONSECURE)
 527                                 perm[4] = '-';
 528                         else
 529                                 perm[4] = 'S';
 530
 531                         perm[5] = ']';
 532                         perm[6] = '\0';
 533                         break;
 534
 535                 default:
 536                         perm[0] = '\0';
 537                         break;
 538                 }
 539
 540                 value = mc_readl(mc, MC_ERR_ADR);
 541                 addr |= value;
 542
 543                 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
 544                                     client, secure, direction, &addr, error,
 545                                     desc, perm);
 546         }
 547
 548         /* clear interrupts */
 549         mc_writel(mc, status, MC_INTSTATUS);
 550
 551         return IRQ_HANDLED;
 552 }
 553
 554 static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
 555 {
 556         struct tegra_mc *mc = data;
 557         unsigned long status;
 558         unsigned int bit;
 559
 560         /* mask all interrupts to avoid flooding */
 561         status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
 562         if (!status)
 563                 return IRQ_NONE;
 564
 565         for_each_set_bit(bit, &status, 32) {
 566                 const char *direction = "read", *secure = "";
 567                 const char *error = status_names[bit];
 568                 const char *client, *desc;
 569                 phys_addr_t addr;
 570                 u32 value, reg;
 571                 u8 id, type;
 572
 573                 switch (BIT(bit)) {
 574                 case MC_INT_DECERR_EMEM:
 575                         reg = MC_DECERR_EMEM_OTHERS_STATUS;
 576                         value = mc_readl(mc, reg);
 577
 578                         id = value & mc->soc->client_id_mask;
 579                         desc = error_names[2];
 580
 581                         if (value & BIT(31))
 582                                 direction = "write";
 583                         break;
 584
 585                 case MC_INT_INVALID_GART_PAGE:
 586                         reg = MC_GART_ERROR_REQ;
 587                         value = mc_readl(mc, reg);
 588
 589                         id = (value >> 1) & mc->soc->client_id_mask;
 590                         desc = error_names[2];
 591
 592                         if (value & BIT(0))
 593                                 direction = "write";
 594                         break;
 595
 596                 case MC_INT_SECURITY_VIOLATION:
 597                         reg = MC_SECURITY_VIOLATION_STATUS;
 598                         value = mc_readl(mc, reg);
 599
 600                         id = value & mc->soc->client_id_mask;
 601                         type = (value & BIT(30)) ? 4 : 3;
 602                         desc = error_names[type];
 603                         secure = "secure ";
 604
 605                         if (value & BIT(31))
 606                                 direction = "write";
 607                         break;
 608
 609                 default:
 610                         continue;
 611                 }
 612
 613                 client = mc->soc->clients[id].name;
 614                 addr = mc_readl(mc, reg + sizeof(u32));
 615
 616                 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
 617                                     client, secure, direction, &addr, error,
 618                                     desc);
 619         }
 620
 621         /* clear interrupts */
 622         mc_writel(mc, status, MC_INTSTATUS);
 623
 624         return IRQ_HANDLED;
 625 }
 626
 627 static int tegra_mc_probe(struct platform_device *pdev)
 628 {
 629         struct resource *res;
 630         struct tegra_mc *mc;
 631         void *isr;
 632         int err;
 633
 634         mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
 635         if (!mc)
 636                 return -ENOMEM;
 637
 638         platform_set_drvdata(pdev, mc);
 639         spin_lock_init(&mc->lock);
 640         mc->soc = of_device_get_match_data(&pdev->dev);
 641         mc->dev = &pdev->dev;
 642
 643         /* length of MC tick in nanoseconds */
 644         mc->tick = 30;
 645
 646         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 647         mc->regs = devm_ioremap_resource(&pdev->dev, res);
 648         if (IS_ERR(mc->regs))
 649                 return PTR_ERR(mc->regs);
 650
 651         mc->clk = devm_clk_get(&pdev->dev, "mc");
 652         if (IS_ERR(mc->clk)) {
 653                 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
 654                         PTR_ERR(mc->clk));
 655                 return PTR_ERR(mc->clk);
 656         }
 657
 658 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 659         if (mc->soc == &tegra20_mc_soc) {
 660                 isr = tegra20_mc_irq;
 661         } else
 662 #endif
 663         {
 664                 err = tegra_mc_setup_latency_allowance(mc);
 665                 if (err < 0) {
 666                         dev_err(&pdev->dev,
 667                                 "failed to setup latency allowance: %d\n",
 668                                 err);
 669                         return err;
 670                 }
 671
 672                 isr = tegra_mc_irq;
 673
 674                 err = tegra_mc_setup_timings(mc);
 675                 if (err < 0) {
 676                         dev_err(&pdev->dev, "failed to setup timings: %d\n",
 677                                 err);
 678                         return err;
 679                 }
 680         }
 681
 682         mc->irq = platform_get_irq(pdev, 0);
 683         if (mc->irq < 0) {
 684                 dev_err(&pdev->dev, "interrupt not specified\n");
 685                 return mc->irq;
 686         }
 687
 688         WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
 689
 690         mc_writel(mc, mc->soc->intmask, MC_INTMASK);
 691
 692         err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
 693                                dev_name(&pdev->dev), mc);
 694         if (err < 0) {
 695                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
 696                         err);
 697                 return err;
 698         }
 699
 700         err = tegra_mc_reset_setup(mc);
 701         if (err < 0)
 702                 dev_err(&pdev->dev, "failed to register reset controller: %d\n",
 703                         err);
 704
 705         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
 706                 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
 707                 if (IS_ERR(mc->smmu)) {
 708                         dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
 709                                 PTR_ERR(mc->smmu));
 710                         mc->smmu = NULL;
 711                 }
 712         }
 713
 714         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
 715                 mc->gart = tegra_gart_probe(&pdev->dev, mc);
 716                 if (IS_ERR(mc->gart)) {
 717                         dev_err(&pdev->dev, "failed to probe GART: %ld\n",
 718                                 PTR_ERR(mc->gart));
 719                         mc->gart = NULL;
 720                 }
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int tegra_mc_suspend(struct device *dev)
 727 {
 728         struct tegra_mc *mc = dev_get_drvdata(dev);
 729         int err;
 730
 731         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
 732                 err = tegra_gart_suspend(mc->gart);
 733                 if (err)
 734                         return err;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int tegra_mc_resume(struct device *dev)
 741 {
 742         struct tegra_mc *mc = dev_get_drvdata(dev);
 743         int err;
 744
 745         if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
 746                 err = tegra_gart_resume(mc->gart);
 747                 if (err)
 748                         return err;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static const struct dev_pm_ops tegra_mc_pm_ops = {
 755         .suspend = tegra_mc_suspend,
 756         .resume = tegra_mc_resume,
 757 };
 758
 759 static struct platform_driver tegra_mc_driver = {
 760         .driver = {
 761                 .name = "tegra-mc",
 762                 .of_match_table = tegra_mc_of_match,
 763                 .pm = &tegra_mc_pm_ops,
 764                 .suppress_bind_attrs = true,
 765         },
 766         .prevent_deferred_probe = true,
 767         .probe = tegra_mc_probe,
 768 };
 769
 770 static int tegra_mc_init(void)
 771 {
 772         return platform_driver_register(&tegra_mc_driver);
 773 }
 774 arch_initcall(tegra_mc_init);
 775
 776 MODULE_AUTHOR("Thierry Reding <[email protected]>");
 777 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
 778 MODULE_LICENSE("GPL v2");