drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53
  54 /*
  55  * Global memory.
  56  */
  57 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  58 {
  59         return ttm_mem_global_init(ref->object);
  60 }
  61
  62 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  63 {
  64         ttm_mem_global_release(ref->object);
  65 }
  66
  67 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  68 {
  69         struct drm_global_reference *global_ref;
  70         struct amdgpu_ring *ring;
  71         struct amd_sched_rq *rq;
  72         int r;
  73
  74         adev->mman.mem_global_referenced = false;
  75         global_ref = &adev->mman.mem_global_ref;
  76         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  77         global_ref->size = sizeof(struct ttm_mem_global);
  78         global_ref->init = &amdgpu_ttm_mem_global_init;
  79         global_ref->release = &amdgpu_ttm_mem_global_release;
  80         r = drm_global_item_ref(global_ref);
  81         if (r) {
  82                 DRM_ERROR("Failed setting up TTM memory accounting "
  83                           "subsystem.\n");
  84                 goto error_mem;
  85         }
  86
  87         adev->mman.bo_global_ref.mem_glob =
  88                 adev->mman.mem_global_ref.object;
  89         global_ref = &adev->mman.bo_global_ref.ref;
  90         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  91         global_ref->size = sizeof(struct ttm_bo_global);
  92         global_ref->init = &ttm_bo_global_init;
  93         global_ref->release = &ttm_bo_global_release;
  94         r = drm_global_item_ref(global_ref);
  95         if (r) {
  96                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  97                 goto error_bo;
  98         }
  99
 100         ring = adev->mman.buffer_funcs_ring;
 101         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 102         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 103                                   rq, amdgpu_sched_jobs);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 106                 goto error_entity;
 107         }
 108
 109         adev->mman.mem_global_referenced = true;
 110
 111         return 0;
 112
 113 error_entity:
 114         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 115 error_bo:
 116         drm_global_item_unref(&adev->mman.mem_global_ref);
 117 error_mem:
 118         return r;
 119 }
 120
 121 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 122 {
 123         if (adev->mman.mem_global_referenced) {
 124                 amd_sched_entity_fini(adev->mman.entity.sched,
 125                                       &adev->mman.entity);
 126                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 127                 drm_global_item_unref(&adev->mman.mem_global_ref);
 128                 adev->mman.mem_global_referenced = false;
 129         }
 130 }
 131
 132 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 133 {
 134         return 0;
 135 }
 136
 137 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 138                                 struct ttm_mem_type_manager *man)
 139 {
 140         struct amdgpu_device *adev;
 141
 142         adev = amdgpu_ttm_adev(bdev);
 143
 144         switch (type) {
 145         case TTM_PL_SYSTEM:
 146                 /* System memory */
 147                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 148                 man->available_caching = TTM_PL_MASK_CACHING;
 149                 man->default_caching = TTM_PL_FLAG_CACHED;
 150                 break;
 151         case TTM_PL_TT:
 152                 man->func = &amdgpu_gtt_mgr_func;
 153                 man->gpu_offset = adev->mc.gtt_start;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 157                 break;
 158         case TTM_PL_VRAM:
 159                 /* "On-card" video ram */
 160                 man->func = &amdgpu_vram_mgr_func;
 161                 man->gpu_offset = adev->mc.vram_start;
 162                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 163                              TTM_MEMTYPE_FLAG_MAPPABLE;
 164                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 165                 man->default_caching = TTM_PL_FLAG_WC;
 166                 break;
 167         case AMDGPU_PL_GDS:
 168         case AMDGPU_PL_GWS:
 169         case AMDGPU_PL_OA:
 170                 /* On-chip GDS memory*/
 171                 man->func = &ttm_bo_manager_func;
 172                 man->gpu_offset = 0;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 174                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 175                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 176                 break;
 177         default:
 178                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 179                 return -EINVAL;
 180         }
 181         return 0;
 182 }
 183
 184 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 185                                 struct ttm_placement *placement)
 186 {
 187         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 188         struct amdgpu_bo *abo;
 189         static struct ttm_place placements = {
 190                 .fpfn = 0,
 191                 .lpfn = 0,
 192                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 193         };
 194         unsigned i;
 195
 196         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 197                 placement->placement = &placements;
 198                 placement->busy_placement = &placements;
 199                 placement->num_placement = 1;
 200                 placement->num_busy_placement = 1;
 201                 return;
 202         }
 203         abo = container_of(bo, struct amdgpu_bo, tbo);
 204         switch (bo->mem.mem_type) {
 205         case TTM_PL_VRAM:
 206                 if (adev->mman.buffer_funcs_ring->ready == false) {
 207                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 208                 } else {
 209                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 210                         for (i = 0; i < abo->placement.num_placement; ++i) {
 211                                 if (!(abo->placements[i].flags &
 212                                       TTM_PL_FLAG_TT))
 213                                         continue;
 214
 215                                 if (abo->placements[i].lpfn)
 216                                         continue;
 217
 218                                 /* set an upper limit to force directly
 219                                  * allocating address space for the BO.
 220                                  */
 221                                 abo->placements[i].lpfn =
 222                                         adev->mc.gtt_size >> PAGE_SHIFT;
 223                         }
 224                 }
 225                 break;
 226         case TTM_PL_TT:
 227         default:
 228                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 229         }
 230         *placement = abo->placement;
 231 }
 232
 233 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 234 {
 235         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 236
 237         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 238                 return -EPERM;
 239         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 240                                           filp->private_data);
 241 }
 242
 243 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 244                              struct ttm_mem_reg *new_mem)
 245 {
 246         struct ttm_mem_reg *old_mem = &bo->mem;
 247
 248         BUG_ON(old_mem->mm_node != NULL);
 249         *old_mem = *new_mem;
 250         new_mem->mm_node = NULL;
 251 }
 252
 253 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 254                                struct drm_mm_node *mm_node,
 255                                struct ttm_mem_reg *mem,
 256                                uint64_t *addr)
 257 {
 258         int r;
 259
 260         switch (mem->mem_type) {
 261         case TTM_PL_TT:
 262                 r = amdgpu_ttm_bind(bo, mem);
 263                 if (r)
 264                         return r;
 265
 266         case TTM_PL_VRAM:
 267                 *addr = mm_node->start << PAGE_SHIFT;
 268                 *addr += bo->bdev->man[mem->mem_type].gpu_offset;
 269                 break;
 270         default:
 271                 DRM_ERROR("Unknown placement %d\n", mem->mem_type);
 272                 return -EINVAL;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 279                             bool evict, bool no_wait_gpu,
 280                             struct ttm_mem_reg *new_mem,
 281                             struct ttm_mem_reg *old_mem)
 282 {
 283         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 284         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 285
 286         struct drm_mm_node *old_mm, *new_mm;
 287         uint64_t old_start, old_size, new_start, new_size;
 288         unsigned long num_pages;
 289         struct dma_fence *fence = NULL;
 290         int r;
 291
 292         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 293
 294         if (!ring->ready) {
 295                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 296                 return -EINVAL;
 297         }
 298
 299         old_mm = old_mem->mm_node;
 300         r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start);
 301         if (r)
 302                 return r;
 303         old_size = old_mm->size;
 304
 305
 306         new_mm = new_mem->mm_node;
 307         r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start);
 308         if (r)
 309                 return r;
 310         new_size = new_mm->size;
 311
 312         num_pages = new_mem->num_pages;
 313         while (num_pages) {
 314                 unsigned long cur_pages = min(old_size, new_size);
 315                 struct dma_fence *next;
 316
 317                 r = amdgpu_copy_buffer(ring, old_start, new_start,
 318                                        cur_pages * PAGE_SIZE,
 319                                        bo->resv, &next, false);
 320                 if (r)
 321                         goto error;
 322
 323                 dma_fence_put(fence);
 324                 fence = next;
 325
 326                 num_pages -= cur_pages;
 327                 if (!num_pages)
 328                         break;
 329
 330                 old_size -= cur_pages;
 331                 if (!old_size) {
 332                         r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
 333                                                 &old_start);
 334                         if (r)
 335                                 goto error;
 336                         old_size = old_mm->size;
 337                 } else {
 338                         old_start += cur_pages * PAGE_SIZE;
 339                 }
 340
 341                 new_size -= cur_pages;
 342                 if (!new_size) {
 343                         r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
 344                                                 &new_start);
 345                         if (r)
 346                                 goto error;
 347
 348                         new_size = new_mm->size;
 349                 } else {
 350                         new_start += cur_pages * PAGE_SIZE;
 351                 }
 352         }
 353
 354         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 355         dma_fence_put(fence);
 356         return r;
 357
 358 error:
 359         if (fence)
 360                 dma_fence_wait(fence, false);
 361         dma_fence_put(fence);
 362         return r;
 363 }
 364
 365 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 366                                 bool evict, bool interruptible,
 367                                 bool no_wait_gpu,
 368                                 struct ttm_mem_reg *new_mem)
 369 {
 370         struct amdgpu_device *adev;
 371         struct ttm_mem_reg *old_mem = &bo->mem;
 372         struct ttm_mem_reg tmp_mem;
 373         struct ttm_place placements;
 374         struct ttm_placement placement;
 375         int r;
 376
 377         adev = amdgpu_ttm_adev(bo->bdev);
 378         tmp_mem = *new_mem;
 379         tmp_mem.mm_node = NULL;
 380         placement.num_placement = 1;
 381         placement.placement = &placements;
 382         placement.num_busy_placement = 1;
 383         placement.busy_placement = &placements;
 384         placements.fpfn = 0;
 385         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 386         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 387         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 388                              interruptible, no_wait_gpu);
 389         if (unlikely(r)) {
 390                 return r;
 391         }
 392
 393         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 394         if (unlikely(r)) {
 395                 goto out_cleanup;
 396         }
 397
 398         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 399         if (unlikely(r)) {
 400                 goto out_cleanup;
 401         }
 402         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 403         if (unlikely(r)) {
 404                 goto out_cleanup;
 405         }
 406         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 407 out_cleanup:
 408         ttm_bo_mem_put(bo, &tmp_mem);
 409         return r;
 410 }
 411
 412 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 413                                 bool evict, bool interruptible,
 414                                 bool no_wait_gpu,
 415                                 struct ttm_mem_reg *new_mem)
 416 {
 417         struct amdgpu_device *adev;
 418         struct ttm_mem_reg *old_mem = &bo->mem;
 419         struct ttm_mem_reg tmp_mem;
 420         struct ttm_placement placement;
 421         struct ttm_place placements;
 422         int r;
 423
 424         adev = amdgpu_ttm_adev(bo->bdev);
 425         tmp_mem = *new_mem;
 426         tmp_mem.mm_node = NULL;
 427         placement.num_placement = 1;
 428         placement.placement = &placements;
 429         placement.num_busy_placement = 1;
 430         placement.busy_placement = &placements;
 431         placements.fpfn = 0;
 432         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 433         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 434         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 435                              interruptible, no_wait_gpu);
 436         if (unlikely(r)) {
 437                 return r;
 438         }
 439         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 440         if (unlikely(r)) {
 441                 goto out_cleanup;
 442         }
 443         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 444         if (unlikely(r)) {
 445                 goto out_cleanup;
 446         }
 447 out_cleanup:
 448         ttm_bo_mem_put(bo, &tmp_mem);
 449         return r;
 450 }
 451
 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 453                         bool evict, bool interruptible,
 454                         bool no_wait_gpu,
 455                         struct ttm_mem_reg *new_mem)
 456 {
 457         struct amdgpu_device *adev;
 458         struct amdgpu_bo *abo;
 459         struct ttm_mem_reg *old_mem = &bo->mem;
 460         int r;
 461
 462         /* Can't move a pinned BO */
 463         abo = container_of(bo, struct amdgpu_bo, tbo);
 464         if (WARN_ON_ONCE(abo->pin_count > 0))
 465                 return -EINVAL;
 466
 467         adev = amdgpu_ttm_adev(bo->bdev);
 468
 469         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 470                 amdgpu_move_null(bo, new_mem);
 471                 return 0;
 472         }
 473         if ((old_mem->mem_type == TTM_PL_TT &&
 474              new_mem->mem_type == TTM_PL_SYSTEM) ||
 475             (old_mem->mem_type == TTM_PL_SYSTEM &&
 476              new_mem->mem_type == TTM_PL_TT)) {
 477                 /* bind is enough */
 478                 amdgpu_move_null(bo, new_mem);
 479                 return 0;
 480         }
 481         if (adev->mman.buffer_funcs == NULL ||
 482             adev->mman.buffer_funcs_ring == NULL ||
 483             !adev->mman.buffer_funcs_ring->ready) {
 484                 /* use memcpy */
 485                 goto memcpy;
 486         }
 487
 488         if (old_mem->mem_type == TTM_PL_VRAM &&
 489             new_mem->mem_type == TTM_PL_SYSTEM) {
 490                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 491                                         no_wait_gpu, new_mem);
 492         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 493                    new_mem->mem_type == TTM_PL_VRAM) {
 494                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 495                                             no_wait_gpu, new_mem);
 496         } else {
 497                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 498         }
 499
 500         if (r) {
 501 memcpy:
 502                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 503                 if (r) {
 504                         return r;
 505                 }
 506         }
 507
 508         /* update statistics */
 509         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 510         return 0;
 511 }
 512
 513 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 514 {
 515         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 516         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 517
 518         mem->bus.addr = NULL;
 519         mem->bus.offset = 0;
 520         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 521         mem->bus.base = 0;
 522         mem->bus.is_iomem = false;
 523         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 524                 return -EINVAL;
 525         switch (mem->mem_type) {
 526         case TTM_PL_SYSTEM:
 527                 /* system memory */
 528                 return 0;
 529         case TTM_PL_TT:
 530                 break;
 531         case TTM_PL_VRAM:
 532                 mem->bus.offset = mem->start << PAGE_SHIFT;
 533                 /* check if it's visible */
 534                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 535                         return -EINVAL;
 536                 mem->bus.base = adev->mc.aper_base;
 537                 mem->bus.is_iomem = true;
 538 #ifdef __alpha__
 539                 /*
 540                  * Alpha: use bus.addr to hold the ioremap() return,
 541                  * so we can modify bus.base below.
 542                  */
 543                 if (mem->placement & TTM_PL_FLAG_WC)
 544                         mem->bus.addr =
 545                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 546                                            mem->bus.size);
 547                 else
 548                         mem->bus.addr =
 549                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 550                                                 mem->bus.size);
 551                 if (!mem->bus.addr)
 552                         return -ENOMEM;
 553
 554                 /*
 555                  * Alpha: Use just the bus offset plus
 556                  * the hose/domain memory base for bus.base.
 557                  * It then can be used to build PTEs for VRAM
 558                  * access, as done in ttm_bo_vm_fault().
 559                  */
 560                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 561                         adev->ddev->hose->dense_mem_base;
 562 #endif
 563                 break;
 564         default:
 565                 return -EINVAL;
 566         }
 567         return 0;
 568 }
 569
 570 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 571 {
 572 }
 573
 574 /*
 575  * TTM backend functions.
 576  */
 577 struct amdgpu_ttm_gup_task_list {
 578         struct list_head        list;
 579         struct task_struct      *task;
 580 };
 581
 582 struct amdgpu_ttm_tt {
 583         struct ttm_dma_tt       ttm;
 584         struct amdgpu_device    *adev;
 585         u64                     offset;
 586         uint64_t                userptr;
 587         struct mm_struct        *usermm;
 588         uint32_t                userflags;
 589         spinlock_t              guptasklock;
 590         struct list_head        guptasks;
 591         atomic_t                mmu_invalidations;
 592         struct list_head        list;
 593 };
 594
 595 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 596 {
 597         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 598         unsigned int flags = 0;
 599         unsigned pinned = 0;
 600         int r;
 601
 602         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 603                 flags |= FOLL_WRITE;
 604
 605         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 606                 /* check that we only use anonymous memory
 607                    to prevent problems with writeback */
 608                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 609                 struct vm_area_struct *vma;
 610
 611                 vma = find_vma(gtt->usermm, gtt->userptr);
 612                 if (!vma || vma->vm_file || vma->vm_end < end)
 613                         return -EPERM;
 614         }
 615
 616         do {
 617                 unsigned num_pages = ttm->num_pages - pinned;
 618                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 619                 struct page **p = pages + pinned;
 620                 struct amdgpu_ttm_gup_task_list guptask;
 621
 622                 guptask.task = current;
 623                 spin_lock(&gtt->guptasklock);
 624                 list_add(&guptask.list, &gtt->guptasks);
 625                 spin_unlock(&gtt->guptasklock);
 626
 627                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 628
 629                 spin_lock(&gtt->guptasklock);
 630                 list_del(&guptask.list);
 631                 spin_unlock(&gtt->guptasklock);
 632
 633                 if (r < 0)
 634                         goto release_pages;
 635
 636                 pinned += r;
 637
 638         } while (pinned < ttm->num_pages);
 639
 640         return 0;
 641
 642 release_pages:
 643         release_pages(pages, pinned, 0);
 644         return r;
 645 }
 646
 647 /* prepare the sg table with the user pages */
 648 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 649 {
 650         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 651         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 652         unsigned nents;
 653         int r;
 654
 655         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 656         enum dma_data_direction direction = write ?
 657                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 658
 659         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 660                                       ttm->num_pages << PAGE_SHIFT,
 661                                       GFP_KERNEL);
 662         if (r)
 663                 goto release_sg;
 664
 665         r = -ENOMEM;
 666         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 667         if (nents != ttm->sg->nents)
 668                 goto release_sg;
 669
 670         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 671                                          gtt->ttm.dma_address, ttm->num_pages);
 672
 673         return 0;
 674
 675 release_sg:
 676         kfree(ttm->sg);
 677         return r;
 678 }
 679
 680 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 681 {
 682         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 683         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 684         struct sg_page_iter sg_iter;
 685
 686         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 687         enum dma_data_direction direction = write ?
 688                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 689
 690         /* double check that we don't free the table twice */
 691         if (!ttm->sg->sgl)
 692                 return;
 693
 694         /* free the sg table and pages again */
 695         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 696
 697         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 698                 struct page *page = sg_page_iter_page(&sg_iter);
 699                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 700                         set_page_dirty(page);
 701
 702                 mark_page_accessed(page);
 703                 put_page(page);
 704         }
 705
 706         sg_free_table(ttm->sg);
 707 }
 708
 709 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 710                                    struct ttm_mem_reg *bo_mem)
 711 {
 712         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 713         int r;
 714
 715         if (gtt->userptr) {
 716                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 717                 if (r) {
 718                         DRM_ERROR("failed to pin userptr\n");
 719                         return r;
 720                 }
 721         }
 722         if (!ttm->num_pages) {
 723                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 724                      ttm->num_pages, bo_mem, ttm);
 725         }
 726
 727         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 728             bo_mem->mem_type == AMDGPU_PL_GWS ||
 729             bo_mem->mem_type == AMDGPU_PL_OA)
 730                 return -EINVAL;
 731
 732         return 0;
 733 }
 734
 735 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 736 {
 737         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 738
 739         return gtt && !list_empty(&gtt->list);
 740 }
 741
 742 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 743 {
 744         struct ttm_tt *ttm = bo->ttm;
 745         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 746         uint32_t flags;
 747         int r;
 748
 749         if (!ttm || amdgpu_ttm_is_bound(ttm))
 750                 return 0;
 751
 752         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 753                                  NULL, bo_mem);
 754         if (r) {
 755                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 756                 return r;
 757         }
 758
 759         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 760         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 761         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 762                 ttm->pages, gtt->ttm.dma_address, flags);
 763
 764         if (r) {
 765                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 766                           ttm->num_pages, gtt->offset);
 767                 return r;
 768         }
 769         spin_lock(&gtt->adev->gtt_list_lock);
 770         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 771         spin_unlock(&gtt->adev->gtt_list_lock);
 772         return 0;
 773 }
 774
 775 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 776 {
 777         struct amdgpu_ttm_tt *gtt, *tmp;
 778         struct ttm_mem_reg bo_mem;
 779         uint32_t flags;
 780         int r;
 781
 782         bo_mem.mem_type = TTM_PL_TT;
 783         spin_lock(&adev->gtt_list_lock);
 784         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 785                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 786                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 787                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 788                                      flags);
 789                 if (r) {
 790                         spin_unlock(&adev->gtt_list_lock);
 791                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 792                                   gtt->ttm.ttm.num_pages, gtt->offset);
 793                         return r;
 794                 }
 795         }
 796         spin_unlock(&adev->gtt_list_lock);
 797         return 0;
 798 }
 799
 800 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 801 {
 802         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 803
 804         if (gtt->userptr)
 805                 amdgpu_ttm_tt_unpin_userptr(ttm);
 806
 807         if (!amdgpu_ttm_is_bound(ttm))
 808                 return 0;
 809
 810         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 811         if (gtt->adev->gart.ready)
 812                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 813
 814         spin_lock(&gtt->adev->gtt_list_lock);
 815         list_del_init(&gtt->list);
 816         spin_unlock(&gtt->adev->gtt_list_lock);
 817
 818         return 0;
 819 }
 820
 821 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 822 {
 823         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 824
 825         ttm_dma_tt_fini(&gtt->ttm);
 826         kfree(gtt);
 827 }
 828
 829 static struct ttm_backend_func amdgpu_backend_func = {
 830         .bind = &amdgpu_ttm_backend_bind,
 831         .unbind = &amdgpu_ttm_backend_unbind,
 832         .destroy = &amdgpu_ttm_backend_destroy,
 833 };
 834
 835 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 836                                     unsigned long size, uint32_t page_flags,
 837                                     struct page *dummy_read_page)
 838 {
 839         struct amdgpu_device *adev;
 840         struct amdgpu_ttm_tt *gtt;
 841
 842         adev = amdgpu_ttm_adev(bdev);
 843
 844         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 845         if (gtt == NULL) {
 846                 return NULL;
 847         }
 848         gtt->ttm.ttm.func = &amdgpu_backend_func;
 849         gtt->adev = adev;
 850         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 851                 kfree(gtt);
 852                 return NULL;
 853         }
 854         INIT_LIST_HEAD(&gtt->list);
 855         return &gtt->ttm.ttm;
 856 }
 857
 858 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 859 {
 860         struct amdgpu_device *adev;
 861         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 862         unsigned i;
 863         int r;
 864         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 865
 866         if (ttm->state != tt_unpopulated)
 867                 return 0;
 868
 869         if (gtt && gtt->userptr) {
 870                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 871                 if (!ttm->sg)
 872                         return -ENOMEM;
 873
 874                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 875                 ttm->state = tt_unbound;
 876                 return 0;
 877         }
 878
 879         if (slave && ttm->sg) {
 880                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 881                                                  gtt->ttm.dma_address, ttm->num_pages);
 882                 ttm->state = tt_unbound;
 883                 return 0;
 884         }
 885
 886         adev = amdgpu_ttm_adev(ttm->bdev);
 887
 888 #ifdef CONFIG_SWIOTLB
 889         if (swiotlb_nr_tbl()) {
 890                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 891         }
 892 #endif
 893
 894         r = ttm_pool_populate(ttm);
 895         if (r) {
 896                 return r;
 897         }
 898
 899         for (i = 0; i < ttm->num_pages; i++) {
 900                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 901                                                        0, PAGE_SIZE,
 902                                                        PCI_DMA_BIDIRECTIONAL);
 903                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 904                         while (i--) {
 905                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 906                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 907                                 gtt->ttm.dma_address[i] = 0;
 908                         }
 909                         ttm_pool_unpopulate(ttm);
 910                         return -EFAULT;
 911                 }
 912         }
 913         return 0;
 914 }
 915
 916 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 917 {
 918         struct amdgpu_device *adev;
 919         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 920         unsigned i;
 921         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 922
 923         if (gtt && gtt->userptr) {
 924                 kfree(ttm->sg);
 925                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 926                 return;
 927         }
 928
 929         if (slave)
 930                 return;
 931
 932         adev = amdgpu_ttm_adev(ttm->bdev);
 933
 934 #ifdef CONFIG_SWIOTLB
 935         if (swiotlb_nr_tbl()) {
 936                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 937                 return;
 938         }
 939 #endif
 940
 941         for (i = 0; i < ttm->num_pages; i++) {
 942                 if (gtt->ttm.dma_address[i]) {
 943                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 944                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 945                 }
 946         }
 947
 948         ttm_pool_unpopulate(ttm);
 949 }
 950
 951 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 952                               uint32_t flags)
 953 {
 954         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 955
 956         if (gtt == NULL)
 957                 return -EINVAL;
 958
 959         gtt->userptr = addr;
 960         gtt->usermm = current->mm;
 961         gtt->userflags = flags;
 962         spin_lock_init(&gtt->guptasklock);
 963         INIT_LIST_HEAD(&gtt->guptasks);
 964         atomic_set(&gtt->mmu_invalidations, 0);
 965
 966         return 0;
 967 }
 968
 969 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 970 {
 971         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 972
 973         if (gtt == NULL)
 974                 return NULL;
 975
 976         return gtt->usermm;
 977 }
 978
 979 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 980                                   unsigned long end)
 981 {
 982         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 983         struct amdgpu_ttm_gup_task_list *entry;
 984         unsigned long size;
 985
 986         if (gtt == NULL || !gtt->userptr)
 987                 return false;
 988
 989         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 990         if (gtt->userptr > end || gtt->userptr + size <= start)
 991                 return false;
 992
 993         spin_lock(&gtt->guptasklock);
 994         list_for_each_entry(entry, &gtt->guptasks, list) {
 995                 if (entry->task == current) {
 996                         spin_unlock(&gtt->guptasklock);
 997                         return false;
 998                 }
 999         }
1000         spin_unlock(&gtt->guptasklock);
1001
1002         atomic_inc(&gtt->mmu_invalidations);
1003
1004         return true;
1005 }
1006
1007 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1008                                        int *last_invalidated)
1009 {
1010         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1011         int prev_invalidated = *last_invalidated;
1012
1013         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1014         return prev_invalidated != *last_invalidated;
1015 }
1016
1017 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1018 {
1019         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1020
1021         if (gtt == NULL)
1022                 return false;
1023
1024         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1025 }
1026
1027 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1028                                  struct ttm_mem_reg *mem)
1029 {
1030         uint32_t flags = 0;
1031
1032         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1033                 flags |= AMDGPU_PTE_VALID;
1034
1035         if (mem && mem->mem_type == TTM_PL_TT) {
1036                 flags |= AMDGPU_PTE_SYSTEM;
1037
1038                 if (ttm->caching_state == tt_cached)
1039                         flags |= AMDGPU_PTE_SNOOPED;
1040         }
1041
1042         if (adev->asic_type >= CHIP_TONGA)
1043                 flags |= AMDGPU_PTE_EXECUTABLE;
1044
1045         flags |= AMDGPU_PTE_READABLE;
1046
1047         if (!amdgpu_ttm_tt_is_readonly(ttm))
1048                 flags |= AMDGPU_PTE_WRITEABLE;
1049
1050         return flags;
1051 }
1052
1053 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1054                                             const struct ttm_place *place)
1055 {
1056         if (bo->mem.mem_type == TTM_PL_VRAM &&
1057             bo->mem.start == AMDGPU_BO_INVALID_OFFSET) {
1058                 unsigned long num_pages = bo->mem.num_pages;
1059                 struct drm_mm_node *node = bo->mem.mm_node;
1060
1061                 /* Check each drm MM node individually */
1062                 while (num_pages) {
1063                         if (place->fpfn < (node->start + node->size) &&
1064                             !(place->lpfn && place->lpfn <= node->start))
1065                                 return true;
1066
1067                         num_pages -= node->size;
1068                         ++node;
1069                 }
1070
1071                 return false;
1072         }
1073
1074         return ttm_bo_eviction_valuable(bo, place);
1075 }
1076
1077 static struct ttm_bo_driver amdgpu_bo_driver = {
1078         .ttm_tt_create = &amdgpu_ttm_tt_create,
1079         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1080         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1081         .invalidate_caches = &amdgpu_invalidate_caches,
1082         .init_mem_type = &amdgpu_init_mem_type,
1083         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1084         .evict_flags = &amdgpu_evict_flags,
1085         .move = &amdgpu_bo_move,
1086         .verify_access = &amdgpu_verify_access,
1087         .move_notify = &amdgpu_bo_move_notify,
1088         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1089         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1090         .io_mem_free = &amdgpu_ttm_io_mem_free,
1091 };
1092
1093 int amdgpu_ttm_init(struct amdgpu_device *adev)
1094 {
1095         int r;
1096
1097         r = amdgpu_ttm_global_init(adev);
1098         if (r) {
1099                 return r;
1100         }
1101         /* No others user of address space so set it to 0 */
1102         r = ttm_bo_device_init(&adev->mman.bdev,
1103                                adev->mman.bo_global_ref.ref.object,
1104                                &amdgpu_bo_driver,
1105                                adev->ddev->anon_inode->i_mapping,
1106                                DRM_FILE_PAGE_OFFSET,
1107                                adev->need_dma32);
1108         if (r) {
1109                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1110                 return r;
1111         }
1112         adev->mman.initialized = true;
1113         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1114                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1115         if (r) {
1116                 DRM_ERROR("Failed initializing VRAM heap.\n");
1117                 return r;
1118         }
1119         /* Change the size here instead of the init above so only lpfn is affected */
1120         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1121
1122         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1123                              AMDGPU_GEM_DOMAIN_VRAM,
1124                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1125                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1126                              NULL, NULL, &adev->stollen_vga_memory);
1127         if (r) {
1128                 return r;
1129         }
1130         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1131         if (r)
1132                 return r;
1133         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1134         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1135         if (r) {
1136                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1137                 return r;
1138         }
1139         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1140                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1141         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1142                                 adev->mc.gtt_size >> PAGE_SHIFT);
1143         if (r) {
1144                 DRM_ERROR("Failed initializing GTT heap.\n");
1145                 return r;
1146         }
1147         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1148                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1149
1150         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1151         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1152         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1153         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1154         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1155         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1156         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1157         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1158         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1159         /* GDS Memory */
1160         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1161                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1162         if (r) {
1163                 DRM_ERROR("Failed initializing GDS heap.\n");
1164                 return r;
1165         }
1166
1167         /* GWS */
1168         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1169                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1170         if (r) {
1171                 DRM_ERROR("Failed initializing gws heap.\n");
1172                 return r;
1173         }
1174
1175         /* OA */
1176         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1177                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1178         if (r) {
1179                 DRM_ERROR("Failed initializing oa heap.\n");
1180                 return r;
1181         }
1182
1183         r = amdgpu_ttm_debugfs_init(adev);
1184         if (r) {
1185                 DRM_ERROR("Failed to init debugfs\n");
1186                 return r;
1187         }
1188         return 0;
1189 }
1190
1191 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1192 {
1193         int r;
1194
1195         if (!adev->mman.initialized)
1196                 return;
1197         amdgpu_ttm_debugfs_fini(adev);
1198         if (adev->stollen_vga_memory) {
1199                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1200                 if (r == 0) {
1201                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1202                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1203                 }
1204                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1205         }
1206         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1207         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1208         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1209         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1210         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1211         ttm_bo_device_release(&adev->mman.bdev);
1212         amdgpu_gart_fini(adev);
1213         amdgpu_ttm_global_fini(adev);
1214         adev->mman.initialized = false;
1215         DRM_INFO("amdgpu: ttm finalized\n");
1216 }
1217
1218 /* this should only be called at bootup or when userspace
1219  * isn't running */
1220 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1221 {
1222         struct ttm_mem_type_manager *man;
1223
1224         if (!adev->mman.initialized)
1225                 return;
1226
1227         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1228         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1229         man->size = size >> PAGE_SHIFT;
1230 }
1231
1232 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1233 {
1234         struct drm_file *file_priv;
1235         struct amdgpu_device *adev;
1236
1237         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1238                 return -EINVAL;
1239
1240         file_priv = filp->private_data;
1241         adev = file_priv->minor->dev->dev_private;
1242         if (adev == NULL)
1243                 return -EINVAL;
1244
1245         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1246 }
1247
1248 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1249                        uint64_t src_offset,
1250                        uint64_t dst_offset,
1251                        uint32_t byte_count,
1252                        struct reservation_object *resv,
1253                        struct dma_fence **fence, bool direct_submit)
1254 {
1255         struct amdgpu_device *adev = ring->adev;
1256         struct amdgpu_job *job;
1257
1258         uint32_t max_bytes;
1259         unsigned num_loops, num_dw;
1260         unsigned i;
1261         int r;
1262
1263         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1264         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1265         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1266
1267         /* for IB padding */
1268         while (num_dw & 0x7)
1269                 num_dw++;
1270
1271         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1272         if (r)
1273                 return r;
1274
1275         if (resv) {
1276                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1277                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1278                 if (r) {
1279                         DRM_ERROR("sync failed (%d).\n", r);
1280                         goto error_free;
1281                 }
1282         }
1283
1284         for (i = 0; i < num_loops; i++) {
1285                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1286
1287                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1288                                         dst_offset, cur_size_in_bytes);
1289
1290                 src_offset += cur_size_in_bytes;
1291                 dst_offset += cur_size_in_bytes;
1292                 byte_count -= cur_size_in_bytes;
1293         }
1294
1295         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1296         WARN_ON(job->ibs[0].length_dw > num_dw);
1297         if (direct_submit) {
1298                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1299                                        NULL, fence);
1300                 job->fence = dma_fence_get(*fence);
1301                 if (r)
1302                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1303                 amdgpu_job_free(job);
1304         } else {
1305                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1306                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1307                 if (r)
1308                         goto error_free;
1309         }
1310
1311         return r;
1312
1313 error_free:
1314         amdgpu_job_free(job);
1315         return r;
1316 }
1317
1318 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1319                        uint32_t src_data,
1320                        struct reservation_object *resv,
1321                        struct dma_fence **fence)
1322 {
1323         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1324         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1325         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1326
1327         struct drm_mm_node *mm_node;
1328         unsigned long num_pages;
1329         unsigned int num_loops, num_dw;
1330
1331         struct amdgpu_job *job;
1332         int r;
1333
1334         if (!ring->ready) {
1335                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1336                 return -EINVAL;
1337         }
1338
1339         num_pages = bo->tbo.num_pages;
1340         mm_node = bo->tbo.mem.mm_node;
1341         num_loops = 0;
1342         while (num_pages) {
1343                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1344
1345                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1346                 num_pages -= mm_node->size;
1347                 ++mm_node;
1348         }
1349         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1350
1351         /* for IB padding */
1352         num_dw += 64;
1353
1354         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1355         if (r)
1356                 return r;
1357
1358         if (resv) {
1359                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1360                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1361                 if (r) {
1362                         DRM_ERROR("sync failed (%d).\n", r);
1363                         goto error_free;
1364                 }
1365         }
1366
1367         num_pages = bo->tbo.num_pages;
1368         mm_node = bo->tbo.mem.mm_node;
1369
1370         while (num_pages) {
1371                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1372                 uint64_t dst_addr;
1373
1374                 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1375                                         &bo->tbo.mem, &dst_addr);
1376                 if (r)
1377                         return r;
1378
1379                 while (byte_count) {
1380                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1381
1382                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1383                                                 dst_addr, cur_size_in_bytes);
1384
1385                         dst_addr += cur_size_in_bytes;
1386                         byte_count -= cur_size_in_bytes;
1387                 }
1388
1389                 num_pages -= mm_node->size;
1390                 ++mm_node;
1391         }
1392
1393         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1394         WARN_ON(job->ibs[0].length_dw > num_dw);
1395         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1396                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1397         if (r)
1398                 goto error_free;
1399
1400         return 0;
1401
1402 error_free:
1403         amdgpu_job_free(job);
1404         return r;
1405 }
1406
1407 #if defined(CONFIG_DEBUG_FS)
1408
1409 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1410 {
1411         struct drm_info_node *node = (struct drm_info_node *)m->private;
1412         unsigned ttm_pl = *(int *)node->info_ent->data;
1413         struct drm_device *dev = node->minor->dev;
1414         struct amdgpu_device *adev = dev->dev_private;
1415         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1416         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1417         struct drm_printer p = drm_seq_file_printer(m);
1418
1419         spin_lock(&glob->lru_lock);
1420         drm_mm_print(mm, &p);
1421         spin_unlock(&glob->lru_lock);
1422         if (ttm_pl == TTM_PL_VRAM)
1423                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1424                            adev->mman.bdev.man[ttm_pl].size,
1425                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1426                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1427         return 0;
1428 }
1429
1430 static int ttm_pl_vram = TTM_PL_VRAM;
1431 static int ttm_pl_tt = TTM_PL_TT;
1432
1433 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1434         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1435         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1436         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1437 #ifdef CONFIG_SWIOTLB
1438         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1439 #endif
1440 };
1441
1442 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1443                                     size_t size, loff_t *pos)
1444 {
1445         struct amdgpu_device *adev = file_inode(f)->i_private;
1446         ssize_t result = 0;
1447         int r;
1448
1449         if (size & 0x3 || *pos & 0x3)
1450                 return -EINVAL;
1451
1452         while (size) {
1453                 unsigned long flags;
1454                 uint32_t value;
1455
1456                 if (*pos >= adev->mc.mc_vram_size)
1457                         return result;
1458
1459                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1460                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1461                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1462                 value = RREG32(mmMM_DATA);
1463                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1464
1465                 r = put_user(value, (uint32_t *)buf);
1466                 if (r)
1467                         return r;
1468
1469                 result += 4;
1470                 buf += 4;
1471                 *pos += 4;
1472                 size -= 4;
1473         }
1474
1475         return result;
1476 }
1477
1478 static const struct file_operations amdgpu_ttm_vram_fops = {
1479         .owner = THIS_MODULE,
1480         .read = amdgpu_ttm_vram_read,
1481         .llseek = default_llseek
1482 };
1483
1484 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1485
1486 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1487                                    size_t size, loff_t *pos)
1488 {
1489         struct amdgpu_device *adev = file_inode(f)->i_private;
1490         ssize_t result = 0;
1491         int r;
1492
1493         while (size) {
1494                 loff_t p = *pos / PAGE_SIZE;
1495                 unsigned off = *pos & ~PAGE_MASK;
1496                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1497                 struct page *page;
1498                 void *ptr;
1499
1500                 if (p >= adev->gart.num_cpu_pages)
1501                         return result;
1502
1503                 page = adev->gart.pages[p];
1504                 if (page) {
1505                         ptr = kmap(page);
1506                         ptr += off;
1507
1508                         r = copy_to_user(buf, ptr, cur_size);
1509                         kunmap(adev->gart.pages[p]);
1510                 } else
1511                         r = clear_user(buf, cur_size);
1512
1513                 if (r)
1514                         return -EFAULT;
1515
1516                 result += cur_size;
1517                 buf += cur_size;
1518                 *pos += cur_size;
1519                 size -= cur_size;
1520         }
1521
1522         return result;
1523 }
1524
1525 static const struct file_operations amdgpu_ttm_gtt_fops = {
1526         .owner = THIS_MODULE,
1527         .read = amdgpu_ttm_gtt_read,
1528         .llseek = default_llseek
1529 };
1530
1531 #endif
1532
1533 #endif
1534
1535 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1536 {
1537 #if defined(CONFIG_DEBUG_FS)
1538         unsigned count;
1539
1540         struct drm_minor *minor = adev->ddev->primary;
1541         struct dentry *ent, *root = minor->debugfs_root;
1542
1543         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1544                                   adev, &amdgpu_ttm_vram_fops);
1545         if (IS_ERR(ent))
1546                 return PTR_ERR(ent);
1547         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1548         adev->mman.vram = ent;
1549
1550 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1551         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1552                                   adev, &amdgpu_ttm_gtt_fops);
1553         if (IS_ERR(ent))
1554                 return PTR_ERR(ent);
1555         i_size_write(ent->d_inode, adev->mc.gtt_size);
1556         adev->mman.gtt = ent;
1557
1558 #endif
1559         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1560
1561 #ifdef CONFIG_SWIOTLB
1562         if (!swiotlb_nr_tbl())
1563                 --count;
1564 #endif
1565
1566         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1567 #else
1568
1569         return 0;
1570 #endif
1571 }
1572
1573 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1574 {
1575 #if defined(CONFIG_DEBUG_FS)
1576
1577         debugfs_remove(adev->mman.vram);
1578         adev->mman.vram = NULL;
1579
1580 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1581         debugfs_remove(adev->mman.gtt);
1582         adev->mman.gtt = NULL;
1583 #endif
1584
1585 #endif
1586 }