drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  50 {
  51         return INTEL_GEN(dev_priv) <= 3;
  52 }
  53
  54 /*
  55  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  56  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  57  * origin so the x and y offsets can actually fit the registers. As a
  58  * consequence, the fence doesn't really start exactly at the display plane
  59  * address we program because it starts at the real start of the buffer, so we
  60  * have to take this into consideration here.
  61  */
  62 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  63 {
  64         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  65 }
  66
  67 /*
  68  * For SKL+, the plane source size used by the hardware is based on the value we
  69  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  70  * we wrote to PIPESRC.
  71  */
  72 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  73                                             int *width, int *height)
  74 {
  75         if (width)
  76                 *width = cache->plane.src_w;
  77         if (height)
  78                 *height = cache->plane.src_h;
  79 }
  80
  81 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  82                                         struct intel_fbc_state_cache *cache)
  83 {
  84         int lines;
  85
  86         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  87         if (INTEL_GEN(dev_priv) == 7)
  88                 lines = min(lines, 2048);
  89         else if (INTEL_GEN(dev_priv) >= 8)
  90                 lines = min(lines, 2560);
  91
  92         /* Hardware needs the full buffer stride, not just the active area. */
  93         return lines * cache->fb.stride;
  94 }
  95
  96 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  97 {
  98         u32 fbc_ctl;
  99
 100         /* Disable compression */
 101         fbc_ctl = I915_READ(FBC_CONTROL);
 102         if ((fbc_ctl & FBC_CTL_EN) == 0)
 103                 return;
 104
 105         fbc_ctl &= ~FBC_CTL_EN;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         /* Wait for compressing bit to clear */
 109         if (intel_wait_for_register(dev_priv,
 110                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 111                                     10)) {
 112                 DRM_DEBUG_KMS("FBC idle timed out\n");
 113                 return;
 114         }
 115 }
 116
 117 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 118 {
 119         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 120         int cfb_pitch;
 121         int i;
 122         u32 fbc_ctl;
 123
 124         /* Note: fbc.threshold == 1 for i8xx */
 125         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 126         if (params->fb.stride < cfb_pitch)
 127                 cfb_pitch = params->fb.stride;
 128
 129         /* FBC_CTL wants 32B or 64B units */
 130         if (IS_GEN2(dev_priv))
 131                 cfb_pitch = (cfb_pitch / 32) - 1;
 132         else
 133                 cfb_pitch = (cfb_pitch / 64) - 1;
 134
 135         /* Clear old tags */
 136         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 137                 I915_WRITE(FBC_TAG(i), 0);
 138
 139         if (IS_GEN4(dev_priv)) {
 140                 u32 fbc_ctl2;
 141
 142                 /* Set it up... */
 143                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 144                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 145                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 146                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 147         }
 148
 149         /* enable it... */
 150         fbc_ctl = I915_READ(FBC_CONTROL);
 151         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 152         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 153         if (IS_I945GM(dev_priv))
 154                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 155         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 156         fbc_ctl |= params->vma->fence->id;
 157         I915_WRITE(FBC_CONTROL, fbc_ctl);
 158 }
 159
 160 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 161 {
 162         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 163 }
 164
 165 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 166 {
 167         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 168         u32 dpfc_ctl;
 169
 170         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 171         if (params->fb.format->cpp[0] == 2)
 172                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 173         else
 174                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 175
 176         if (params->flags & PLANE_HAS_FENCE) {
 177                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 178                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 179         } else {
 180                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 181         }
 182
 183         /* enable it... */
 184         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 185 }
 186
 187 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 188 {
 189         u32 dpfc_ctl;
 190
 191         /* Disable compression */
 192         dpfc_ctl = I915_READ(DPFC_CONTROL);
 193         if (dpfc_ctl & DPFC_CTL_EN) {
 194                 dpfc_ctl &= ~DPFC_CTL_EN;
 195                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 196         }
 197 }
 198
 199 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 200 {
 201         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 202 }
 203
 204 /* This function forces a CFB recompression through the nuke operation. */
 205 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 206 {
 207         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 208         POSTING_READ(MSG_FBC_REND_STATE);
 209 }
 210
 211 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 212 {
 213         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 214         u32 dpfc_ctl;
 215         int threshold = dev_priv->fbc.threshold;
 216
 217         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 218         if (params->fb.format->cpp[0] == 2)
 219                 threshold++;
 220
 221         switch (threshold) {
 222         case 4:
 223         case 3:
 224                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 225                 break;
 226         case 2:
 227                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 228                 break;
 229         case 1:
 230                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 231                 break;
 232         }
 233
 234         if (params->flags & PLANE_HAS_FENCE) {
 235                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236                 if (IS_GEN5(dev_priv))
 237                         dpfc_ctl |= params->vma->fence->id;
 238                 if (IS_GEN6(dev_priv)) {
 239                         I915_WRITE(SNB_DPFC_CTL_SA,
 240                                    SNB_CPU_FENCE_ENABLE |
 241                                    params->vma->fence->id);
 242                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 243                                    params->crtc.fence_y_offset);
 244                 }
 245         } else {
 246                 if (IS_GEN6(dev_priv)) {
 247                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 248                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 249                 }
 250         }
 251
 252         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 253         I915_WRITE(ILK_FBC_RT_BASE,
 254                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 255         /* enable it... */
 256         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 257
 258         intel_fbc_recompress(dev_priv);
 259 }
 260
 261 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 262 {
 263         u32 dpfc_ctl;
 264
 265         /* Disable compression */
 266         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 267         if (dpfc_ctl & DPFC_CTL_EN) {
 268                 dpfc_ctl &= ~DPFC_CTL_EN;
 269                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 270         }
 271 }
 272
 273 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 274 {
 275         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 276 }
 277
 278 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 279 {
 280         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 281         u32 dpfc_ctl;
 282         int threshold = dev_priv->fbc.threshold;
 283
 284         /* Display WA #0529: skl, kbl, bxt. */
 285         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
 286                 u32 val = I915_READ(CHICKEN_MISC_4);
 287
 288                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 289
 290                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 291                     I915_TILING_X)
 292                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 293
 294                 I915_WRITE(CHICKEN_MISC_4, val);
 295         }
 296
 297         dpfc_ctl = 0;
 298         if (IS_IVYBRIDGE(dev_priv))
 299                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 300
 301         if (params->fb.format->cpp[0] == 2)
 302                 threshold++;
 303
 304         switch (threshold) {
 305         case 4:
 306         case 3:
 307                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 308                 break;
 309         case 2:
 310                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 311                 break;
 312         case 1:
 313                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 314                 break;
 315         }
 316
 317         if (params->flags & PLANE_HAS_FENCE) {
 318                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 319                 I915_WRITE(SNB_DPFC_CTL_SA,
 320                            SNB_CPU_FENCE_ENABLE |
 321                            params->vma->fence->id);
 322                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 323         } else {
 324                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 325                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 326         }
 327
 328         if (dev_priv->fbc.false_color)
 329                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 330
 331         if (IS_IVYBRIDGE(dev_priv)) {
 332                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 333                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 334                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 335                            ILK_FBCQ_DIS);
 336         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 337                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 338                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 339                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 340                            HSW_FBCQ_DIS);
 341         }
 342
 343         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 344
 345         intel_fbc_recompress(dev_priv);
 346 }
 347
 348 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 349 {
 350         if (INTEL_GEN(dev_priv) >= 5)
 351                 return ilk_fbc_is_active(dev_priv);
 352         else if (IS_GM45(dev_priv))
 353                 return g4x_fbc_is_active(dev_priv);
 354         else
 355                 return i8xx_fbc_is_active(dev_priv);
 356 }
 357
 358 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 359 {
 360         struct intel_fbc *fbc = &dev_priv->fbc;
 361
 362         fbc->active = true;
 363
 364         if (INTEL_GEN(dev_priv) >= 7)
 365                 gen7_fbc_activate(dev_priv);
 366         else if (INTEL_GEN(dev_priv) >= 5)
 367                 ilk_fbc_activate(dev_priv);
 368         else if (IS_GM45(dev_priv))
 369                 g4x_fbc_activate(dev_priv);
 370         else
 371                 i8xx_fbc_activate(dev_priv);
 372 }
 373
 374 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 375 {
 376         struct intel_fbc *fbc = &dev_priv->fbc;
 377
 378         fbc->active = false;
 379
 380         if (INTEL_GEN(dev_priv) >= 5)
 381                 ilk_fbc_deactivate(dev_priv);
 382         else if (IS_GM45(dev_priv))
 383                 g4x_fbc_deactivate(dev_priv);
 384         else
 385                 i8xx_fbc_deactivate(dev_priv);
 386 }
 387
 388 /**
 389  * intel_fbc_is_active - Is FBC active?
 390  * @dev_priv: i915 device instance
 391  *
 392  * This function is used to verify the current state of FBC.
 393  *
 394  * FIXME: This should be tracked in the plane config eventually
 395  * instead of queried at runtime for most callers.
 396  */
 397 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 398 {
 399         return dev_priv->fbc.active;
 400 }
 401
 402 static void intel_fbc_work_fn(struct work_struct *__work)
 403 {
 404         struct drm_i915_private *dev_priv =
 405                 container_of(__work, struct drm_i915_private, fbc.work.work);
 406         struct intel_fbc *fbc = &dev_priv->fbc;
 407         struct intel_fbc_work *work = &fbc->work;
 408         struct intel_crtc *crtc = fbc->crtc;
 409         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 410
 411         if (drm_crtc_vblank_get(&crtc->base)) {
 412                 /* CRTC is now off, leave FBC deactivated */
 413                 mutex_lock(&fbc->lock);
 414                 work->scheduled = false;
 415                 mutex_unlock(&fbc->lock);
 416                 return;
 417         }
 418
 419 retry:
 420         /* Delay the actual enabling to let pageflipping cease and the
 421          * display to settle before starting the compression. Note that
 422          * this delay also serves a second purpose: it allows for a
 423          * vblank to pass after disabling the FBC before we attempt
 424          * to modify the control registers.
 425          *
 426          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 427          *
 428          * It is also worth mentioning that since work->scheduled_vblank can be
 429          * updated multiple times by the other threads, hitting the timeout is
 430          * not an error condition. We'll just end up hitting the "goto retry"
 431          * case below.
 432          */
 433         wait_event_timeout(vblank->queue,
 434                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 435                 msecs_to_jiffies(50));
 436
 437         mutex_lock(&fbc->lock);
 438
 439         /* Were we cancelled? */
 440         if (!work->scheduled)
 441                 goto out;
 442
 443         /* Were we delayed again while this function was sleeping? */
 444         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 445                 mutex_unlock(&fbc->lock);
 446                 goto retry;
 447         }
 448
 449         intel_fbc_hw_activate(dev_priv);
 450
 451         work->scheduled = false;
 452
 453 out:
 454         mutex_unlock(&fbc->lock);
 455         drm_crtc_vblank_put(&crtc->base);
 456 }
 457
 458 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 459 {
 460         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 461         struct intel_fbc *fbc = &dev_priv->fbc;
 462         struct intel_fbc_work *work = &fbc->work;
 463
 464         WARN_ON(!mutex_is_locked(&fbc->lock));
 465         if (WARN_ON(!fbc->enabled))
 466                 return;
 467
 468         if (drm_crtc_vblank_get(&crtc->base)) {
 469                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 470                           pipe_name(crtc->pipe));
 471                 return;
 472         }
 473
 474         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 475          * this function since we're not releasing fbc.lock, so it won't have an
 476          * opportunity to grab it to discover that it was cancelled. So we just
 477          * update the expected jiffy count. */
 478         work->scheduled = true;
 479         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 480         drm_crtc_vblank_put(&crtc->base);
 481
 482         schedule_work(&work->work);
 483 }
 484
 485 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 486                                  const char *reason)
 487 {
 488         struct intel_fbc *fbc = &dev_priv->fbc;
 489
 490         WARN_ON(!mutex_is_locked(&fbc->lock));
 491
 492         /* Calling cancel_work() here won't help due to the fact that the work
 493          * function grabs fbc->lock. Just set scheduled to false so the work
 494          * function can know it was cancelled. */
 495         fbc->work.scheduled = false;
 496
 497         if (fbc->active)
 498                 intel_fbc_hw_deactivate(dev_priv);
 499
 500         fbc->no_fbc_reason = reason;
 501 }
 502
 503 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 504                               struct intel_plane_state *plane_state)
 505 {
 506         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 507         struct intel_fbc *fbc = &dev_priv->fbc;
 508         enum pipe pipe = crtc->pipe;
 509
 510         /* Don't even bother tracking anything we don't need. */
 511         if (!no_fbc_on_multiple_pipes(dev_priv))
 512                 return true;
 513
 514         if (plane_state->base.visible)
 515                 fbc->visible_pipes_mask |= (1 << pipe);
 516         else
 517                 fbc->visible_pipes_mask &= ~(1 << pipe);
 518
 519         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 520 }
 521
 522 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 523                                       struct drm_mm_node *node,
 524                                       int size,
 525                                       int fb_cpp)
 526 {
 527         int compression_threshold = 1;
 528         int ret;
 529         u64 end;
 530
 531         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 532          * reserved range size, so it always assumes the maximum (8mb) is used.
 533          * If we enable FBC using a CFB on that memory range we'll get FIFO
 534          * underruns, even if that range is not reserved by the BIOS. */
 535         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 536                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 537         else
 538                 end = U64_MAX;
 539
 540         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 541          * code changes, this code needs to change as well.
 542          *
 543          * The enable_fbc code will attempt to use one of our 2 compression
 544          * thresholds, therefore, in that case, we only have 1 resort.
 545          */
 546
 547         /* Try to over-allocate to reduce reallocations and fragmentation. */
 548         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 549                                                    4096, 0, end);
 550         if (ret == 0)
 551                 return compression_threshold;
 552
 553 again:
 554         /* HW's ability to limit the CFB is 1:4 */
 555         if (compression_threshold > 4 ||
 556             (fb_cpp == 2 && compression_threshold == 2))
 557                 return 0;
 558
 559         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 560                                                    4096, 0, end);
 561         if (ret && INTEL_GEN(dev_priv) <= 4) {
 562                 return 0;
 563         } else if (ret) {
 564                 compression_threshold <<= 1;
 565                 goto again;
 566         } else {
 567                 return compression_threshold;
 568         }
 569 }
 570
 571 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 572 {
 573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 574         struct intel_fbc *fbc = &dev_priv->fbc;
 575         struct drm_mm_node *uninitialized_var(compressed_llb);
 576         int size, fb_cpp, ret;
 577
 578         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 579
 580         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 581         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 582
 583         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 584                                          size, fb_cpp);
 585         if (!ret)
 586                 goto err_llb;
 587         else if (ret > 1) {
 588                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 589
 590         }
 591
 592         fbc->threshold = ret;
 593
 594         if (INTEL_GEN(dev_priv) >= 5)
 595                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 596         else if (IS_GM45(dev_priv)) {
 597                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 598         } else {
 599                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 600                 if (!compressed_llb)
 601                         goto err_fb;
 602
 603                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 604                                                   4096, 4096);
 605                 if (ret)
 606                         goto err_fb;
 607
 608                 fbc->compressed_llb = compressed_llb;
 609
 610                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 611                                              fbc->compressed_fb.start,
 612                                              U32_MAX));
 613                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 614                                              fbc->compressed_llb->start,
 615                                              U32_MAX));
 616                 I915_WRITE(FBC_CFB_BASE,
 617                            dev_priv->dsm.start + fbc->compressed_fb.start);
 618                 I915_WRITE(FBC_LL_BASE,
 619                            dev_priv->dsm.start + compressed_llb->start);
 620         }
 621
 622         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 623                       fbc->compressed_fb.size, fbc->threshold);
 624
 625         return 0;
 626
 627 err_fb:
 628         kfree(compressed_llb);
 629         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 630 err_llb:
 631         if (drm_mm_initialized(&dev_priv->mm.stolen))
 632                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 633         return -ENOSPC;
 634 }
 635
 636 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 637 {
 638         struct intel_fbc *fbc = &dev_priv->fbc;
 639
 640         if (drm_mm_node_allocated(&fbc->compressed_fb))
 641                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 642
 643         if (fbc->compressed_llb) {
 644                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 645                 kfree(fbc->compressed_llb);
 646         }
 647 }
 648
 649 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 650 {
 651         struct intel_fbc *fbc = &dev_priv->fbc;
 652
 653         if (!fbc_supported(dev_priv))
 654                 return;
 655
 656         mutex_lock(&fbc->lock);
 657         __intel_fbc_cleanup_cfb(dev_priv);
 658         mutex_unlock(&fbc->lock);
 659 }
 660
 661 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 662                             unsigned int stride)
 663 {
 664         /* This should have been caught earlier. */
 665         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 666                 return false;
 667
 668         /* Below are the additional FBC restrictions. */
 669         if (stride < 512)
 670                 return false;
 671
 672         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 673                 return stride == 4096 || stride == 8192;
 674
 675         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 676                 return false;
 677
 678         if (stride > 16384)
 679                 return false;
 680
 681         return true;
 682 }
 683
 684 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 685                                   uint32_t pixel_format)
 686 {
 687         switch (pixel_format) {
 688         case DRM_FORMAT_XRGB8888:
 689         case DRM_FORMAT_XBGR8888:
 690                 return true;
 691         case DRM_FORMAT_XRGB1555:
 692         case DRM_FORMAT_RGB565:
 693                 /* 16bpp not supported on gen2 */
 694                 if (IS_GEN2(dev_priv))
 695                         return false;
 696                 /* WaFbcOnly1to1Ratio:ctg */
 697                 if (IS_G4X(dev_priv))
 698                         return false;
 699                 return true;
 700         default:
 701                 return false;
 702         }
 703 }
 704
 705 /*
 706  * For some reason, the hardware tracking starts looking at whatever we
 707  * programmed as the display plane base address register. It does not look at
 708  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 709  * variables instead of just looking at the pipe/plane size.
 710  */
 711 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 712 {
 713         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 714         struct intel_fbc *fbc = &dev_priv->fbc;
 715         unsigned int effective_w, effective_h, max_w, max_h;
 716
 717         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 718                 max_w = 4096;
 719                 max_h = 4096;
 720         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 721                 max_w = 4096;
 722                 max_h = 2048;
 723         } else {
 724                 max_w = 2048;
 725                 max_h = 1536;
 726         }
 727
 728         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 729                                         &effective_h);
 730         effective_w += fbc->state_cache.plane.adjusted_x;
 731         effective_h += fbc->state_cache.plane.adjusted_y;
 732
 733         return effective_w <= max_w && effective_h <= max_h;
 734 }
 735
 736 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 737                                          struct intel_crtc_state *crtc_state,
 738                                          struct intel_plane_state *plane_state)
 739 {
 740         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 741         struct intel_fbc *fbc = &dev_priv->fbc;
 742         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 743         struct drm_framebuffer *fb = plane_state->base.fb;
 744
 745         cache->vma = NULL;
 746         cache->flags = 0;
 747
 748         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 749         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 750                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 751
 752         cache->plane.rotation = plane_state->base.rotation;
 753         /*
 754          * Src coordinates are already rotated by 270 degrees for
 755          * the 90/270 degree plane rotation cases (to match the
 756          * GTT mapping), hence no need to account for rotation here.
 757          */
 758         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 759         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 760         cache->plane.visible = plane_state->base.visible;
 761         cache->plane.adjusted_x = plane_state->main.x;
 762         cache->plane.adjusted_y = plane_state->main.y;
 763         cache->plane.y = plane_state->base.src.y1 >> 16;
 764
 765         if (!cache->plane.visible)
 766                 return;
 767
 768         cache->fb.format = fb->format;
 769         cache->fb.stride = fb->pitches[0];
 770
 771         cache->vma = plane_state->vma;
 772         cache->flags = plane_state->flags;
 773         if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
 774                 cache->flags &= ~PLANE_HAS_FENCE;
 775 }
 776
 777 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 778 {
 779         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 780         struct intel_fbc *fbc = &dev_priv->fbc;
 781         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 782
 783         /* We don't need to use a state cache here since this information is
 784          * global for all CRTC.
 785          */
 786         if (fbc->underrun_detected) {
 787                 fbc->no_fbc_reason = "underrun detected";
 788                 return false;
 789         }
 790
 791         if (!cache->vma) {
 792                 fbc->no_fbc_reason = "primary plane not visible";
 793                 return false;
 794         }
 795
 796         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 797                 fbc->no_fbc_reason = "incompatible mode";
 798                 return false;
 799         }
 800
 801         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 802                 fbc->no_fbc_reason = "mode too large for compression";
 803                 return false;
 804         }
 805
 806         /* The use of a CPU fence is mandatory in order to detect writes
 807          * by the CPU to the scanout and trigger updates to the FBC.
 808          *
 809          * Note that is possible for a tiled surface to be unmappable (and
 810          * so have no fence associated with it) due to aperture constaints
 811          * at the time of pinning.
 812          *
 813          * FIXME with 90/270 degree rotation we should use the fence on
 814          * the normal GTT view (the rotated view doesn't even have a
 815          * fence). Would need changes to the FBC fence Y offset as well.
 816          * For now this will effecively disable FBC with 90/270 degree
 817          * rotation.
 818          */
 819         if (!(cache->flags & PLANE_HAS_FENCE)) {
 820                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 821                 return false;
 822         }
 823         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 824             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 825                 fbc->no_fbc_reason = "rotation unsupported";
 826                 return false;
 827         }
 828
 829         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 830                 fbc->no_fbc_reason = "framebuffer stride not supported";
 831                 return false;
 832         }
 833
 834         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 835                 fbc->no_fbc_reason = "pixel format is invalid";
 836                 return false;
 837         }
 838
 839         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 840         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 841             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 842                 fbc->no_fbc_reason = "pixel rate is too big";
 843                 return false;
 844         }
 845
 846         /* It is possible for the required CFB size change without a
 847          * crtc->disable + crtc->enable since it is possible to change the
 848          * stride without triggering a full modeset. Since we try to
 849          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 850          * if this happens, but if we exceed the current CFB size we'll have to
 851          * disable FBC. Notice that it would be possible to disable FBC, wait
 852          * for a frame, free the stolen node, then try to reenable FBC in case
 853          * we didn't get any invalidate/deactivate calls, but this would require
 854          * a lot of tracking just for a specific case. If we conclude it's an
 855          * important case, we can implement it later. */
 856         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 857             fbc->compressed_fb.size * fbc->threshold) {
 858                 fbc->no_fbc_reason = "CFB requirements changed";
 859                 return false;
 860         }
 861
 862         /*
 863          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 864          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 865          * and screen flicker.
 866          */
 867         if (IS_GEN(dev_priv, 9, 10) &&
 868             (fbc->state_cache.plane.adjusted_y & 3)) {
 869                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 870                 return false;
 871         }
 872
 873         return true;
 874 }
 875
 876 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 877 {
 878         struct intel_fbc *fbc = &dev_priv->fbc;
 879
 880         if (intel_vgpu_active(dev_priv)) {
 881                 fbc->no_fbc_reason = "VGPU is active";
 882                 return false;
 883         }
 884
 885         if (!i915_modparams.enable_fbc) {
 886                 fbc->no_fbc_reason = "disabled per module param or by default";
 887                 return false;
 888         }
 889
 890         if (fbc->underrun_detected) {
 891                 fbc->no_fbc_reason = "underrun detected";
 892                 return false;
 893         }
 894
 895         return true;
 896 }
 897
 898 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 899                                      struct intel_fbc_reg_params *params)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 902         struct intel_fbc *fbc = &dev_priv->fbc;
 903         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 904
 905         /* Since all our fields are integer types, use memset here so the
 906          * comparison function can rely on memcmp because the padding will be
 907          * zero. */
 908         memset(params, 0, sizeof(*params));
 909
 910         params->vma = cache->vma;
 911         params->flags = cache->flags;
 912
 913         params->crtc.pipe = crtc->pipe;
 914         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 915         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 916
 917         params->fb.format = cache->fb.format;
 918         params->fb.stride = cache->fb.stride;
 919
 920         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 921
 922         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 923                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 924                                                 32 * fbc->threshold) * 8;
 925 }
 926
 927 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 928                                        struct intel_fbc_reg_params *params2)
 929 {
 930         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 931         return memcmp(params1, params2, sizeof(*params1)) == 0;
 932 }
 933
 934 void intel_fbc_pre_update(struct intel_crtc *crtc,
 935                           struct intel_crtc_state *crtc_state,
 936                           struct intel_plane_state *plane_state)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 939         struct intel_fbc *fbc = &dev_priv->fbc;
 940         const char *reason = "update pending";
 941
 942         if (!fbc_supported(dev_priv))
 943                 return;
 944
 945         mutex_lock(&fbc->lock);
 946
 947         if (!multiple_pipes_ok(crtc, plane_state)) {
 948                 reason = "more than one pipe active";
 949                 goto deactivate;
 950         }
 951
 952         if (!fbc->enabled || fbc->crtc != crtc)
 953                 goto unlock;
 954
 955         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 956
 957 deactivate:
 958         intel_fbc_deactivate(dev_priv, reason);
 959 unlock:
 960         mutex_unlock(&fbc->lock);
 961 }
 962
 963 /**
 964  * __intel_fbc_disable - disable FBC
 965  * @dev_priv: i915 device instance
 966  *
 967  * This is the low level function that actually disables FBC. Callers should
 968  * grab the FBC lock.
 969  */
 970 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 971 {
 972         struct intel_fbc *fbc = &dev_priv->fbc;
 973         struct intel_crtc *crtc = fbc->crtc;
 974
 975         WARN_ON(!mutex_is_locked(&fbc->lock));
 976         WARN_ON(!fbc->enabled);
 977         WARN_ON(fbc->active);
 978
 979         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 980
 981         __intel_fbc_cleanup_cfb(dev_priv);
 982
 983         fbc->enabled = false;
 984         fbc->crtc = NULL;
 985 }
 986
 987 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 988 {
 989         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 990         struct intel_fbc *fbc = &dev_priv->fbc;
 991         struct intel_fbc_reg_params old_params;
 992
 993         WARN_ON(!mutex_is_locked(&fbc->lock));
 994
 995         if (!fbc->enabled || fbc->crtc != crtc)
 996                 return;
 997
 998         if (!i915_modparams.enable_fbc) {
 999                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1000                 __intel_fbc_disable(dev_priv);
1001
1002                 return;
1003         }
1004
1005         if (!intel_fbc_can_activate(crtc)) {
1006                 WARN_ON(fbc->active);
1007                 return;
1008         }
1009
1010         old_params = fbc->params;
1011         intel_fbc_get_reg_params(crtc, &fbc->params);
1012
1013         /* If the scanout has not changed, don't modify the FBC settings.
1014          * Note that we make the fundamental assumption that the fb->obj
1015          * cannot be unpinned (and have its GTT offset and fence revoked)
1016          * without first being decoupled from the scanout and FBC disabled.
1017          */
1018         if (fbc->active &&
1019             intel_fbc_reg_params_equal(&old_params, &fbc->params))
1020                 return;
1021
1022         intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
1023         intel_fbc_schedule_activation(crtc);
1024 }
1025
1026 void intel_fbc_post_update(struct intel_crtc *crtc)
1027 {
1028         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1029         struct intel_fbc *fbc = &dev_priv->fbc;
1030
1031         if (!fbc_supported(dev_priv))
1032                 return;
1033
1034         mutex_lock(&fbc->lock);
1035         __intel_fbc_post_update(crtc);
1036         mutex_unlock(&fbc->lock);
1037 }
1038
1039 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1040 {
1041         if (fbc->enabled)
1042                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1043         else
1044                 return fbc->possible_framebuffer_bits;
1045 }
1046
1047 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1048                           unsigned int frontbuffer_bits,
1049                           enum fb_op_origin origin)
1050 {
1051         struct intel_fbc *fbc = &dev_priv->fbc;
1052
1053         if (!fbc_supported(dev_priv))
1054                 return;
1055
1056         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1057                 return;
1058
1059         mutex_lock(&fbc->lock);
1060
1061         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1062
1063         if (fbc->enabled && fbc->busy_bits)
1064                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1065
1066         mutex_unlock(&fbc->lock);
1067 }
1068
1069 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1070                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1071 {
1072         struct intel_fbc *fbc = &dev_priv->fbc;
1073
1074         if (!fbc_supported(dev_priv))
1075                 return;
1076
1077         mutex_lock(&fbc->lock);
1078
1079         fbc->busy_bits &= ~frontbuffer_bits;
1080
1081         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1082                 goto out;
1083
1084         if (!fbc->busy_bits && fbc->enabled &&
1085             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1086                 if (fbc->active)
1087                         intel_fbc_recompress(dev_priv);
1088                 else
1089                         __intel_fbc_post_update(fbc->crtc);
1090         }
1091
1092 out:
1093         mutex_unlock(&fbc->lock);
1094 }
1095
1096 /**
1097  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1098  * @dev_priv: i915 device instance
1099  * @state: the atomic state structure
1100  *
1101  * This function looks at the proposed state for CRTCs and planes, then chooses
1102  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1103  * true.
1104  *
1105  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1106  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1107  */
1108 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1109                            struct intel_atomic_state *state)
1110 {
1111         struct intel_fbc *fbc = &dev_priv->fbc;
1112         struct intel_plane *plane;
1113         struct intel_plane_state *plane_state;
1114         bool crtc_chosen = false;
1115         int i;
1116
1117         mutex_lock(&fbc->lock);
1118
1119         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1120         if (fbc->crtc &&
1121             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1122                 goto out;
1123
1124         if (!intel_fbc_can_enable(dev_priv))
1125                 goto out;
1126
1127         /* Simply choose the first CRTC that is compatible and has a visible
1128          * plane. We could go for fancier schemes such as checking the plane
1129          * size, but this would just affect the few platforms that don't tie FBC
1130          * to pipe or plane A. */
1131         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1132                 struct intel_crtc_state *crtc_state;
1133                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1134
1135                 if (!plane->has_fbc)
1136                         continue;
1137
1138                 if (!plane_state->base.visible)
1139                         continue;
1140
1141                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1142
1143                 crtc_state->enable_fbc = true;
1144                 crtc_chosen = true;
1145                 break;
1146         }
1147
1148         if (!crtc_chosen)
1149                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1150
1151 out:
1152         mutex_unlock(&fbc->lock);
1153 }
1154
1155 /**
1156  * intel_fbc_enable: tries to enable FBC on the CRTC
1157  * @crtc: the CRTC
1158  * @crtc_state: corresponding &drm_crtc_state for @crtc
1159  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1160  *
1161  * This function checks if the given CRTC was chosen for FBC, then enables it if
1162  * possible. Notice that it doesn't activate FBC. It is valid to call
1163  * intel_fbc_enable multiple times for the same pipe without an
1164  * intel_fbc_disable in the middle, as long as it is deactivated.
1165  */
1166 void intel_fbc_enable(struct intel_crtc *crtc,
1167                       struct intel_crtc_state *crtc_state,
1168                       struct intel_plane_state *plane_state)
1169 {
1170         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1171         struct intel_fbc *fbc = &dev_priv->fbc;
1172
1173         if (!fbc_supported(dev_priv))
1174                 return;
1175
1176         mutex_lock(&fbc->lock);
1177
1178         if (fbc->enabled) {
1179                 WARN_ON(fbc->crtc == NULL);
1180                 if (fbc->crtc == crtc) {
1181                         WARN_ON(!crtc_state->enable_fbc);
1182                         WARN_ON(fbc->active);
1183                 }
1184                 goto out;
1185         }
1186
1187         if (!crtc_state->enable_fbc)
1188                 goto out;
1189
1190         WARN_ON(fbc->active);
1191         WARN_ON(fbc->crtc != NULL);
1192
1193         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1194         if (intel_fbc_alloc_cfb(crtc)) {
1195                 fbc->no_fbc_reason = "not enough stolen memory";
1196                 goto out;
1197         }
1198
1199         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1200         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1201
1202         fbc->enabled = true;
1203         fbc->crtc = crtc;
1204 out:
1205         mutex_unlock(&fbc->lock);
1206 }
1207
1208 /**
1209  * intel_fbc_disable - disable FBC if it's associated with crtc
1210  * @crtc: the CRTC
1211  *
1212  * This function disables FBC if it's associated with the provided CRTC.
1213  */
1214 void intel_fbc_disable(struct intel_crtc *crtc)
1215 {
1216         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1217         struct intel_fbc *fbc = &dev_priv->fbc;
1218
1219         if (!fbc_supported(dev_priv))
1220                 return;
1221
1222         WARN_ON(crtc->active);
1223
1224         mutex_lock(&fbc->lock);
1225         if (fbc->crtc == crtc)
1226                 __intel_fbc_disable(dev_priv);
1227         mutex_unlock(&fbc->lock);
1228
1229         cancel_work_sync(&fbc->work.work);
1230 }
1231
1232 /**
1233  * intel_fbc_global_disable - globally disable FBC
1234  * @dev_priv: i915 device instance
1235  *
1236  * This function disables FBC regardless of which CRTC is associated with it.
1237  */
1238 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1239 {
1240         struct intel_fbc *fbc = &dev_priv->fbc;
1241
1242         if (!fbc_supported(dev_priv))
1243                 return;
1244
1245         mutex_lock(&fbc->lock);
1246         if (fbc->enabled) {
1247                 WARN_ON(fbc->crtc->active);
1248                 __intel_fbc_disable(dev_priv);
1249         }
1250         mutex_unlock(&fbc->lock);
1251
1252         cancel_work_sync(&fbc->work.work);
1253 }
1254
1255 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1256 {
1257         struct drm_i915_private *dev_priv =
1258                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1259         struct intel_fbc *fbc = &dev_priv->fbc;
1260
1261         mutex_lock(&fbc->lock);
1262
1263         /* Maybe we were scheduled twice. */
1264         if (fbc->underrun_detected || !fbc->enabled)
1265                 goto out;
1266
1267         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1268         fbc->underrun_detected = true;
1269
1270         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1271 out:
1272         mutex_unlock(&fbc->lock);
1273 }
1274
1275 /*
1276  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1277  * @dev_priv: i915 device instance
1278  *
1279  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1280  * want to re-enable FBC after an underrun to increase test coverage.
1281  */
1282 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1283 {
1284         int ret;
1285
1286         cancel_work_sync(&dev_priv->fbc.underrun_work);
1287
1288         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1289         if (ret)
1290                 return ret;
1291
1292         if (dev_priv->fbc.underrun_detected) {
1293                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1294                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1295         }
1296
1297         dev_priv->fbc.underrun_detected = false;
1298         mutex_unlock(&dev_priv->fbc.lock);
1299
1300         return 0;
1301 }
1302
1303 /**
1304  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1305  * @dev_priv: i915 device instance
1306  *
1307  * Without FBC, most underruns are harmless and don't really cause too many
1308  * problems, except for an annoying message on dmesg. With FBC, underruns can
1309  * become black screens or even worse, especially when paired with bad
1310  * watermarks. So in order for us to be on the safe side, completely disable FBC
1311  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1312  * already suggests that watermarks may be bad, so try to be as safe as
1313  * possible.
1314  *
1315  * This function is called from the IRQ handler.
1316  */
1317 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1318 {
1319         struct intel_fbc *fbc = &dev_priv->fbc;
1320
1321         if (!fbc_supported(dev_priv))
1322                 return;
1323
1324         /* There's no guarantee that underrun_detected won't be set to true
1325          * right after this check and before the work is scheduled, but that's
1326          * not a problem since we'll check it again under the work function
1327          * while FBC is locked. This check here is just to prevent us from
1328          * unnecessarily scheduling the work, and it relies on the fact that we
1329          * never switch underrun_detect back to false after it's true. */
1330         if (READ_ONCE(fbc->underrun_detected))
1331                 return;
1332
1333         schedule_work(&fbc->underrun_work);
1334 }
1335
1336 /**
1337  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1338  * @dev_priv: i915 device instance
1339  *
1340  * The FBC code needs to track CRTC visibility since the older platforms can't
1341  * have FBC enabled while multiple pipes are used. This function does the
1342  * initial setup at driver load to make sure FBC is matching the real hardware.
1343  */
1344 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1345 {
1346         struct intel_crtc *crtc;
1347
1348         /* Don't even bother tracking anything if we don't need. */
1349         if (!no_fbc_on_multiple_pipes(dev_priv))
1350                 return;
1351
1352         for_each_intel_crtc(&dev_priv->drm, crtc)
1353                 if (intel_crtc_active(crtc) &&
1354                     crtc->base.primary->state->visible)
1355                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1356 }
1357
1358 /*
1359  * The DDX driver changes its behavior depending on the value it reads from
1360  * i915.enable_fbc, so sanitize it by translating the default value into either
1361  * 0 or 1 in order to allow it to know what's going on.
1362  *
1363  * Notice that this is done at driver initialization and we still allow user
1364  * space to change the value during runtime without sanitizing it again. IGT
1365  * relies on being able to change i915.enable_fbc at runtime.
1366  */
1367 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1368 {
1369         if (i915_modparams.enable_fbc >= 0)
1370                 return !!i915_modparams.enable_fbc;
1371
1372         if (!HAS_FBC(dev_priv))
1373                 return 0;
1374
1375         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1376                 return 1;
1377
1378         return 0;
1379 }
1380
1381 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1382 {
1383         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1384         if (intel_vtd_active() &&
1385             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1386                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1387                 return true;
1388         }
1389
1390         return false;
1391 }
1392
1393 /**
1394  * intel_fbc_init - Initialize FBC
1395  * @dev_priv: the i915 device
1396  *
1397  * This function might be called during PM init process.
1398  */
1399 void intel_fbc_init(struct drm_i915_private *dev_priv)
1400 {
1401         struct intel_fbc *fbc = &dev_priv->fbc;
1402
1403         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1404         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1405         mutex_init(&fbc->lock);
1406         fbc->enabled = false;
1407         fbc->active = false;
1408         fbc->work.scheduled = false;
1409
1410         if (need_fbc_vtd_wa(dev_priv))
1411                 mkwrite_device_info(dev_priv)->has_fbc = false;
1412
1413         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1414         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1415                       i915_modparams.enable_fbc);
1416
1417         if (!HAS_FBC(dev_priv)) {
1418                 fbc->no_fbc_reason = "unsupported by this chipset";
1419                 return;
1420         }
1421
1422         /* This value was pulled out of someone's hat */
1423         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1424                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1425
1426         /* We still don't have any sort of hardware state readout for FBC, so
1427          * deactivate it in case the BIOS activated it to make sure software
1428          * matches the hardware state. */
1429         if (intel_fbc_hw_is_active(dev_priv))
1430                 intel_fbc_hw_deactivate(dev_priv);
1431 }