1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * amd-pstate.c - AMD Processor P-state Frequency Driver
5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved.
9 * AMD P-State introduces a new CPU performance scaling design for AMD
10 * processors using the ACPI Collaborative Performance and Power Control (CPPC)
11 * feature which works with the AMD SMU firmware providing a finer grained
12 * frequency control range. It is to replace the legacy ACPI P-States control,
13 * allows a flexible, low-latency interface for the Linux kernel to directly
14 * communicate the performance hints to hardware.
16 * AMD P-State is supported on recent AMD Zen base CPU series include some of
17 * Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD
18 * P-State supported system. And there are two types of hardware implementations
19 * for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution.
20 * X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/smp.h>
29 #include <linux/sched.h>
30 #include <linux/cpufreq.h>
31 #include <linux/compiler.h>
32 #include <linux/dmi.h>
33 #include <linux/slab.h>
34 #include <linux/acpi.h>
36 #include <linux/delay.h>
37 #include <linux/uaccess.h>
38 #include <linux/static_call.h>
39 #include <linux/topology.h>
41 #include <acpi/processor.h>
42 #include <acpi/cppc_acpi.h>
45 #include <asm/processor.h>
46 #include <asm/cpufeature.h>
47 #include <asm/cpu_device_id.h>
49 #include "amd-pstate.h"
50 #include "amd-pstate-trace.h"
52 #define AMD_PSTATE_TRANSITION_LATENCY 20000
53 #define AMD_PSTATE_TRANSITION_DELAY 1000
54 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
55 #define CPPC_HIGHEST_PERF_PERFORMANCE 196
56 #define CPPC_HIGHEST_PERF_DEFAULT 166
58 #define AMD_CPPC_EPP_PERFORMANCE 0x00
59 #define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
60 #define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
61 #define AMD_CPPC_EPP_POWERSAVE 0xFF
64 * enum amd_pstate_mode - driver working mode of amd pstate
66 enum amd_pstate_mode {
67 AMD_PSTATE_UNDEFINED = 0,
75 static const char * const amd_pstate_mode_string[] = {
76 [AMD_PSTATE_UNDEFINED] = "undefined",
77 [AMD_PSTATE_DISABLE] = "disable",
78 [AMD_PSTATE_PASSIVE] = "passive",
79 [AMD_PSTATE_ACTIVE] = "active",
80 [AMD_PSTATE_GUIDED] = "guided",
89 static struct cpufreq_driver *current_pstate_driver;
90 static struct cpufreq_driver amd_pstate_driver;
91 static struct cpufreq_driver amd_pstate_epp_driver;
92 static int cppc_state = AMD_PSTATE_UNDEFINED;
93 static bool cppc_enabled;
94 static bool amd_pstate_prefcore = true;
95 static struct quirk_entry *quirks;
98 * AMD Energy Preference Performance (EPP)
99 * The EPP is used in the CCLK DPM controller to drive
100 * the frequency that a core is going to operate during
101 * short periods of activity. EPP values will be utilized for
102 * different OS profiles (balanced, performance, power savings)
103 * display strings corresponding to EPP index in the
104 * energy_perf_strings[]
106 *-------------------------------------
109 * 2 balance_performance
113 enum energy_perf_value_index {
114 EPP_INDEX_DEFAULT = 0,
115 EPP_INDEX_PERFORMANCE,
116 EPP_INDEX_BALANCE_PERFORMANCE,
117 EPP_INDEX_BALANCE_POWERSAVE,
121 static const char * const energy_perf_strings[] = {
122 [EPP_INDEX_DEFAULT] = "default",
123 [EPP_INDEX_PERFORMANCE] = "performance",
124 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
125 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
126 [EPP_INDEX_POWERSAVE] = "power",
130 static unsigned int epp_values[] = {
131 [EPP_INDEX_DEFAULT] = 0,
132 [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
133 [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
134 [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
135 [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
138 typedef int (*cppc_mode_transition_fn)(int);
140 static struct quirk_entry quirk_amd_7k62 = {
141 .nominal_freq = 2600,
145 static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi)
148 * match the broken bios for family 17h processor support CPPC V2
149 * broken BIOS lack of nominal_freq and lowest_freq capabilities
150 * definition in ACPI tables
152 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) {
153 quirks = dmi->driver_data;
154 pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident);
161 static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = {
163 .callback = dmi_matched_7k62_bios_bug,
164 .ident = "AMD EPYC 7K62",
166 DMI_MATCH(DMI_BIOS_VERSION, "5.14"),
167 DMI_MATCH(DMI_BIOS_RELEASE, "12/12/2019"),
169 .driver_data = &quirk_amd_7k62,
173 MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table);
175 static inline int get_mode_idx_from_str(const char *str, size_t size)
179 for (i=0; i < AMD_PSTATE_MAX; i++) {
180 if (!strncmp(str, amd_pstate_mode_string[i], size))
186 static DEFINE_MUTEX(amd_pstate_limits_lock);
187 static DEFINE_MUTEX(amd_pstate_driver_lock);
189 static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
194 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
195 if (!cppc_req_cached) {
196 epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
201 epp = (cppc_req_cached >> 24) & 0xFF;
203 ret = cppc_get_epp_perf(cpudata->cpu, &epp);
205 pr_debug("Could not retrieve energy perf value (%d)\n", ret);
210 return (s16)(epp & 0xff);
213 static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
218 epp = amd_pstate_get_epp(cpudata, 0);
223 case AMD_CPPC_EPP_PERFORMANCE:
224 index = EPP_INDEX_PERFORMANCE;
226 case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
227 index = EPP_INDEX_BALANCE_PERFORMANCE;
229 case AMD_CPPC_EPP_BALANCE_POWERSAVE:
230 index = EPP_INDEX_BALANCE_POWERSAVE;
232 case AMD_CPPC_EPP_POWERSAVE:
233 index = EPP_INDEX_POWERSAVE;
242 static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
243 u32 des_perf, u32 max_perf, bool fast_switch)
246 wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
248 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
249 READ_ONCE(cpudata->cppc_req_cached));
252 DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
254 static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
255 u32 min_perf, u32 des_perf,
256 u32 max_perf, bool fast_switch)
258 static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
259 max_perf, fast_switch);
262 static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
265 struct cppc_perf_ctrls perf_ctrls;
267 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
268 u64 value = READ_ONCE(cpudata->cppc_req_cached);
270 value &= ~GENMASK_ULL(31, 24);
271 value |= (u64)epp << 24;
272 WRITE_ONCE(cpudata->cppc_req_cached, value);
274 ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
276 cpudata->epp_cached = epp;
278 amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,
279 cpudata->max_limit_perf, false);
281 perf_ctrls.energy_perf = epp;
282 ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
284 pr_debug("failed to set energy perf value (%d)\n", ret);
287 cpudata->epp_cached = epp;
293 static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
300 epp = cpudata->epp_default;
303 epp = epp_values[pref_index];
305 if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
306 pr_debug("EPP cannot be set under performance policy\n");
310 ret = amd_pstate_set_epp(cpudata, epp);
315 static inline int pstate_enable(bool enable)
318 unsigned long logical_proc_id_mask = 0;
320 if (enable == cppc_enabled)
323 for_each_present_cpu(cpu) {
324 unsigned long logical_id = topology_logical_package_id(cpu);
326 if (test_bit(logical_id, &logical_proc_id_mask))
329 set_bit(logical_id, &logical_proc_id_mask);
331 ret = wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE,
337 cppc_enabled = enable;
341 static int cppc_enable(bool enable)
344 struct cppc_perf_ctrls perf_ctrls;
346 if (enable == cppc_enabled)
349 for_each_present_cpu(cpu) {
350 ret = cppc_set_enable(cpu, enable);
354 /* Enable autonomous mode for EPP */
355 if (cppc_state == AMD_PSTATE_ACTIVE) {
356 /* Set desired perf as zero to allow EPP firmware control */
357 perf_ctrls.desired_perf = 0;
358 ret = cppc_set_perf(cpu, &perf_ctrls);
364 cppc_enabled = enable;
368 DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
370 static inline int amd_pstate_enable(bool enable)
372 return static_call(amd_pstate_enable)(enable);
375 static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata)
377 struct cpuinfo_x86 *c = &cpu_data(0);
380 * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f,
381 * the highest performance level is set to 196.
382 * https://bugzilla.kernel.org/show_bug.cgi?id=218759
384 if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f))
385 return CPPC_HIGHEST_PERF_PERFORMANCE;
387 return CPPC_HIGHEST_PERF_DEFAULT;
390 static int pstate_init_perf(struct amd_cpudata *cpudata)
395 int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
400 /* For platforms that do not support the preferred core feature, the
401 * highest_pef may be configured with 166 or 255, to avoid max frequency
402 * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
403 * the default max perf.
405 if (cpudata->hw_prefcore)
406 highest_perf = amd_pstate_highest_perf_set(cpudata);
408 highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
410 WRITE_ONCE(cpudata->highest_perf, highest_perf);
411 WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
412 WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
413 WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
414 WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
415 WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
416 WRITE_ONCE(cpudata->min_limit_perf, AMD_CPPC_LOWEST_PERF(cap1));
420 static int cppc_init_perf(struct amd_cpudata *cpudata)
422 struct cppc_perf_caps cppc_perf;
425 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
429 if (cpudata->hw_prefcore)
430 highest_perf = amd_pstate_highest_perf_set(cpudata);
432 highest_perf = cppc_perf.highest_perf;
434 WRITE_ONCE(cpudata->highest_perf, highest_perf);
435 WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
436 WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
437 WRITE_ONCE(cpudata->lowest_nonlinear_perf,
438 cppc_perf.lowest_nonlinear_perf);
439 WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
440 WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf);
441 WRITE_ONCE(cpudata->min_limit_perf, cppc_perf.lowest_perf);
443 if (cppc_state == AMD_PSTATE_ACTIVE)
446 ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf);
448 pr_warn("failed to get auto_sel, ret: %d\n", ret);
452 ret = cppc_set_auto_sel(cpudata->cpu,
453 (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1);
456 pr_warn("failed to set auto_sel, ret: %d\n", ret);
461 DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
463 static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
465 return static_call(amd_pstate_init_perf)(cpudata);
468 static void cppc_update_perf(struct amd_cpudata *cpudata,
469 u32 min_perf, u32 des_perf,
470 u32 max_perf, bool fast_switch)
472 struct cppc_perf_ctrls perf_ctrls;
474 perf_ctrls.max_perf = max_perf;
475 perf_ctrls.min_perf = min_perf;
476 perf_ctrls.desired_perf = des_perf;
478 cppc_set_perf(cpudata->cpu, &perf_ctrls);
481 static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
483 u64 aperf, mperf, tsc;
486 local_irq_save(flags);
487 rdmsrl(MSR_IA32_APERF, aperf);
488 rdmsrl(MSR_IA32_MPERF, mperf);
491 if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
492 local_irq_restore(flags);
496 local_irq_restore(flags);
498 cpudata->cur.aperf = aperf;
499 cpudata->cur.mperf = mperf;
500 cpudata->cur.tsc = tsc;
501 cpudata->cur.aperf -= cpudata->prev.aperf;
502 cpudata->cur.mperf -= cpudata->prev.mperf;
503 cpudata->cur.tsc -= cpudata->prev.tsc;
505 cpudata->prev.aperf = aperf;
506 cpudata->prev.mperf = mperf;
507 cpudata->prev.tsc = tsc;
509 cpudata->freq = div64_u64((cpudata->cur.aperf * cpu_khz), cpudata->cur.mperf);
514 static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
515 u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags)
517 unsigned long max_freq;
518 struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu);
519 u64 prev = READ_ONCE(cpudata->cppc_req_cached);
520 u32 nominal_perf = READ_ONCE(cpudata->nominal_perf);
523 min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf,
524 cpudata->max_limit_perf);
525 max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf,
526 cpudata->max_limit_perf);
527 des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
529 max_freq = READ_ONCE(cpudata->max_limit_freq);
530 policy->cur = div_u64(des_perf * max_freq, max_perf);
532 if ((cppc_state == AMD_PSTATE_GUIDED) && (gov_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) {
537 value &= ~AMD_CPPC_MIN_PERF(~0L);
538 value |= AMD_CPPC_MIN_PERF(min_perf);
540 value &= ~AMD_CPPC_DES_PERF(~0L);
541 value |= AMD_CPPC_DES_PERF(des_perf);
543 /* limit the max perf when core performance boost feature is disabled */
544 if (!cpudata->boost_supported)
545 max_perf = min_t(unsigned long, nominal_perf, max_perf);
547 value &= ~AMD_CPPC_MAX_PERF(~0L);
548 value |= AMD_CPPC_MAX_PERF(max_perf);
550 if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
551 trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
552 cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc,
553 cpudata->cpu, (value != prev), fast_switch);
559 WRITE_ONCE(cpudata->cppc_req_cached, value);
561 amd_pstate_update_perf(cpudata, min_perf, des_perf,
562 max_perf, fast_switch);
565 static int amd_pstate_verify(struct cpufreq_policy_data *policy)
567 cpufreq_verify_within_cpu_limits(policy);
572 static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy)
574 u32 max_limit_perf, min_limit_perf, lowest_perf;
575 struct amd_cpudata *cpudata = policy->driver_data;
577 max_limit_perf = div_u64(policy->max * cpudata->highest_perf, cpudata->max_freq);
578 min_limit_perf = div_u64(policy->min * cpudata->highest_perf, cpudata->max_freq);
580 lowest_perf = READ_ONCE(cpudata->lowest_perf);
581 if (min_limit_perf < lowest_perf)
582 min_limit_perf = lowest_perf;
584 if (max_limit_perf < min_limit_perf)
585 max_limit_perf = min_limit_perf;
587 WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf);
588 WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf);
589 WRITE_ONCE(cpudata->max_limit_freq, policy->max);
590 WRITE_ONCE(cpudata->min_limit_freq, policy->min);
595 static int amd_pstate_update_freq(struct cpufreq_policy *policy,
596 unsigned int target_freq, bool fast_switch)
598 struct cpufreq_freqs freqs;
599 struct amd_cpudata *cpudata = policy->driver_data;
600 unsigned long max_perf, min_perf, des_perf, cap_perf;
602 if (!cpudata->max_freq)
605 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq)
606 amd_pstate_update_min_max_limit(policy);
608 cap_perf = READ_ONCE(cpudata->highest_perf);
609 min_perf = READ_ONCE(cpudata->lowest_perf);
612 freqs.old = policy->cur;
613 freqs.new = target_freq;
615 des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf,
618 WARN_ON(fast_switch && !policy->fast_switch_enabled);
620 * If fast_switch is desired, then there aren't any registered
621 * transition notifiers. See comment for
622 * cpufreq_enable_fast_switch().
625 cpufreq_freq_transition_begin(policy, &freqs);
627 amd_pstate_update(cpudata, min_perf, des_perf,
628 max_perf, fast_switch, policy->governor->flags);
631 cpufreq_freq_transition_end(policy, &freqs, false);
636 static int amd_pstate_target(struct cpufreq_policy *policy,
637 unsigned int target_freq,
638 unsigned int relation)
640 return amd_pstate_update_freq(policy, target_freq, false);
643 static unsigned int amd_pstate_fast_switch(struct cpufreq_policy *policy,
644 unsigned int target_freq)
646 if (!amd_pstate_update_freq(policy, target_freq, true))
651 static void amd_pstate_adjust_perf(unsigned int cpu,
652 unsigned long _min_perf,
653 unsigned long target_perf,
654 unsigned long capacity)
656 unsigned long max_perf, min_perf, des_perf,
657 cap_perf, lowest_nonlinear_perf;
658 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
659 struct amd_cpudata *cpudata = policy->driver_data;
661 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq)
662 amd_pstate_update_min_max_limit(policy);
665 cap_perf = READ_ONCE(cpudata->highest_perf);
666 lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
669 if (target_perf < capacity)
670 des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
672 min_perf = READ_ONCE(cpudata->lowest_perf);
673 if (_min_perf < capacity)
674 min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
676 if (min_perf < lowest_nonlinear_perf)
677 min_perf = lowest_nonlinear_perf;
680 if (max_perf < min_perf)
683 des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
685 amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true,
686 policy->governor->flags);
687 cpufreq_cpu_put(policy);
690 static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on)
692 struct amd_cpudata *cpudata = policy->driver_data;
693 struct cppc_perf_ctrls perf_ctrls;
694 u32 highest_perf, nominal_perf, nominal_freq, max_freq;
697 highest_perf = READ_ONCE(cpudata->highest_perf);
698 nominal_perf = READ_ONCE(cpudata->nominal_perf);
699 nominal_freq = READ_ONCE(cpudata->nominal_freq);
700 max_freq = READ_ONCE(cpudata->max_freq);
702 if (boot_cpu_has(X86_FEATURE_CPPC)) {
703 u64 value = READ_ONCE(cpudata->cppc_req_cached);
705 value &= ~GENMASK_ULL(7, 0);
706 value |= on ? highest_perf : nominal_perf;
707 WRITE_ONCE(cpudata->cppc_req_cached, value);
709 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
711 perf_ctrls.max_perf = on ? highest_perf : nominal_perf;
712 ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
714 cpufreq_cpu_release(policy);
715 pr_debug("Failed to set max perf on CPU:%d. ret:%d\n",
722 policy->cpuinfo.max_freq = max_freq;
723 else if (policy->cpuinfo.max_freq > nominal_freq * 1000)
724 policy->cpuinfo.max_freq = nominal_freq * 1000;
726 policy->max = policy->cpuinfo.max_freq;
728 if (cppc_state == AMD_PSTATE_PASSIVE) {
729 ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq);
731 pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu);
734 return ret < 0 ? ret : 0;
737 static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state)
739 struct amd_cpudata *cpudata = policy->driver_data;
742 if (!cpudata->boost_supported) {
743 pr_err("Boost mode is not supported by this processor or SBIOS\n");
746 mutex_lock(&amd_pstate_driver_lock);
747 ret = amd_pstate_cpu_boost_update(policy, state);
748 WRITE_ONCE(cpudata->boost_state, !ret ? state : false);
749 policy->boost_enabled = !ret ? state : false;
750 refresh_frequency_limits(policy);
751 mutex_unlock(&amd_pstate_driver_lock);
756 static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata)
762 * If platform has no CPB support or disable it, initialize current driver
763 * boost_enabled state to be false, it is not an error for cpufreq core to handle.
765 if (!cpu_feature_enabled(X86_FEATURE_CPB)) {
766 pr_debug_once("Boost CPB capabilities not present in the processor\n");
771 /* at least one CPU supports CPB, even if others fail later on to set up */
772 current_pstate_driver->boost_enabled = true;
774 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val);
776 pr_err_once("failed to read initial CPU boost state!\n");
781 if (!(boost_val & MSR_K7_HWCR_CPB_DIS))
782 cpudata->boost_supported = true;
787 cpudata->boost_supported = false;
791 static void amd_perf_ctl_reset(unsigned int cpu)
793 wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
797 * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks
798 * due to locking, so queue the work for later.
800 static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
802 sched_set_itmt_support();
804 static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
807 * Get the highest performance register value.
808 * @cpu: CPU from which to get highest performance.
809 * @highest_perf: Return address.
811 * Return: 0 for success, -EIO otherwise.
813 static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf)
817 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
820 ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1);
823 WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
825 u64 cppc_highest_perf;
827 ret = cppc_get_highest_perf(cpu, &cppc_highest_perf);
830 WRITE_ONCE(*highest_perf, cppc_highest_perf);
836 #define CPPC_MAX_PERF U8_MAX
838 static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata)
843 ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf);
847 cpudata->hw_prefcore = true;
848 /* check if CPPC preferred core feature is enabled*/
849 if (highest_perf < CPPC_MAX_PERF)
850 prio = (int)highest_perf;
852 pr_debug("AMD CPPC preferred core is unsupported!\n");
853 cpudata->hw_prefcore = false;
857 if (!amd_pstate_prefcore)
861 * The priorities can be set regardless of whether or not
862 * sched_set_itmt_support(true) has been called and it is valid to
863 * update them at any time after it has been called.
865 sched_set_itmt_core_prio(prio, cpudata->cpu);
867 schedule_work(&sched_prefcore_work);
870 static void amd_pstate_update_limits(unsigned int cpu)
872 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
873 struct amd_cpudata *cpudata = policy->driver_data;
874 u32 prev_high = 0, cur_high = 0;
876 bool highest_perf_changed = false;
878 mutex_lock(&amd_pstate_driver_lock);
879 if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore))
880 goto free_cpufreq_put;
882 ret = amd_pstate_get_highest_perf(cpu, &cur_high);
884 goto free_cpufreq_put;
886 prev_high = READ_ONCE(cpudata->prefcore_ranking);
887 if (prev_high != cur_high) {
888 highest_perf_changed = true;
889 WRITE_ONCE(cpudata->prefcore_ranking, cur_high);
891 if (cur_high < CPPC_MAX_PERF)
892 sched_set_itmt_core_prio((int)cur_high, cpu);
896 cpufreq_cpu_put(policy);
898 if (!highest_perf_changed)
899 cpufreq_update_policy(cpu);
901 mutex_unlock(&amd_pstate_driver_lock);
905 * Get pstate transition delay time from ACPI tables that firmware set
906 * instead of using hardcode value directly.
908 static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
910 u32 transition_delay_ns;
912 transition_delay_ns = cppc_get_transition_latency(cpu);
913 if (transition_delay_ns == CPUFREQ_ETERNAL) {
914 if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC))
915 return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY;
917 return AMD_PSTATE_TRANSITION_DELAY;
920 return transition_delay_ns / NSEC_PER_USEC;
924 * Get pstate transition latency value from ACPI tables that firmware
925 * set instead of using hardcode value directly.
927 static u32 amd_pstate_get_transition_latency(unsigned int cpu)
929 u32 transition_latency;
931 transition_latency = cppc_get_transition_latency(cpu);
932 if (transition_latency == CPUFREQ_ETERNAL)
933 return AMD_PSTATE_TRANSITION_LATENCY;
935 return transition_latency;
939 * amd_pstate_init_freq: Initialize the max_freq, min_freq,
940 * nominal_freq and lowest_nonlinear_freq for
941 * the @cpudata object.
943 * Requires: highest_perf, lowest_perf, nominal_perf and
944 * lowest_nonlinear_perf members of @cpudata to be
947 * Returns 0 on success, non-zero value on failure.
949 static int amd_pstate_init_freq(struct amd_cpudata *cpudata)
953 u32 highest_perf, max_freq;
954 u32 nominal_perf, nominal_freq;
955 u32 lowest_nonlinear_perf, lowest_nonlinear_freq;
956 u32 boost_ratio, lowest_nonlinear_ratio;
957 struct cppc_perf_caps cppc_perf;
959 ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
963 if (quirks && quirks->lowest_freq)
964 min_freq = quirks->lowest_freq * 1000;
966 min_freq = cppc_perf.lowest_freq * 1000;
968 if (quirks && quirks->nominal_freq)
969 nominal_freq = quirks->nominal_freq ;
971 nominal_freq = cppc_perf.nominal_freq;
973 nominal_perf = READ_ONCE(cpudata->nominal_perf);
975 highest_perf = READ_ONCE(cpudata->highest_perf);
976 boost_ratio = div_u64(highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf);
977 max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
979 lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
980 lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT,
982 lowest_nonlinear_freq = (nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
984 WRITE_ONCE(cpudata->min_freq, min_freq);
985 WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq);
986 WRITE_ONCE(cpudata->nominal_freq, nominal_freq);
987 WRITE_ONCE(cpudata->max_freq, max_freq);
990 * Below values need to be initialized correctly, otherwise driver will fail to load
991 * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf
992 * lowest_nonlinear_freq is a value between [min_freq, nominal_freq]
993 * Check _CPC in ACPI table objects if any values are incorrect
995 if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) {
996 pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n",
997 min_freq, max_freq, nominal_freq * 1000);
1001 if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) {
1002 pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n",
1003 lowest_nonlinear_freq, min_freq, nominal_freq * 1000);
1010 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
1012 int min_freq, max_freq, ret;
1014 struct amd_cpudata *cpudata;
1017 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
1018 * which is ideal for initialization process.
1020 amd_perf_ctl_reset(policy->cpu);
1021 dev = get_cpu_device(policy->cpu);
1025 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
1029 cpudata->cpu = policy->cpu;
1031 amd_pstate_init_prefcore(cpudata);
1033 ret = amd_pstate_init_perf(cpudata);
1037 ret = amd_pstate_init_freq(cpudata);
1041 ret = amd_pstate_init_boost_support(cpudata);
1045 min_freq = READ_ONCE(cpudata->min_freq);
1046 max_freq = READ_ONCE(cpudata->max_freq);
1048 policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu);
1049 policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu);
1051 policy->min = min_freq;
1052 policy->max = max_freq;
1054 policy->cpuinfo.min_freq = min_freq;
1055 policy->cpuinfo.max_freq = max_freq;
1057 policy->boost_enabled = READ_ONCE(cpudata->boost_supported);
1059 /* It will be updated by governor */
1060 policy->cur = policy->cpuinfo.min_freq;
1062 if (cpu_feature_enabled(X86_FEATURE_CPPC))
1063 policy->fast_switch_possible = true;
1065 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
1066 FREQ_QOS_MIN, policy->cpuinfo.min_freq);
1068 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
1072 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1],
1073 FREQ_QOS_MAX, policy->cpuinfo.max_freq);
1075 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
1079 cpudata->max_limit_freq = max_freq;
1080 cpudata->min_limit_freq = min_freq;
1082 policy->driver_data = cpudata;
1084 if (!current_pstate_driver->adjust_perf)
1085 current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
1090 freq_qos_remove_request(&cpudata->req[0]);
1096 static void amd_pstate_cpu_exit(struct cpufreq_policy *policy)
1098 struct amd_cpudata *cpudata = policy->driver_data;
1100 freq_qos_remove_request(&cpudata->req[1]);
1101 freq_qos_remove_request(&cpudata->req[0]);
1102 policy->fast_switch_possible = false;
1106 static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
1110 ret = amd_pstate_enable(true);
1112 pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
1117 static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
1121 ret = amd_pstate_enable(false);
1123 pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
1128 /* Sysfs attributes */
1131 * This frequency is to indicate the maximum hardware frequency.
1132 * If boost is not active but supported, the frequency will be larger than the
1135 static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy,
1139 struct amd_cpudata *cpudata = policy->driver_data;
1141 max_freq = READ_ONCE(cpudata->max_freq);
1145 return sysfs_emit(buf, "%u\n", max_freq);
1148 static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy,
1152 struct amd_cpudata *cpudata = policy->driver_data;
1154 freq = READ_ONCE(cpudata->lowest_nonlinear_freq);
1158 return sysfs_emit(buf, "%u\n", freq);
1162 * In some of ASICs, the highest_perf is not the one in the _CPC table, so we
1163 * need to expose it to sysfs.
1165 static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
1169 struct amd_cpudata *cpudata = policy->driver_data;
1171 perf = READ_ONCE(cpudata->highest_perf);
1173 return sysfs_emit(buf, "%u\n", perf);
1176 static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy,
1180 struct amd_cpudata *cpudata = policy->driver_data;
1182 perf = READ_ONCE(cpudata->prefcore_ranking);
1184 return sysfs_emit(buf, "%u\n", perf);
1187 static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy,
1191 struct amd_cpudata *cpudata = policy->driver_data;
1193 hw_prefcore = READ_ONCE(cpudata->hw_prefcore);
1195 return sysfs_emit(buf, "%s\n", str_enabled_disabled(hw_prefcore));
1198 static ssize_t show_energy_performance_available_preferences(
1199 struct cpufreq_policy *policy, char *buf)
1203 struct amd_cpudata *cpudata = policy->driver_data;
1205 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1206 return sysfs_emit_at(buf, offset, "%s\n",
1207 energy_perf_strings[EPP_INDEX_PERFORMANCE]);
1209 while (energy_perf_strings[i] != NULL)
1210 offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]);
1212 offset += sysfs_emit_at(buf, offset, "\n");
1217 static ssize_t store_energy_performance_preference(
1218 struct cpufreq_policy *policy, const char *buf, size_t count)
1220 struct amd_cpudata *cpudata = policy->driver_data;
1221 char str_preference[21];
1224 ret = sscanf(buf, "%20s", str_preference);
1228 ret = match_string(energy_perf_strings, -1, str_preference);
1232 mutex_lock(&amd_pstate_limits_lock);
1233 ret = amd_pstate_set_energy_pref_index(cpudata, ret);
1234 mutex_unlock(&amd_pstate_limits_lock);
1236 return ret ?: count;
1239 static ssize_t show_energy_performance_preference(
1240 struct cpufreq_policy *policy, char *buf)
1242 struct amd_cpudata *cpudata = policy->driver_data;
1245 preference = amd_pstate_get_energy_pref_index(cpudata);
1249 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]);
1252 static void amd_pstate_driver_cleanup(void)
1254 amd_pstate_enable(false);
1255 cppc_state = AMD_PSTATE_DISABLE;
1256 current_pstate_driver = NULL;
1259 static int amd_pstate_register_driver(int mode)
1263 if (mode == AMD_PSTATE_PASSIVE || mode == AMD_PSTATE_GUIDED)
1264 current_pstate_driver = &amd_pstate_driver;
1265 else if (mode == AMD_PSTATE_ACTIVE)
1266 current_pstate_driver = &amd_pstate_epp_driver;
1271 ret = cpufreq_register_driver(current_pstate_driver);
1273 amd_pstate_driver_cleanup();
1279 static int amd_pstate_unregister_driver(int dummy)
1281 cpufreq_unregister_driver(current_pstate_driver);
1282 amd_pstate_driver_cleanup();
1286 static int amd_pstate_change_mode_without_dvr_change(int mode)
1292 if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE)
1295 for_each_present_cpu(cpu) {
1296 cppc_set_auto_sel(cpu, (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1);
1302 static int amd_pstate_change_driver_mode(int mode)
1306 ret = amd_pstate_unregister_driver(0);
1310 ret = amd_pstate_register_driver(mode);
1317 static cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = {
1318 [AMD_PSTATE_DISABLE] = {
1319 [AMD_PSTATE_DISABLE] = NULL,
1320 [AMD_PSTATE_PASSIVE] = amd_pstate_register_driver,
1321 [AMD_PSTATE_ACTIVE] = amd_pstate_register_driver,
1322 [AMD_PSTATE_GUIDED] = amd_pstate_register_driver,
1324 [AMD_PSTATE_PASSIVE] = {
1325 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1326 [AMD_PSTATE_PASSIVE] = NULL,
1327 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode,
1328 [AMD_PSTATE_GUIDED] = amd_pstate_change_mode_without_dvr_change,
1330 [AMD_PSTATE_ACTIVE] = {
1331 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1332 [AMD_PSTATE_PASSIVE] = amd_pstate_change_driver_mode,
1333 [AMD_PSTATE_ACTIVE] = NULL,
1334 [AMD_PSTATE_GUIDED] = amd_pstate_change_driver_mode,
1336 [AMD_PSTATE_GUIDED] = {
1337 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1338 [AMD_PSTATE_PASSIVE] = amd_pstate_change_mode_without_dvr_change,
1339 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode,
1340 [AMD_PSTATE_GUIDED] = NULL,
1344 static ssize_t amd_pstate_show_status(char *buf)
1346 if (!current_pstate_driver)
1347 return sysfs_emit(buf, "disable\n");
1349 return sysfs_emit(buf, "%s\n", amd_pstate_mode_string[cppc_state]);
1352 static int amd_pstate_update_status(const char *buf, size_t size)
1356 if (size > strlen("passive") || size < strlen("active"))
1359 mode_idx = get_mode_idx_from_str(buf, size);
1361 if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX)
1364 if (mode_state_machine[cppc_state][mode_idx])
1365 return mode_state_machine[cppc_state][mode_idx](mode_idx);
1370 static ssize_t status_show(struct device *dev,
1371 struct device_attribute *attr, char *buf)
1375 mutex_lock(&amd_pstate_driver_lock);
1376 ret = amd_pstate_show_status(buf);
1377 mutex_unlock(&amd_pstate_driver_lock);
1382 static ssize_t status_store(struct device *a, struct device_attribute *b,
1383 const char *buf, size_t count)
1385 char *p = memchr(buf, '\n', count);
1388 mutex_lock(&amd_pstate_driver_lock);
1389 ret = amd_pstate_update_status(buf, p ? p - buf : count);
1390 mutex_unlock(&amd_pstate_driver_lock);
1392 return ret < 0 ? ret : count;
1395 static ssize_t prefcore_show(struct device *dev,
1396 struct device_attribute *attr, char *buf)
1398 return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore));
1401 cpufreq_freq_attr_ro(amd_pstate_max_freq);
1402 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
1404 cpufreq_freq_attr_ro(amd_pstate_highest_perf);
1405 cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking);
1406 cpufreq_freq_attr_ro(amd_pstate_hw_prefcore);
1407 cpufreq_freq_attr_rw(energy_performance_preference);
1408 cpufreq_freq_attr_ro(energy_performance_available_preferences);
1409 static DEVICE_ATTR_RW(status);
1410 static DEVICE_ATTR_RO(prefcore);
1412 static struct freq_attr *amd_pstate_attr[] = {
1413 &amd_pstate_max_freq,
1414 &amd_pstate_lowest_nonlinear_freq,
1415 &amd_pstate_highest_perf,
1416 &amd_pstate_prefcore_ranking,
1417 &amd_pstate_hw_prefcore,
1421 static struct freq_attr *amd_pstate_epp_attr[] = {
1422 &amd_pstate_max_freq,
1423 &amd_pstate_lowest_nonlinear_freq,
1424 &amd_pstate_highest_perf,
1425 &amd_pstate_prefcore_ranking,
1426 &amd_pstate_hw_prefcore,
1427 &energy_performance_preference,
1428 &energy_performance_available_preferences,
1432 static struct attribute *pstate_global_attributes[] = {
1433 &dev_attr_status.attr,
1434 &dev_attr_prefcore.attr,
1438 static const struct attribute_group amd_pstate_global_attr_group = {
1439 .name = "amd_pstate",
1440 .attrs = pstate_global_attributes,
1443 static bool amd_pstate_acpi_pm_profile_server(void)
1445 switch (acpi_gbl_FADT.preferred_profile) {
1446 case PM_ENTERPRISE_SERVER:
1447 case PM_SOHO_SERVER:
1448 case PM_PERFORMANCE_SERVER:
1454 static bool amd_pstate_acpi_pm_profile_undefined(void)
1456 if (acpi_gbl_FADT.preferred_profile == PM_UNSPECIFIED)
1458 if (acpi_gbl_FADT.preferred_profile >= NR_PM_PROFILES)
1463 static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
1465 int min_freq, max_freq, ret;
1466 struct amd_cpudata *cpudata;
1471 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
1472 * which is ideal for initialization process.
1474 amd_perf_ctl_reset(policy->cpu);
1475 dev = get_cpu_device(policy->cpu);
1479 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
1483 cpudata->cpu = policy->cpu;
1484 cpudata->epp_policy = 0;
1486 amd_pstate_init_prefcore(cpudata);
1488 ret = amd_pstate_init_perf(cpudata);
1492 ret = amd_pstate_init_freq(cpudata);
1496 ret = amd_pstate_init_boost_support(cpudata);
1500 min_freq = READ_ONCE(cpudata->min_freq);
1501 max_freq = READ_ONCE(cpudata->max_freq);
1503 policy->cpuinfo.min_freq = min_freq;
1504 policy->cpuinfo.max_freq = max_freq;
1505 /* It will be updated by governor */
1506 policy->cur = policy->cpuinfo.min_freq;
1508 policy->driver_data = cpudata;
1510 cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata, 0);
1512 policy->min = policy->cpuinfo.min_freq;
1513 policy->max = policy->cpuinfo.max_freq;
1515 policy->boost_enabled = READ_ONCE(cpudata->boost_supported);
1518 * Set the policy to provide a valid fallback value in case
1519 * the default cpufreq governor is neither powersave nor performance.
1521 if (amd_pstate_acpi_pm_profile_server() ||
1522 amd_pstate_acpi_pm_profile_undefined())
1523 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1525 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1527 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1528 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
1531 WRITE_ONCE(cpudata->cppc_req_cached, value);
1533 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
1536 WRITE_ONCE(cpudata->cppc_cap1_cached, value);
1546 static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
1548 struct amd_cpudata *cpudata = policy->driver_data;
1552 policy->driver_data = NULL;
1555 pr_debug("CPU %d exiting\n", policy->cpu);
1558 static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
1560 struct amd_cpudata *cpudata = policy->driver_data;
1561 u32 max_perf, min_perf, min_limit_perf, max_limit_perf;
1565 max_perf = READ_ONCE(cpudata->highest_perf);
1566 min_perf = READ_ONCE(cpudata->lowest_perf);
1567 max_limit_perf = div_u64(policy->max * cpudata->highest_perf, cpudata->max_freq);
1568 min_limit_perf = div_u64(policy->min * cpudata->highest_perf, cpudata->max_freq);
1570 if (min_limit_perf < min_perf)
1571 min_limit_perf = min_perf;
1573 if (max_limit_perf < min_limit_perf)
1574 max_limit_perf = min_limit_perf;
1576 WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf);
1577 WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf);
1579 max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf,
1580 cpudata->max_limit_perf);
1581 min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf,
1582 cpudata->max_limit_perf);
1583 value = READ_ONCE(cpudata->cppc_req_cached);
1585 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1586 min_perf = max_perf;
1588 /* Initial min/max values for CPPC Performance Controls Register */
1589 value &= ~AMD_CPPC_MIN_PERF(~0L);
1590 value |= AMD_CPPC_MIN_PERF(min_perf);
1592 value &= ~AMD_CPPC_MAX_PERF(~0L);
1593 value |= AMD_CPPC_MAX_PERF(max_perf);
1595 /* CPPC EPP feature require to set zero to the desire perf bit */
1596 value &= ~AMD_CPPC_DES_PERF(~0L);
1597 value |= AMD_CPPC_DES_PERF(0);
1599 cpudata->epp_policy = cpudata->policy;
1601 /* Get BIOS pre-defined epp value */
1602 epp = amd_pstate_get_epp(cpudata, value);
1605 * This return value can only be negative for shared_memory
1606 * systems where EPP register read/write not supported.
1611 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1614 /* Set initial EPP value */
1615 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1616 value &= ~GENMASK_ULL(31, 24);
1617 value |= (u64)epp << 24;
1620 WRITE_ONCE(cpudata->cppc_req_cached, value);
1621 amd_pstate_set_epp(cpudata, epp);
1624 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
1626 struct amd_cpudata *cpudata = policy->driver_data;
1628 if (!policy->cpuinfo.max_freq)
1631 pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
1632 policy->cpuinfo.max_freq, policy->max);
1634 cpudata->policy = policy->policy;
1636 amd_pstate_epp_update_limit(policy);
1639 * policy->cur is never updated with the amd_pstate_epp driver, but it
1640 * is used as a stale frequency value. So, keep it within limits.
1642 policy->cur = policy->min;
1647 static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
1649 struct cppc_perf_ctrls perf_ctrls;
1650 u64 value, max_perf;
1653 ret = amd_pstate_enable(true);
1655 pr_err("failed to enable amd pstate during resume, return %d\n", ret);
1657 value = READ_ONCE(cpudata->cppc_req_cached);
1658 max_perf = READ_ONCE(cpudata->highest_perf);
1660 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1661 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
1663 perf_ctrls.max_perf = max_perf;
1664 perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
1665 cppc_set_perf(cpudata->cpu, &perf_ctrls);
1669 static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
1671 struct amd_cpudata *cpudata = policy->driver_data;
1673 pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
1675 if (cppc_state == AMD_PSTATE_ACTIVE) {
1676 amd_pstate_epp_reenable(cpudata);
1677 cpudata->suspended = false;
1683 static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
1685 struct amd_cpudata *cpudata = policy->driver_data;
1686 struct cppc_perf_ctrls perf_ctrls;
1690 min_perf = READ_ONCE(cpudata->lowest_perf);
1691 value = READ_ONCE(cpudata->cppc_req_cached);
1693 mutex_lock(&amd_pstate_limits_lock);
1694 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1695 cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1697 /* Set max perf same as min perf */
1698 value &= ~AMD_CPPC_MAX_PERF(~0L);
1699 value |= AMD_CPPC_MAX_PERF(min_perf);
1700 value &= ~AMD_CPPC_MIN_PERF(~0L);
1701 value |= AMD_CPPC_MIN_PERF(min_perf);
1702 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
1704 perf_ctrls.desired_perf = 0;
1705 perf_ctrls.max_perf = min_perf;
1706 perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
1707 cppc_set_perf(cpudata->cpu, &perf_ctrls);
1709 mutex_unlock(&amd_pstate_limits_lock);
1712 static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
1714 struct amd_cpudata *cpudata = policy->driver_data;
1716 pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu);
1718 if (cpudata->suspended)
1721 if (cppc_state == AMD_PSTATE_ACTIVE)
1722 amd_pstate_epp_offline(policy);
1727 static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy)
1729 cpufreq_verify_within_cpu_limits(policy);
1730 pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min);
1734 static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
1736 struct amd_cpudata *cpudata = policy->driver_data;
1739 /* avoid suspending when EPP is not enabled */
1740 if (cppc_state != AMD_PSTATE_ACTIVE)
1743 /* set this flag to avoid setting core offline*/
1744 cpudata->suspended = true;
1746 /* disable CPPC in lowlevel firmware */
1747 ret = amd_pstate_enable(false);
1749 pr_err("failed to suspend, return %d\n", ret);
1754 static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
1756 struct amd_cpudata *cpudata = policy->driver_data;
1758 if (cpudata->suspended) {
1759 mutex_lock(&amd_pstate_limits_lock);
1761 /* enable amd pstate from suspend state*/
1762 amd_pstate_epp_reenable(cpudata);
1764 mutex_unlock(&amd_pstate_limits_lock);
1766 cpudata->suspended = false;
1772 static struct cpufreq_driver amd_pstate_driver = {
1773 .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
1774 .verify = amd_pstate_verify,
1775 .target = amd_pstate_target,
1776 .fast_switch = amd_pstate_fast_switch,
1777 .init = amd_pstate_cpu_init,
1778 .exit = amd_pstate_cpu_exit,
1779 .suspend = amd_pstate_cpu_suspend,
1780 .resume = amd_pstate_cpu_resume,
1781 .set_boost = amd_pstate_set_boost,
1782 .update_limits = amd_pstate_update_limits,
1783 .name = "amd-pstate",
1784 .attr = amd_pstate_attr,
1787 static struct cpufreq_driver amd_pstate_epp_driver = {
1788 .flags = CPUFREQ_CONST_LOOPS,
1789 .verify = amd_pstate_epp_verify_policy,
1790 .setpolicy = amd_pstate_epp_set_policy,
1791 .init = amd_pstate_epp_cpu_init,
1792 .exit = amd_pstate_epp_cpu_exit,
1793 .offline = amd_pstate_epp_cpu_offline,
1794 .online = amd_pstate_epp_cpu_online,
1795 .suspend = amd_pstate_epp_suspend,
1796 .resume = amd_pstate_epp_resume,
1797 .update_limits = amd_pstate_update_limits,
1798 .set_boost = amd_pstate_set_boost,
1799 .name = "amd-pstate-epp",
1800 .attr = amd_pstate_epp_attr,
1803 static int __init amd_pstate_set_driver(int mode_idx)
1805 if (mode_idx >= AMD_PSTATE_DISABLE && mode_idx < AMD_PSTATE_MAX) {
1806 cppc_state = mode_idx;
1807 if (cppc_state == AMD_PSTATE_DISABLE)
1808 pr_info("driver is explicitly disabled\n");
1810 if (cppc_state == AMD_PSTATE_ACTIVE)
1811 current_pstate_driver = &amd_pstate_epp_driver;
1813 if (cppc_state == AMD_PSTATE_PASSIVE || cppc_state == AMD_PSTATE_GUIDED)
1814 current_pstate_driver = &amd_pstate_driver;
1823 * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F.
1824 * show the debug message that helps to check if the CPU has CPPC support for loading issue.
1826 static bool amd_cppc_supported(void)
1828 struct cpuinfo_x86 *c = &cpu_data(0);
1831 if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) {
1832 pr_debug_once("CPPC feature is not supported by the processor\n");
1837 * If the CPPC feature is disabled in the BIOS for processors
1838 * that support MSR-based CPPC, the AMD Pstate driver may not
1839 * function correctly.
1841 * For such processors, check the CPPC flag and display a
1842 * warning message if the platform supports CPPC.
1844 * Note: The code check below will not abort the driver
1845 * registration process because of the code is added for
1846 * debugging purposes. Besides, it may still be possible for
1847 * the driver to work using the shared-memory mechanism.
1849 if (!cpu_feature_enabled(X86_FEATURE_CPPC)) {
1850 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) {
1851 switch (c->x86_model) {
1857 } else if (cpu_feature_enabled(X86_FEATURE_ZEN3) ||
1858 cpu_feature_enabled(X86_FEATURE_ZEN4)) {
1859 switch (c->x86_model) {
1865 } else if (cpu_feature_enabled(X86_FEATURE_ZEN5)) {
1871 pr_warn_once("The CPPC feature is supported but currently disabled by the BIOS.\n"
1872 "Please enable it if your BIOS has the CPPC option.\n");
1876 static int __init amd_pstate_init(void)
1878 struct device *dev_root;
1881 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1884 /* show debug message only if CPPC is not supported */
1885 if (!amd_cppc_supported())
1888 /* show warning message when BIOS broken or ACPI disabled */
1889 if (!acpi_cpc_valid()) {
1890 pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n");
1894 /* don't keep reloading if cpufreq_driver exists */
1895 if (cpufreq_get_current_driver())
1900 /* check if this machine need CPPC quirks */
1901 dmi_check_system(amd_pstate_quirks_table);
1904 * determine the driver mode from the command line or kernel config.
1905 * If no command line input is provided, cppc_state will be AMD_PSTATE_UNDEFINED.
1906 * command line options will override the kernel config settings.
1909 if (cppc_state == AMD_PSTATE_UNDEFINED) {
1910 /* Disable on the following configs by default:
1911 * 1. Undefined platforms
1912 * 2. Server platforms
1914 if (amd_pstate_acpi_pm_profile_undefined() ||
1915 amd_pstate_acpi_pm_profile_server()) {
1916 pr_info("driver load is disabled, boot with specific mode to enable this\n");
1919 /* get driver mode from kernel config option [1:4] */
1920 cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE;
1923 switch (cppc_state) {
1924 case AMD_PSTATE_DISABLE:
1925 pr_info("driver load is disabled, boot with specific mode to enable this\n");
1927 case AMD_PSTATE_PASSIVE:
1928 case AMD_PSTATE_ACTIVE:
1929 case AMD_PSTATE_GUIDED:
1930 ret = amd_pstate_set_driver(cppc_state);
1938 /* capability check */
1939 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1940 pr_debug("AMD CPPC MSR based functionality is supported\n");
1941 if (cppc_state != AMD_PSTATE_ACTIVE)
1942 current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
1944 pr_debug("AMD CPPC shared memory based functionality is supported\n");
1945 static_call_update(amd_pstate_enable, cppc_enable);
1946 static_call_update(amd_pstate_init_perf, cppc_init_perf);
1947 static_call_update(amd_pstate_update_perf, cppc_update_perf);
1950 /* enable amd pstate feature */
1951 ret = amd_pstate_enable(true);
1953 pr_err("failed to enable driver mode(%d)\n", cppc_state);
1957 ret = cpufreq_register_driver(current_pstate_driver);
1959 pr_err("failed to register with return %d\n", ret);
1960 goto disable_driver;
1963 dev_root = bus_get_dev_root(&cpu_subsys);
1965 ret = sysfs_create_group(&dev_root->kobj, &amd_pstate_global_attr_group);
1966 put_device(dev_root);
1968 pr_err("sysfs attribute export failed with error %d.\n", ret);
1969 goto global_attr_free;
1976 cpufreq_unregister_driver(current_pstate_driver);
1978 amd_pstate_enable(false);
1981 device_initcall(amd_pstate_init);
1983 static int __init amd_pstate_param(char *str)
1992 mode_idx = get_mode_idx_from_str(str, size);
1994 return amd_pstate_set_driver(mode_idx);
1997 static int __init amd_prefcore_param(char *str)
1999 if (!strcmp(str, "disable"))
2000 amd_pstate_prefcore = false;
2005 early_param("amd_pstate", amd_pstate_param);
2006 early_param("amd_prefcore", amd_prefcore_param);
2009 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");