1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
4 * such as Graviton and Alpine)
6 * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
11 #include <linux/pci.h>
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
14 #include "../../pci.h"
16 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
19 void __iomem *dbi_base;
22 static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
25 struct pci_config_window *cfg = bus->sysdata;
26 struct al_pcie_acpi *pcie = cfg->priv;
27 void __iomem *dbi_base = pcie->dbi_base;
29 if (bus->number == cfg->busr.start) {
31 * The DW PCIe core doesn't filter out transactions to other
32 * devices/functions on the root bus num, so we do this here.
34 if (PCI_SLOT(devfn) > 0)
37 return dbi_base + where;
40 return pci_ecam_map_bus(bus, devfn, where);
43 static int al_pcie_init(struct pci_config_window *cfg)
45 struct device *dev = cfg->parent;
46 struct acpi_device *adev = to_acpi_device(dev);
47 struct acpi_pci_root *root = acpi_driver_data(adev);
48 struct al_pcie_acpi *al_pcie;
52 al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
56 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
60 ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);
62 dev_err(dev, "can't get rc dbi base address for SEG %d\n",
67 dev_dbg(dev, "Root port dbi res: %pR\n", res);
69 al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);
70 if (IS_ERR(al_pcie->dbi_base)) {
71 long err = PTR_ERR(al_pcie->dbi_base);
73 dev_err(dev, "couldn't remap dbi base %pR (err:%ld)\n",
83 struct pci_ecam_ops al_pcie_ops = {
87 .map_bus = al_pcie_map_bus,
88 .read = pci_generic_config_read,
89 .write = pci_generic_config_write,
93 #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */