drivers/gpu/drm/omapdrm/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <[email protected]>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/err.h>
  30 #include <linux/delay.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/clk.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/gfp.h>
  37 #include <linux/sizes.h>
  38 #include <linux/mfd/syscon.h>
  39 #include <linux/regmap.h>
  40 #include <linux/of.h>
  41 #include <linux/regulator/consumer.h>
  42 #include <linux/suspend.h>
  43 #include <linux/component.h>
  44
  45 #include <video/omapdss.h>
  46
  47 #include "dss.h"
  48 #include "dss_features.h"
  49
  50 #define DSS_SZ_REGS                     SZ_512
  51
  52 struct dss_reg {
  53         u16 idx;
  54 };
  55
  56 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  57
  58 #define DSS_REVISION                    DSS_REG(0x0000)
  59 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  60 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  61 #define DSS_CONTROL                     DSS_REG(0x0040)
  62 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  63 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  64 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  65
  66 #define REG_GET(idx, start, end) \
  67         FLD_GET(dss_read_reg(idx), start, end)
  68
  69 #define REG_FLD_MOD(idx, val, start, end) \
  70         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  71
  72 struct dss_features {
  73         u8 fck_div_max;
  74         u8 dss_fck_multiplier;
  75         const char *parent_clk_name;
  76         const enum omap_display_type *ports;
  77         int num_ports;
  78         int (*dpi_select_source)(int port, enum omap_channel channel);
  79 };
  80
  81 static struct {
  82         struct platform_device *pdev;
  83         void __iomem    *base;
  84         struct regmap   *syscon_pll_ctrl;
  85         u32             syscon_pll_ctrl_offset;
  86
  87         struct clk      *parent_clk;
  88         struct clk      *dss_clk;
  89         unsigned long   dss_clk_rate;
  90
  91         unsigned long   cache_req_pck;
  92         unsigned long   cache_prate;
  93         struct dispc_clock_info cache_dispc_cinfo;
  94
  95         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  96         enum omap_dss_clk_source dispc_clk_source;
  97         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  98
  99         bool            ctx_valid;
 100         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
 101
 102         const struct dss_features *feat;
 103
 104         struct dss_pll  *video1_pll;
 105         struct dss_pll  *video2_pll;
 106 } dss;
 107
 108 static const char * const dss_generic_clk_source_names[] = {
 109         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
 110         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
 111         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 112         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 113         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 114 };
 115
 116 static bool dss_initialized;
 117
 118 bool omapdss_is_initialized(void)
 119 {
 120         return dss_initialized;
 121 }
 122 EXPORT_SYMBOL(omapdss_is_initialized);
 123
 124 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 125 {
 126         __raw_writel(val, dss.base + idx.idx);
 127 }
 128
 129 static inline u32 dss_read_reg(const struct dss_reg idx)
 130 {
 131         return __raw_readl(dss.base + idx.idx);
 132 }
 133
 134 #define SR(reg) \
 135         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 136 #define RR(reg) \
 137         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 138
 139 static void dss_save_context(void)
 140 {
 141         DSSDBG("dss_save_context\n");
 142
 143         SR(CONTROL);
 144
 145         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 146                         OMAP_DISPLAY_TYPE_SDI) {
 147                 SR(SDI_CONTROL);
 148                 SR(PLL_CONTROL);
 149         }
 150
 151         dss.ctx_valid = true;
 152
 153         DSSDBG("context saved\n");
 154 }
 155
 156 static void dss_restore_context(void)
 157 {
 158         DSSDBG("dss_restore_context\n");
 159
 160         if (!dss.ctx_valid)
 161                 return;
 162
 163         RR(CONTROL);
 164
 165         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 166                         OMAP_DISPLAY_TYPE_SDI) {
 167                 RR(SDI_CONTROL);
 168                 RR(PLL_CONTROL);
 169         }
 170
 171         DSSDBG("context restored\n");
 172 }
 173
 174 #undef SR
 175 #undef RR
 176
 177 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
 178 {
 179         unsigned shift;
 180         unsigned val;
 181
 182         if (!dss.syscon_pll_ctrl)
 183                 return;
 184
 185         val = !enable;
 186
 187         switch (pll_id) {
 188         case DSS_PLL_VIDEO1:
 189                 shift = 0;
 190                 break;
 191         case DSS_PLL_VIDEO2:
 192                 shift = 1;
 193                 break;
 194         case DSS_PLL_HDMI:
 195                 shift = 2;
 196                 break;
 197         default:
 198                 DSSERR("illegal DSS PLL ID %d\n", pll_id);
 199                 return;
 200         }
 201
 202         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 203                 1 << shift, val << shift);
 204 }
 205
 206 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
 207         enum omap_channel channel)
 208 {
 209         unsigned shift, val;
 210
 211         if (!dss.syscon_pll_ctrl)
 212                 return;
 213
 214         switch (channel) {
 215         case OMAP_DSS_CHANNEL_LCD:
 216                 shift = 3;
 217
 218                 switch (pll_id) {
 219                 case DSS_PLL_VIDEO1:
 220                         val = 0; break;
 221                 case DSS_PLL_HDMI:
 222                         val = 1; break;
 223                 default:
 224                         DSSERR("error in PLL mux config for LCD\n");
 225                         return;
 226                 }
 227
 228                 break;
 229         case OMAP_DSS_CHANNEL_LCD2:
 230                 shift = 5;
 231
 232                 switch (pll_id) {
 233                 case DSS_PLL_VIDEO1:
 234                         val = 0; break;
 235                 case DSS_PLL_VIDEO2:
 236                         val = 1; break;
 237                 case DSS_PLL_HDMI:
 238                         val = 2; break;
 239                 default:
 240                         DSSERR("error in PLL mux config for LCD2\n");
 241                         return;
 242                 }
 243
 244                 break;
 245         case OMAP_DSS_CHANNEL_LCD3:
 246                 shift = 7;
 247
 248                 switch (pll_id) {
 249                 case DSS_PLL_VIDEO1:
 250                         val = 1; break;
 251                 case DSS_PLL_VIDEO2:
 252                         val = 0; break;
 253                 case DSS_PLL_HDMI:
 254                         val = 2; break;
 255                 default:
 256                         DSSERR("error in PLL mux config for LCD3\n");
 257                         return;
 258                 }
 259
 260                 break;
 261         default:
 262                 DSSERR("error in PLL mux config\n");
 263                 return;
 264         }
 265
 266         regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
 267                 0x3 << shift, val << shift);
 268 }
 269
 270 void dss_sdi_init(int datapairs)
 271 {
 272         u32 l;
 273
 274         BUG_ON(datapairs > 3 || datapairs < 1);
 275
 276         l = dss_read_reg(DSS_SDI_CONTROL);
 277         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 278         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 279         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 280         dss_write_reg(DSS_SDI_CONTROL, l);
 281
 282         l = dss_read_reg(DSS_PLL_CONTROL);
 283         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 284         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 285         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 286         dss_write_reg(DSS_PLL_CONTROL, l);
 287 }
 288
 289 int dss_sdi_enable(void)
 290 {
 291         unsigned long timeout;
 292
 293         dispc_pck_free_enable(1);
 294
 295         /* Reset SDI PLL */
 296         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 297         udelay(1);      /* wait 2x PCLK */
 298
 299         /* Lock SDI PLL */
 300         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 301
 302         /* Waiting for PLL lock request to complete */
 303         timeout = jiffies + msecs_to_jiffies(500);
 304         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 305                 if (time_after_eq(jiffies, timeout)) {
 306                         DSSERR("PLL lock request timed out\n");
 307                         goto err1;
 308                 }
 309         }
 310
 311         /* Clearing PLL_GO bit */
 312         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 313
 314         /* Waiting for PLL to lock */
 315         timeout = jiffies + msecs_to_jiffies(500);
 316         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 317                 if (time_after_eq(jiffies, timeout)) {
 318                         DSSERR("PLL lock timed out\n");
 319                         goto err1;
 320                 }
 321         }
 322
 323         dispc_lcd_enable_signal(1);
 324
 325         /* Waiting for SDI reset to complete */
 326         timeout = jiffies + msecs_to_jiffies(500);
 327         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 328                 if (time_after_eq(jiffies, timeout)) {
 329                         DSSERR("SDI reset timed out\n");
 330                         goto err2;
 331                 }
 332         }
 333
 334         return 0;
 335
 336  err2:
 337         dispc_lcd_enable_signal(0);
 338  err1:
 339         /* Reset SDI PLL */
 340         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 341
 342         dispc_pck_free_enable(0);
 343
 344         return -ETIMEDOUT;
 345 }
 346
 347 void dss_sdi_disable(void)
 348 {
 349         dispc_lcd_enable_signal(0);
 350
 351         dispc_pck_free_enable(0);
 352
 353         /* Reset SDI PLL */
 354         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 355 }
 356
 357 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 358 {
 359         return dss_generic_clk_source_names[clk_src];
 360 }
 361
 362 void dss_dump_clocks(struct seq_file *s)
 363 {
 364         const char *fclk_name, *fclk_real_name;
 365         unsigned long fclk_rate;
 366
 367         if (dss_runtime_get())
 368                 return;
 369
 370         seq_printf(s, "- DSS -\n");
 371
 372         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 373         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 374         fclk_rate = clk_get_rate(dss.dss_clk);
 375
 376         seq_printf(s, "%s (%s) = %lu\n",
 377                         fclk_name, fclk_real_name,
 378                         fclk_rate);
 379
 380         dss_runtime_put();
 381 }
 382
 383 static void dss_dump_regs(struct seq_file *s)
 384 {
 385 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 386
 387         if (dss_runtime_get())
 388                 return;
 389
 390         DUMPREG(DSS_REVISION);
 391         DUMPREG(DSS_SYSCONFIG);
 392         DUMPREG(DSS_SYSSTATUS);
 393         DUMPREG(DSS_CONTROL);
 394
 395         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 396                         OMAP_DISPLAY_TYPE_SDI) {
 397                 DUMPREG(DSS_SDI_CONTROL);
 398                 DUMPREG(DSS_PLL_CONTROL);
 399                 DUMPREG(DSS_SDI_STATUS);
 400         }
 401
 402         dss_runtime_put();
 403 #undef DUMPREG
 404 }
 405
 406 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 407 {
 408         int b;
 409         u8 start, end;
 410
 411         switch (clk_src) {
 412         case OMAP_DSS_CLK_SRC_FCK:
 413                 b = 0;
 414                 break;
 415         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 416                 b = 1;
 417                 break;
 418         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 419                 b = 2;
 420                 break;
 421         default:
 422                 BUG();
 423                 return;
 424         }
 425
 426         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 427
 428         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 429
 430         dss.dispc_clk_source = clk_src;
 431 }
 432
 433 void dss_select_dsi_clk_source(int dsi_module,
 434                 enum omap_dss_clk_source clk_src)
 435 {
 436         int b, pos;
 437
 438         switch (clk_src) {
 439         case OMAP_DSS_CLK_SRC_FCK:
 440                 b = 0;
 441                 break;
 442         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 443                 BUG_ON(dsi_module != 0);
 444                 b = 1;
 445                 break;
 446         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 447                 BUG_ON(dsi_module != 1);
 448                 b = 1;
 449                 break;
 450         default:
 451                 BUG();
 452                 return;
 453         }
 454
 455         pos = dsi_module == 0 ? 1 : 10;
 456         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 457
 458         dss.dsi_clk_source[dsi_module] = clk_src;
 459 }
 460
 461 void dss_select_lcd_clk_source(enum omap_channel channel,
 462                 enum omap_dss_clk_source clk_src)
 463 {
 464         int b, ix, pos;
 465
 466         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 467                 dss_select_dispc_clk_source(clk_src);
 468                 return;
 469         }
 470
 471         switch (clk_src) {
 472         case OMAP_DSS_CLK_SRC_FCK:
 473                 b = 0;
 474                 break;
 475         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 476                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 477                 b = 1;
 478                 break;
 479         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 480                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 481                        channel != OMAP_DSS_CHANNEL_LCD3);
 482                 b = 1;
 483                 break;
 484         default:
 485                 BUG();
 486                 return;
 487         }
 488
 489         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 490              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 491         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 492
 493         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 494             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 495         dss.lcd_clk_source[ix] = clk_src;
 496 }
 497
 498 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 499 {
 500         return dss.dispc_clk_source;
 501 }
 502
 503 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 504 {
 505         return dss.dsi_clk_source[dsi_module];
 506 }
 507
 508 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 509 {
 510         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 511                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 512                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 513                 return dss.lcd_clk_source[ix];
 514         } else {
 515                 /* LCD_CLK source is the same as DISPC_FCLK source for
 516                  * OMAP2 and OMAP3 */
 517                 return dss.dispc_clk_source;
 518         }
 519 }
 520
 521 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 522                 dss_div_calc_func func, void *data)
 523 {
 524         int fckd, fckd_start, fckd_stop;
 525         unsigned long fck;
 526         unsigned long fck_hw_max;
 527         unsigned long fckd_hw_max;
 528         unsigned long prate;
 529         unsigned m;
 530
 531         fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 532
 533         if (dss.parent_clk == NULL) {
 534                 unsigned pckd;
 535
 536                 pckd = fck_hw_max / pck;
 537
 538                 fck = pck * pckd;
 539
 540                 fck = clk_round_rate(dss.dss_clk, fck);
 541
 542                 return func(fck, data);
 543         }
 544
 545         fckd_hw_max = dss.feat->fck_div_max;
 546
 547         m = dss.feat->dss_fck_multiplier;
 548         prate = clk_get_rate(dss.parent_clk);
 549
 550         fck_min = fck_min ? fck_min : 1;
 551
 552         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 553         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 554
 555         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 556                 fck = DIV_ROUND_UP(prate, fckd) * m;
 557
 558                 if (func(fck, data))
 559                         return true;
 560         }
 561
 562         return false;
 563 }
 564
 565 int dss_set_fck_rate(unsigned long rate)
 566 {
 567         int r;
 568
 569         DSSDBG("set fck to %lu\n", rate);
 570
 571         r = clk_set_rate(dss.dss_clk, rate);
 572         if (r)
 573                 return r;
 574
 575         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 576
 577         WARN_ONCE(dss.dss_clk_rate != rate,
 578                         "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
 579                         rate);
 580
 581         return 0;
 582 }
 583
 584 unsigned long dss_get_dispc_clk_rate(void)
 585 {
 586         return dss.dss_clk_rate;
 587 }
 588
 589 static int dss_setup_default_clock(void)
 590 {
 591         unsigned long max_dss_fck, prate;
 592         unsigned long fck;
 593         unsigned fck_div;
 594         int r;
 595
 596         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 597
 598         if (dss.parent_clk == NULL) {
 599                 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
 600         } else {
 601                 prate = clk_get_rate(dss.parent_clk);
 602
 603                 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 604                                 max_dss_fck);
 605                 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
 606         }
 607
 608         r = dss_set_fck_rate(fck);
 609         if (r)
 610                 return r;
 611
 612         return 0;
 613 }
 614
 615 void dss_set_venc_output(enum omap_dss_venc_type type)
 616 {
 617         int l = 0;
 618
 619         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 620                 l = 0;
 621         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 622                 l = 1;
 623         else
 624                 BUG();
 625
 626         /* venc out selection. 0 = comp, 1 = svideo */
 627         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 628 }
 629
 630 void dss_set_dac_pwrdn_bgz(bool enable)
 631 {
 632         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 633 }
 634
 635 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 636 {
 637         enum omap_display_type dp;
 638         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 639
 640         /* Complain about invalid selections */
 641         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 642         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 643
 644         /* Select only if we have options */
 645         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 646                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 647 }
 648
 649 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 650 {
 651         enum omap_display_type displays;
 652
 653         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 654         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 655                 return DSS_VENC_TV_CLK;
 656
 657         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 658                 return DSS_HDMI_M_PCLK;
 659
 660         return REG_GET(DSS_CONTROL, 15, 15);
 661 }
 662
 663 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
 664 {
 665         if (channel != OMAP_DSS_CHANNEL_LCD)
 666                 return -EINVAL;
 667
 668         return 0;
 669 }
 670
 671 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
 672 {
 673         int val;
 674
 675         switch (channel) {
 676         case OMAP_DSS_CHANNEL_LCD2:
 677                 val = 0;
 678                 break;
 679         case OMAP_DSS_CHANNEL_DIGIT:
 680                 val = 1;
 681                 break;
 682         default:
 683                 return -EINVAL;
 684         }
 685
 686         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 687
 688         return 0;
 689 }
 690
 691 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
 692 {
 693         int val;
 694
 695         switch (channel) {
 696         case OMAP_DSS_CHANNEL_LCD:
 697                 val = 1;
 698                 break;
 699         case OMAP_DSS_CHANNEL_LCD2:
 700                 val = 2;
 701                 break;
 702         case OMAP_DSS_CHANNEL_LCD3:
 703                 val = 3;
 704                 break;
 705         case OMAP_DSS_CHANNEL_DIGIT:
 706                 val = 0;
 707                 break;
 708         default:
 709                 return -EINVAL;
 710         }
 711
 712         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 713
 714         return 0;
 715 }
 716
 717 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
 718 {
 719         switch (port) {
 720         case 0:
 721                 return dss_dpi_select_source_omap5(port, channel);
 722         case 1:
 723                 if (channel != OMAP_DSS_CHANNEL_LCD2)
 724                         return -EINVAL;
 725                 break;
 726         case 2:
 727                 if (channel != OMAP_DSS_CHANNEL_LCD3)
 728                         return -EINVAL;
 729                 break;
 730         default:
 731                 return -EINVAL;
 732         }
 733
 734         return 0;
 735 }
 736
 737 int dss_dpi_select_source(int port, enum omap_channel channel)
 738 {
 739         return dss.feat->dpi_select_source(port, channel);
 740 }
 741
 742 static int dss_get_clocks(void)
 743 {
 744         struct clk *clk;
 745
 746         clk = devm_clk_get(&dss.pdev->dev, "fck");
 747         if (IS_ERR(clk)) {
 748                 DSSERR("can't get clock fck\n");
 749                 return PTR_ERR(clk);
 750         }
 751
 752         dss.dss_clk = clk;
 753
 754         if (dss.feat->parent_clk_name) {
 755                 clk = clk_get(NULL, dss.feat->parent_clk_name);
 756                 if (IS_ERR(clk)) {
 757                         DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
 758                         return PTR_ERR(clk);
 759                 }
 760         } else {
 761                 clk = NULL;
 762         }
 763
 764         dss.parent_clk = clk;
 765
 766         return 0;
 767 }
 768
 769 static void dss_put_clocks(void)
 770 {
 771         if (dss.parent_clk)
 772                 clk_put(dss.parent_clk);
 773 }
 774
 775 int dss_runtime_get(void)
 776 {
 777         int r;
 778
 779         DSSDBG("dss_runtime_get\n");
 780
 781         r = pm_runtime_get_sync(&dss.pdev->dev);
 782         WARN_ON(r < 0);
 783         return r < 0 ? r : 0;
 784 }
 785
 786 void dss_runtime_put(void)
 787 {
 788         int r;
 789
 790         DSSDBG("dss_runtime_put\n");
 791
 792         r = pm_runtime_put_sync(&dss.pdev->dev);
 793         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 794 }
 795
 796 /* DEBUGFS */
 797 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 798 void dss_debug_dump_clocks(struct seq_file *s)
 799 {
 800         dss_dump_clocks(s);
 801         dispc_dump_clocks(s);
 802 #ifdef CONFIG_OMAP2_DSS_DSI
 803         dsi_dump_clocks(s);
 804 #endif
 805 }
 806 #endif
 807
 808
 809 static const enum omap_display_type omap2plus_ports[] = {
 810         OMAP_DISPLAY_TYPE_DPI,
 811 };
 812
 813 static const enum omap_display_type omap34xx_ports[] = {
 814         OMAP_DISPLAY_TYPE_DPI,
 815         OMAP_DISPLAY_TYPE_SDI,
 816 };
 817
 818 static const enum omap_display_type dra7xx_ports[] = {
 819         OMAP_DISPLAY_TYPE_DPI,
 820         OMAP_DISPLAY_TYPE_DPI,
 821         OMAP_DISPLAY_TYPE_DPI,
 822 };
 823
 824 static const struct dss_features omap24xx_dss_feats = {
 825         /*
 826          * fck div max is really 16, but the divider range has gaps. The range
 827          * from 1 to 6 has no gaps, so let's use that as a max.
 828          */
 829         .fck_div_max            =       6,
 830         .dss_fck_multiplier     =       2,
 831         .parent_clk_name        =       "core_ck",
 832         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 833         .ports                  =       omap2plus_ports,
 834         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 835 };
 836
 837 static const struct dss_features omap34xx_dss_feats = {
 838         .fck_div_max            =       16,
 839         .dss_fck_multiplier     =       2,
 840         .parent_clk_name        =       "dpll4_ck",
 841         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 842         .ports                  =       omap34xx_ports,
 843         .num_ports              =       ARRAY_SIZE(omap34xx_ports),
 844 };
 845
 846 static const struct dss_features omap3630_dss_feats = {
 847         .fck_div_max            =       32,
 848         .dss_fck_multiplier     =       1,
 849         .parent_clk_name        =       "dpll4_ck",
 850         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 851         .ports                  =       omap2plus_ports,
 852         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 853 };
 854
 855 static const struct dss_features omap44xx_dss_feats = {
 856         .fck_div_max            =       32,
 857         .dss_fck_multiplier     =       1,
 858         .parent_clk_name        =       "dpll_per_x2_ck",
 859         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 860         .ports                  =       omap2plus_ports,
 861         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 862 };
 863
 864 static const struct dss_features omap54xx_dss_feats = {
 865         .fck_div_max            =       64,
 866         .dss_fck_multiplier     =       1,
 867         .parent_clk_name        =       "dpll_per_x2_ck",
 868         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 869         .ports                  =       omap2plus_ports,
 870         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 871 };
 872
 873 static const struct dss_features am43xx_dss_feats = {
 874         .fck_div_max            =       0,
 875         .dss_fck_multiplier     =       0,
 876         .parent_clk_name        =       NULL,
 877         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 878         .ports                  =       omap2plus_ports,
 879         .num_ports              =       ARRAY_SIZE(omap2plus_ports),
 880 };
 881
 882 static const struct dss_features dra7xx_dss_feats = {
 883         .fck_div_max            =       64,
 884         .dss_fck_multiplier     =       1,
 885         .parent_clk_name        =       "dpll_per_x2_ck",
 886         .dpi_select_source      =       &dss_dpi_select_source_dra7xx,
 887         .ports                  =       dra7xx_ports,
 888         .num_ports              =       ARRAY_SIZE(dra7xx_ports),
 889 };
 890
 891 static int dss_init_features(struct platform_device *pdev)
 892 {
 893         const struct dss_features *src;
 894         struct dss_features *dst;
 895
 896         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 897         if (!dst) {
 898                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 899                 return -ENOMEM;
 900         }
 901
 902         switch (omapdss_get_version()) {
 903         case OMAPDSS_VER_OMAP24xx:
 904                 src = &omap24xx_dss_feats;
 905                 break;
 906
 907         case OMAPDSS_VER_OMAP34xx_ES1:
 908         case OMAPDSS_VER_OMAP34xx_ES3:
 909         case OMAPDSS_VER_AM35xx:
 910                 src = &omap34xx_dss_feats;
 911                 break;
 912
 913         case OMAPDSS_VER_OMAP3630:
 914                 src = &omap3630_dss_feats;
 915                 break;
 916
 917         case OMAPDSS_VER_OMAP4430_ES1:
 918         case OMAPDSS_VER_OMAP4430_ES2:
 919         case OMAPDSS_VER_OMAP4:
 920                 src = &omap44xx_dss_feats;
 921                 break;
 922
 923         case OMAPDSS_VER_OMAP5:
 924                 src = &omap54xx_dss_feats;
 925                 break;
 926
 927         case OMAPDSS_VER_AM43xx:
 928                 src = &am43xx_dss_feats;
 929                 break;
 930
 931         case OMAPDSS_VER_DRA7xx:
 932                 src = &dra7xx_dss_feats;
 933                 break;
 934
 935         default:
 936                 return -ENODEV;
 937         }
 938
 939         memcpy(dst, src, sizeof(*dst));
 940         dss.feat = dst;
 941
 942         return 0;
 943 }
 944
 945 static int dss_init_ports(struct platform_device *pdev)
 946 {
 947         struct device_node *parent = pdev->dev.of_node;
 948         struct device_node *port;
 949         int r;
 950
 951         if (parent == NULL)
 952                 return 0;
 953
 954         port = omapdss_of_get_next_port(parent, NULL);
 955         if (!port)
 956                 return 0;
 957
 958         if (dss.feat->num_ports == 0)
 959                 return 0;
 960
 961         do {
 962                 enum omap_display_type port_type;
 963                 u32 reg;
 964
 965                 r = of_property_read_u32(port, "reg", &reg);
 966                 if (r)
 967                         reg = 0;
 968
 969                 if (reg >= dss.feat->num_ports)
 970                         continue;
 971
 972                 port_type = dss.feat->ports[reg];
 973
 974                 switch (port_type) {
 975                 case OMAP_DISPLAY_TYPE_DPI:
 976                         dpi_init_port(pdev, port);
 977                         break;
 978                 case OMAP_DISPLAY_TYPE_SDI:
 979                         sdi_init_port(pdev, port);
 980                         break;
 981                 default:
 982                         break;
 983                 }
 984         } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
 985
 986         return 0;
 987 }
 988
 989 static void dss_uninit_ports(struct platform_device *pdev)
 990 {
 991         struct device_node *parent = pdev->dev.of_node;
 992         struct device_node *port;
 993
 994         if (parent == NULL)
 995                 return;
 996
 997         port = omapdss_of_get_next_port(parent, NULL);
 998         if (!port)
 999                 return;
1000
1001         if (dss.feat->num_ports == 0)
1002                 return;
1003
1004         do {
1005                 enum omap_display_type port_type;
1006                 u32 reg;
1007                 int r;
1008
1009                 r = of_property_read_u32(port, "reg", &reg);
1010                 if (r)
1011                         reg = 0;
1012
1013                 if (reg >= dss.feat->num_ports)
1014                         continue;
1015
1016                 port_type = dss.feat->ports[reg];
1017
1018                 switch (port_type) {
1019                 case OMAP_DISPLAY_TYPE_DPI:
1020                         dpi_uninit_port(port);
1021                         break;
1022                 case OMAP_DISPLAY_TYPE_SDI:
1023                         sdi_uninit_port(port);
1024                         break;
1025                 default:
1026                         break;
1027                 }
1028         } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
1029 }
1030
1031 static int dss_video_pll_probe(struct platform_device *pdev)
1032 {
1033         struct device_node *np = pdev->dev.of_node;
1034         struct regulator *pll_regulator;
1035         int r;
1036
1037         if (!np)
1038                 return 0;
1039
1040         if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1041                 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1042                         "syscon-pll-ctrl");
1043                 if (IS_ERR(dss.syscon_pll_ctrl)) {
1044                         dev_err(&pdev->dev,
1045                                 "failed to get syscon-pll-ctrl regmap\n");
1046                         return PTR_ERR(dss.syscon_pll_ctrl);
1047                 }
1048
1049                 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1050                                 &dss.syscon_pll_ctrl_offset)) {
1051                         dev_err(&pdev->dev,
1052                                 "failed to get syscon-pll-ctrl offset\n");
1053                         return -EINVAL;
1054                 }
1055         }
1056
1057         pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
1058         if (IS_ERR(pll_regulator)) {
1059                 r = PTR_ERR(pll_regulator);
1060
1061                 switch (r) {
1062                 case -ENOENT:
1063                         pll_regulator = NULL;
1064                         break;
1065
1066                 case -EPROBE_DEFER:
1067                         return -EPROBE_DEFER;
1068
1069                 default:
1070                         DSSERR("can't get DPLL VDDA regulator\n");
1071                         return r;
1072                 }
1073         }
1074
1075         if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1076                 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
1077                 if (IS_ERR(dss.video1_pll))
1078                         return PTR_ERR(dss.video1_pll);
1079         }
1080
1081         if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1082                 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
1083                 if (IS_ERR(dss.video2_pll)) {
1084                         dss_video_pll_uninit(dss.video1_pll);
1085                         return PTR_ERR(dss.video2_pll);
1086                 }
1087         }
1088
1089         return 0;
1090 }
1091
1092 /* DSS HW IP initialisation */
1093 static int dss_bind(struct device *dev)
1094 {
1095         struct platform_device *pdev = to_platform_device(dev);
1096         struct resource *dss_mem;
1097         u32 rev;
1098         int r;
1099
1100         dss.pdev = pdev;
1101
1102         r = dss_init_features(dss.pdev);
1103         if (r)
1104                 return r;
1105
1106         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1107         if (!dss_mem) {
1108                 DSSERR("can't get IORESOURCE_MEM DSS\n");
1109                 return -EINVAL;
1110         }
1111
1112         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
1113                                 resource_size(dss_mem));
1114         if (!dss.base) {
1115                 DSSERR("can't ioremap DSS\n");
1116                 return -ENOMEM;
1117         }
1118
1119         r = dss_get_clocks();
1120         if (r)
1121                 return r;
1122
1123         r = dss_setup_default_clock();
1124         if (r)
1125                 goto err_setup_clocks;
1126
1127         r = dss_video_pll_probe(pdev);
1128         if (r)
1129                 goto err_pll_init;
1130
1131         r = dss_init_ports(pdev);
1132         if (r)
1133                 goto err_init_ports;
1134
1135         pm_runtime_enable(&pdev->dev);
1136
1137         r = dss_runtime_get();
1138         if (r)
1139                 goto err_runtime_get;
1140
1141         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1142
1143         /* Select DPLL */
1144         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1145
1146         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
1147
1148 #ifdef CONFIG_OMAP2_DSS_VENC
1149         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
1150         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
1151         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
1152 #endif
1153         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1154         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1155         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
1156         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1157         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1158
1159         rev = dss_read_reg(DSS_REVISION);
1160         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
1161                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1162
1163         dss_runtime_put();
1164
1165         r = component_bind_all(&pdev->dev, NULL);
1166         if (r)
1167                 goto err_component;
1168
1169         dss_debugfs_create_file("dss", dss_dump_regs);
1170
1171         pm_set_vt_switch(0);
1172
1173         dss_initialized = true;
1174
1175         return 0;
1176
1177 err_component:
1178 err_runtime_get:
1179         pm_runtime_disable(&pdev->dev);
1180         dss_uninit_ports(pdev);
1181 err_init_ports:
1182         if (dss.video1_pll)
1183                 dss_video_pll_uninit(dss.video1_pll);
1184
1185         if (dss.video2_pll)
1186                 dss_video_pll_uninit(dss.video2_pll);
1187 err_pll_init:
1188 err_setup_clocks:
1189         dss_put_clocks();
1190         return r;
1191 }
1192
1193 static void dss_unbind(struct device *dev)
1194 {
1195         struct platform_device *pdev = to_platform_device(dev);
1196
1197         dss_initialized = false;
1198
1199         component_unbind_all(&pdev->dev, NULL);
1200
1201         if (dss.video1_pll)
1202                 dss_video_pll_uninit(dss.video1_pll);
1203
1204         if (dss.video2_pll)
1205                 dss_video_pll_uninit(dss.video2_pll);
1206
1207         dss_uninit_ports(pdev);
1208
1209         pm_runtime_disable(&pdev->dev);
1210
1211         dss_put_clocks();
1212 }
1213
1214 static const struct component_master_ops dss_component_ops = {
1215         .bind = dss_bind,
1216         .unbind = dss_unbind,
1217 };
1218
1219 static int dss_component_compare(struct device *dev, void *data)
1220 {
1221         struct device *child = data;
1222         return dev == child;
1223 }
1224
1225 static int dss_add_child_component(struct device *dev, void *data)
1226 {
1227         struct component_match **match = data;
1228
1229         /*
1230          * HACK
1231          * We don't have a working driver for rfbi, so skip it here always.
1232          * Otherwise dss will never get probed successfully, as it will wait
1233          * for rfbi to get probed.
1234          */
1235         if (strstr(dev_name(dev), "rfbi"))
1236                 return 0;
1237
1238         component_match_add(dev->parent, match, dss_component_compare, dev);
1239
1240         return 0;
1241 }
1242
1243 static int dss_probe(struct platform_device *pdev)
1244 {
1245         struct component_match *match = NULL;
1246         int r;
1247
1248         /* add all the child devices as components */
1249         device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1250
1251         r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1252         if (r)
1253                 return r;
1254
1255         return 0;
1256 }
1257
1258 static int dss_remove(struct platform_device *pdev)
1259 {
1260         component_master_del(&pdev->dev, &dss_component_ops);
1261         return 0;
1262 }
1263
1264 static int dss_runtime_suspend(struct device *dev)
1265 {
1266         dss_save_context();
1267         dss_set_min_bus_tput(dev, 0);
1268
1269         pinctrl_pm_select_sleep_state(dev);
1270
1271         return 0;
1272 }
1273
1274 static int dss_runtime_resume(struct device *dev)
1275 {
1276         int r;
1277
1278         pinctrl_pm_select_default_state(dev);
1279
1280         /*
1281          * Set an arbitrarily high tput request to ensure OPP100.
1282          * What we should really do is to make a request to stay in OPP100,
1283          * without any tput requirements, but that is not currently possible
1284          * via the PM layer.
1285          */
1286
1287         r = dss_set_min_bus_tput(dev, 1000000000);
1288         if (r)
1289                 return r;
1290
1291         dss_restore_context();
1292         return 0;
1293 }
1294
1295 static const struct dev_pm_ops dss_pm_ops = {
1296         .runtime_suspend = dss_runtime_suspend,
1297         .runtime_resume = dss_runtime_resume,
1298 };
1299
1300 static const struct of_device_id dss_of_match[] = {
1301         { .compatible = "ti,omap2-dss", },
1302         { .compatible = "ti,omap3-dss", },
1303         { .compatible = "ti,omap4-dss", },
1304         { .compatible = "ti,omap5-dss", },
1305         { .compatible = "ti,dra7-dss", },
1306         {},
1307 };
1308
1309 MODULE_DEVICE_TABLE(of, dss_of_match);
1310
1311 static struct platform_driver omap_dsshw_driver = {
1312         .probe          = dss_probe,
1313         .remove         = dss_remove,
1314         .driver         = {
1315                 .name   = "omapdss_dss",
1316                 .pm     = &dss_pm_ops,
1317                 .of_match_table = dss_of_match,
1318                 .suppress_bind_attrs = true,
1319         },
1320 };
1321
1322 int __init dss_init_platform_driver(void)
1323 {
1324         return platform_driver_register(&omap_dsshw_driver);
1325 }
1326
1327 void dss_uninit_platform_driver(void)
1328 {
1329         platform_driver_unregister(&omap_dsshw_driver);
1330 }