drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gmc_v11_0.h"
  51 #include "gfxhub_v2_0.h"
  52 #include "mmhub_v2_0.h"
  53 #include "nbio_v2_3.h"
  54 #include "nbio_v4_3.h"
  55 #include "nbio_v7_2.h"
  56 #include "nbio_v7_7.h"
  57 #include "hdp_v5_0.h"
  58 #include "hdp_v5_2.h"
  59 #include "hdp_v6_0.h"
  60 #include "nv.h"
  61 #include "soc21.h"
  62 #include "navi10_ih.h"
  63 #include "ih_v6_0.h"
  64 #include "gfx_v10_0.h"
  65 #include "gfx_v11_0.h"
  66 #include "sdma_v5_0.h"
  67 #include "sdma_v5_2.h"
  68 #include "sdma_v6_0.h"
  69 #include "lsdma_v6_0.h"
  70 #include "vcn_v2_0.h"
  71 #include "jpeg_v2_0.h"
  72 #include "vcn_v3_0.h"
  73 #include "jpeg_v3_0.h"
  74 #include "vcn_v4_0.h"
  75 #include "jpeg_v4_0.h"
  76 #include "amdgpu_vkms.h"
  77 #include "mes_v10_1.h"
  78 #include "mes_v11_0.h"
  79 #include "smuio_v11_0.h"
  80 #include "smuio_v11_0_6.h"
  81 #include "smuio_v13_0.h"
  82 #include "smuio_v13_0_6.h"
  83
  84 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  85 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  86
  87 #define mmRCC_CONFIG_MEMSIZE    0xde3
  88 #define mmMM_INDEX              0x0
  89 #define mmMM_INDEX_HI           0x6
  90 #define mmMM_DATA               0x1
  91
  92 static const char *hw_id_names[HW_ID_MAX] = {
  93         [MP1_HWID]              = "MP1",
  94         [MP2_HWID]              = "MP2",
  95         [THM_HWID]              = "THM",
  96         [SMUIO_HWID]            = "SMUIO",
  97         [FUSE_HWID]             = "FUSE",
  98         [CLKA_HWID]             = "CLKA",
  99         [PWR_HWID]              = "PWR",
 100         [GC_HWID]               = "GC",
 101         [UVD_HWID]              = "UVD",
 102         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
 103         [ACP_HWID]              = "ACP",
 104         [DCI_HWID]              = "DCI",
 105         [DMU_HWID]              = "DMU",
 106         [DCO_HWID]              = "DCO",
 107         [DIO_HWID]              = "DIO",
 108         [XDMA_HWID]             = "XDMA",
 109         [DCEAZ_HWID]            = "DCEAZ",
 110         [DAZ_HWID]              = "DAZ",
 111         [SDPMUX_HWID]           = "SDPMUX",
 112         [NTB_HWID]              = "NTB",
 113         [IOHC_HWID]             = "IOHC",
 114         [L2IMU_HWID]            = "L2IMU",
 115         [VCE_HWID]              = "VCE",
 116         [MMHUB_HWID]            = "MMHUB",
 117         [ATHUB_HWID]            = "ATHUB",
 118         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 119         [DFX_HWID]              = "DFX",
 120         [DBGU0_HWID]            = "DBGU0",
 121         [DBGU1_HWID]            = "DBGU1",
 122         [OSSSYS_HWID]           = "OSSSYS",
 123         [HDP_HWID]              = "HDP",
 124         [SDMA0_HWID]            = "SDMA0",
 125         [SDMA1_HWID]            = "SDMA1",
 126         [SDMA2_HWID]            = "SDMA2",
 127         [SDMA3_HWID]            = "SDMA3",
 128         [LSDMA_HWID]            = "LSDMA",
 129         [ISP_HWID]              = "ISP",
 130         [DBGU_IO_HWID]          = "DBGU_IO",
 131         [DF_HWID]               = "DF",
 132         [CLKB_HWID]             = "CLKB",
 133         [FCH_HWID]              = "FCH",
 134         [DFX_DAP_HWID]          = "DFX_DAP",
 135         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 136         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 137         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 138         [L1IMU3_HWID]           = "L1IMU3",
 139         [L1IMU4_HWID]           = "L1IMU4",
 140         [L1IMU5_HWID]           = "L1IMU5",
 141         [L1IMU6_HWID]           = "L1IMU6",
 142         [L1IMU7_HWID]           = "L1IMU7",
 143         [L1IMU8_HWID]           = "L1IMU8",
 144         [L1IMU9_HWID]           = "L1IMU9",
 145         [L1IMU10_HWID]          = "L1IMU10",
 146         [L1IMU11_HWID]          = "L1IMU11",
 147         [L1IMU12_HWID]          = "L1IMU12",
 148         [L1IMU13_HWID]          = "L1IMU13",
 149         [L1IMU14_HWID]          = "L1IMU14",
 150         [L1IMU15_HWID]          = "L1IMU15",
 151         [WAFLC_HWID]            = "WAFLC",
 152         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 153         [PCIE_HWID]             = "PCIE",
 154         [PCS_HWID]              = "PCS",
 155         [DDCL_HWID]             = "DDCL",
 156         [SST_HWID]              = "SST",
 157         [IOAGR_HWID]            = "IOAGR",
 158         [NBIF_HWID]             = "NBIF",
 159         [IOAPIC_HWID]           = "IOAPIC",
 160         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 161         [NTBCCP_HWID]           = "NTBCCP",
 162         [UMC_HWID]              = "UMC",
 163         [SATA_HWID]             = "SATA",
 164         [USB_HWID]              = "USB",
 165         [CCXSEC_HWID]           = "CCXSEC",
 166         [XGMI_HWID]             = "XGMI",
 167         [XGBE_HWID]             = "XGBE",
 168         [MP0_HWID]              = "MP0",
 169 };
 170
 171 static int hw_id_map[MAX_HWIP] = {
 172         [GC_HWIP]       = GC_HWID,
 173         [HDP_HWIP]      = HDP_HWID,
 174         [SDMA0_HWIP]    = SDMA0_HWID,
 175         [SDMA1_HWIP]    = SDMA1_HWID,
 176         [SDMA2_HWIP]    = SDMA2_HWID,
 177         [SDMA3_HWIP]    = SDMA3_HWID,
 178         [LSDMA_HWIP]    = LSDMA_HWID,
 179         [MMHUB_HWIP]    = MMHUB_HWID,
 180         [ATHUB_HWIP]    = ATHUB_HWID,
 181         [NBIO_HWIP]     = NBIF_HWID,
 182         [MP0_HWIP]      = MP0_HWID,
 183         [MP1_HWIP]      = MP1_HWID,
 184         [UVD_HWIP]      = UVD_HWID,
 185         [VCE_HWIP]      = VCE_HWID,
 186         [DF_HWIP]       = DF_HWID,
 187         [DCE_HWIP]      = DMU_HWID,
 188         [OSSSYS_HWIP]   = OSSSYS_HWID,
 189         [SMUIO_HWIP]    = SMUIO_HWID,
 190         [PWR_HWIP]      = PWR_HWID,
 191         [NBIF_HWIP]     = NBIF_HWID,
 192         [THM_HWIP]      = THM_HWID,
 193         [CLK_HWIP]      = CLKA_HWID,
 194         [UMC_HWIP]      = UMC_HWID,
 195         [XGMI_HWIP]     = XGMI_HWID,
 196         [DCI_HWIP]      = DCI_HWID,
 197 };
 198
 199 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 200 {
 201         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 202         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 203
 204         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 205                                   adev->mman.discovery_tmr_size, false);
 206         return 0;
 207 }
 208
 209 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 210 {
 211         const struct firmware *fw;
 212         const char *fw_name;
 213         int r;
 214
 215         switch (amdgpu_discovery) {
 216         case 2:
 217                 fw_name = FIRMWARE_IP_DISCOVERY;
 218                 break;
 219         default:
 220                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 221                 return -EINVAL;
 222         }
 223
 224         r = request_firmware(&fw, fw_name, adev->dev);
 225         if (r) {
 226                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 227                         fw_name);
 228                 return r;
 229         }
 230
 231         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 232         release_firmware(fw);
 233
 234         return 0;
 235 }
 236
 237 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 238 {
 239         uint16_t checksum = 0;
 240         int i;
 241
 242         for (i = 0; i < size; i++)
 243                 checksum += data[i];
 244
 245         return checksum;
 246 }
 247
 248 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 249                                                     uint16_t expected)
 250 {
 251         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 252 }
 253
 254 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 255 {
 256         struct binary_header *bhdr;
 257         bhdr = (struct binary_header *)binary;
 258
 259         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 260 }
 261
 262 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 263 {
 264         /*
 265          * So far, apply this quirk only on those Navy Flounder boards which
 266          * have a bad harvest table of VCN config.
 267          */
 268         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 269                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 270                 switch (adev->pdev->revision) {
 271                 case 0xC1:
 272                 case 0xC2:
 273                 case 0xC3:
 274                 case 0xC5:
 275                 case 0xC7:
 276                 case 0xCF:
 277                 case 0xDF:
 278                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 279                         break;
 280                 default:
 281                         break;
 282                 }
 283         }
 284 }
 285
 286 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 287 {
 288         struct table_info *info;
 289         struct binary_header *bhdr;
 290         uint16_t offset;
 291         uint16_t size;
 292         uint16_t checksum;
 293         int r;
 294
 295         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 296         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 297         if (!adev->mman.discovery_bin)
 298                 return -ENOMEM;
 299
 300         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 301         if (r) {
 302                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 303                 r = -EINVAL;
 304                 goto out;
 305         }
 306
 307         if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 308                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 309                 /* retry read ip discovery binary from file */
 310                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 311                 if (r) {
 312                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 313                         r = -EINVAL;
 314                         goto out;
 315                 }
 316                 /* check the ip discovery binary signature */
 317                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 318                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 319                         r = -EINVAL;
 320                         goto out;
 321                 }
 322         }
 323
 324         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 325
 326         offset = offsetof(struct binary_header, binary_checksum) +
 327                 sizeof(bhdr->binary_checksum);
 328         size = le16_to_cpu(bhdr->binary_size) - offset;
 329         checksum = le16_to_cpu(bhdr->binary_checksum);
 330
 331         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 332                                               size, checksum)) {
 333                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 334                 r = -EINVAL;
 335                 goto out;
 336         }
 337
 338         info = &bhdr->table_list[IP_DISCOVERY];
 339         offset = le16_to_cpu(info->offset);
 340         checksum = le16_to_cpu(info->checksum);
 341
 342         if (offset) {
 343                 struct ip_discovery_header *ihdr =
 344                         (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 345                 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 346                         dev_err(adev->dev, "invalid ip discovery data table signature\n");
 347                         r = -EINVAL;
 348                         goto out;
 349                 }
 350
 351                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 352                                                       le16_to_cpu(ihdr->size), checksum)) {
 353                         dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 354                         r = -EINVAL;
 355                         goto out;
 356                 }
 357         }
 358
 359         info = &bhdr->table_list[GC];
 360         offset = le16_to_cpu(info->offset);
 361         checksum = le16_to_cpu(info->checksum);
 362
 363         if (offset) {
 364                 struct gpu_info_header *ghdr =
 365                         (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 366
 367                 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
 368                         dev_err(adev->dev, "invalid ip discovery gc table id\n");
 369                         r = -EINVAL;
 370                         goto out;
 371                 }
 372
 373                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 374                                                       le32_to_cpu(ghdr->size), checksum)) {
 375                         dev_err(adev->dev, "invalid gc data table checksum\n");
 376                         r = -EINVAL;
 377                         goto out;
 378                 }
 379         }
 380
 381         info = &bhdr->table_list[HARVEST_INFO];
 382         offset = le16_to_cpu(info->offset);
 383         checksum = le16_to_cpu(info->checksum);
 384
 385         if (offset) {
 386                 struct harvest_info_header *hhdr =
 387                         (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
 388
 389                 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
 390                         dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
 391                         r = -EINVAL;
 392                         goto out;
 393                 }
 394
 395                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 396                                                       sizeof(struct harvest_table), checksum)) {
 397                         dev_err(adev->dev, "invalid harvest data table checksum\n");
 398                         r = -EINVAL;
 399                         goto out;
 400                 }
 401         }
 402
 403         info = &bhdr->table_list[VCN_INFO];
 404         offset = le16_to_cpu(info->offset);
 405         checksum = le16_to_cpu(info->checksum);
 406
 407         if (offset) {
 408                 struct vcn_info_header *vhdr =
 409                         (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
 410
 411                 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
 412                         dev_err(adev->dev, "invalid ip discovery vcn table id\n");
 413                         r = -EINVAL;
 414                         goto out;
 415                 }
 416
 417                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 418                                                       le32_to_cpu(vhdr->size_bytes), checksum)) {
 419                         dev_err(adev->dev, "invalid vcn data table checksum\n");
 420                         r = -EINVAL;
 421                         goto out;
 422                 }
 423         }
 424
 425         info = &bhdr->table_list[MALL_INFO];
 426         offset = le16_to_cpu(info->offset);
 427         checksum = le16_to_cpu(info->checksum);
 428
 429         if (0 && offset) {
 430                 struct mall_info_header *mhdr =
 431                         (struct mall_info_header *)(adev->mman.discovery_bin + offset);
 432
 433                 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
 434                         dev_err(adev->dev, "invalid ip discovery mall table id\n");
 435                         r = -EINVAL;
 436                         goto out;
 437                 }
 438
 439                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 440                                                       le32_to_cpu(mhdr->size_bytes), checksum)) {
 441                         dev_err(adev->dev, "invalid mall data table checksum\n");
 442                         r = -EINVAL;
 443                         goto out;
 444                 }
 445         }
 446
 447         return 0;
 448
 449 out:
 450         kfree(adev->mman.discovery_bin);
 451         adev->mman.discovery_bin = NULL;
 452
 453         return r;
 454 }
 455
 456 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 457
 458 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 459 {
 460         amdgpu_discovery_sysfs_fini(adev);
 461         kfree(adev->mman.discovery_bin);
 462         adev->mman.discovery_bin = NULL;
 463 }
 464
 465 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 466 {
 467         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 468                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 469                           ip->number_instance);
 470                 return -EINVAL;
 471         }
 472         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 473                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 474                           le16_to_cpu(ip->hw_id));
 475                 return -EINVAL;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 482                                                 uint32_t *vcn_harvest_count)
 483 {
 484         struct binary_header *bhdr;
 485         struct ip_discovery_header *ihdr;
 486         struct die_header *dhdr;
 487         struct ip *ip;
 488         uint16_t die_offset, ip_offset, num_dies, num_ips;
 489         int i, j;
 490
 491         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 492         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 493                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 494         num_dies = le16_to_cpu(ihdr->num_dies);
 495
 496         /* scan harvest bit of all IP data structures */
 497         for (i = 0; i < num_dies; i++) {
 498                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 499                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 500                 num_ips = le16_to_cpu(dhdr->num_ips);
 501                 ip_offset = die_offset + sizeof(*dhdr);
 502
 503                 for (j = 0; j < num_ips; j++) {
 504                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 505
 506                         if (amdgpu_discovery_validate_ip(ip))
 507                                 goto next_ip;
 508
 509                         if (le16_to_cpu(ip->harvest) == 1) {
 510                                 switch (le16_to_cpu(ip->hw_id)) {
 511                                 case VCN_HWID:
 512                                         (*vcn_harvest_count)++;
 513                                         if (ip->number_instance == 0)
 514                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 515                                         else
 516                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 517                                         break;
 518                                 case DMU_HWID:
 519                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 520                                         break;
 521                                 default:
 522                                         break;
 523                                 }
 524                         }
 525 next_ip:
 526                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 527                 }
 528         }
 529 }
 530
 531 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 532                                                      uint32_t *vcn_harvest_count,
 533                                                      uint32_t *umc_harvest_count)
 534 {
 535         struct binary_header *bhdr;
 536         struct harvest_table *harvest_info;
 537         u16 offset;
 538         int i;
 539
 540         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 541         offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
 542
 543         if (!offset) {
 544                 dev_err(adev->dev, "invalid harvest table offset\n");
 545                 return;
 546         }
 547
 548         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
 549
 550         for (i = 0; i < 32; i++) {
 551                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 552                         break;
 553
 554                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 555                 case VCN_HWID:
 556                         (*vcn_harvest_count)++;
 557                         if (harvest_info->list[i].number_instance == 0)
 558                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 559                         else
 560                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 561                         break;
 562                 case DMU_HWID:
 563                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 564                         break;
 565                 case UMC_HWID:
 566                         (*umc_harvest_count)++;
 567                         break;
 568                 default:
 569                         break;
 570                 }
 571         }
 572 }
 573
 574 /* ================================================== */
 575
 576 struct ip_hw_instance {
 577         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 578
 579         int hw_id;
 580         u8  num_instance;
 581         u8  major, minor, revision;
 582         u8  harvest;
 583
 584         int num_base_addresses;
 585         u32 base_addr[];
 586 };
 587
 588 struct ip_hw_id {
 589         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 590         int hw_id;
 591 };
 592
 593 struct ip_die_entry {
 594         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 595         u16 num_ips;
 596 };
 597
 598 /* -------------------------------------------------- */
 599
 600 struct ip_hw_instance_attr {
 601         struct attribute attr;
 602         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 603 };
 604
 605 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 606 {
 607         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 608 }
 609
 610 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 611 {
 612         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 613 }
 614
 615 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 616 {
 617         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 618 }
 619
 620 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 621 {
 622         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 623 }
 624
 625 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 626 {
 627         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 628 }
 629
 630 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 631 {
 632         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 633 }
 634
 635 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 636 {
 637         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 638 }
 639
 640 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 641 {
 642         ssize_t res, at;
 643         int ii;
 644
 645         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 646                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 647                  */
 648                 if (at + 12 > PAGE_SIZE)
 649                         break;
 650                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 651                                     ip_hw_instance->base_addr[ii]);
 652                 if (res <= 0)
 653                         break;
 654                 at += res;
 655         }
 656
 657         return res < 0 ? res : at;
 658 }
 659
 660 static struct ip_hw_instance_attr ip_hw_attr[] = {
 661         __ATTR_RO(hw_id),
 662         __ATTR_RO(num_instance),
 663         __ATTR_RO(major),
 664         __ATTR_RO(minor),
 665         __ATTR_RO(revision),
 666         __ATTR_RO(harvest),
 667         __ATTR_RO(num_base_addresses),
 668         __ATTR_RO(base_addr),
 669 };
 670
 671 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 672 ATTRIBUTE_GROUPS(ip_hw_instance);
 673
 674 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 675 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 676
 677 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 678                                         struct attribute *attr,
 679                                         char *buf)
 680 {
 681         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 682         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 683
 684         if (!ip_hw_attr->show)
 685                 return -EIO;
 686
 687         return ip_hw_attr->show(ip_hw_instance, buf);
 688 }
 689
 690 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 691         .show = ip_hw_instance_attr_show,
 692 };
 693
 694 static void ip_hw_instance_release(struct kobject *kobj)
 695 {
 696         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 697
 698         kfree(ip_hw_instance);
 699 }
 700
 701 static struct kobj_type ip_hw_instance_ktype = {
 702         .release = ip_hw_instance_release,
 703         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 704         .default_groups = ip_hw_instance_groups,
 705 };
 706
 707 /* -------------------------------------------------- */
 708
 709 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 710
 711 static void ip_hw_id_release(struct kobject *kobj)
 712 {
 713         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 714
 715         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 716                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 717         kfree(ip_hw_id);
 718 }
 719
 720 static struct kobj_type ip_hw_id_ktype = {
 721         .release = ip_hw_id_release,
 722         .sysfs_ops = &kobj_sysfs_ops,
 723 };
 724
 725 /* -------------------------------------------------- */
 726
 727 static void die_kobj_release(struct kobject *kobj);
 728 static void ip_disc_release(struct kobject *kobj);
 729
 730 struct ip_die_entry_attribute {
 731         struct attribute attr;
 732         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 733 };
 734
 735 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 736
 737 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 738 {
 739         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 740 }
 741
 742 /* If there are more ip_die_entry attrs, other than the number of IPs,
 743  * we can make this intro an array of attrs, and then initialize
 744  * ip_die_entry_attrs in a loop.
 745  */
 746 static struct ip_die_entry_attribute num_ips_attr =
 747         __ATTR_RO(num_ips);
 748
 749 static struct attribute *ip_die_entry_attrs[] = {
 750         &num_ips_attr.attr,
 751         NULL,
 752 };
 753 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 754
 755 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 756
 757 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 758                                       struct attribute *attr,
 759                                       char *buf)
 760 {
 761         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 762         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 763
 764         if (!ip_die_entry_attr->show)
 765                 return -EIO;
 766
 767         return ip_die_entry_attr->show(ip_die_entry, buf);
 768 }
 769
 770 static void ip_die_entry_release(struct kobject *kobj)
 771 {
 772         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 773
 774         if (!list_empty(&ip_die_entry->ip_kset.list))
 775                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 776         kfree(ip_die_entry);
 777 }
 778
 779 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 780         .show = ip_die_entry_attr_show,
 781 };
 782
 783 static struct kobj_type ip_die_entry_ktype = {
 784         .release = ip_die_entry_release,
 785         .sysfs_ops = &ip_die_entry_sysfs_ops,
 786         .default_groups = ip_die_entry_groups,
 787 };
 788
 789 static struct kobj_type die_kobj_ktype = {
 790         .release = die_kobj_release,
 791         .sysfs_ops = &kobj_sysfs_ops,
 792 };
 793
 794 static struct kobj_type ip_discovery_ktype = {
 795         .release = ip_disc_release,
 796         .sysfs_ops = &kobj_sysfs_ops,
 797 };
 798
 799 struct ip_discovery_top {
 800         struct kobject kobj;    /* ip_discovery/ */
 801         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 802         struct amdgpu_device *adev;
 803 };
 804
 805 static void die_kobj_release(struct kobject *kobj)
 806 {
 807         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 808                                                        struct ip_discovery_top,
 809                                                        die_kset);
 810         if (!list_empty(&ip_top->die_kset.list))
 811                 DRM_ERROR("ip_top->die_kset is not empty");
 812 }
 813
 814 static void ip_disc_release(struct kobject *kobj)
 815 {
 816         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 817                                                        kobj);
 818         struct amdgpu_device *adev = ip_top->adev;
 819
 820         adev->ip_top = NULL;
 821         kfree(ip_top);
 822 }
 823
 824 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 825                                       struct ip_die_entry *ip_die_entry,
 826                                       const size_t _ip_offset, const int num_ips)
 827 {
 828         int ii, jj, kk, res;
 829
 830         DRM_DEBUG("num_ips:%d", num_ips);
 831
 832         /* Find all IPs of a given HW ID, and add their instance to
 833          * #die/#hw_id/#instance/<attributes>
 834          */
 835         for (ii = 0; ii < HW_ID_MAX; ii++) {
 836                 struct ip_hw_id *ip_hw_id = NULL;
 837                 size_t ip_offset = _ip_offset;
 838
 839                 for (jj = 0; jj < num_ips; jj++) {
 840                         struct ip *ip;
 841                         struct ip_hw_instance *ip_hw_instance;
 842
 843                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 844                         if (amdgpu_discovery_validate_ip(ip) ||
 845                             le16_to_cpu(ip->hw_id) != ii)
 846                                 goto next_ip;
 847
 848                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 849
 850                         /* We have a hw_id match; register the hw
 851                          * block if not yet registered.
 852                          */
 853                         if (!ip_hw_id) {
 854                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 855                                 if (!ip_hw_id)
 856                                         return -ENOMEM;
 857                                 ip_hw_id->hw_id = ii;
 858
 859                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 860                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 861                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 862                                 res = kset_register(&ip_hw_id->hw_id_kset);
 863                                 if (res) {
 864                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 865                                         kfree(ip_hw_id);
 866                                         return res;
 867                                 }
 868                                 if (hw_id_names[ii]) {
 869                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 870                                                                 &ip_hw_id->hw_id_kset.kobj,
 871                                                                 hw_id_names[ii]);
 872                                         if (res) {
 873                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 874                                                           hw_id_names[ii],
 875                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 876                                         }
 877                                 }
 878                         }
 879
 880                         /* Now register its instance.
 881                          */
 882                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 883                                                              base_addr,
 884                                                              ip->num_base_address),
 885                                                  GFP_KERNEL);
 886                         if (!ip_hw_instance) {
 887                                 DRM_ERROR("no memory for ip_hw_instance");
 888                                 return -ENOMEM;
 889                         }
 890                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 891                         ip_hw_instance->num_instance = ip->number_instance;
 892                         ip_hw_instance->major = ip->major;
 893                         ip_hw_instance->minor = ip->minor;
 894                         ip_hw_instance->revision = ip->revision;
 895                         ip_hw_instance->harvest = ip->harvest;
 896                         ip_hw_instance->num_base_addresses = ip->num_base_address;
 897
 898                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
 899                                 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
 900
 901                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
 902                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
 903                         res = kobject_add(&ip_hw_instance->kobj, NULL,
 904                                           "%d", ip_hw_instance->num_instance);
 905 next_ip:
 906                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 907                 }
 908         }
 909
 910         return 0;
 911 }
 912
 913 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
 914 {
 915         struct binary_header *bhdr;
 916         struct ip_discovery_header *ihdr;
 917         struct die_header *dhdr;
 918         struct kset *die_kset = &adev->ip_top->die_kset;
 919         u16 num_dies, die_offset, num_ips;
 920         size_t ip_offset;
 921         int ii, res;
 922
 923         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 924         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 925                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 926         num_dies = le16_to_cpu(ihdr->num_dies);
 927
 928         DRM_DEBUG("number of dies: %d\n", num_dies);
 929
 930         for (ii = 0; ii < num_dies; ii++) {
 931                 struct ip_die_entry *ip_die_entry;
 932
 933                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
 934                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 935                 num_ips = le16_to_cpu(dhdr->num_ips);
 936                 ip_offset = die_offset + sizeof(*dhdr);
 937
 938                 /* Add the die to the kset.
 939                  *
 940                  * dhdr->die_id == ii, which was checked in
 941                  * amdgpu_discovery_reg_base_init().
 942                  */
 943
 944                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
 945                 if (!ip_die_entry)
 946                         return -ENOMEM;
 947
 948                 ip_die_entry->num_ips = num_ips;
 949
 950                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
 951                 ip_die_entry->ip_kset.kobj.kset = die_kset;
 952                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
 953                 res = kset_register(&ip_die_entry->ip_kset);
 954                 if (res) {
 955                         DRM_ERROR("Couldn't register ip_die_entry kset");
 956                         kfree(ip_die_entry);
 957                         return res;
 958                 }
 959
 960                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
 961         }
 962
 963         return 0;
 964 }
 965
 966 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
 967 {
 968         struct kset *die_kset;
 969         int res, ii;
 970
 971         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
 972         if (!adev->ip_top)
 973                 return -ENOMEM;
 974
 975         adev->ip_top->adev = adev;
 976
 977         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
 978                                    &adev->dev->kobj, "ip_discovery");
 979         if (res) {
 980                 DRM_ERROR("Couldn't init and add ip_discovery/");
 981                 goto Err;
 982         }
 983
 984         die_kset = &adev->ip_top->die_kset;
 985         kobject_set_name(&die_kset->kobj, "%s", "die");
 986         die_kset->kobj.parent = &adev->ip_top->kobj;
 987         die_kset->kobj.ktype = &die_kobj_ktype;
 988         res = kset_register(&adev->ip_top->die_kset);
 989         if (res) {
 990                 DRM_ERROR("Couldn't register die_kset");
 991                 goto Err;
 992         }
 993
 994         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
 995                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
 996         ip_hw_instance_attrs[ii] = NULL;
 997
 998         res = amdgpu_discovery_sysfs_recurse(adev);
 999
1000         return res;
1001 Err:
1002         kobject_put(&adev->ip_top->kobj);
1003         return res;
1004 }
1005
1006 /* -------------------------------------------------- */
1007
1008 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1009
1010 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1011 {
1012         struct list_head *el, *tmp;
1013         struct kset *hw_id_kset;
1014
1015         hw_id_kset = &ip_hw_id->hw_id_kset;
1016         spin_lock(&hw_id_kset->list_lock);
1017         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1018                 list_del_init(el);
1019                 spin_unlock(&hw_id_kset->list_lock);
1020                 /* kobject is embedded in ip_hw_instance */
1021                 kobject_put(list_to_kobj(el));
1022                 spin_lock(&hw_id_kset->list_lock);
1023         }
1024         spin_unlock(&hw_id_kset->list_lock);
1025         kobject_put(&ip_hw_id->hw_id_kset.kobj);
1026 }
1027
1028 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1029 {
1030         struct list_head *el, *tmp;
1031         struct kset *ip_kset;
1032
1033         ip_kset = &ip_die_entry->ip_kset;
1034         spin_lock(&ip_kset->list_lock);
1035         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1036                 list_del_init(el);
1037                 spin_unlock(&ip_kset->list_lock);
1038                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1039                 spin_lock(&ip_kset->list_lock);
1040         }
1041         spin_unlock(&ip_kset->list_lock);
1042         kobject_put(&ip_die_entry->ip_kset.kobj);
1043 }
1044
1045 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1046 {
1047         struct list_head *el, *tmp;
1048         struct kset *die_kset;
1049
1050         die_kset = &adev->ip_top->die_kset;
1051         spin_lock(&die_kset->list_lock);
1052         list_for_each_prev_safe(el, tmp, &die_kset->list) {
1053                 list_del_init(el);
1054                 spin_unlock(&die_kset->list_lock);
1055                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1056                 spin_lock(&die_kset->list_lock);
1057         }
1058         spin_unlock(&die_kset->list_lock);
1059         kobject_put(&adev->ip_top->die_kset.kobj);
1060         kobject_put(&adev->ip_top->kobj);
1061 }
1062
1063 /* ================================================== */
1064
1065 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1066 {
1067         struct binary_header *bhdr;
1068         struct ip_discovery_header *ihdr;
1069         struct die_header *dhdr;
1070         struct ip *ip;
1071         uint16_t die_offset;
1072         uint16_t ip_offset;
1073         uint16_t num_dies;
1074         uint16_t num_ips;
1075         uint8_t num_base_address;
1076         int hw_ip;
1077         int i, j, k;
1078         int r;
1079
1080         r = amdgpu_discovery_init(adev);
1081         if (r) {
1082                 DRM_ERROR("amdgpu_discovery_init failed\n");
1083                 return r;
1084         }
1085
1086         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1087         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1088                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1089         num_dies = le16_to_cpu(ihdr->num_dies);
1090
1091         DRM_DEBUG("number of dies: %d\n", num_dies);
1092
1093         for (i = 0; i < num_dies; i++) {
1094                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1095                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1096                 num_ips = le16_to_cpu(dhdr->num_ips);
1097                 ip_offset = die_offset + sizeof(*dhdr);
1098
1099                 if (le16_to_cpu(dhdr->die_id) != i) {
1100                         DRM_ERROR("invalid die id %d, expected %d\n",
1101                                         le16_to_cpu(dhdr->die_id), i);
1102                         return -EINVAL;
1103                 }
1104
1105                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1106                                 le16_to_cpu(dhdr->die_id), num_ips);
1107
1108                 for (j = 0; j < num_ips; j++) {
1109                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1110
1111                         if (amdgpu_discovery_validate_ip(ip))
1112                                 goto next_ip;
1113
1114                         num_base_address = ip->num_base_address;
1115
1116                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1117                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1118                                   le16_to_cpu(ip->hw_id),
1119                                   ip->number_instance,
1120                                   ip->major, ip->minor,
1121                                   ip->revision);
1122
1123                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1124                                 /* Bit [5:0]: original revision value
1125                                  * Bit [7:6]: en/decode capability:
1126                                  *     0b00 : VCN function normally
1127                                  *     0b10 : encode is disabled
1128                                  *     0b01 : decode is disabled
1129                                  */
1130                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1131                                         ip->revision & 0xc0;
1132                                 ip->revision &= ~0xc0;
1133                                 if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES)
1134                                         adev->vcn.num_vcn_inst++;
1135                                 else
1136                                         dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1137                                                 adev->vcn.num_vcn_inst + 1,
1138                                                 AMDGPU_MAX_VCN_INSTANCES);
1139                         }
1140                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1141                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1142                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1143                             le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1144                                 if (adev->sdma.num_instances < AMDGPU_MAX_SDMA_INSTANCES)
1145                                         adev->sdma.num_instances++;
1146                                 else
1147                                         dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1148                                                 adev->sdma.num_instances + 1,
1149                                                 AMDGPU_MAX_SDMA_INSTANCES);
1150                         }
1151
1152                         if (le16_to_cpu(ip->hw_id) == UMC_HWID)
1153                                 adev->gmc.num_umc++;
1154
1155                         for (k = 0; k < num_base_address; k++) {
1156                                 /*
1157                                  * convert the endianness of base addresses in place,
1158                                  * so that we don't need to convert them when accessing adev->reg_offset.
1159                                  */
1160                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1161                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1162                         }
1163
1164                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1165                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
1166                                         DRM_DEBUG("set register base offset for %s\n",
1167                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1168                                         adev->reg_offset[hw_ip][ip->number_instance] =
1169                                                 ip->base_address;
1170                                         /* Instance support is somewhat inconsistent.
1171                                          * SDMA is a good example.  Sienna cichlid has 4 total
1172                                          * SDMA instances, each enumerated separately (HWIDs
1173                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1174                                          * but they are enumerated as multiple instances of the
1175                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1176                                          * example.  On most chips there are multiple instances
1177                                          * with the same HWID.
1178                                          */
1179                                         adev->ip_versions[hw_ip][ip->number_instance] =
1180                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1181                                 }
1182                         }
1183
1184 next_ip:
1185                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1186                 }
1187         }
1188
1189         amdgpu_discovery_sysfs_init(adev);
1190
1191         return 0;
1192 }
1193
1194 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1195                                     int *major, int *minor, int *revision)
1196 {
1197         struct binary_header *bhdr;
1198         struct ip_discovery_header *ihdr;
1199         struct die_header *dhdr;
1200         struct ip *ip;
1201         uint16_t die_offset;
1202         uint16_t ip_offset;
1203         uint16_t num_dies;
1204         uint16_t num_ips;
1205         int i, j;
1206
1207         if (!adev->mman.discovery_bin) {
1208                 DRM_ERROR("ip discovery uninitialized\n");
1209                 return -EINVAL;
1210         }
1211
1212         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1213         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1214                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1215         num_dies = le16_to_cpu(ihdr->num_dies);
1216
1217         for (i = 0; i < num_dies; i++) {
1218                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1219                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1220                 num_ips = le16_to_cpu(dhdr->num_ips);
1221                 ip_offset = die_offset + sizeof(*dhdr);
1222
1223                 for (j = 0; j < num_ips; j++) {
1224                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1225
1226                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1227                                 if (major)
1228                                         *major = ip->major;
1229                                 if (minor)
1230                                         *minor = ip->minor;
1231                                 if (revision)
1232                                         *revision = ip->revision;
1233                                 return 0;
1234                         }
1235                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1236                 }
1237         }
1238
1239         return -EINVAL;
1240 }
1241
1242 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1243 {
1244         int vcn_harvest_count = 0;
1245         int umc_harvest_count = 0;
1246
1247         /*
1248          * Harvest table does not fit Navi1x and legacy GPUs,
1249          * so read harvest bit per IP data structure to set
1250          * harvest configuration.
1251          */
1252         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
1253                 if ((adev->pdev->device == 0x731E &&
1254                         (adev->pdev->revision == 0xC6 ||
1255                          adev->pdev->revision == 0xC7)) ||
1256                         (adev->pdev->device == 0x7340 &&
1257                          adev->pdev->revision == 0xC9) ||
1258                         (adev->pdev->device == 0x7360 &&
1259                          adev->pdev->revision == 0xC7))
1260                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1261                                 &vcn_harvest_count);
1262         } else {
1263                 amdgpu_discovery_read_from_harvest_table(adev,
1264                                                          &vcn_harvest_count,
1265                                                          &umc_harvest_count);
1266         }
1267
1268         amdgpu_discovery_harvest_config_quirk(adev);
1269
1270         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1271                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1272                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1273         }
1274
1275         if (umc_harvest_count < adev->gmc.num_umc) {
1276                 adev->gmc.num_umc -= umc_harvest_count;
1277         }
1278 }
1279
1280 union gc_info {
1281         struct gc_info_v1_0 v1;
1282         struct gc_info_v1_1 v1_1;
1283         struct gc_info_v1_2 v1_2;
1284         struct gc_info_v2_0 v2;
1285 };
1286
1287 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1288 {
1289         struct binary_header *bhdr;
1290         union gc_info *gc_info;
1291         u16 offset;
1292
1293         if (!adev->mman.discovery_bin) {
1294                 DRM_ERROR("ip discovery uninitialized\n");
1295                 return -EINVAL;
1296         }
1297
1298         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1299         offset = le16_to_cpu(bhdr->table_list[GC].offset);
1300
1301         if (!offset)
1302                 return 0;
1303
1304         gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1305
1306         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1307         case 1:
1308                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1309                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1310                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1311                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1312                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1313                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1314                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1315                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1316                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1317                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1318                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1319                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1320                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1321                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1322                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1323                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1324                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1325                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1326                 if (gc_info->v1.header.version_minor >= 1) {
1327                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1328                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1329                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1330                 }
1331                 if (gc_info->v1.header.version_minor >= 2) {
1332                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1333                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1334                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1335                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1336                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1337                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1338                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1339                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1340                 }
1341                 break;
1342         case 2:
1343                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1344                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1345                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1346                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1347                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1348                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1349                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1350                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1351                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1352                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1353                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1354                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1355                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1356                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1357                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1358                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1359                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1360                 break;
1361         default:
1362                 dev_err(adev->dev,
1363                         "Unhandled GC info table %d.%d\n",
1364                         le16_to_cpu(gc_info->v1.header.version_major),
1365                         le16_to_cpu(gc_info->v1.header.version_minor));
1366                 return -EINVAL;
1367         }
1368         return 0;
1369 }
1370
1371 union mall_info {
1372         struct mall_info_v1_0 v1;
1373 };
1374
1375 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1376 {
1377         struct binary_header *bhdr;
1378         union mall_info *mall_info;
1379         u32 u, mall_size_per_umc, m_s_present, half_use;
1380         u64 mall_size;
1381         u16 offset;
1382
1383         if (!adev->mman.discovery_bin) {
1384                 DRM_ERROR("ip discovery uninitialized\n");
1385                 return -EINVAL;
1386         }
1387
1388         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1389         offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1390
1391         if (!offset)
1392                 return 0;
1393
1394         mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1395
1396         switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1397         case 1:
1398                 mall_size = 0;
1399                 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1400                 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1401                 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1402                 for (u = 0; u < adev->gmc.num_umc; u++) {
1403                         if (m_s_present & (1 << u))
1404                                 mall_size += mall_size_per_umc * 2;
1405                         else if (half_use & (1 << u))
1406                                 mall_size += mall_size_per_umc / 2;
1407                         else
1408                                 mall_size += mall_size_per_umc;
1409                 }
1410                 adev->gmc.mall_size = mall_size;
1411                 break;
1412         default:
1413                 dev_err(adev->dev,
1414                         "Unhandled MALL info table %d.%d\n",
1415                         le16_to_cpu(mall_info->v1.header.version_major),
1416                         le16_to_cpu(mall_info->v1.header.version_minor));
1417                 return -EINVAL;
1418         }
1419         return 0;
1420 }
1421
1422 union vcn_info {
1423         struct vcn_info_v1_0 v1;
1424 };
1425
1426 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1427 {
1428         struct binary_header *bhdr;
1429         union vcn_info *vcn_info;
1430         u16 offset;
1431         int v;
1432
1433         if (!adev->mman.discovery_bin) {
1434                 DRM_ERROR("ip discovery uninitialized\n");
1435                 return -EINVAL;
1436         }
1437
1438         if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1439                 dev_err(adev->dev, "invalid vcn instances\n");
1440                 return -EINVAL;
1441         }
1442
1443         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1444         offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1445
1446         if (!offset)
1447                 return 0;
1448
1449         vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1450
1451         switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1452         case 1:
1453                 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1454                         adev->vcn.vcn_codec_disable_mask[v] =
1455                                 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1456                 }
1457                 break;
1458         default:
1459                 dev_err(adev->dev,
1460                         "Unhandled VCN info table %d.%d\n",
1461                         le16_to_cpu(vcn_info->v1.header.version_major),
1462                         le16_to_cpu(vcn_info->v1.header.version_minor));
1463                 return -EINVAL;
1464         }
1465         return 0;
1466 }
1467
1468 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1469 {
1470         /* what IP to use for this? */
1471         switch (adev->ip_versions[GC_HWIP][0]) {
1472         case IP_VERSION(9, 0, 1):
1473         case IP_VERSION(9, 1, 0):
1474         case IP_VERSION(9, 2, 1):
1475         case IP_VERSION(9, 2, 2):
1476         case IP_VERSION(9, 3, 0):
1477         case IP_VERSION(9, 4, 0):
1478         case IP_VERSION(9, 4, 1):
1479         case IP_VERSION(9, 4, 2):
1480                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1481                 break;
1482         case IP_VERSION(10, 1, 10):
1483         case IP_VERSION(10, 1, 1):
1484         case IP_VERSION(10, 1, 2):
1485         case IP_VERSION(10, 1, 3):
1486         case IP_VERSION(10, 1, 4):
1487         case IP_VERSION(10, 3, 0):
1488         case IP_VERSION(10, 3, 1):
1489         case IP_VERSION(10, 3, 2):
1490         case IP_VERSION(10, 3, 3):
1491         case IP_VERSION(10, 3, 4):
1492         case IP_VERSION(10, 3, 5):
1493         case IP_VERSION(10, 3, 6):
1494         case IP_VERSION(10, 3, 7):
1495                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1496                 break;
1497         case IP_VERSION(11, 0, 0):
1498         case IP_VERSION(11, 0, 1):
1499         case IP_VERSION(11, 0, 2):
1500                 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1501                 break;
1502         default:
1503                 dev_err(adev->dev,
1504                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1505                         adev->ip_versions[GC_HWIP][0]);
1506                 return -EINVAL;
1507         }
1508         return 0;
1509 }
1510
1511 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1512 {
1513         /* use GC or MMHUB IP version */
1514         switch (adev->ip_versions[GC_HWIP][0]) {
1515         case IP_VERSION(9, 0, 1):
1516         case IP_VERSION(9, 1, 0):
1517         case IP_VERSION(9, 2, 1):
1518         case IP_VERSION(9, 2, 2):
1519         case IP_VERSION(9, 3, 0):
1520         case IP_VERSION(9, 4, 0):
1521         case IP_VERSION(9, 4, 1):
1522         case IP_VERSION(9, 4, 2):
1523                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1524                 break;
1525         case IP_VERSION(10, 1, 10):
1526         case IP_VERSION(10, 1, 1):
1527         case IP_VERSION(10, 1, 2):
1528         case IP_VERSION(10, 1, 3):
1529         case IP_VERSION(10, 1, 4):
1530         case IP_VERSION(10, 3, 0):
1531         case IP_VERSION(10, 3, 1):
1532         case IP_VERSION(10, 3, 2):
1533         case IP_VERSION(10, 3, 3):
1534         case IP_VERSION(10, 3, 4):
1535         case IP_VERSION(10, 3, 5):
1536         case IP_VERSION(10, 3, 6):
1537         case IP_VERSION(10, 3, 7):
1538                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1539                 break;
1540         case IP_VERSION(11, 0, 0):
1541         case IP_VERSION(11, 0, 1):
1542         case IP_VERSION(11, 0, 2):
1543                 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1544                 break;
1545         default:
1546                 dev_err(adev->dev,
1547                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1548                         adev->ip_versions[GC_HWIP][0]);
1549                 return -EINVAL;
1550         }
1551         return 0;
1552 }
1553
1554 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1555 {
1556         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1557         case IP_VERSION(4, 0, 0):
1558         case IP_VERSION(4, 0, 1):
1559         case IP_VERSION(4, 1, 0):
1560         case IP_VERSION(4, 1, 1):
1561         case IP_VERSION(4, 3, 0):
1562                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1563                 break;
1564         case IP_VERSION(4, 2, 0):
1565         case IP_VERSION(4, 2, 1):
1566         case IP_VERSION(4, 4, 0):
1567                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1568                 break;
1569         case IP_VERSION(5, 0, 0):
1570         case IP_VERSION(5, 0, 1):
1571         case IP_VERSION(5, 0, 2):
1572         case IP_VERSION(5, 0, 3):
1573         case IP_VERSION(5, 2, 0):
1574         case IP_VERSION(5, 2, 1):
1575                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1576                 break;
1577         case IP_VERSION(6, 0, 0):
1578         case IP_VERSION(6, 0, 1):
1579         case IP_VERSION(6, 0, 2):
1580                 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
1581                 break;
1582         default:
1583                 dev_err(adev->dev,
1584                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1585                         adev->ip_versions[OSSSYS_HWIP][0]);
1586                 return -EINVAL;
1587         }
1588         return 0;
1589 }
1590
1591 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1592 {
1593         switch (adev->ip_versions[MP0_HWIP][0]) {
1594         case IP_VERSION(9, 0, 0):
1595                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1596                 break;
1597         case IP_VERSION(10, 0, 0):
1598         case IP_VERSION(10, 0, 1):
1599                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1600                 break;
1601         case IP_VERSION(11, 0, 0):
1602         case IP_VERSION(11, 0, 2):
1603         case IP_VERSION(11, 0, 4):
1604         case IP_VERSION(11, 0, 5):
1605         case IP_VERSION(11, 0, 9):
1606         case IP_VERSION(11, 0, 7):
1607         case IP_VERSION(11, 0, 11):
1608         case IP_VERSION(11, 0, 12):
1609         case IP_VERSION(11, 0, 13):
1610         case IP_VERSION(11, 5, 0):
1611                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1612                 break;
1613         case IP_VERSION(11, 0, 8):
1614                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1615                 break;
1616         case IP_VERSION(11, 0, 3):
1617         case IP_VERSION(12, 0, 1):
1618                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1619                 break;
1620         case IP_VERSION(13, 0, 0):
1621         case IP_VERSION(13, 0, 1):
1622         case IP_VERSION(13, 0, 2):
1623         case IP_VERSION(13, 0, 3):
1624         case IP_VERSION(13, 0, 4):
1625         case IP_VERSION(13, 0, 5):
1626         case IP_VERSION(13, 0, 7):
1627         case IP_VERSION(13, 0, 8):
1628                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1629                 break;
1630         default:
1631                 dev_err(adev->dev,
1632                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1633                         adev->ip_versions[MP0_HWIP][0]);
1634                 return -EINVAL;
1635         }
1636         return 0;
1637 }
1638
1639 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1640 {
1641         switch (adev->ip_versions[MP1_HWIP][0]) {
1642         case IP_VERSION(9, 0, 0):
1643         case IP_VERSION(10, 0, 0):
1644         case IP_VERSION(10, 0, 1):
1645         case IP_VERSION(11, 0, 2):
1646                 if (adev->asic_type == CHIP_ARCTURUS)
1647                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1648                 else
1649                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1650                 break;
1651         case IP_VERSION(11, 0, 0):
1652         case IP_VERSION(11, 0, 5):
1653         case IP_VERSION(11, 0, 9):
1654         case IP_VERSION(11, 0, 7):
1655         case IP_VERSION(11, 0, 8):
1656         case IP_VERSION(11, 0, 11):
1657         case IP_VERSION(11, 0, 12):
1658         case IP_VERSION(11, 0, 13):
1659         case IP_VERSION(11, 5, 0):
1660                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1661                 break;
1662         case IP_VERSION(12, 0, 0):
1663         case IP_VERSION(12, 0, 1):
1664                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1665                 break;
1666         case IP_VERSION(13, 0, 0):
1667         case IP_VERSION(13, 0, 1):
1668         case IP_VERSION(13, 0, 2):
1669         case IP_VERSION(13, 0, 3):
1670         case IP_VERSION(13, 0, 4):
1671         case IP_VERSION(13, 0, 5):
1672         case IP_VERSION(13, 0, 7):
1673         case IP_VERSION(13, 0, 8):
1674                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1675                 break;
1676         default:
1677                 dev_err(adev->dev,
1678                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1679                         adev->ip_versions[MP1_HWIP][0]);
1680                 return -EINVAL;
1681         }
1682         return 0;
1683 }
1684
1685 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1686 {
1687         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1688                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1689                 return 0;
1690         }
1691
1692         if (!amdgpu_device_has_dc_support(adev))
1693                 return 0;
1694
1695 #if defined(CONFIG_DRM_AMD_DC)
1696         if (adev->ip_versions[DCE_HWIP][0]) {
1697                 switch (adev->ip_versions[DCE_HWIP][0]) {
1698                 case IP_VERSION(1, 0, 0):
1699                 case IP_VERSION(1, 0, 1):
1700                 case IP_VERSION(2, 0, 2):
1701                 case IP_VERSION(2, 0, 0):
1702                 case IP_VERSION(2, 0, 3):
1703                 case IP_VERSION(2, 1, 0):
1704                 case IP_VERSION(3, 0, 0):
1705                 case IP_VERSION(3, 0, 2):
1706                 case IP_VERSION(3, 0, 3):
1707                 case IP_VERSION(3, 0, 1):
1708                 case IP_VERSION(3, 1, 2):
1709                 case IP_VERSION(3, 1, 3):
1710                 case IP_VERSION(3, 1, 5):
1711                 case IP_VERSION(3, 1, 6):
1712                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1713                         break;
1714                 default:
1715                         dev_err(adev->dev,
1716                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1717                                 adev->ip_versions[DCE_HWIP][0]);
1718                         return -EINVAL;
1719                 }
1720         } else if (adev->ip_versions[DCI_HWIP][0]) {
1721                 switch (adev->ip_versions[DCI_HWIP][0]) {
1722                 case IP_VERSION(12, 0, 0):
1723                 case IP_VERSION(12, 0, 1):
1724                 case IP_VERSION(12, 1, 0):
1725                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1726                         break;
1727                 default:
1728                         dev_err(adev->dev,
1729                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1730                                 adev->ip_versions[DCI_HWIP][0]);
1731                         return -EINVAL;
1732                 }
1733         }
1734 #endif
1735         return 0;
1736 }
1737
1738 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1739 {
1740         switch (adev->ip_versions[GC_HWIP][0]) {
1741         case IP_VERSION(9, 0, 1):
1742         case IP_VERSION(9, 1, 0):
1743         case IP_VERSION(9, 2, 1):
1744         case IP_VERSION(9, 2, 2):
1745         case IP_VERSION(9, 3, 0):
1746         case IP_VERSION(9, 4, 0):
1747         case IP_VERSION(9, 4, 1):
1748         case IP_VERSION(9, 4, 2):
1749                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1750                 break;
1751         case IP_VERSION(10, 1, 10):
1752         case IP_VERSION(10, 1, 2):
1753         case IP_VERSION(10, 1, 1):
1754         case IP_VERSION(10, 1, 3):
1755         case IP_VERSION(10, 1, 4):
1756         case IP_VERSION(10, 3, 0):
1757         case IP_VERSION(10, 3, 2):
1758         case IP_VERSION(10, 3, 1):
1759         case IP_VERSION(10, 3, 4):
1760         case IP_VERSION(10, 3, 5):
1761         case IP_VERSION(10, 3, 6):
1762         case IP_VERSION(10, 3, 3):
1763         case IP_VERSION(10, 3, 7):
1764                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1765                 break;
1766         case IP_VERSION(11, 0, 0):
1767         case IP_VERSION(11, 0, 1):
1768         case IP_VERSION(11, 0, 2):
1769                 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
1770                 break;
1771         default:
1772                 dev_err(adev->dev,
1773                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1774                         adev->ip_versions[GC_HWIP][0]);
1775                 return -EINVAL;
1776         }
1777         return 0;
1778 }
1779
1780 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1781 {
1782         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1783         case IP_VERSION(4, 0, 0):
1784         case IP_VERSION(4, 0, 1):
1785         case IP_VERSION(4, 1, 0):
1786         case IP_VERSION(4, 1, 1):
1787         case IP_VERSION(4, 1, 2):
1788         case IP_VERSION(4, 2, 0):
1789         case IP_VERSION(4, 2, 2):
1790         case IP_VERSION(4, 4, 0):
1791                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1792                 break;
1793         case IP_VERSION(5, 0, 0):
1794         case IP_VERSION(5, 0, 1):
1795         case IP_VERSION(5, 0, 2):
1796         case IP_VERSION(5, 0, 5):
1797                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1798                 break;
1799         case IP_VERSION(5, 2, 0):
1800         case IP_VERSION(5, 2, 2):
1801         case IP_VERSION(5, 2, 4):
1802         case IP_VERSION(5, 2, 5):
1803         case IP_VERSION(5, 2, 6):
1804         case IP_VERSION(5, 2, 3):
1805         case IP_VERSION(5, 2, 1):
1806         case IP_VERSION(5, 2, 7):
1807                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1808                 break;
1809         case IP_VERSION(6, 0, 0):
1810         case IP_VERSION(6, 0, 1):
1811         case IP_VERSION(6, 0, 2):
1812                 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
1813                 break;
1814         default:
1815                 dev_err(adev->dev,
1816                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1817                         adev->ip_versions[SDMA0_HWIP][0]);
1818                 return -EINVAL;
1819         }
1820         return 0;
1821 }
1822
1823 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1824 {
1825         if (adev->ip_versions[VCE_HWIP][0]) {
1826                 switch (adev->ip_versions[UVD_HWIP][0]) {
1827                 case IP_VERSION(7, 0, 0):
1828                 case IP_VERSION(7, 2, 0):
1829                         /* UVD is not supported on vega20 SR-IOV */
1830                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1831                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1832                         break;
1833                 default:
1834                         dev_err(adev->dev,
1835                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1836                                 adev->ip_versions[UVD_HWIP][0]);
1837                         return -EINVAL;
1838                 }
1839                 switch (adev->ip_versions[VCE_HWIP][0]) {
1840                 case IP_VERSION(4, 0, 0):
1841                 case IP_VERSION(4, 1, 0):
1842                         /* VCE is not supported on vega20 SR-IOV */
1843                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1844                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1845                         break;
1846                 default:
1847                         dev_err(adev->dev,
1848                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1849                                 adev->ip_versions[VCE_HWIP][0]);
1850                         return -EINVAL;
1851                 }
1852         } else {
1853                 switch (adev->ip_versions[UVD_HWIP][0]) {
1854                 case IP_VERSION(1, 0, 0):
1855                 case IP_VERSION(1, 0, 1):
1856                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1857                         break;
1858                 case IP_VERSION(2, 0, 0):
1859                 case IP_VERSION(2, 0, 2):
1860                 case IP_VERSION(2, 2, 0):
1861                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1862                         if (!amdgpu_sriov_vf(adev))
1863                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1864                         break;
1865                 case IP_VERSION(2, 0, 3):
1866                         break;
1867                 case IP_VERSION(2, 5, 0):
1868                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1869                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1870                         break;
1871                 case IP_VERSION(2, 6, 0):
1872                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1873                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1874                         break;
1875                 case IP_VERSION(3, 0, 0):
1876                 case IP_VERSION(3, 0, 16):
1877                 case IP_VERSION(3, 1, 1):
1878                 case IP_VERSION(3, 1, 2):
1879                 case IP_VERSION(3, 0, 2):
1880                 case IP_VERSION(3, 0, 192):
1881                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1882                         if (!amdgpu_sriov_vf(adev))
1883                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1884                         break;
1885                 case IP_VERSION(3, 0, 33):
1886                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1887                         break;
1888                 case IP_VERSION(4, 0, 0):
1889                 case IP_VERSION(4, 0, 4):
1890                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
1891                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
1892                         break;
1893                 default:
1894                         dev_err(adev->dev,
1895                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1896                                 adev->ip_versions[UVD_HWIP][0]);
1897                         return -EINVAL;
1898                 }
1899         }
1900         return 0;
1901 }
1902
1903 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1904 {
1905         switch (adev->ip_versions[GC_HWIP][0]) {
1906         case IP_VERSION(10, 1, 10):
1907         case IP_VERSION(10, 1, 1):
1908         case IP_VERSION(10, 1, 2):
1909         case IP_VERSION(10, 1, 3):
1910         case IP_VERSION(10, 1, 4):
1911         case IP_VERSION(10, 3, 0):
1912         case IP_VERSION(10, 3, 1):
1913         case IP_VERSION(10, 3, 2):
1914         case IP_VERSION(10, 3, 3):
1915         case IP_VERSION(10, 3, 4):
1916         case IP_VERSION(10, 3, 5):
1917         case IP_VERSION(10, 3, 6):
1918                 if (amdgpu_mes) {
1919                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1920                         adev->enable_mes = true;
1921                         if (amdgpu_mes_kiq)
1922                                 adev->enable_mes_kiq = true;
1923                 }
1924                 break;
1925         case IP_VERSION(11, 0, 0):
1926         case IP_VERSION(11, 0, 1):
1927         case IP_VERSION(11, 0, 2):
1928                 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
1929                 adev->enable_mes = true;
1930                 adev->enable_mes_kiq = true;
1931                 break;
1932         default:
1933                 break;
1934         }
1935         return 0;
1936 }
1937
1938 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1939 {
1940         int r;
1941
1942         switch (adev->asic_type) {
1943         case CHIP_VEGA10:
1944                 vega10_reg_base_init(adev);
1945                 adev->sdma.num_instances = 2;
1946                 adev->gmc.num_umc = 4;
1947                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1948                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1949                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1950                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1951                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1952                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1953                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1954                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1955                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1956                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1957                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1958                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1959                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1960                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1961                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1962                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1963                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1964                 break;
1965         case CHIP_VEGA12:
1966                 vega10_reg_base_init(adev);
1967                 adev->sdma.num_instances = 2;
1968                 adev->gmc.num_umc = 4;
1969                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1970                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1971                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1972                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1973                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1974                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1975                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1976                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1977                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1978                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1979                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1980                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1981                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1982                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1983                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1984                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1985                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1986                 break;
1987         case CHIP_RAVEN:
1988                 vega10_reg_base_init(adev);
1989                 adev->sdma.num_instances = 1;
1990                 adev->vcn.num_vcn_inst = 1;
1991                 adev->gmc.num_umc = 2;
1992                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1993                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1994                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1995                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1996                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1997                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1998                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1999                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2000                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2001                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2002                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2003                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2004                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2005                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2006                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2007                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2008                 } else {
2009                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2010                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2011                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2012                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2013                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2014                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2015                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2016                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2017                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2018                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2019                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2020                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2021                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2022                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2023                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2024                 }
2025                 break;
2026         case CHIP_VEGA20:
2027                 vega20_reg_base_init(adev);
2028                 adev->sdma.num_instances = 2;
2029                 adev->gmc.num_umc = 8;
2030                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2031                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2032                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2033                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2034                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2035                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2036                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2037                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2038                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2039                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2040                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2041                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2042                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2043                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2044                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2045                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2046                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2047                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2048                 break;
2049         case CHIP_ARCTURUS:
2050                 arct_reg_base_init(adev);
2051                 adev->sdma.num_instances = 8;
2052                 adev->vcn.num_vcn_inst = 2;
2053                 adev->gmc.num_umc = 8;
2054                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2055                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2056                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2057                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2058                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2059                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2060                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2061                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2062                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2063                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2064                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2065                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2066                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2067                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2068                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2069                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2070                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2071                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2072                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2073                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2074                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2075                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2076                 break;
2077         case CHIP_ALDEBARAN:
2078                 aldebaran_reg_base_init(adev);
2079                 adev->sdma.num_instances = 5;
2080                 adev->vcn.num_vcn_inst = 2;
2081                 adev->gmc.num_umc = 4;
2082                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2083                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2084                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2085                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2086                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2087                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2088                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2089                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2090                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2091                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2092                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2093                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2094                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2095                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2096                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2097                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2098                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2099                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2100                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2101                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2102                 break;
2103         default:
2104                 r = amdgpu_discovery_reg_base_init(adev);
2105                 if (r)
2106                         return -EINVAL;
2107
2108                 amdgpu_discovery_harvest_ip(adev);
2109                 amdgpu_discovery_get_gfx_info(adev);
2110                 amdgpu_discovery_get_mall_info(adev);
2111                 amdgpu_discovery_get_vcn_info(adev);
2112                 break;
2113         }
2114
2115         switch (adev->ip_versions[GC_HWIP][0]) {
2116         case IP_VERSION(9, 0, 1):
2117         case IP_VERSION(9, 2, 1):
2118         case IP_VERSION(9, 4, 0):
2119         case IP_VERSION(9, 4, 1):
2120         case IP_VERSION(9, 4, 2):
2121                 adev->family = AMDGPU_FAMILY_AI;
2122                 break;
2123         case IP_VERSION(9, 1, 0):
2124         case IP_VERSION(9, 2, 2):
2125         case IP_VERSION(9, 3, 0):
2126                 adev->family = AMDGPU_FAMILY_RV;
2127                 break;
2128         case IP_VERSION(10, 1, 10):
2129         case IP_VERSION(10, 1, 1):
2130         case IP_VERSION(10, 1, 2):
2131         case IP_VERSION(10, 1, 3):
2132         case IP_VERSION(10, 1, 4):
2133         case IP_VERSION(10, 3, 0):
2134         case IP_VERSION(10, 3, 2):
2135         case IP_VERSION(10, 3, 4):
2136         case IP_VERSION(10, 3, 5):
2137                 adev->family = AMDGPU_FAMILY_NV;
2138                 break;
2139         case IP_VERSION(10, 3, 1):
2140                 adev->family = AMDGPU_FAMILY_VGH;
2141                 break;
2142         case IP_VERSION(10, 3, 3):
2143                 adev->family = AMDGPU_FAMILY_YC;
2144                 break;
2145         case IP_VERSION(10, 3, 6):
2146                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2147                 break;
2148         case IP_VERSION(10, 3, 7):
2149                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2150                 break;
2151         case IP_VERSION(11, 0, 0):
2152         case IP_VERSION(11, 0, 2):
2153                 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2154                 break;
2155         case IP_VERSION(11, 0, 1):
2156                 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2157                 break;
2158         default:
2159                 return -EINVAL;
2160         }
2161
2162         switch (adev->ip_versions[GC_HWIP][0]) {
2163         case IP_VERSION(9, 1, 0):
2164         case IP_VERSION(9, 2, 2):
2165         case IP_VERSION(9, 3, 0):
2166         case IP_VERSION(10, 1, 3):
2167         case IP_VERSION(10, 1, 4):
2168         case IP_VERSION(10, 3, 1):
2169         case IP_VERSION(10, 3, 3):
2170         case IP_VERSION(10, 3, 6):
2171         case IP_VERSION(10, 3, 7):
2172         case IP_VERSION(11, 0, 1):
2173                 adev->flags |= AMD_IS_APU;
2174                 break;
2175         default:
2176                 break;
2177         }
2178
2179         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
2180                 adev->gmc.xgmi.supported = true;
2181
2182         /* set NBIO version */
2183         switch (adev->ip_versions[NBIO_HWIP][0]) {
2184         case IP_VERSION(6, 1, 0):
2185         case IP_VERSION(6, 2, 0):
2186                 adev->nbio.funcs = &nbio_v6_1_funcs;
2187                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2188                 break;
2189         case IP_VERSION(7, 0, 0):
2190         case IP_VERSION(7, 0, 1):
2191         case IP_VERSION(2, 5, 0):
2192                 adev->nbio.funcs = &nbio_v7_0_funcs;
2193                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2194                 break;
2195         case IP_VERSION(7, 4, 0):
2196         case IP_VERSION(7, 4, 1):
2197                 adev->nbio.funcs = &nbio_v7_4_funcs;
2198                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2199                 break;
2200         case IP_VERSION(7, 4, 4):
2201                 adev->nbio.funcs = &nbio_v7_4_funcs;
2202                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
2203                 break;
2204         case IP_VERSION(7, 2, 0):
2205         case IP_VERSION(7, 2, 1):
2206         case IP_VERSION(7, 3, 0):
2207         case IP_VERSION(7, 5, 0):
2208         case IP_VERSION(7, 5, 1):
2209                 adev->nbio.funcs = &nbio_v7_2_funcs;
2210                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2211                 break;
2212         case IP_VERSION(2, 1, 1):
2213         case IP_VERSION(2, 3, 0):
2214         case IP_VERSION(2, 3, 1):
2215         case IP_VERSION(2, 3, 2):
2216                 adev->nbio.funcs = &nbio_v2_3_funcs;
2217                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2218                 break;
2219         case IP_VERSION(3, 3, 0):
2220         case IP_VERSION(3, 3, 1):
2221         case IP_VERSION(3, 3, 2):
2222         case IP_VERSION(3, 3, 3):
2223                 adev->nbio.funcs = &nbio_v2_3_funcs;
2224                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
2225                 break;
2226         case IP_VERSION(4, 3, 0):
2227         case IP_VERSION(4, 3, 1):
2228                 adev->nbio.funcs = &nbio_v4_3_funcs;
2229                 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2230                 break;
2231         case IP_VERSION(7, 7, 0):
2232                 adev->nbio.funcs = &nbio_v7_7_funcs;
2233                 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2234                 break;
2235         default:
2236                 break;
2237         }
2238
2239         switch (adev->ip_versions[HDP_HWIP][0]) {
2240         case IP_VERSION(4, 0, 0):
2241         case IP_VERSION(4, 0, 1):
2242         case IP_VERSION(4, 1, 0):
2243         case IP_VERSION(4, 1, 1):
2244         case IP_VERSION(4, 1, 2):
2245         case IP_VERSION(4, 2, 0):
2246         case IP_VERSION(4, 2, 1):
2247         case IP_VERSION(4, 4, 0):
2248                 adev->hdp.funcs = &hdp_v4_0_funcs;
2249                 break;
2250         case IP_VERSION(5, 0, 0):
2251         case IP_VERSION(5, 0, 1):
2252         case IP_VERSION(5, 0, 2):
2253         case IP_VERSION(5, 0, 3):
2254         case IP_VERSION(5, 0, 4):
2255         case IP_VERSION(5, 2, 0):
2256                 adev->hdp.funcs = &hdp_v5_0_funcs;
2257                 break;
2258         case IP_VERSION(5, 2, 1):
2259                 adev->hdp.funcs = &hdp_v5_2_funcs;
2260                 break;
2261         case IP_VERSION(6, 0, 0):
2262         case IP_VERSION(6, 0, 1):
2263                 adev->hdp.funcs = &hdp_v6_0_funcs;
2264                 break;
2265         default:
2266                 break;
2267         }
2268
2269         switch (adev->ip_versions[DF_HWIP][0]) {
2270         case IP_VERSION(3, 6, 0):
2271         case IP_VERSION(3, 6, 1):
2272         case IP_VERSION(3, 6, 2):
2273                 adev->df.funcs = &df_v3_6_funcs;
2274                 break;
2275         case IP_VERSION(2, 1, 0):
2276         case IP_VERSION(2, 1, 1):
2277         case IP_VERSION(2, 5, 0):
2278         case IP_VERSION(3, 5, 1):
2279         case IP_VERSION(3, 5, 2):
2280                 adev->df.funcs = &df_v1_7_funcs;
2281                 break;
2282         default:
2283                 break;
2284         }
2285
2286         switch (adev->ip_versions[SMUIO_HWIP][0]) {
2287         case IP_VERSION(9, 0, 0):
2288         case IP_VERSION(9, 0, 1):
2289         case IP_VERSION(10, 0, 0):
2290         case IP_VERSION(10, 0, 1):
2291         case IP_VERSION(10, 0, 2):
2292                 adev->smuio.funcs = &smuio_v9_0_funcs;
2293                 break;
2294         case IP_VERSION(11, 0, 0):
2295         case IP_VERSION(11, 0, 2):
2296         case IP_VERSION(11, 0, 3):
2297         case IP_VERSION(11, 0, 4):
2298         case IP_VERSION(11, 0, 7):
2299         case IP_VERSION(11, 0, 8):
2300                 adev->smuio.funcs = &smuio_v11_0_funcs;
2301                 break;
2302         case IP_VERSION(11, 0, 6):
2303         case IP_VERSION(11, 0, 10):
2304         case IP_VERSION(11, 0, 11):
2305         case IP_VERSION(11, 5, 0):
2306         case IP_VERSION(13, 0, 1):
2307         case IP_VERSION(13, 0, 9):
2308         case IP_VERSION(13, 0, 10):
2309                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2310                 break;
2311         case IP_VERSION(13, 0, 2):
2312                 adev->smuio.funcs = &smuio_v13_0_funcs;
2313                 break;
2314         case IP_VERSION(13, 0, 6):
2315         case IP_VERSION(13, 0, 8):
2316                 adev->smuio.funcs = &smuio_v13_0_6_funcs;
2317                 break;
2318         default:
2319                 break;
2320         }
2321
2322         switch (adev->ip_versions[LSDMA_HWIP][0]) {
2323         case IP_VERSION(6, 0, 0):
2324         case IP_VERSION(6, 0, 2):
2325                 adev->lsdma.funcs = &lsdma_v6_0_funcs;
2326                 break;
2327         default:
2328                 break;
2329         }
2330
2331         r = amdgpu_discovery_set_common_ip_blocks(adev);
2332         if (r)
2333                 return r;
2334
2335         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2336         if (r)
2337                 return r;
2338
2339         /* For SR-IOV, PSP needs to be initialized before IH */
2340         if (amdgpu_sriov_vf(adev)) {
2341                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2342                 if (r)
2343                         return r;
2344                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2345                 if (r)
2346                         return r;
2347         } else {
2348                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2349                 if (r)
2350                         return r;
2351
2352                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2353                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2354                         if (r)
2355                                 return r;
2356                 }
2357         }
2358
2359         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2360                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2361                 if (r)
2362                         return r;
2363         }
2364
2365         r = amdgpu_discovery_set_display_ip_blocks(adev);
2366         if (r)
2367                 return r;
2368
2369         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2370         if (r)
2371                 return r;
2372
2373         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2374         if (r)
2375                 return r;
2376
2377         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2378              !amdgpu_sriov_vf(adev)) ||
2379             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
2380                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2381                 if (r)
2382                         return r;
2383         }
2384
2385         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2386         if (r)
2387                 return r;
2388
2389         r = amdgpu_discovery_set_mes_ip_blocks(adev);
2390         if (r)
2391                 return r;
2392
2393         return 0;
2394 }
2395