drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/kthread.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27
  28 #include <drm/drm_drv.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32 #include "amdgpu_reset.h"
  33
  34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
  35 {
  36         struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  37         struct amdgpu_job *job = to_amdgpu_job(s_job);
  38         struct amdgpu_task_info ti;
  39         struct amdgpu_device *adev = ring->adev;
  40         int idx;
  41         int r;
  42
  43         if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
  44                 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
  45                          __func__, s_job->sched->name);
  46
  47                 /* Effectively the job is aborted as the device is gone */
  48                 return DRM_GPU_SCHED_STAT_ENODEV;
  49         }
  50
  51         memset(&ti, 0, sizeof(struct amdgpu_task_info));
  52
  53         if (amdgpu_gpu_recovery &&
  54             amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
  55                 DRM_ERROR("ring %s timeout, but soft recovered\n",
  56                           s_job->sched->name);
  57                 goto exit;
  58         }
  59
  60         amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
  61         DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
  62                   job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
  63                   ring->fence_drv.sync_seq);
  64         DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
  65                   ti.process_name, ti.tgid, ti.task_name, ti.pid);
  66
  67         if (amdgpu_device_should_recover_gpu(ring->adev)) {
  68                 struct amdgpu_reset_context reset_context;
  69                 memset(&reset_context, 0, sizeof(reset_context));
  70
  71                 reset_context.method = AMD_RESET_METHOD_NONE;
  72                 reset_context.reset_req_dev = adev;
  73                 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
  74
  75                 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
  76                 if (r)
  77                         DRM_ERROR("GPU Recovery Failed: %d\n", r);
  78         } else {
  79                 drm_sched_suspend_timeout(&ring->sched);
  80                 if (amdgpu_sriov_vf(adev))
  81                         adev->virt.tdr_debug = true;
  82         }
  83
  84 exit:
  85         drm_dev_exit(idx);
  86         return DRM_GPU_SCHED_STAT_NOMINAL;
  87 }
  88
  89 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  90                      struct amdgpu_job **job, struct amdgpu_vm *vm)
  91 {
  92         if (num_ibs == 0)
  93                 return -EINVAL;
  94
  95         *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
  96         if (!*job)
  97                 return -ENOMEM;
  98
  99         /*
 100          * Initialize the scheduler to at least some ring so that we always
 101          * have a pointer to adev.
 102          */
 103         (*job)->base.sched = &adev->rings[0]->sched;
 104         (*job)->vm = vm;
 105         (*job)->num_ibs = num_ibs;
 106
 107         amdgpu_sync_create(&(*job)->sync);
 108         amdgpu_sync_create(&(*job)->sched_sync);
 109         (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
 110         (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
 111
 112         return 0;
 113 }
 114
 115 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 116                 enum amdgpu_ib_pool_type pool_type,
 117                 struct amdgpu_job **job)
 118 {
 119         int r;
 120
 121         r = amdgpu_job_alloc(adev, 1, job, NULL);
 122         if (r)
 123                 return r;
 124
 125         r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
 126         if (r)
 127                 kfree(*job);
 128
 129         return r;
 130 }
 131
 132 void amdgpu_job_free_resources(struct amdgpu_job *job)
 133 {
 134         struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
 135         struct dma_fence *f;
 136         unsigned i;
 137
 138         /* use sched fence if available */
 139         f = job->base.s_fence ? &job->base.s_fence->finished :  &job->hw_fence;
 140         for (i = 0; i < job->num_ibs; ++i)
 141                 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
 142 }
 143
 144 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
 145 {
 146         struct amdgpu_job *job = to_amdgpu_job(s_job);
 147
 148         drm_sched_job_cleanup(s_job);
 149
 150         amdgpu_sync_free(&job->sync);
 151         amdgpu_sync_free(&job->sched_sync);
 152
 153         dma_fence_put(&job->hw_fence);
 154 }
 155
 156 void amdgpu_job_free(struct amdgpu_job *job)
 157 {
 158         amdgpu_job_free_resources(job);
 159         amdgpu_sync_free(&job->sync);
 160         amdgpu_sync_free(&job->sched_sync);
 161
 162         dma_fence_put(&job->hw_fence);
 163 }
 164
 165 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
 166                       void *owner, struct dma_fence **f)
 167 {
 168         int r;
 169
 170         if (!f)
 171                 return -EINVAL;
 172
 173         r = drm_sched_job_init(&job->base, entity, owner);
 174         if (r)
 175                 return r;
 176
 177         drm_sched_job_arm(&job->base);
 178
 179         *f = dma_fence_get(&job->base.s_fence->finished);
 180         amdgpu_job_free_resources(job);
 181         drm_sched_entity_push_job(&job->base);
 182
 183         return 0;
 184 }
 185
 186 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
 187                              struct dma_fence **fence)
 188 {
 189         int r;
 190
 191         job->base.sched = &ring->sched;
 192         r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
 193
 194         if (r)
 195                 return r;
 196
 197         amdgpu_job_free(job);
 198         return 0;
 199 }
 200
 201 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
 202                                                struct drm_sched_entity *s_entity)
 203 {
 204         struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
 205         struct amdgpu_job *job = to_amdgpu_job(sched_job);
 206         struct amdgpu_vm *vm = job->vm;
 207         struct dma_fence *fence;
 208         int r;
 209
 210         fence = amdgpu_sync_get_fence(&job->sync);
 211         if (fence && drm_sched_dependency_optimized(fence, s_entity)) {
 212                 r = amdgpu_sync_fence(&job->sched_sync, fence);
 213                 if (r)
 214                         DRM_ERROR("Error adding fence (%d)\n", r);
 215         }
 216
 217         while (fence == NULL && vm && !job->vmid) {
 218                 r = amdgpu_vmid_grab(vm, ring, &job->sync,
 219                                      &job->base.s_fence->finished,
 220                                      job);
 221                 if (r)
 222                         DRM_ERROR("Error getting VM ID (%d)\n", r);
 223
 224                 fence = amdgpu_sync_get_fence(&job->sync);
 225         }
 226
 227         return fence;
 228 }
 229
 230 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 231 {
 232         struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
 233         struct dma_fence *fence = NULL, *finished;
 234         struct amdgpu_job *job;
 235         int r = 0;
 236
 237         job = to_amdgpu_job(sched_job);
 238         finished = &job->base.s_fence->finished;
 239
 240         BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
 241
 242         trace_amdgpu_sched_run_job(job);
 243
 244         if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
 245                 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
 246
 247         if (finished->error < 0) {
 248                 DRM_INFO("Skip scheduling IBs!\n");
 249         } else {
 250                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
 251                                        &fence);
 252                 if (r)
 253                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
 254         }
 255
 256         job->job_run_counter++;
 257         amdgpu_job_free_resources(job);
 258
 259         fence = r ? ERR_PTR(r) : fence;
 260         return fence;
 261 }
 262
 263 #define to_drm_sched_job(sched_job)             \
 264                 container_of((sched_job), struct drm_sched_job, queue_node)
 265
 266 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
 267 {
 268         struct drm_sched_job *s_job;
 269         struct drm_sched_entity *s_entity = NULL;
 270         int i;
 271
 272         /* Signal all jobs not yet scheduled */
 273         for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
 274                 struct drm_sched_rq *rq = &sched->sched_rq[i];
 275                 spin_lock(&rq->lock);
 276                 list_for_each_entry(s_entity, &rq->entities, list) {
 277                         while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
 278                                 struct drm_sched_fence *s_fence = s_job->s_fence;
 279
 280                                 dma_fence_signal(&s_fence->scheduled);
 281                                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 282                                 dma_fence_signal(&s_fence->finished);
 283                         }
 284                 }
 285                 spin_unlock(&rq->lock);
 286         }
 287
 288         /* Signal all jobs already scheduled to HW */
 289         list_for_each_entry(s_job, &sched->pending_list, list) {
 290                 struct drm_sched_fence *s_fence = s_job->s_fence;
 291
 292                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 293                 dma_fence_signal(&s_fence->finished);
 294         }
 295 }
 296
 297 const struct drm_sched_backend_ops amdgpu_sched_ops = {
 298         .dependency = amdgpu_job_dependency,
 299         .run_job = amdgpu_job_run,
 300         .timedout_job = amdgpu_job_timedout,
 301         .free_job = amdgpu_job_free_cb
 302 };