drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/GC/gc_9_0_offset.h"
  32 #include "vega10/GC/gc_9_0_sh_mask.h"
  33 #include "vega10/vega10_enum.h"
  34 #include "vega10/HDP/hdp_4_0_offset.h"
  35
  36 #include "soc15_common.h"
  37 #include "clearstate_gfx9.h"
  38 #include "v9_structs.h"
  39
  40 #define GFX9_NUM_GFX_RINGS     1
  41 #define GFX9_MEC_HPD_SIZE 2048
  42 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  43 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  44 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
  45
  46 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  52
  53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  59
  60 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  61 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  62 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  63 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  64 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  65 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  66
  67 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  68 {
  69         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
  70                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
  71         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
  72                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
  73         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
  74                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
  75         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
  76                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
  77         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
  78                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
  79         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
  80                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
  81         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
  82                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
  83         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
  84                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
  85         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
  86                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
  87         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
  88                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
  89         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
  90                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
  91         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
  92                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
  93         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
  94                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
  95         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
  96                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
  97         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
  98                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
  99         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
 100                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
 101 };
 102
 103 static const u32 golden_settings_gc_9_0[] =
 104 {
 105         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 106         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 107         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 108         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 109         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 110         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 111         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 112         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 113         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 114         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 115         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 116         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 117         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 118         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 119         SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
 120         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 121         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
 122         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
 123         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 124         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
 125         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 126 };
 127
 128 static const u32 golden_settings_gc_9_0_vg10[] =
 129 {
 130         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
 131         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 132         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
 133         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
 134         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
 135         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 136         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
 137 };
 138
 139 static const u32 golden_settings_gc_9_1[] =
 140 {
 141         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
 142         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 143         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 144         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 145         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 146         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 147         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 148         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 149         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 150         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 151         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 152         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 153         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 154         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 155         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 156         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 157         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
 158         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
 159         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 160         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
 161         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 162 };
 163
 164 static const u32 golden_settings_gc_9_1_rv1[] =
 165 {
 166         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 167         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
 168         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
 169         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
 170         SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
 171         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 172         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
 173 };
 174
 175 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 176 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 177
 178 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 179 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 180 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 181 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 182 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 183                                  struct amdgpu_cu_info *cu_info);
 184 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 185 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 186 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 187
 188 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 189 {
 190         switch (adev->asic_type) {
 191         case CHIP_VEGA10:
 192                 amdgpu_program_register_sequence(adev,
 193                                                  golden_settings_gc_9_0,
 194                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
 195                 amdgpu_program_register_sequence(adev,
 196                                                  golden_settings_gc_9_0_vg10,
 197                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 198                 break;
 199         case CHIP_RAVEN:
 200                 amdgpu_program_register_sequence(adev,
 201                                                  golden_settings_gc_9_1,
 202                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
 203                 amdgpu_program_register_sequence(adev,
 204                                                  golden_settings_gc_9_1_rv1,
 205                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 206                 break;
 207         default:
 208                 break;
 209         }
 210 }
 211
 212 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 213 {
 214         adev->gfx.scratch.num_reg = 7;
 215         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 216         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 217 }
 218
 219 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 220                                        bool wc, uint32_t reg, uint32_t val)
 221 {
 222         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 223         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 224                                 WRITE_DATA_DST_SEL(0) |
 225                                 (wc ? WR_CONFIRM : 0));
 226         amdgpu_ring_write(ring, reg);
 227         amdgpu_ring_write(ring, 0);
 228         amdgpu_ring_write(ring, val);
 229 }
 230
 231 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 232                                   int mem_space, int opt, uint32_t addr0,
 233                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 234                                   uint32_t inv)
 235 {
 236         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 237         amdgpu_ring_write(ring,
 238                                  /* memory (1) or register (0) */
 239                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 240                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 241                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 242                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 243
 244         if (mem_space)
 245                 BUG_ON(addr0 & 0x3); /* Dword align */
 246         amdgpu_ring_write(ring, addr0);
 247         amdgpu_ring_write(ring, addr1);
 248         amdgpu_ring_write(ring, ref);
 249         amdgpu_ring_write(ring, mask);
 250         amdgpu_ring_write(ring, inv); /* poll interval */
 251 }
 252
 253 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 254 {
 255         struct amdgpu_device *adev = ring->adev;
 256         uint32_t scratch;
 257         uint32_t tmp = 0;
 258         unsigned i;
 259         int r;
 260
 261         r = amdgpu_gfx_scratch_get(adev, &scratch);
 262         if (r) {
 263                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 264                 return r;
 265         }
 266         WREG32(scratch, 0xCAFEDEAD);
 267         r = amdgpu_ring_alloc(ring, 3);
 268         if (r) {
 269                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 270                           ring->idx, r);
 271                 amdgpu_gfx_scratch_free(adev, scratch);
 272                 return r;
 273         }
 274         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 275         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 276         amdgpu_ring_write(ring, 0xDEADBEEF);
 277         amdgpu_ring_commit(ring);
 278
 279         for (i = 0; i < adev->usec_timeout; i++) {
 280                 tmp = RREG32(scratch);
 281                 if (tmp == 0xDEADBEEF)
 282                         break;
 283                 DRM_UDELAY(1);
 284         }
 285         if (i < adev->usec_timeout) {
 286                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 287                          ring->idx, i);
 288         } else {
 289                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 290                           ring->idx, scratch, tmp);
 291                 r = -EINVAL;
 292         }
 293         amdgpu_gfx_scratch_free(adev, scratch);
 294         return r;
 295 }
 296
 297 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 298 {
 299         struct amdgpu_device *adev = ring->adev;
 300         struct amdgpu_ib ib;
 301         struct dma_fence *f = NULL;
 302         uint32_t scratch;
 303         uint32_t tmp = 0;
 304         long r;
 305
 306         r = amdgpu_gfx_scratch_get(adev, &scratch);
 307         if (r) {
 308                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 309                 return r;
 310         }
 311         WREG32(scratch, 0xCAFEDEAD);
 312         memset(&ib, 0, sizeof(ib));
 313         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 314         if (r) {
 315                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 316                 goto err1;
 317         }
 318         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 319         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 320         ib.ptr[2] = 0xDEADBEEF;
 321         ib.length_dw = 3;
 322
 323         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 324         if (r)
 325                 goto err2;
 326
 327         r = dma_fence_wait_timeout(f, false, timeout);
 328         if (r == 0) {
 329                 DRM_ERROR("amdgpu: IB test timed out.\n");
 330                 r = -ETIMEDOUT;
 331                 goto err2;
 332         } else if (r < 0) {
 333                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 334                 goto err2;
 335         }
 336         tmp = RREG32(scratch);
 337         if (tmp == 0xDEADBEEF) {
 338                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 339                 r = 0;
 340         } else {
 341                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 342                           scratch, tmp);
 343                 r = -EINVAL;
 344         }
 345 err2:
 346         amdgpu_ib_free(adev, &ib, NULL);
 347         dma_fence_put(f);
 348 err1:
 349         amdgpu_gfx_scratch_free(adev, scratch);
 350         return r;
 351 }
 352
 353 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 354 {
 355         const char *chip_name;
 356         char fw_name[30];
 357         int err;
 358         struct amdgpu_firmware_info *info = NULL;
 359         const struct common_firmware_header *header = NULL;
 360         const struct gfx_firmware_header_v1_0 *cp_hdr;
 361         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 362         unsigned int *tmp = NULL;
 363         unsigned int i = 0;
 364
 365         DRM_DEBUG("\n");
 366
 367         switch (adev->asic_type) {
 368         case CHIP_VEGA10:
 369                 chip_name = "vega10";
 370                 break;
 371         case CHIP_RAVEN:
 372                 chip_name = "raven";
 373                 break;
 374         default:
 375                 BUG();
 376         }
 377
 378         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 379         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 380         if (err)
 381                 goto out;
 382         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 383         if (err)
 384                 goto out;
 385         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 386         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 387         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 388
 389         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 390         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 391         if (err)
 392                 goto out;
 393         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 394         if (err)
 395                 goto out;
 396         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 397         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 398         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 399
 400         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 401         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 402         if (err)
 403                 goto out;
 404         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 405         if (err)
 406                 goto out;
 407         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 408         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 409         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 410
 411         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 412         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 413         if (err)
 414                 goto out;
 415         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 416         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 417         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 418         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 419         adev->gfx.rlc.save_and_restore_offset =
 420                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 421         adev->gfx.rlc.clear_state_descriptor_offset =
 422                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 423         adev->gfx.rlc.avail_scratch_ram_locations =
 424                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 425         adev->gfx.rlc.reg_restore_list_size =
 426                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 427         adev->gfx.rlc.reg_list_format_start =
 428                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 429         adev->gfx.rlc.reg_list_format_separate_start =
 430                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 431         adev->gfx.rlc.starting_offsets_start =
 432                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 433         adev->gfx.rlc.reg_list_format_size_bytes =
 434                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 435         adev->gfx.rlc.reg_list_size_bytes =
 436                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 437         adev->gfx.rlc.register_list_format =
 438                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 439                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 440         if (!adev->gfx.rlc.register_list_format) {
 441                 err = -ENOMEM;
 442                 goto out;
 443         }
 444
 445         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 446                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 447         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 448                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 449
 450         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 451
 452         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 453                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 454         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 455                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 456
 457         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 458         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 459         if (err)
 460                 goto out;
 461         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 462         if (err)
 463                 goto out;
 464         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 465         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 466         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 467
 468
 469         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 470         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 471         if (!err) {
 472                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 473                 if (err)
 474                         goto out;
 475                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 476                 adev->gfx.mec2_fw->data;
 477                 adev->gfx.mec2_fw_version =
 478                 le32_to_cpu(cp_hdr->header.ucode_version);
 479                 adev->gfx.mec2_feature_version =
 480                 le32_to_cpu(cp_hdr->ucode_feature_version);
 481         } else {
 482                 err = 0;
 483                 adev->gfx.mec2_fw = NULL;
 484         }
 485
 486         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 487                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 488                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 489                 info->fw = adev->gfx.pfp_fw;
 490                 header = (const struct common_firmware_header *)info->fw->data;
 491                 adev->firmware.fw_size +=
 492                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 493
 494                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 495                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 496                 info->fw = adev->gfx.me_fw;
 497                 header = (const struct common_firmware_header *)info->fw->data;
 498                 adev->firmware.fw_size +=
 499                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 500
 501                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 502                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 503                 info->fw = adev->gfx.ce_fw;
 504                 header = (const struct common_firmware_header *)info->fw->data;
 505                 adev->firmware.fw_size +=
 506                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 507
 508                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 509                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 510                 info->fw = adev->gfx.rlc_fw;
 511                 header = (const struct common_firmware_header *)info->fw->data;
 512                 adev->firmware.fw_size +=
 513                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 514
 515                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 516                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 517                 info->fw = adev->gfx.mec_fw;
 518                 header = (const struct common_firmware_header *)info->fw->data;
 519                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 520                 adev->firmware.fw_size +=
 521                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 522
 523                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 524                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 525                 info->fw = adev->gfx.mec_fw;
 526                 adev->firmware.fw_size +=
 527                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 528
 529                 if (adev->gfx.mec2_fw) {
 530                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 531                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 532                         info->fw = adev->gfx.mec2_fw;
 533                         header = (const struct common_firmware_header *)info->fw->data;
 534                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 535                         adev->firmware.fw_size +=
 536                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 537                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 538                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 539                         info->fw = adev->gfx.mec2_fw;
 540                         adev->firmware.fw_size +=
 541                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 542                 }
 543
 544         }
 545
 546 out:
 547         if (err) {
 548                 dev_err(adev->dev,
 549                         "gfx9: Failed to load firmware \"%s\"\n",
 550                         fw_name);
 551                 release_firmware(adev->gfx.pfp_fw);
 552                 adev->gfx.pfp_fw = NULL;
 553                 release_firmware(adev->gfx.me_fw);
 554                 adev->gfx.me_fw = NULL;
 555                 release_firmware(adev->gfx.ce_fw);
 556                 adev->gfx.ce_fw = NULL;
 557                 release_firmware(adev->gfx.rlc_fw);
 558                 adev->gfx.rlc_fw = NULL;
 559                 release_firmware(adev->gfx.mec_fw);
 560                 adev->gfx.mec_fw = NULL;
 561                 release_firmware(adev->gfx.mec2_fw);
 562                 adev->gfx.mec2_fw = NULL;
 563         }
 564         return err;
 565 }
 566
 567 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 568 {
 569         u32 count = 0;
 570         const struct cs_section_def *sect = NULL;
 571         const struct cs_extent_def *ext = NULL;
 572
 573         /* begin clear state */
 574         count += 2;
 575         /* context control state */
 576         count += 3;
 577
 578         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 579                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 580                         if (sect->id == SECT_CONTEXT)
 581                                 count += 2 + ext->reg_count;
 582                         else
 583                                 return 0;
 584                 }
 585         }
 586
 587         /* end clear state */
 588         count += 2;
 589         /* clear state */
 590         count += 2;
 591
 592         return count;
 593 }
 594
 595 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 596                                     volatile u32 *buffer)
 597 {
 598         u32 count = 0, i;
 599         const struct cs_section_def *sect = NULL;
 600         const struct cs_extent_def *ext = NULL;
 601
 602         if (adev->gfx.rlc.cs_data == NULL)
 603                 return;
 604         if (buffer == NULL)
 605                 return;
 606
 607         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 608         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 609
 610         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 611         buffer[count++] = cpu_to_le32(0x80000000);
 612         buffer[count++] = cpu_to_le32(0x80000000);
 613
 614         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 615                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 616                         if (sect->id == SECT_CONTEXT) {
 617                                 buffer[count++] =
 618                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 619                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 620                                                 PACKET3_SET_CONTEXT_REG_START);
 621                                 for (i = 0; i < ext->reg_count; i++)
 622                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 623                         } else {
 624                                 return;
 625                         }
 626                 }
 627         }
 628
 629         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 630         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 631
 632         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 633         buffer[count++] = cpu_to_le32(0);
 634 }
 635
 636 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 637 {
 638         uint32_t data = 0;
 639
 640         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 641         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 642         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 643         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 644         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 645
 646         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 647         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 648
 649         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 650         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 651
 652         mutex_lock(&adev->grbm_idx_mutex);
 653         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 654         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 655         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 656
 657         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 658         data |= (0x0003 << RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT) &
 659                 RLC_LB_PARAMS__FIFO_SAMPLES_MASK;
 660         data |= (0x0010 << RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT) &
 661                 RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK;
 662         data |= (0x033F << RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT) &
 663                 RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK;
 664         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 665
 666         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 667         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 668         data &= 0x0000FFFF;
 669         data |= 0x00C00000;
 670         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 671
 672         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 673         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 674
 675         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 676          * but used for RLC_LB_CNTL configuration */
 677         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 678         data |= (0x09 << RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT) &
 679                 RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK;
 680         data |= (0x80000 << RLC_LB_CNTL__RESERVED__SHIFT) &
 681                 RLC_LB_CNTL__RESERVED_MASK;
 682         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 683         mutex_unlock(&adev->grbm_idx_mutex);
 684 }
 685
 686 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 687 {
 688         uint32_t data = 0;
 689
 690         data = RREG32_SOC15(GC, 0, mmRLC_LB_CNTL);
 691         if (enable)
 692                 data |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
 693         else
 694                 data &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
 695         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 696 }
 697
 698 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 699 {
 700         const __le32 *fw_data;
 701         volatile u32 *dst_ptr;
 702         int me, i, max_me = 5;
 703         u32 bo_offset = 0;
 704         u32 table_offset, table_size;
 705
 706         /* write the cp table buffer */
 707         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 708         for (me = 0; me < max_me; me++) {
 709                 if (me == 0) {
 710                         const struct gfx_firmware_header_v1_0 *hdr =
 711                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 712                         fw_data = (const __le32 *)
 713                                 (adev->gfx.ce_fw->data +
 714                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 715                         table_offset = le32_to_cpu(hdr->jt_offset);
 716                         table_size = le32_to_cpu(hdr->jt_size);
 717                 } else if (me == 1) {
 718                         const struct gfx_firmware_header_v1_0 *hdr =
 719                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 720                         fw_data = (const __le32 *)
 721                                 (adev->gfx.pfp_fw->data +
 722                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 723                         table_offset = le32_to_cpu(hdr->jt_offset);
 724                         table_size = le32_to_cpu(hdr->jt_size);
 725                 } else if (me == 2) {
 726                         const struct gfx_firmware_header_v1_0 *hdr =
 727                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 728                         fw_data = (const __le32 *)
 729                                 (adev->gfx.me_fw->data +
 730                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 731                         table_offset = le32_to_cpu(hdr->jt_offset);
 732                         table_size = le32_to_cpu(hdr->jt_size);
 733                 } else if (me == 3) {
 734                         const struct gfx_firmware_header_v1_0 *hdr =
 735                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 736                         fw_data = (const __le32 *)
 737                                 (adev->gfx.mec_fw->data +
 738                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 739                         table_offset = le32_to_cpu(hdr->jt_offset);
 740                         table_size = le32_to_cpu(hdr->jt_size);
 741                 } else  if (me == 4) {
 742                         const struct gfx_firmware_header_v1_0 *hdr =
 743                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 744                         fw_data = (const __le32 *)
 745                                 (adev->gfx.mec2_fw->data +
 746                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 747                         table_offset = le32_to_cpu(hdr->jt_offset);
 748                         table_size = le32_to_cpu(hdr->jt_size);
 749                 }
 750
 751                 for (i = 0; i < table_size; i ++) {
 752                         dst_ptr[bo_offset + i] =
 753                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 754                 }
 755
 756                 bo_offset += table_size;
 757         }
 758 }
 759
 760 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 761 {
 762         /* clear state block */
 763         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 764                         &adev->gfx.rlc.clear_state_gpu_addr,
 765                         (void **)&adev->gfx.rlc.cs_ptr);
 766
 767         /* jump table block */
 768         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 769                         &adev->gfx.rlc.cp_table_gpu_addr,
 770                         (void **)&adev->gfx.rlc.cp_table_ptr);
 771 }
 772
 773 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 774 {
 775         volatile u32 *dst_ptr;
 776         u32 dws;
 777         const struct cs_section_def *cs_data;
 778         int r;
 779
 780         adev->gfx.rlc.cs_data = gfx9_cs_data;
 781
 782         cs_data = adev->gfx.rlc.cs_data;
 783
 784         if (cs_data) {
 785                 /* clear state block */
 786                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 787                 if (adev->gfx.rlc.clear_state_obj == NULL) {
 788                         r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
 789                                                 AMDGPU_GEM_DOMAIN_VRAM,
 790                                                 &adev->gfx.rlc.clear_state_obj,
 791                                                 &adev->gfx.rlc.clear_state_gpu_addr,
 792                                                 (void **)&adev->gfx.rlc.cs_ptr);
 793                         if (r) {
 794                                 dev_err(adev->dev,
 795                                         "(%d) failed to create rlc csb bo\n", r);
 796                                 gfx_v9_0_rlc_fini(adev);
 797                                 return r;
 798                         }
 799                 }
 800                 /* set up the cs buffer */
 801                 dst_ptr = adev->gfx.rlc.cs_ptr;
 802                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 803                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 804                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 805         }
 806
 807         if (adev->asic_type == CHIP_RAVEN) {
 808                 /* TODO: double check the cp_table_size for RV */
 809                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 810                 if (adev->gfx.rlc.cp_table_obj == NULL) {
 811                         r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
 812                                                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 813                                                 &adev->gfx.rlc.cp_table_obj,
 814                                                 &adev->gfx.rlc.cp_table_gpu_addr,
 815                                                 (void **)&adev->gfx.rlc.cp_table_ptr);
 816                         if (r) {
 817                                 dev_err(adev->dev,
 818                                         "(%d) failed to create cp table bo\n", r);
 819                                 gfx_v9_0_rlc_fini(adev);
 820                                 return r;
 821                         }
 822                 }
 823
 824                 rv_init_cp_jump_table(adev);
 825                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 826                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 827
 828                 gfx_v9_0_init_lbpw(adev);
 829         }
 830
 831         return 0;
 832 }
 833
 834 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 835 {
 836         int r;
 837
 838         if (adev->gfx.mec.hpd_eop_obj) {
 839                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
 840                 if (unlikely(r != 0))
 841                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 842                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 843                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 844
 845                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 846                 adev->gfx.mec.hpd_eop_obj = NULL;
 847         }
 848         if (adev->gfx.mec.mec_fw_obj) {
 849                 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
 850                 if (unlikely(r != 0))
 851                         dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
 852                 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
 853                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 854
 855                 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
 856                 adev->gfx.mec.mec_fw_obj = NULL;
 857         }
 858 }
 859
 860 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 861 {
 862         int r;
 863         u32 *hpd;
 864         const __le32 *fw_data;
 865         unsigned fw_size;
 866         u32 *fw;
 867         size_t mec_hpd_size;
 868
 869         const struct gfx_firmware_header_v1_0 *mec_hdr;
 870
 871         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 872
 873         switch (adev->asic_type) {
 874         case CHIP_VEGA10:
 875                 adev->gfx.mec.num_mec = 2;
 876                 break;
 877         default:
 878                 adev->gfx.mec.num_mec = 1;
 879                 break;
 880         }
 881
 882         adev->gfx.mec.num_pipe_per_mec = 4;
 883         adev->gfx.mec.num_queue_per_pipe = 8;
 884
 885         /* take ownership of the relevant compute queues */
 886         amdgpu_gfx_compute_queue_acquire(adev);
 887         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 888
 889         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 890                 r = amdgpu_bo_create(adev,
 891                                      mec_hpd_size,
 892                                      PAGE_SIZE, true,
 893                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 894                                      &adev->gfx.mec.hpd_eop_obj);
 895                 if (r) {
 896                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 897                         return r;
 898                 }
 899         }
 900
 901         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 902         if (unlikely(r != 0)) {
 903                 gfx_v9_0_mec_fini(adev);
 904                 return r;
 905         }
 906         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 907                           &adev->gfx.mec.hpd_eop_gpu_addr);
 908         if (r) {
 909                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 910                 gfx_v9_0_mec_fini(adev);
 911                 return r;
 912         }
 913         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 914         if (r) {
 915                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 916                 gfx_v9_0_mec_fini(adev);
 917                 return r;
 918         }
 919
 920         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
 921
 922         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 923         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 924
 925         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 926
 927         fw_data = (const __le32 *)
 928                 (adev->gfx.mec_fw->data +
 929                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 930         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
 931
 932         if (adev->gfx.mec.mec_fw_obj == NULL) {
 933                 r = amdgpu_bo_create(adev,
 934                         mec_hdr->header.ucode_size_bytes,
 935                         PAGE_SIZE, true,
 936                         AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 937                         &adev->gfx.mec.mec_fw_obj);
 938                 if (r) {
 939                         dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 940                         return r;
 941                 }
 942         }
 943
 944         r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
 945         if (unlikely(r != 0)) {
 946                 gfx_v9_0_mec_fini(adev);
 947                 return r;
 948         }
 949         r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
 950                         &adev->gfx.mec.mec_fw_gpu_addr);
 951         if (r) {
 952                 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
 953                 gfx_v9_0_mec_fini(adev);
 954                 return r;
 955         }
 956         r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
 957         if (r) {
 958                 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
 959                 gfx_v9_0_mec_fini(adev);
 960                 return r;
 961         }
 962         memcpy(fw, fw_data, fw_size);
 963
 964         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 965         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 966
 967
 968         return 0;
 969 }
 970
 971 static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
 972 {
 973         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 974
 975         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 976 }
 977
 978 static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
 979 {
 980         int r;
 981         u32 *hpd;
 982         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 983
 984         r = amdgpu_bo_create_kernel(adev, GFX9_MEC_HPD_SIZE, PAGE_SIZE,
 985                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 986                                     &kiq->eop_gpu_addr, (void **)&hpd);
 987         if (r) {
 988                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 989                 return r;
 990         }
 991
 992         memset(hpd, 0, GFX9_MEC_HPD_SIZE);
 993
 994         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 995         if (unlikely(r != 0))
 996                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 997         amdgpu_bo_kunmap(kiq->eop_obj);
 998         amdgpu_bo_unreserve(kiq->eop_obj);
 999
1000         return 0;
1001 }
1002
1003 static int gfx_v9_0_kiq_acquire(struct amdgpu_device *adev,
1004                                  struct amdgpu_ring *ring)
1005 {
1006         int queue_bit;
1007         int mec, pipe, queue;
1008
1009         queue_bit = adev->gfx.mec.num_mec
1010                     * adev->gfx.mec.num_pipe_per_mec
1011                     * adev->gfx.mec.num_queue_per_pipe;
1012
1013         while (queue_bit-- >= 0) {
1014                 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
1015                         continue;
1016
1017                 amdgpu_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
1018
1019                 /* Using pipes 2/3 from MEC 2 seems cause problems */
1020                 if (mec == 1 && pipe > 1)
1021                         continue;
1022
1023                 ring->me = mec + 1;
1024                 ring->pipe = pipe;
1025                 ring->queue = queue;
1026
1027                 return 0;
1028         }
1029
1030         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
1031         return -EINVAL;
1032 }
1033
1034 static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
1035                                   struct amdgpu_ring *ring,
1036                                   struct amdgpu_irq_src *irq)
1037 {
1038         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
1039         int r = 0;
1040
1041         mutex_init(&kiq->ring_mutex);
1042
1043         r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
1044         if (r)
1045                 return r;
1046
1047         ring->adev = NULL;
1048         ring->ring_obj = NULL;
1049         ring->use_doorbell = true;
1050         ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
1051
1052         r = gfx_v9_0_kiq_acquire(adev, ring);
1053         if (r)
1054                 return r;
1055
1056         ring->queue = 0;
1057         ring->eop_gpu_addr = kiq->eop_gpu_addr;
1058         sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
1059         r = amdgpu_ring_init(adev, ring, 1024,
1060                              irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
1061         if (r)
1062                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
1063
1064         return r;
1065 }
1066 static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
1067                                    struct amdgpu_irq_src *irq)
1068 {
1069         amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
1070         amdgpu_ring_fini(ring);
1071 }
1072
1073 /* create MQD for each compute queue */
1074 static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
1075 {
1076         struct amdgpu_ring *ring = NULL;
1077         int r, i;
1078
1079         /* create MQD for KIQ */
1080         ring = &adev->gfx.kiq.ring;
1081         if (!ring->mqd_obj) {
1082                 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
1083                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1084                                             &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1085                 if (r) {
1086                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
1087                         return r;
1088                 }
1089
1090                 /* prepare MQD backup */
1091                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
1092                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
1093                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
1094         }
1095
1096         /* create MQD for each KCQ */
1097         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1098                 ring = &adev->gfx.compute_ring[i];
1099                 if (!ring->mqd_obj) {
1100                         r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
1101                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1102                                                     &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1103                         if (r) {
1104                                 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
1105                                 return r;
1106                         }
1107
1108                         /* prepare MQD backup */
1109                         adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
1110                         if (!adev->gfx.mec.mqd_backup[i])
1111                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
1112                 }
1113         }
1114
1115         return 0;
1116 }
1117
1118 static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
1119 {
1120         struct amdgpu_ring *ring = NULL;
1121         int i;
1122
1123         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1124                 ring = &adev->gfx.compute_ring[i];
1125                 kfree(adev->gfx.mec.mqd_backup[i]);
1126                 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1127         }
1128
1129         ring = &adev->gfx.kiq.ring;
1130         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
1131         amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1132 }
1133
1134 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1135 {
1136         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1137                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1138                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1139                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1140                 (SQ_IND_INDEX__FORCE_READ_MASK));
1141         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1142 }
1143
1144 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1145                            uint32_t wave, uint32_t thread,
1146                            uint32_t regno, uint32_t num, uint32_t *out)
1147 {
1148         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1149                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1150                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1151                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1152                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1153                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1154                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1155         while (num--)
1156                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1157 }
1158
1159 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1160 {
1161         /* type 1 wave data */
1162         dst[(*no_fields)++] = 1;
1163         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1164         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1165         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1166         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1167         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1168         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1169         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1170         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1171         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1172         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1173         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1174         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1175         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1176         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1177 }
1178
1179 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1180                                      uint32_t wave, uint32_t start,
1181                                      uint32_t size, uint32_t *dst)
1182 {
1183         wave_read_regs(
1184                 adev, simd, wave, 0,
1185                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1186 }
1187
1188
1189 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1190         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1191         .select_se_sh = &gfx_v9_0_select_se_sh,
1192         .read_wave_data = &gfx_v9_0_read_wave_data,
1193         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1194 };
1195
1196 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1197 {
1198         u32 gb_addr_config;
1199
1200         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1201
1202         switch (adev->asic_type) {
1203         case CHIP_VEGA10:
1204                 adev->gfx.config.max_hw_contexts = 8;
1205                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1206                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1207                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1208                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1209                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1210                 break;
1211         case CHIP_RAVEN:
1212                 adev->gfx.config.max_hw_contexts = 8;
1213                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1214                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1215                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1216                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1217                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1218                 break;
1219         default:
1220                 BUG();
1221                 break;
1222         }
1223
1224         adev->gfx.config.gb_addr_config = gb_addr_config;
1225
1226         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1227                         REG_GET_FIELD(
1228                                         adev->gfx.config.gb_addr_config,
1229                                         GB_ADDR_CONFIG,
1230                                         NUM_PIPES);
1231
1232         adev->gfx.config.max_tile_pipes =
1233                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1234
1235         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1236                         REG_GET_FIELD(
1237                                         adev->gfx.config.gb_addr_config,
1238                                         GB_ADDR_CONFIG,
1239                                         NUM_BANKS);
1240         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1241                         REG_GET_FIELD(
1242                                         adev->gfx.config.gb_addr_config,
1243                                         GB_ADDR_CONFIG,
1244                                         MAX_COMPRESSED_FRAGS);
1245         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1246                         REG_GET_FIELD(
1247                                         adev->gfx.config.gb_addr_config,
1248                                         GB_ADDR_CONFIG,
1249                                         NUM_RB_PER_SE);
1250         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1251                         REG_GET_FIELD(
1252                                         adev->gfx.config.gb_addr_config,
1253                                         GB_ADDR_CONFIG,
1254                                         NUM_SHADER_ENGINES);
1255         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1256                         REG_GET_FIELD(
1257                                         adev->gfx.config.gb_addr_config,
1258                                         GB_ADDR_CONFIG,
1259                                         PIPE_INTERLEAVE_SIZE));
1260 }
1261
1262 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1263                                    struct amdgpu_ngg_buf *ngg_buf,
1264                                    int size_se,
1265                                    int default_size_se)
1266 {
1267         int r;
1268
1269         if (size_se < 0) {
1270                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1271                 return -EINVAL;
1272         }
1273         size_se = size_se ? size_se : default_size_se;
1274
1275         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1276         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1277                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1278                                     &ngg_buf->bo,
1279                                     &ngg_buf->gpu_addr,
1280                                     NULL);
1281         if (r) {
1282                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1283                 return r;
1284         }
1285         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1286
1287         return r;
1288 }
1289
1290 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1291 {
1292         int i;
1293
1294         for (i = 0; i < NGG_BUF_MAX; i++)
1295                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1296                                       &adev->gfx.ngg.buf[i].gpu_addr,
1297                                       NULL);
1298
1299         memset(&adev->gfx.ngg.buf[0], 0,
1300                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1301
1302         adev->gfx.ngg.init = false;
1303
1304         return 0;
1305 }
1306
1307 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1308 {
1309         int r;
1310
1311         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1312                 return 0;
1313
1314         /* GDS reserve memory: 64 bytes alignment */
1315         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1316         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1317         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1318         adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1319         adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1320
1321         /* Primitive Buffer */
1322         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1323                                     amdgpu_prim_buf_per_se,
1324                                     64 * 1024);
1325         if (r) {
1326                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1327                 goto err;
1328         }
1329
1330         /* Position Buffer */
1331         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1332                                     amdgpu_pos_buf_per_se,
1333                                     256 * 1024);
1334         if (r) {
1335                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1336                 goto err;
1337         }
1338
1339         /* Control Sideband */
1340         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1341                                     amdgpu_cntl_sb_buf_per_se,
1342                                     256);
1343         if (r) {
1344                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1345                 goto err;
1346         }
1347
1348         /* Parameter Cache, not created by default */
1349         if (amdgpu_param_buf_per_se <= 0)
1350                 goto out;
1351
1352         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1353                                     amdgpu_param_buf_per_se,
1354                                     512 * 1024);
1355         if (r) {
1356                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1357                 goto err;
1358         }
1359
1360 out:
1361         adev->gfx.ngg.init = true;
1362         return 0;
1363 err:
1364         gfx_v9_0_ngg_fini(adev);
1365         return r;
1366 }
1367
1368 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1369 {
1370         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1371         int r;
1372         u32 data;
1373         u32 size;
1374         u32 base;
1375
1376         if (!amdgpu_ngg)
1377                 return 0;
1378
1379         /* Program buffer size */
1380         data = 0;
1381         size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
1382         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1383
1384         size = adev->gfx.ngg.buf[NGG_POS].size / 256;
1385         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1386
1387         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1388
1389         data = 0;
1390         size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
1391         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1392
1393         size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
1394         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1395
1396         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1397
1398         /* Program buffer base address */
1399         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1400         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1401         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1402
1403         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1404         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1405         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1406
1407         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1408         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1409         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1410
1411         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1412         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1413         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1414
1415         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1416         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1417         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1418
1419         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1420         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1421         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1422
1423         /* Clear GDS reserved memory */
1424         r = amdgpu_ring_alloc(ring, 17);
1425         if (r) {
1426                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1427                           ring->idx, r);
1428                 return r;
1429         }
1430
1431         gfx_v9_0_write_data_to_reg(ring, 0, false,
1432                                    amdgpu_gds_reg_offset[0].mem_size,
1433                                    (adev->gds.mem.total_size +
1434                                     adev->gfx.ngg.gds_reserve_size) >>
1435                                    AMDGPU_GDS_SHIFT);
1436
1437         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1438         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1439                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1440         amdgpu_ring_write(ring, 0);
1441         amdgpu_ring_write(ring, 0);
1442         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1443         amdgpu_ring_write(ring, 0);
1444         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1445
1446
1447         gfx_v9_0_write_data_to_reg(ring, 0, false,
1448                                    amdgpu_gds_reg_offset[0].mem_size, 0);
1449
1450         amdgpu_ring_commit(ring);
1451
1452         return 0;
1453 }
1454
1455 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1456                                       int mec, int pipe, int queue)
1457 {
1458         int r;
1459         unsigned irq_type;
1460         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1461
1462         ring = &adev->gfx.compute_ring[ring_id];
1463
1464         /* mec0 is me1 */
1465         ring->me = mec + 1;
1466         ring->pipe = pipe;
1467         ring->queue = queue;
1468
1469         ring->ring_obj = NULL;
1470         ring->use_doorbell = true;
1471         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1472         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1473                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1474         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1475
1476         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1477                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1478                 + ring->pipe;
1479
1480         /* type-2 packets are deprecated on MEC, use type-3 instead */
1481         r = amdgpu_ring_init(adev, ring, 1024,
1482                              &adev->gfx.eop_irq, irq_type);
1483         if (r)
1484                 return r;
1485
1486
1487         return 0;
1488 }
1489
1490 static int gfx_v9_0_sw_init(void *handle)
1491 {
1492         int i, j, k, r, ring_id;
1493         struct amdgpu_ring *ring;
1494         struct amdgpu_kiq *kiq;
1495         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1496
1497         /* KIQ event */
1498         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1499         if (r)
1500                 return r;
1501
1502         /* EOP Event */
1503         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1504         if (r)
1505                 return r;
1506
1507         /* Privileged reg */
1508         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1509                               &adev->gfx.priv_reg_irq);
1510         if (r)
1511                 return r;
1512
1513         /* Privileged inst */
1514         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1515                               &adev->gfx.priv_inst_irq);
1516         if (r)
1517                 return r;
1518
1519         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1520
1521         gfx_v9_0_scratch_init(adev);
1522
1523         r = gfx_v9_0_init_microcode(adev);
1524         if (r) {
1525                 DRM_ERROR("Failed to load gfx firmware!\n");
1526                 return r;
1527         }
1528
1529         r = gfx_v9_0_rlc_init(adev);
1530         if (r) {
1531                 DRM_ERROR("Failed to init rlc BOs!\n");
1532                 return r;
1533         }
1534
1535         r = gfx_v9_0_mec_init(adev);
1536         if (r) {
1537                 DRM_ERROR("Failed to init MEC BOs!\n");
1538                 return r;
1539         }
1540
1541         /* set up the gfx ring */
1542         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1543                 ring = &adev->gfx.gfx_ring[i];
1544                 ring->ring_obj = NULL;
1545                 sprintf(ring->name, "gfx");
1546                 ring->use_doorbell = true;
1547                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1548                 r = amdgpu_ring_init(adev, ring, 1024,
1549                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1550                 if (r)
1551                         return r;
1552         }
1553
1554         /* set up the compute queues - allocate horizontally across pipes */
1555         ring_id = 0;
1556         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1557                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1558                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1559                                 if (!amdgpu_is_mec_queue_enabled(adev, i, k, j))
1560                                         continue;
1561
1562                                 r = gfx_v9_0_compute_ring_init(adev,
1563                                                                ring_id,
1564                                                                i, k, j);
1565                                 if (r)
1566                                         return r;
1567
1568                                 ring_id++;
1569                         }
1570                 }
1571         }
1572
1573         r = gfx_v9_0_kiq_init(adev);
1574         if (r) {
1575                 DRM_ERROR("Failed to init KIQ BOs!\n");
1576                 return r;
1577         }
1578
1579         kiq = &adev->gfx.kiq;
1580         r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1581         if (r)
1582                 return r;
1583
1584         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1585         r = gfx_v9_0_compute_mqd_sw_init(adev);
1586         if (r)
1587                 return r;
1588
1589         /* reserve GDS, GWS and OA resource for gfx */
1590         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1591                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1592                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1593         if (r)
1594                 return r;
1595
1596         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1597                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1598                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1599         if (r)
1600                 return r;
1601
1602         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1603                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1604                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1605         if (r)
1606                 return r;
1607
1608         adev->gfx.ce_ram_size = 0x8000;
1609
1610         gfx_v9_0_gpu_early_init(adev);
1611
1612         r = gfx_v9_0_ngg_init(adev);
1613         if (r)
1614                 return r;
1615
1616         return 0;
1617 }
1618
1619
1620 static int gfx_v9_0_sw_fini(void *handle)
1621 {
1622         int i;
1623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1624
1625         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1626         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1627         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1628
1629         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1630                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1631         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1632                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1633
1634         gfx_v9_0_compute_mqd_sw_fini(adev);
1635         gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1636         gfx_v9_0_kiq_fini(adev);
1637
1638         gfx_v9_0_mec_fini(adev);
1639         gfx_v9_0_ngg_fini(adev);
1640
1641         return 0;
1642 }
1643
1644
1645 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1646 {
1647         /* TODO */
1648 }
1649
1650 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1651 {
1652         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1653
1654         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1655                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1656                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1657         } else if (se_num == 0xffffffff) {
1658                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1659                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1660         } else if (sh_num == 0xffffffff) {
1661                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1662                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1663         } else {
1664                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1665                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1666         }
1667         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1668 }
1669
1670 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1671 {
1672         u32 data, mask;
1673
1674         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1675         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1676
1677         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1678         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1679
1680         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1681                                          adev->gfx.config.max_sh_per_se);
1682
1683         return (~data) & mask;
1684 }
1685
1686 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1687 {
1688         int i, j;
1689         u32 data;
1690         u32 active_rbs = 0;
1691         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1692                                         adev->gfx.config.max_sh_per_se;
1693
1694         mutex_lock(&adev->grbm_idx_mutex);
1695         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1696                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1697                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1698                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1699                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1700                                                rb_bitmap_width_per_sh);
1701                 }
1702         }
1703         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1704         mutex_unlock(&adev->grbm_idx_mutex);
1705
1706         adev->gfx.config.backend_enable_mask = active_rbs;
1707         adev->gfx.config.num_rbs = hweight32(active_rbs);
1708 }
1709
1710 #define DEFAULT_SH_MEM_BASES    (0x6000)
1711 #define FIRST_COMPUTE_VMID      (8)
1712 #define LAST_COMPUTE_VMID       (16)
1713 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1714 {
1715         int i;
1716         uint32_t sh_mem_config;
1717         uint32_t sh_mem_bases;
1718
1719         /*
1720          * Configure apertures:
1721          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1722          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1723          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1724          */
1725         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1726
1727         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1728                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1729                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1730
1731         mutex_lock(&adev->srbm_mutex);
1732         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1733                 soc15_grbm_select(adev, 0, 0, 0, i);
1734                 /* CP and shaders */
1735                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1736                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1737         }
1738         soc15_grbm_select(adev, 0, 0, 0, 0);
1739         mutex_unlock(&adev->srbm_mutex);
1740 }
1741
1742 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1743 {
1744         u32 tmp;
1745         int i;
1746
1747         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1748
1749         gfx_v9_0_tiling_mode_table_init(adev);
1750
1751         gfx_v9_0_setup_rb(adev);
1752         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1753
1754         /* XXX SH_MEM regs */
1755         /* where to put LDS, scratch, GPUVM in FSA64 space */
1756         mutex_lock(&adev->srbm_mutex);
1757         for (i = 0; i < 16; i++) {
1758                 soc15_grbm_select(adev, 0, 0, 0, i);
1759                 /* CP and shaders */
1760                 tmp = 0;
1761                 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1762                                     SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1763                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1764                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1765         }
1766         soc15_grbm_select(adev, 0, 0, 0, 0);
1767
1768         mutex_unlock(&adev->srbm_mutex);
1769
1770         gfx_v9_0_init_compute_vmid(adev);
1771
1772         mutex_lock(&adev->grbm_idx_mutex);
1773         /*
1774          * making sure that the following register writes will be broadcasted
1775          * to all the shaders
1776          */
1777         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1778
1779         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1780                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1781                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1782                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1783                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1784                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1785                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1786                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1787                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1788         mutex_unlock(&adev->grbm_idx_mutex);
1789
1790 }
1791
1792 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1793 {
1794         u32 i, j, k;
1795         u32 mask;
1796
1797         mutex_lock(&adev->grbm_idx_mutex);
1798         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1799                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1800                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1801                         for (k = 0; k < adev->usec_timeout; k++) {
1802                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1803                                         break;
1804                                 udelay(1);
1805                         }
1806                 }
1807         }
1808         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1809         mutex_unlock(&adev->grbm_idx_mutex);
1810
1811         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1812                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1813                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1814                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1815         for (k = 0; k < adev->usec_timeout; k++) {
1816                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1817                         break;
1818                 udelay(1);
1819         }
1820 }
1821
1822 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1823                                                bool enable)
1824 {
1825         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1826
1827         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1828         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1829         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1830         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1831
1832         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1833 }
1834
1835 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1836 {
1837         /* csib */
1838         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1839                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1840         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1841                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1842         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1843                         adev->gfx.rlc.clear_state_size);
1844 }
1845
1846 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1847                                 int indirect_offset,
1848                                 int list_size,
1849                                 int *unique_indirect_regs,
1850                                 int *unique_indirect_reg_count,
1851                                 int max_indirect_reg_count,
1852                                 int *indirect_start_offsets,
1853                                 int *indirect_start_offsets_count,
1854                                 int max_indirect_start_offsets_count)
1855 {
1856         int idx;
1857         bool new_entry = true;
1858
1859         for (; indirect_offset < list_size; indirect_offset++) {
1860
1861                 if (new_entry) {
1862                         new_entry = false;
1863                         indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1864                         *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1865                         BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1866                 }
1867
1868                 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1869                         new_entry = true;
1870                         continue;
1871                 }
1872
1873                 indirect_offset += 2;
1874
1875                 /* look for the matching indice */
1876                 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1877                         if (unique_indirect_regs[idx] ==
1878                                 register_list_format[indirect_offset])
1879                                 break;
1880                 }
1881
1882                 if (idx >= *unique_indirect_reg_count) {
1883                         unique_indirect_regs[*unique_indirect_reg_count] =
1884                                 register_list_format[indirect_offset];
1885                         idx = *unique_indirect_reg_count;
1886                         *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1887                         BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1888                 }
1889
1890                 register_list_format[indirect_offset] = idx;
1891         }
1892 }
1893
1894 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1895 {
1896         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1897         int unique_indirect_reg_count = 0;
1898
1899         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1900         int indirect_start_offsets_count = 0;
1901
1902         int list_size = 0;
1903         int i = 0;
1904         u32 tmp = 0;
1905
1906         u32 *register_list_format =
1907                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1908         if (!register_list_format)
1909                 return -ENOMEM;
1910         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1911                 adev->gfx.rlc.reg_list_format_size_bytes);
1912
1913         /* setup unique_indirect_regs array and indirect_start_offsets array */
1914         gfx_v9_0_parse_ind_reg_list(register_list_format,
1915                                 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1916                                 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1917                                 unique_indirect_regs,
1918                                 &unique_indirect_reg_count,
1919                                 sizeof(unique_indirect_regs)/sizeof(int),
1920                                 indirect_start_offsets,
1921                                 &indirect_start_offsets_count,
1922                                 sizeof(indirect_start_offsets)/sizeof(int));
1923
1924         /* enable auto inc in case it is disabled */
1925         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1926         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1927         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1928
1929         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1930         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1931                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1932         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1933                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1934                         adev->gfx.rlc.register_restore[i]);
1935
1936         /* load direct register */
1937         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1938         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1939                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1940                         adev->gfx.rlc.register_restore[i]);
1941
1942         /* load indirect register */
1943         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1944                 adev->gfx.rlc.reg_list_format_start);
1945         for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1946                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1947                         register_list_format[i]);
1948
1949         /* set save/restore list size */
1950         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1951         list_size = list_size >> 1;
1952         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1953                 adev->gfx.rlc.reg_restore_list_size);
1954         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1955
1956         /* write the starting offsets to RLC scratch ram */
1957         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1958                 adev->gfx.rlc.starting_offsets_start);
1959         for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1960                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1961                         indirect_start_offsets[i]);
1962
1963         /* load unique indirect regs*/
1964         for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1965                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1966                         unique_indirect_regs[i] & 0x3FFFF);
1967                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1968                         unique_indirect_regs[i] >> 20);
1969         }
1970
1971         kfree(register_list_format);
1972         return 0;
1973 }
1974
1975 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1976 {
1977         u32 tmp = 0;
1978
1979         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1980         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1981         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1982 }
1983
1984 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1985                                              bool enable)
1986 {
1987         uint32_t data = 0;
1988         uint32_t default_data = 0;
1989
1990         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1991         if (enable == true) {
1992                 /* enable GFXIP control over CGPG */
1993                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1994                 if(default_data != data)
1995                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1996
1997                 /* update status */
1998                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1999                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2000                 if(default_data != data)
2001                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2002         } else {
2003                 /* restore GFXIP control over GCPG */
2004                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2005                 if(default_data != data)
2006                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2007         }
2008 }
2009
2010 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2011 {
2012         uint32_t data = 0;
2013
2014         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2015                               AMD_PG_SUPPORT_GFX_SMG |
2016                               AMD_PG_SUPPORT_GFX_DMG)) {
2017                 /* init IDLE_POLL_COUNT = 60 */
2018                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2019                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2020                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2021                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2022
2023                 /* init RLC PG Delay */
2024                 data = 0;
2025                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2026                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2027                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2028                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2029                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2030
2031                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2032                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2033                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2034                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2035
2036                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2037                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2038                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2039                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2040
2041                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2042                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2043
2044                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2045                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2046                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2047
2048                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2049         }
2050 }
2051
2052 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2053                                                 bool enable)
2054 {
2055         uint32_t data = 0;
2056         uint32_t default_data = 0;
2057
2058         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2059
2060         if (enable == true) {
2061                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
2062                 if (default_data != data)
2063                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2064         } else {
2065                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
2066                 if(default_data != data)
2067                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2068         }
2069 }
2070
2071 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2072                                                 bool enable)
2073 {
2074         uint32_t data = 0;
2075         uint32_t default_data = 0;
2076
2077         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2078
2079         if (enable == true) {
2080                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
2081                 if(default_data != data)
2082                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2083         } else {
2084                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
2085                 if(default_data != data)
2086                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2087         }
2088 }
2089
2090 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2091                                         bool enable)
2092 {
2093         uint32_t data = 0;
2094         uint32_t default_data = 0;
2095
2096         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2097
2098         if (enable == true) {
2099                 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
2100                 if(default_data != data)
2101                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2102         } else {
2103                 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
2104                 if(default_data != data)
2105                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2106         }
2107 }
2108
2109 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2110                                                 bool enable)
2111 {
2112         uint32_t data, default_data;
2113
2114         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2115         if (enable == true)
2116                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2117         else
2118                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2119         if(default_data != data)
2120                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2121 }
2122
2123 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2124                                                 bool enable)
2125 {
2126         uint32_t data, default_data;
2127
2128         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2129         if (enable == true)
2130                 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2131         else
2132                 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2133         if(default_data != data)
2134                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2135
2136         if (!enable)
2137                 /* read any GFX register to wake up GFX */
2138                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2139 }
2140
2141 void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2142                                                 bool enable)
2143 {
2144         uint32_t data, default_data;
2145
2146         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2147         if (enable == true)
2148                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2149         else
2150                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2151         if(default_data != data)
2152                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2153 }
2154
2155 void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2156                                                 bool enable)
2157 {
2158         uint32_t data, default_data;
2159
2160         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2161         if (enable == true)
2162                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2163         else
2164                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2165         if(default_data != data)
2166                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2167 }
2168
2169 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2170 {
2171         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2172                               AMD_PG_SUPPORT_GFX_SMG |
2173                               AMD_PG_SUPPORT_GFX_DMG |
2174                               AMD_PG_SUPPORT_CP |
2175                               AMD_PG_SUPPORT_GDS |
2176                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2177                 gfx_v9_0_init_csb(adev);
2178                 gfx_v9_0_init_rlc_save_restore_list(adev);
2179                 gfx_v9_0_enable_save_restore_machine(adev);
2180
2181                 if (adev->asic_type == CHIP_RAVEN) {
2182                         WREG32(mmRLC_JUMP_TABLE_RESTORE,
2183                                 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2184                         gfx_v9_0_init_gfx_power_gating(adev);
2185
2186                         if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2187                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2188                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2189                         } else {
2190                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2191                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2192                         }
2193
2194                         if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2195                                 gfx_v9_0_enable_cp_power_gating(adev, true);
2196                         else
2197                                 gfx_v9_0_enable_cp_power_gating(adev, false);
2198                 }
2199         }
2200 }
2201
2202 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2203 {
2204         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2205
2206         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2207         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
2208
2209         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2210
2211         gfx_v9_0_wait_for_rlc_serdes(adev);
2212 }
2213
2214 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2215 {
2216         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2217         udelay(50);
2218         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2219         udelay(50);
2220 }
2221
2222 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2223 {
2224 #ifdef AMDGPU_RLC_DEBUG_RETRY
2225         u32 rlc_ucode_ver;
2226 #endif
2227
2228         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2229
2230         /* carrizo do enable cp interrupt after cp inited */
2231         if (!(adev->flags & AMD_IS_APU))
2232                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2233
2234         udelay(50);
2235
2236 #ifdef AMDGPU_RLC_DEBUG_RETRY
2237         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2238         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2239         if(rlc_ucode_ver == 0x108) {
2240                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2241                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2242                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2243                  * default is 0x9C4 to create a 100us interval */
2244                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2245                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2246                  * to disable the page fault retry interrupts, default is
2247                  * 0x100 (256) */
2248                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2249         }
2250 #endif
2251 }
2252
2253 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2254 {
2255         const struct rlc_firmware_header_v2_0 *hdr;
2256         const __le32 *fw_data;
2257         unsigned i, fw_size;
2258
2259         if (!adev->gfx.rlc_fw)
2260                 return -EINVAL;
2261
2262         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2263         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2264
2265         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2266                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2267         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2268
2269         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2270                         RLCG_UCODE_LOADING_START_ADDRESS);
2271         for (i = 0; i < fw_size; i++)
2272                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2273         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2274
2275         return 0;
2276 }
2277
2278 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2279 {
2280         int r;
2281
2282         if (amdgpu_sriov_vf(adev))
2283                 return 0;
2284
2285         gfx_v9_0_rlc_stop(adev);
2286
2287         /* disable CG */
2288         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2289
2290         /* disable PG */
2291         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2292
2293         gfx_v9_0_rlc_reset(adev);
2294
2295         gfx_v9_0_init_pg(adev);
2296
2297         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2298                 /* legacy rlc firmware loading */
2299                 r = gfx_v9_0_rlc_load_microcode(adev);
2300                 if (r)
2301                         return r;
2302         }
2303
2304         if (adev->asic_type == CHIP_RAVEN) {
2305                 if (amdgpu_lbpw != 0)
2306                         gfx_v9_0_enable_lbpw(adev, true);
2307                 else
2308                         gfx_v9_0_enable_lbpw(adev, false);
2309         }
2310
2311         gfx_v9_0_rlc_start(adev);
2312
2313         return 0;
2314 }
2315
2316 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2317 {
2318         int i;
2319         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2320
2321         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2322         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2323         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2324         if (!enable) {
2325                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2326                         adev->gfx.gfx_ring[i].ready = false;
2327         }
2328         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2329         udelay(50);
2330 }
2331
2332 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2333 {
2334         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2335         const struct gfx_firmware_header_v1_0 *ce_hdr;
2336         const struct gfx_firmware_header_v1_0 *me_hdr;
2337         const __le32 *fw_data;
2338         unsigned i, fw_size;
2339
2340         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2341                 return -EINVAL;
2342
2343         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2344                 adev->gfx.pfp_fw->data;
2345         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2346                 adev->gfx.ce_fw->data;
2347         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2348                 adev->gfx.me_fw->data;
2349
2350         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2351         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2352         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2353
2354         gfx_v9_0_cp_gfx_enable(adev, false);
2355
2356         /* PFP */
2357         fw_data = (const __le32 *)
2358                 (adev->gfx.pfp_fw->data +
2359                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2360         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2361         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2362         for (i = 0; i < fw_size; i++)
2363                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2364         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2365
2366         /* CE */
2367         fw_data = (const __le32 *)
2368                 (adev->gfx.ce_fw->data +
2369                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2370         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2371         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2372         for (i = 0; i < fw_size; i++)
2373                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2374         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2375
2376         /* ME */
2377         fw_data = (const __le32 *)
2378                 (adev->gfx.me_fw->data +
2379                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2380         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2381         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2382         for (i = 0; i < fw_size; i++)
2383                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2384         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2385
2386         return 0;
2387 }
2388
2389 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2390 {
2391         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2392         const struct cs_section_def *sect = NULL;
2393         const struct cs_extent_def *ext = NULL;
2394         int r, i;
2395
2396         /* init the CP */
2397         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2398         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2399
2400         gfx_v9_0_cp_gfx_enable(adev, true);
2401
2402         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2403         if (r) {
2404                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2405                 return r;
2406         }
2407
2408         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2409         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2410
2411         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2412         amdgpu_ring_write(ring, 0x80000000);
2413         amdgpu_ring_write(ring, 0x80000000);
2414
2415         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2416                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2417                         if (sect->id == SECT_CONTEXT) {
2418                                 amdgpu_ring_write(ring,
2419                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2420                                                ext->reg_count));
2421                                 amdgpu_ring_write(ring,
2422                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2423                                 for (i = 0; i < ext->reg_count; i++)
2424                                         amdgpu_ring_write(ring, ext->extent[i]);
2425                         }
2426                 }
2427         }
2428
2429         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2430         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2431
2432         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2433         amdgpu_ring_write(ring, 0);
2434
2435         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2436         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2437         amdgpu_ring_write(ring, 0x8000);
2438         amdgpu_ring_write(ring, 0x8000);
2439
2440         amdgpu_ring_commit(ring);
2441
2442         return 0;
2443 }
2444
2445 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2446 {
2447         struct amdgpu_ring *ring;
2448         u32 tmp;
2449         u32 rb_bufsz;
2450         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2451
2452         /* Set the write pointer delay */
2453         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2454
2455         /* set the RB to use vmid 0 */
2456         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2457
2458         /* Set ring buffer size */
2459         ring = &adev->gfx.gfx_ring[0];
2460         rb_bufsz = order_base_2(ring->ring_size / 8);
2461         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2462         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2463 #ifdef __BIG_ENDIAN
2464         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2465 #endif
2466         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2467
2468         /* Initialize the ring buffer's write pointers */
2469         ring->wptr = 0;
2470         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2471         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2472
2473         /* set the wb address wether it's enabled or not */
2474         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2475         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2476         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2477
2478         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2479         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2480         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2481
2482         mdelay(1);
2483         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2484
2485         rb_addr = ring->gpu_addr >> 8;
2486         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2487         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2488
2489         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2490         if (ring->use_doorbell) {
2491                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2492                                     DOORBELL_OFFSET, ring->doorbell_index);
2493                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2494                                     DOORBELL_EN, 1);
2495         } else {
2496                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2497         }
2498         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2499
2500         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2501                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2502         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2503
2504         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2505                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2506
2507
2508         /* start the ring */
2509         gfx_v9_0_cp_gfx_start(adev);
2510         ring->ready = true;
2511
2512         return 0;
2513 }
2514
2515 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2516 {
2517         int i;
2518
2519         if (enable) {
2520                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2521         } else {
2522                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2523                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2524                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2525                         adev->gfx.compute_ring[i].ready = false;
2526                 adev->gfx.kiq.ring.ready = false;
2527         }
2528         udelay(50);
2529 }
2530
2531 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2532 {
2533         const struct gfx_firmware_header_v1_0 *mec_hdr;
2534         const __le32 *fw_data;
2535         unsigned i;
2536         u32 tmp;
2537
2538         if (!adev->gfx.mec_fw)
2539                 return -EINVAL;
2540
2541         gfx_v9_0_cp_compute_enable(adev, false);
2542
2543         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2544         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2545
2546         fw_data = (const __le32 *)
2547                 (adev->gfx.mec_fw->data +
2548                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2549         tmp = 0;
2550         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2551         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2552         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2553
2554         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2555                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2556         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2557                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2558
2559         /* MEC1 */
2560         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2561                          mec_hdr->jt_offset);
2562         for (i = 0; i < mec_hdr->jt_size; i++)
2563                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2564                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2565
2566         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2567                         adev->gfx.mec_fw_version);
2568         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2569
2570         return 0;
2571 }
2572
2573 /* KIQ functions */
2574 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2575 {
2576         uint32_t tmp;
2577         struct amdgpu_device *adev = ring->adev;
2578
2579         /* tell RLC which is KIQ queue */
2580         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2581         tmp &= 0xffffff00;
2582         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2583         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2584         tmp |= 0x80;
2585         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2586 }
2587
2588 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2589 {
2590         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2591         uint32_t scratch, tmp = 0;
2592         uint64_t queue_mask = 0;
2593         int r, i;
2594
2595         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2596                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2597                         continue;
2598
2599                 /* This situation may be hit in the future if a new HW
2600                  * generation exposes more than 64 queues. If so, the
2601                  * definition of queue_mask needs updating */
2602                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
2603                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2604                         break;
2605                 }
2606
2607                 queue_mask |= (1ull << i);
2608         }
2609
2610         r = amdgpu_gfx_scratch_get(adev, &scratch);
2611         if (r) {
2612                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2613                 return r;
2614         }
2615         WREG32(scratch, 0xCAFEDEAD);
2616
2617         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2618         if (r) {
2619                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2620                 amdgpu_gfx_scratch_free(adev, scratch);
2621                 return r;
2622         }
2623
2624         /* set resources */
2625         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2626         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2627                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2628         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2629         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2630         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2631         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2632         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2633         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2634         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2635                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2636                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2637                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2638
2639                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2640                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2641                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2642                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2643                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2644                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2645                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2646                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2647                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2648                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2649                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2650                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2651                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2652                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2653                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2654                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2655                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2656         }
2657         /* write to scratch for completion */
2658         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2659         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2660         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2661         amdgpu_ring_commit(kiq_ring);
2662
2663         for (i = 0; i < adev->usec_timeout; i++) {
2664                 tmp = RREG32(scratch);
2665                 if (tmp == 0xDEADBEEF)
2666                         break;
2667                 DRM_UDELAY(1);
2668         }
2669         if (i >= adev->usec_timeout) {
2670                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2671                           scratch, tmp);
2672                 r = -EINVAL;
2673         }
2674         amdgpu_gfx_scratch_free(adev, scratch);
2675
2676         return r;
2677 }
2678
2679 static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
2680 {
2681         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2682         uint32_t scratch, tmp = 0;
2683         int r, i;
2684
2685         r = amdgpu_gfx_scratch_get(adev, &scratch);
2686         if (r) {
2687                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2688                 return r;
2689         }
2690         WREG32(scratch, 0xCAFEDEAD);
2691
2692         r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
2693         if (r) {
2694                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2695                 amdgpu_gfx_scratch_free(adev, scratch);
2696                 return r;
2697         }
2698         /* unmap queues */
2699         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2700         amdgpu_ring_write(kiq_ring,
2701                           PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
2702                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
2703         amdgpu_ring_write(kiq_ring, 0);
2704         amdgpu_ring_write(kiq_ring, 0);
2705         amdgpu_ring_write(kiq_ring, 0);
2706         amdgpu_ring_write(kiq_ring, 0);
2707         /* write to scratch for completion */
2708         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2709         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2710         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2711         amdgpu_ring_commit(kiq_ring);
2712
2713         for (i = 0; i < adev->usec_timeout; i++) {
2714                 tmp = RREG32(scratch);
2715                 if (tmp == 0xDEADBEEF)
2716                         break;
2717                 DRM_UDELAY(1);
2718         }
2719         if (i >= adev->usec_timeout) {
2720                 DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
2721                           scratch, tmp);
2722                 r = -EINVAL;
2723         }
2724         amdgpu_gfx_scratch_free(adev, scratch);
2725
2726         return r;
2727 }
2728
2729 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2730 {
2731         struct amdgpu_device *adev = ring->adev;
2732         struct v9_mqd *mqd = ring->mqd_ptr;
2733         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2734         uint32_t tmp;
2735
2736         mqd->header = 0xC0310800;
2737         mqd->compute_pipelinestat_enable = 0x00000001;
2738         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2739         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2740         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2741         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2742         mqd->compute_misc_reserved = 0x00000003;
2743
2744         eop_base_addr = ring->eop_gpu_addr >> 8;
2745         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2746         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2747
2748         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2749         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2750         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2751                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2752
2753         mqd->cp_hqd_eop_control = tmp;
2754
2755         /* enable doorbell? */
2756         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2757
2758         if (ring->use_doorbell) {
2759                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2760                                     DOORBELL_OFFSET, ring->doorbell_index);
2761                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2762                                     DOORBELL_EN, 1);
2763                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2764                                     DOORBELL_SOURCE, 0);
2765                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2766                                     DOORBELL_HIT, 0);
2767         }
2768         else
2769                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2770                                          DOORBELL_EN, 0);
2771
2772         mqd->cp_hqd_pq_doorbell_control = tmp;
2773
2774         /* disable the queue if it's active */
2775         ring->wptr = 0;
2776         mqd->cp_hqd_dequeue_request = 0;
2777         mqd->cp_hqd_pq_rptr = 0;
2778         mqd->cp_hqd_pq_wptr_lo = 0;
2779         mqd->cp_hqd_pq_wptr_hi = 0;
2780
2781         /* set the pointer to the MQD */
2782         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2783         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2784
2785         /* set MQD vmid to 0 */
2786         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2787         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2788         mqd->cp_mqd_control = tmp;
2789
2790         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2791         hqd_gpu_addr = ring->gpu_addr >> 8;
2792         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2793         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2794
2795         /* set up the HQD, this is similar to CP_RB0_CNTL */
2796         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2797         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2798                             (order_base_2(ring->ring_size / 4) - 1));
2799         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2800                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2801 #ifdef __BIG_ENDIAN
2802         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2803 #endif
2804         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2805         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2806         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2807         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2808         mqd->cp_hqd_pq_control = tmp;
2809
2810         /* set the wb address whether it's enabled or not */
2811         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2812         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2813         mqd->cp_hqd_pq_rptr_report_addr_hi =
2814                 upper_32_bits(wb_gpu_addr) & 0xffff;
2815
2816         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2817         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2818         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2819         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2820
2821         tmp = 0;
2822         /* enable the doorbell if requested */
2823         if (ring->use_doorbell) {
2824                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2825                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2826                                 DOORBELL_OFFSET, ring->doorbell_index);
2827
2828                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2829                                          DOORBELL_EN, 1);
2830                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2831                                          DOORBELL_SOURCE, 0);
2832                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2833                                          DOORBELL_HIT, 0);
2834         }
2835
2836         mqd->cp_hqd_pq_doorbell_control = tmp;
2837
2838         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2839         ring->wptr = 0;
2840         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2841
2842         /* set the vmid for the queue */
2843         mqd->cp_hqd_vmid = 0;
2844
2845         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2846         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2847         mqd->cp_hqd_persistent_state = tmp;
2848
2849         /* set MIN_IB_AVAIL_SIZE */
2850         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2851         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2852         mqd->cp_hqd_ib_control = tmp;
2853
2854         /* activate the queue */
2855         mqd->cp_hqd_active = 1;
2856
2857         return 0;
2858 }
2859
2860 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2861 {
2862         struct amdgpu_device *adev = ring->adev;
2863         struct v9_mqd *mqd = ring->mqd_ptr;
2864         int j;
2865
2866         /* disable wptr polling */
2867         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2868
2869         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2870                mqd->cp_hqd_eop_base_addr_lo);
2871         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2872                mqd->cp_hqd_eop_base_addr_hi);
2873
2874         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2875         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2876                mqd->cp_hqd_eop_control);
2877
2878         /* enable doorbell? */
2879         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2880                mqd->cp_hqd_pq_doorbell_control);
2881
2882         /* disable the queue if it's active */
2883         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2884                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2885                 for (j = 0; j < adev->usec_timeout; j++) {
2886                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2887                                 break;
2888                         udelay(1);
2889                 }
2890                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2891                        mqd->cp_hqd_dequeue_request);
2892                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2893                        mqd->cp_hqd_pq_rptr);
2894                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2895                        mqd->cp_hqd_pq_wptr_lo);
2896                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2897                        mqd->cp_hqd_pq_wptr_hi);
2898         }
2899
2900         /* set the pointer to the MQD */
2901         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2902                mqd->cp_mqd_base_addr_lo);
2903         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2904                mqd->cp_mqd_base_addr_hi);
2905
2906         /* set MQD vmid to 0 */
2907         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2908                mqd->cp_mqd_control);
2909
2910         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2911         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2912                mqd->cp_hqd_pq_base_lo);
2913         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2914                mqd->cp_hqd_pq_base_hi);
2915
2916         /* set up the HQD, this is similar to CP_RB0_CNTL */
2917         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2918                mqd->cp_hqd_pq_control);
2919
2920         /* set the wb address whether it's enabled or not */
2921         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2922                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2923         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2924                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2925
2926         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2927         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2928                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2929         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2930                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2931
2932         /* enable the doorbell if requested */
2933         if (ring->use_doorbell) {
2934                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2935                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2936                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2937                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2938         }
2939
2940         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2941                mqd->cp_hqd_pq_doorbell_control);
2942
2943         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2944         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2945                mqd->cp_hqd_pq_wptr_lo);
2946         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2947                mqd->cp_hqd_pq_wptr_hi);
2948
2949         /* set the vmid for the queue */
2950         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2951
2952         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2953                mqd->cp_hqd_persistent_state);
2954
2955         /* activate the queue */
2956         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2957                mqd->cp_hqd_active);
2958
2959         if (ring->use_doorbell)
2960                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2961
2962         return 0;
2963 }
2964
2965 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2966 {
2967         struct amdgpu_device *adev = ring->adev;
2968         struct v9_mqd *mqd = ring->mqd_ptr;
2969         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2970
2971         gfx_v9_0_kiq_setting(ring);
2972
2973         if (adev->gfx.in_reset) { /* for GPU_RESET case */
2974                 /* reset MQD to a clean status */
2975                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2976                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2977
2978                 /* reset ring buffer */
2979                 ring->wptr = 0;
2980                 amdgpu_ring_clear_ring(ring);
2981
2982                 mutex_lock(&adev->srbm_mutex);
2983                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2984                 gfx_v9_0_kiq_init_register(ring);
2985                 soc15_grbm_select(adev, 0, 0, 0, 0);
2986                 mutex_unlock(&adev->srbm_mutex);
2987         } else {
2988                 memset((void *)mqd, 0, sizeof(*mqd));
2989                 mutex_lock(&adev->srbm_mutex);
2990                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2991                 gfx_v9_0_mqd_init(ring);
2992                 gfx_v9_0_kiq_init_register(ring);
2993                 soc15_grbm_select(adev, 0, 0, 0, 0);
2994                 mutex_unlock(&adev->srbm_mutex);
2995
2996                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2997                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3004 {
3005         struct amdgpu_device *adev = ring->adev;
3006         struct v9_mqd *mqd = ring->mqd_ptr;
3007         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3008
3009         if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
3010                 memset((void *)mqd, 0, sizeof(*mqd));
3011                 mutex_lock(&adev->srbm_mutex);
3012                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3013                 gfx_v9_0_mqd_init(ring);
3014                 soc15_grbm_select(adev, 0, 0, 0, 0);
3015                 mutex_unlock(&adev->srbm_mutex);
3016
3017                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3018                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3019         } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
3020                 /* reset MQD to a clean status */
3021                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3022                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3023
3024                 /* reset ring buffer */
3025                 ring->wptr = 0;
3026                 amdgpu_ring_clear_ring(ring);
3027         } else {
3028                 amdgpu_ring_clear_ring(ring);
3029         }
3030
3031         return 0;
3032 }
3033
3034 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3035 {
3036         struct amdgpu_ring *ring = NULL;
3037         int r = 0, i;
3038
3039         gfx_v9_0_cp_compute_enable(adev, true);
3040
3041         ring = &adev->gfx.kiq.ring;
3042
3043         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3044         if (unlikely(r != 0))
3045                 goto done;
3046
3047         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3048         if (!r) {
3049                 r = gfx_v9_0_kiq_init_queue(ring);
3050                 amdgpu_bo_kunmap(ring->mqd_obj);
3051                 ring->mqd_ptr = NULL;
3052         }
3053         amdgpu_bo_unreserve(ring->mqd_obj);
3054         if (r)
3055                 goto done;
3056
3057         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3058                 ring = &adev->gfx.compute_ring[i];
3059
3060                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3061                 if (unlikely(r != 0))
3062                         goto done;
3063                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3064                 if (!r) {
3065                         r = gfx_v9_0_kcq_init_queue(ring);
3066                         amdgpu_bo_kunmap(ring->mqd_obj);
3067                         ring->mqd_ptr = NULL;
3068                 }
3069                 amdgpu_bo_unreserve(ring->mqd_obj);
3070                 if (r)
3071                         goto done;
3072         }
3073
3074         r = gfx_v9_0_kiq_kcq_enable(adev);
3075 done:
3076         return r;
3077 }
3078
3079 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3080 {
3081         int r, i;
3082         struct amdgpu_ring *ring;
3083
3084         if (!(adev->flags & AMD_IS_APU))
3085                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3086
3087         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3088                 /* legacy firmware loading */
3089                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3090                 if (r)
3091                         return r;
3092
3093                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3094                 if (r)
3095                         return r;
3096         }
3097
3098         r = gfx_v9_0_cp_gfx_resume(adev);
3099         if (r)
3100                 return r;
3101
3102         r = gfx_v9_0_kiq_resume(adev);
3103         if (r)
3104                 return r;
3105
3106         ring = &adev->gfx.gfx_ring[0];
3107         r = amdgpu_ring_test_ring(ring);
3108         if (r) {
3109                 ring->ready = false;
3110                 return r;
3111         }
3112
3113         ring = &adev->gfx.kiq.ring;
3114         ring->ready = true;
3115         r = amdgpu_ring_test_ring(ring);
3116         if (r)
3117                 ring->ready = false;
3118
3119         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3120                 ring = &adev->gfx.compute_ring[i];
3121
3122                 ring->ready = true;
3123                 r = amdgpu_ring_test_ring(ring);
3124                 if (r)
3125                         ring->ready = false;
3126         }
3127
3128         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3129
3130         return 0;
3131 }
3132
3133 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3134 {
3135         gfx_v9_0_cp_gfx_enable(adev, enable);
3136         gfx_v9_0_cp_compute_enable(adev, enable);
3137 }
3138
3139 static int gfx_v9_0_hw_init(void *handle)
3140 {
3141         int r;
3142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3143
3144         gfx_v9_0_init_golden_registers(adev);
3145
3146         gfx_v9_0_gpu_init(adev);
3147
3148         r = gfx_v9_0_rlc_resume(adev);
3149         if (r)
3150                 return r;
3151
3152         r = gfx_v9_0_cp_resume(adev);
3153         if (r)
3154                 return r;
3155
3156         r = gfx_v9_0_ngg_en(adev);
3157         if (r)
3158                 return r;
3159
3160         return r;
3161 }
3162
3163 static int gfx_v9_0_hw_fini(void *handle)
3164 {
3165         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3166
3167         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3168         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3169         if (amdgpu_sriov_vf(adev)) {
3170                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3171                 return 0;
3172         }
3173         gfx_v9_0_kiq_kcq_disable(adev);
3174         gfx_v9_0_cp_enable(adev, false);
3175         gfx_v9_0_rlc_stop(adev);
3176
3177         return 0;
3178 }
3179
3180 static int gfx_v9_0_suspend(void *handle)
3181 {
3182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3183
3184         adev->gfx.in_suspend = true;
3185         return gfx_v9_0_hw_fini(adev);
3186 }
3187
3188 static int gfx_v9_0_resume(void *handle)
3189 {
3190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3191         int r;
3192
3193         r = gfx_v9_0_hw_init(adev);
3194         adev->gfx.in_suspend = false;
3195         return r;
3196 }
3197
3198 static bool gfx_v9_0_is_idle(void *handle)
3199 {
3200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3201
3202         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3203                                 GRBM_STATUS, GUI_ACTIVE))
3204                 return false;
3205         else
3206                 return true;
3207 }
3208
3209 static int gfx_v9_0_wait_for_idle(void *handle)
3210 {
3211         unsigned i;
3212         u32 tmp;
3213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3214
3215         for (i = 0; i < adev->usec_timeout; i++) {
3216                 /* read MC_STATUS */
3217                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3218                         GRBM_STATUS__GUI_ACTIVE_MASK;
3219
3220                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3221                         return 0;
3222                 udelay(1);
3223         }
3224         return -ETIMEDOUT;
3225 }
3226
3227 static int gfx_v9_0_soft_reset(void *handle)
3228 {
3229         u32 grbm_soft_reset = 0;
3230         u32 tmp;
3231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3232
3233         /* GRBM_STATUS */
3234         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3235         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3236                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3237                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3238                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3239                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3240                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3241                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3242                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3243                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3244                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3245         }
3246
3247         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3248                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3249                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3250         }
3251
3252         /* GRBM_STATUS2 */
3253         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3254         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3255                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3256                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3257
3258
3259         if (grbm_soft_reset) {
3260                 /* stop the rlc */
3261                 gfx_v9_0_rlc_stop(adev);
3262
3263                 /* Disable GFX parsing/prefetching */
3264                 gfx_v9_0_cp_gfx_enable(adev, false);
3265
3266                 /* Disable MEC parsing/prefetching */
3267                 gfx_v9_0_cp_compute_enable(adev, false);
3268
3269                 if (grbm_soft_reset) {
3270                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3271                         tmp |= grbm_soft_reset;
3272                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3273                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3274                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3275
3276                         udelay(50);
3277
3278                         tmp &= ~grbm_soft_reset;
3279                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3280                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3281                 }
3282
3283                 /* Wait a little for things to settle down */
3284                 udelay(50);
3285         }
3286         return 0;
3287 }
3288
3289 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3290 {
3291         uint64_t clock;
3292
3293         mutex_lock(&adev->gfx.gpu_clock_mutex);
3294         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3295         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3296                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3297         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3298         return clock;
3299 }
3300
3301 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3302                                           uint32_t vmid,
3303                                           uint32_t gds_base, uint32_t gds_size,
3304                                           uint32_t gws_base, uint32_t gws_size,
3305                                           uint32_t oa_base, uint32_t oa_size)
3306 {
3307         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3308         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3309
3310         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3311         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3312
3313         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3314         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3315
3316         /* GDS Base */
3317         gfx_v9_0_write_data_to_reg(ring, 0, false,
3318                                    amdgpu_gds_reg_offset[vmid].mem_base,
3319                                    gds_base);
3320
3321         /* GDS Size */
3322         gfx_v9_0_write_data_to_reg(ring, 0, false,
3323                                    amdgpu_gds_reg_offset[vmid].mem_size,
3324                                    gds_size);
3325
3326         /* GWS */
3327         gfx_v9_0_write_data_to_reg(ring, 0, false,
3328                                    amdgpu_gds_reg_offset[vmid].gws,
3329                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3330
3331         /* OA */
3332         gfx_v9_0_write_data_to_reg(ring, 0, false,
3333                                    amdgpu_gds_reg_offset[vmid].oa,
3334                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3335 }
3336
3337 static int gfx_v9_0_early_init(void *handle)
3338 {
3339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3340
3341         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3342         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3343         gfx_v9_0_set_ring_funcs(adev);
3344         gfx_v9_0_set_irq_funcs(adev);
3345         gfx_v9_0_set_gds_init(adev);
3346         gfx_v9_0_set_rlc_funcs(adev);
3347
3348         return 0;
3349 }
3350
3351 static int gfx_v9_0_late_init(void *handle)
3352 {
3353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3354         int r;
3355
3356         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3357         if (r)
3358                 return r;
3359
3360         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3361         if (r)
3362                 return r;
3363
3364         return 0;
3365 }
3366
3367 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3368 {
3369         uint32_t rlc_setting, data;
3370         unsigned i;
3371
3372         if (adev->gfx.rlc.in_safe_mode)
3373                 return;
3374
3375         /* if RLC is not enabled, do nothing */
3376         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3377         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3378                 return;
3379
3380         if (adev->cg_flags &
3381             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3382              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3383                 data = RLC_SAFE_MODE__CMD_MASK;
3384                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3385                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3386
3387                 /* wait for RLC_SAFE_MODE */
3388                 for (i = 0; i < adev->usec_timeout; i++) {
3389                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3390                                 break;
3391                         udelay(1);
3392                 }
3393                 adev->gfx.rlc.in_safe_mode = true;
3394         }
3395 }
3396
3397 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3398 {
3399         uint32_t rlc_setting, data;
3400
3401         if (!adev->gfx.rlc.in_safe_mode)
3402                 return;
3403
3404         /* if RLC is not enabled, do nothing */
3405         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3406         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3407                 return;
3408
3409         if (adev->cg_flags &
3410             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3411                 /*
3412                  * Try to exit safe mode only if it is already in safe
3413                  * mode.
3414                  */
3415                 data = RLC_SAFE_MODE__CMD_MASK;
3416                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3417                 adev->gfx.rlc.in_safe_mode = false;
3418         }
3419 }
3420
3421 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3422                                                 bool enable)
3423 {
3424         /* TODO: double check if we need to perform under safe mdoe */
3425         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3426
3427         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3428                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3429                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3430                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3431         } else {
3432                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3433                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3434         }
3435
3436         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3437 }
3438
3439 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3440                                                 bool enable)
3441 {
3442         /* TODO: double check if we need to perform under safe mode */
3443         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3444
3445         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3446                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3447         else
3448                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3449
3450         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3451                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3452         else
3453                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3454
3455         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3456 }
3457
3458 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3459                                                       bool enable)
3460 {
3461         uint32_t data, def;
3462
3463         /* It is disabled by HW by default */
3464         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3465                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3466                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3467                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3468                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3469                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3470                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3471
3472                 /* only for Vega10 & Raven1 */
3473                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3474
3475                 if (def != data)
3476                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3477
3478                 /* MGLS is a global flag to control all MGLS in GFX */
3479                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3480                         /* 2 - RLC memory Light sleep */
3481                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3482                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3483                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3484                                 if (def != data)
3485                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3486                         }
3487                         /* 3 - CP memory Light sleep */
3488                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3489                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3490                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3491                                 if (def != data)
3492                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3493                         }
3494                 }
3495         } else {
3496                 /* 1 - MGCG_OVERRIDE */
3497                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3498                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3499                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3500                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3501                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3502                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3503                 if (def != data)
3504                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3505
3506                 /* 2 - disable MGLS in RLC */
3507                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3508                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3509                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3510                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3511                 }
3512
3513                 /* 3 - disable MGLS in CP */
3514                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3515                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3516                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3517                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3518                 }
3519         }
3520 }
3521
3522 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3523                                            bool enable)
3524 {
3525         uint32_t data, def;
3526
3527         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3528
3529         /* Enable 3D CGCG/CGLS */
3530         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3531                 /* write cmd to clear cgcg/cgls ov */
3532                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3533                 /* unset CGCG override */
3534                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3535                 /* update CGCG and CGLS override bits */
3536                 if (def != data)
3537                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3538                 /* enable 3Dcgcg FSM(0x0020003f) */
3539                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3540                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3541                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3542                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3543                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3544                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3545                 if (def != data)
3546                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3547
3548                 /* set IDLE_POLL_COUNT(0x00900100) */
3549                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3550                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3551                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3552                 if (def != data)
3553                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3554         } else {
3555                 /* Disable CGCG/CGLS */
3556                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3557                 /* disable cgcg, cgls should be disabled */
3558                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3559                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3560                 /* disable cgcg and cgls in FSM */
3561                 if (def != data)
3562                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3563         }
3564
3565         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3566 }
3567
3568 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3569                                                       bool enable)
3570 {
3571         uint32_t def, data;
3572
3573         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3574
3575         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3576                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3577                 /* unset CGCG override */
3578                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3579                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3580                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3581                 else
3582                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3583                 /* update CGCG and CGLS override bits */
3584                 if (def != data)
3585                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3586
3587                 /* enable cgcg FSM(0x0020003F) */
3588                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3589                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3590                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3591                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3592                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3593                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3594                 if (def != data)
3595                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3596
3597                 /* set IDLE_POLL_COUNT(0x00900100) */
3598                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3599                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3600                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3601                 if (def != data)
3602                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3603         } else {
3604                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3605                 /* reset CGCG/CGLS bits */
3606                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3607                 /* disable cgcg and cgls in FSM */
3608                 if (def != data)
3609                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3610         }
3611
3612         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3613 }
3614
3615 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3616                                             bool enable)
3617 {
3618         if (enable) {
3619                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3620                  * ===  MGCG + MGLS ===
3621                  */
3622                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3623                 /* ===  CGCG /CGLS for GFX 3D Only === */
3624                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3625                 /* ===  CGCG + CGLS === */
3626                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3627         } else {
3628                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3629                  * ===  CGCG + CGLS ===
3630                  */
3631                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3632                 /* ===  CGCG /CGLS for GFX 3D Only === */
3633                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3634                 /* ===  MGCG + MGLS === */
3635                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3636         }
3637         return 0;
3638 }
3639
3640 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3641         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3642         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3643 };
3644
3645 static int gfx_v9_0_set_powergating_state(void *handle,
3646                                           enum amd_powergating_state state)
3647 {
3648         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3649         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3650
3651         switch (adev->asic_type) {
3652         case CHIP_RAVEN:
3653                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3654                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3655                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3656                 } else {
3657                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3658                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3659                 }
3660
3661                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3662                         gfx_v9_0_enable_cp_power_gating(adev, true);
3663                 else
3664                         gfx_v9_0_enable_cp_power_gating(adev, false);
3665
3666                 /* update gfx cgpg state */
3667                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3668
3669                 /* update mgcg state */
3670                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3671                 break;
3672         default:
3673                 break;
3674         }
3675
3676         return 0;
3677 }
3678
3679 static int gfx_v9_0_set_clockgating_state(void *handle,
3680                                           enum amd_clockgating_state state)
3681 {
3682         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3683
3684         if (amdgpu_sriov_vf(adev))
3685                 return 0;
3686
3687         switch (adev->asic_type) {
3688         case CHIP_VEGA10:
3689         case CHIP_RAVEN:
3690                 gfx_v9_0_update_gfx_clock_gating(adev,
3691                                                  state == AMD_CG_STATE_GATE ? true : false);
3692                 break;
3693         default:
3694                 break;
3695         }
3696         return 0;
3697 }
3698
3699 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3700 {
3701         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3702         int data;
3703
3704         if (amdgpu_sriov_vf(adev))
3705                 *flags = 0;
3706
3707         /* AMD_CG_SUPPORT_GFX_MGCG */
3708         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3709         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3710                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3711
3712         /* AMD_CG_SUPPORT_GFX_CGCG */
3713         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3714         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3715                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3716
3717         /* AMD_CG_SUPPORT_GFX_CGLS */
3718         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3719                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3720
3721         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3722         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3723         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3724                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3725
3726         /* AMD_CG_SUPPORT_GFX_CP_LS */
3727         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3728         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3729                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3730
3731         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3732         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3733         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3734                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3735
3736         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3737         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3738                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3739 }
3740
3741 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3742 {
3743         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3744 }
3745
3746 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3747 {
3748         struct amdgpu_device *adev = ring->adev;
3749         u64 wptr;
3750
3751         /* XXX check if swapping is necessary on BE */
3752         if (ring->use_doorbell) {
3753                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3754         } else {
3755                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3756                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3757         }
3758
3759         return wptr;
3760 }
3761
3762 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3763 {
3764         struct amdgpu_device *adev = ring->adev;
3765
3766         if (ring->use_doorbell) {
3767                 /* XXX check if swapping is necessary on BE */
3768                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3769                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3770         } else {
3771                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3772                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3773         }
3774 }
3775
3776 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3777 {
3778         u32 ref_and_mask, reg_mem_engine;
3779         struct nbio_hdp_flush_reg *nbio_hf_reg;
3780
3781         if (ring->adev->asic_type == CHIP_VEGA10)
3782                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3783
3784         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3785                 switch (ring->me) {
3786                 case 1:
3787                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3788                         break;
3789                 case 2:
3790                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3791                         break;
3792                 default:
3793                         return;
3794                 }
3795                 reg_mem_engine = 0;
3796         } else {
3797                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3798                 reg_mem_engine = 1; /* pfp */
3799         }
3800
3801         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3802                               nbio_hf_reg->hdp_flush_req_offset,
3803                               nbio_hf_reg->hdp_flush_done_offset,
3804                               ref_and_mask, ref_and_mask, 0x20);
3805 }
3806
3807 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3808 {
3809         gfx_v9_0_write_data_to_reg(ring, 0, true,
3810                                    SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3811 }
3812
3813 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3814                                       struct amdgpu_ib *ib,
3815                                       unsigned vm_id, bool ctx_switch)
3816 {
3817         u32 header, control = 0;
3818
3819         if (ib->flags & AMDGPU_IB_FLAG_CE)
3820                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3821         else
3822                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3823
3824         control |= ib->length_dw | (vm_id << 24);
3825
3826         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3827                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3828
3829                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3830                         gfx_v9_0_ring_emit_de_meta(ring);
3831         }
3832
3833         amdgpu_ring_write(ring, header);
3834 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3835         amdgpu_ring_write(ring,
3836 #ifdef __BIG_ENDIAN
3837                 (2 << 0) |
3838 #endif
3839                 lower_32_bits(ib->gpu_addr));
3840         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3841         amdgpu_ring_write(ring, control);
3842 }
3843
3844 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3845                                           struct amdgpu_ib *ib,
3846                                           unsigned vm_id, bool ctx_switch)
3847 {
3848         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3849
3850         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3851         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3852         amdgpu_ring_write(ring,
3853 #ifdef __BIG_ENDIAN
3854                                 (2 << 0) |
3855 #endif
3856                                 lower_32_bits(ib->gpu_addr));
3857         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3858         amdgpu_ring_write(ring, control);
3859 }
3860
3861 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3862                                      u64 seq, unsigned flags)
3863 {
3864         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3865         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3866
3867         /* RELEASE_MEM - flush caches, send int */
3868         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3869         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3870                                  EOP_TC_ACTION_EN |
3871                                  EOP_TC_WB_ACTION_EN |
3872                                  EOP_TC_MD_ACTION_EN |
3873                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3874                                  EVENT_INDEX(5)));
3875         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3876
3877         /*
3878          * the address should be Qword aligned if 64bit write, Dword
3879          * aligned if only send 32bit data low (discard data high)
3880          */
3881         if (write64bit)
3882                 BUG_ON(addr & 0x7);
3883         else
3884                 BUG_ON(addr & 0x3);
3885         amdgpu_ring_write(ring, lower_32_bits(addr));
3886         amdgpu_ring_write(ring, upper_32_bits(addr));
3887         amdgpu_ring_write(ring, lower_32_bits(seq));
3888         amdgpu_ring_write(ring, upper_32_bits(seq));
3889         amdgpu_ring_write(ring, 0);
3890 }
3891
3892 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3893 {
3894         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3895         uint32_t seq = ring->fence_drv.sync_seq;
3896         uint64_t addr = ring->fence_drv.gpu_addr;
3897
3898         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3899                               lower_32_bits(addr), upper_32_bits(addr),
3900                               seq, 0xffffffff, 4);
3901 }
3902
3903 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3904                                         unsigned vm_id, uint64_t pd_addr)
3905 {
3906         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
3907         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3908         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
3909         unsigned eng = ring->vm_inv_eng;
3910
3911         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3912         pd_addr |= AMDGPU_PTE_VALID;
3913
3914         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3915                                    hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3916                                    lower_32_bits(pd_addr));
3917
3918         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3919                                    hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3920                                    upper_32_bits(pd_addr));
3921
3922         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3923                                    hub->vm_inv_eng0_req + eng, req);
3924
3925         /* wait for the invalidate to complete */
3926         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3927                               eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
3928
3929         /* compute doesn't have PFP */
3930         if (usepfp) {
3931                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3932                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3933                 amdgpu_ring_write(ring, 0x0);
3934         }
3935 }
3936
3937 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3938 {
3939         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3940 }
3941
3942 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3943 {
3944         u64 wptr;
3945
3946         /* XXX check if swapping is necessary on BE */
3947         if (ring->use_doorbell)
3948                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3949         else
3950                 BUG();
3951         return wptr;
3952 }
3953
3954 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3955 {
3956         struct amdgpu_device *adev = ring->adev;
3957
3958         /* XXX check if swapping is necessary on BE */
3959         if (ring->use_doorbell) {
3960                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3961                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3962         } else{
3963                 BUG(); /* only DOORBELL method supported on gfx9 now */
3964         }
3965 }
3966
3967 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3968                                          u64 seq, unsigned int flags)
3969 {
3970         /* we only allocate 32bit for each seq wb address */
3971         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3972
3973         /* write fence seq to the "addr" */
3974         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3975         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3976                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3977         amdgpu_ring_write(ring, lower_32_bits(addr));
3978         amdgpu_ring_write(ring, upper_32_bits(addr));
3979         amdgpu_ring_write(ring, lower_32_bits(seq));
3980
3981         if (flags & AMDGPU_FENCE_FLAG_INT) {
3982                 /* set register to trigger INT */
3983                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3984                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3985                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3986                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3987                 amdgpu_ring_write(ring, 0);
3988                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3989         }
3990 }
3991
3992 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3993 {
3994         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3995         amdgpu_ring_write(ring, 0);
3996 }
3997
3998 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3999 {
4000         static struct v9_ce_ib_state ce_payload = {0};
4001         uint64_t csa_addr;
4002         int cnt;
4003
4004         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4005         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
4006
4007         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4008         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4009                                  WRITE_DATA_DST_SEL(8) |
4010                                  WR_CONFIRM) |
4011                                  WRITE_DATA_CACHE_POLICY(0));
4012         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4013         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4014         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4015 }
4016
4017 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4018 {
4019         static struct v9_de_ib_state de_payload = {0};
4020         uint64_t csa_addr, gds_addr;
4021         int cnt;
4022
4023         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
4024         gds_addr = csa_addr + 4096;
4025         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4026         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4027
4028         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4029         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4030         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4031                                  WRITE_DATA_DST_SEL(8) |
4032                                  WR_CONFIRM) |
4033                                  WRITE_DATA_CACHE_POLICY(0));
4034         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4035         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4036         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4037 }
4038
4039 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4040 {
4041         uint32_t dw2 = 0;
4042
4043         if (amdgpu_sriov_vf(ring->adev))
4044                 gfx_v9_0_ring_emit_ce_meta(ring);
4045
4046         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4047         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4048                 /* set load_global_config & load_global_uconfig */
4049                 dw2 |= 0x8001;
4050                 /* set load_cs_sh_regs */
4051                 dw2 |= 0x01000000;
4052                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4053                 dw2 |= 0x10002;
4054
4055                 /* set load_ce_ram if preamble presented */
4056                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4057                         dw2 |= 0x10000000;
4058         } else {
4059                 /* still load_ce_ram if this is the first time preamble presented
4060                  * although there is no context switch happens.
4061                  */
4062                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4063                         dw2 |= 0x10000000;
4064         }
4065
4066         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4067         amdgpu_ring_write(ring, dw2);
4068         amdgpu_ring_write(ring, 0);
4069 }
4070
4071 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4072 {
4073         unsigned ret;
4074         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4075         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4076         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4077         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4078         ret = ring->wptr & ring->buf_mask;
4079         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4080         return ret;
4081 }
4082
4083 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4084 {
4085         unsigned cur;
4086         BUG_ON(offset > ring->buf_mask);
4087         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4088
4089         cur = (ring->wptr & ring->buf_mask) - 1;
4090         if (likely(cur > offset))
4091                 ring->ring[offset] = cur - offset;
4092         else
4093                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4094 }
4095
4096 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4097 {
4098         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4099         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4100 }
4101
4102 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4103 {
4104         struct amdgpu_device *adev = ring->adev;
4105
4106         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4107         amdgpu_ring_write(ring, 0 |     /* src: register*/
4108                                 (5 << 8) |      /* dst: memory */
4109                                 (1 << 20));     /* write confirm */
4110         amdgpu_ring_write(ring, reg);
4111         amdgpu_ring_write(ring, 0);
4112         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4113                                 adev->virt.reg_val_offs * 4));
4114         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4115                                 adev->virt.reg_val_offs * 4));
4116 }
4117
4118 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4119                                   uint32_t val)
4120 {
4121         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4122         amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
4123         amdgpu_ring_write(ring, reg);
4124         amdgpu_ring_write(ring, 0);
4125         amdgpu_ring_write(ring, val);
4126 }
4127
4128 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4129                                                  enum amdgpu_interrupt_state state)
4130 {
4131         switch (state) {
4132         case AMDGPU_IRQ_STATE_DISABLE:
4133         case AMDGPU_IRQ_STATE_ENABLE:
4134                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4135                                TIME_STAMP_INT_ENABLE,
4136                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4137                 break;
4138         default:
4139                 break;
4140         }
4141 }
4142
4143 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4144                                                      int me, int pipe,
4145                                                      enum amdgpu_interrupt_state state)
4146 {
4147         /* Me 0 is reserved for graphics */
4148         if (me < 1 || me > adev->gfx.mec.num_mec) {
4149                 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
4150                 return;
4151         }
4152
4153         if (pipe >= adev->gfx.mec.num_pipe_per_mec) {
4154                 DRM_ERROR("Ignoring request to enable interrupts for invalid "
4155                                 "me:%d pipe:%d\n", pipe, me);
4156                 return;
4157         }
4158
4159         mutex_lock(&adev->srbm_mutex);
4160         soc15_grbm_select(adev, me, pipe, 0, 0);
4161
4162         WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
4163                         state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
4164
4165         soc15_grbm_select(adev, 0, 0, 0, 0);
4166         mutex_unlock(&adev->srbm_mutex);
4167 }
4168
4169 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4170                                              struct amdgpu_irq_src *source,
4171                                              unsigned type,
4172                                              enum amdgpu_interrupt_state state)
4173 {
4174         switch (state) {
4175         case AMDGPU_IRQ_STATE_DISABLE:
4176         case AMDGPU_IRQ_STATE_ENABLE:
4177                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4178                                PRIV_REG_INT_ENABLE,
4179                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4180                 break;
4181         default:
4182                 break;
4183         }
4184
4185         return 0;
4186 }
4187
4188 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4189                                               struct amdgpu_irq_src *source,
4190                                               unsigned type,
4191                                               enum amdgpu_interrupt_state state)
4192 {
4193         switch (state) {
4194         case AMDGPU_IRQ_STATE_DISABLE:
4195         case AMDGPU_IRQ_STATE_ENABLE:
4196                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4197                                PRIV_INSTR_INT_ENABLE,
4198                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4199         default:
4200                 break;
4201         }
4202
4203         return 0;
4204 }
4205
4206 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4207                                             struct amdgpu_irq_src *src,
4208                                             unsigned type,
4209                                             enum amdgpu_interrupt_state state)
4210 {
4211         switch (type) {
4212         case AMDGPU_CP_IRQ_GFX_EOP:
4213                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4214                 break;
4215         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4216                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4217                 break;
4218         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4219                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4220                 break;
4221         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4222                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4223                 break;
4224         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4225                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4226                 break;
4227         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4228                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4229                 break;
4230         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4231                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4232                 break;
4233         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4234                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4235                 break;
4236         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4237                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4238                 break;
4239         default:
4240                 break;
4241         }
4242         return 0;
4243 }
4244
4245 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4246                             struct amdgpu_irq_src *source,
4247                             struct amdgpu_iv_entry *entry)
4248 {
4249         int i;
4250         u8 me_id, pipe_id, queue_id;
4251         struct amdgpu_ring *ring;
4252
4253         DRM_DEBUG("IH: CP EOP\n");
4254         me_id = (entry->ring_id & 0x0c) >> 2;
4255         pipe_id = (entry->ring_id & 0x03) >> 0;
4256         queue_id = (entry->ring_id & 0x70) >> 4;
4257
4258         switch (me_id) {
4259         case 0:
4260                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4261                 break;
4262         case 1:
4263         case 2:
4264                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4265                         ring = &adev->gfx.compute_ring[i];
4266                         /* Per-queue interrupt is supported for MEC starting from VI.
4267                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4268                           */
4269                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4270                                 amdgpu_fence_process(ring);
4271                 }
4272                 break;
4273         }
4274         return 0;
4275 }
4276
4277 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4278                                  struct amdgpu_irq_src *source,
4279                                  struct amdgpu_iv_entry *entry)
4280 {
4281         DRM_ERROR("Illegal register access in command stream\n");
4282         schedule_work(&adev->reset_work);
4283         return 0;
4284 }
4285
4286 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4287                                   struct amdgpu_irq_src *source,
4288                                   struct amdgpu_iv_entry *entry)
4289 {
4290         DRM_ERROR("Illegal instruction in command stream\n");
4291         schedule_work(&adev->reset_work);
4292         return 0;
4293 }
4294
4295 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4296                                             struct amdgpu_irq_src *src,
4297                                             unsigned int type,
4298                                             enum amdgpu_interrupt_state state)
4299 {
4300         uint32_t tmp, target;
4301         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4302
4303         if (ring->me == 1)
4304                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4305         else
4306                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4307         target += ring->pipe;
4308
4309         switch (type) {
4310         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4311                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4312                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4313                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4314                                                  GENERIC2_INT_ENABLE, 0);
4315                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4316
4317                         tmp = RREG32(target);
4318                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4319                                                  GENERIC2_INT_ENABLE, 0);
4320                         WREG32(target, tmp);
4321                 } else {
4322                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4323                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4324                                                  GENERIC2_INT_ENABLE, 1);
4325                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4326
4327                         tmp = RREG32(target);
4328                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4329                                                  GENERIC2_INT_ENABLE, 1);
4330                         WREG32(target, tmp);
4331                 }
4332                 break;
4333         default:
4334                 BUG(); /* kiq only support GENERIC2_INT now */
4335                 break;
4336         }
4337         return 0;
4338 }
4339
4340 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4341                             struct amdgpu_irq_src *source,
4342                             struct amdgpu_iv_entry *entry)
4343 {
4344         u8 me_id, pipe_id, queue_id;
4345         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4346
4347         me_id = (entry->ring_id & 0x0c) >> 2;
4348         pipe_id = (entry->ring_id & 0x03) >> 0;
4349         queue_id = (entry->ring_id & 0x70) >> 4;
4350         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4351                    me_id, pipe_id, queue_id);
4352
4353         amdgpu_fence_process(ring);
4354         return 0;
4355 }
4356
4357 const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4358         .name = "gfx_v9_0",
4359         .early_init = gfx_v9_0_early_init,
4360         .late_init = gfx_v9_0_late_init,
4361         .sw_init = gfx_v9_0_sw_init,
4362         .sw_fini = gfx_v9_0_sw_fini,
4363         .hw_init = gfx_v9_0_hw_init,
4364         .hw_fini = gfx_v9_0_hw_fini,
4365         .suspend = gfx_v9_0_suspend,
4366         .resume = gfx_v9_0_resume,
4367         .is_idle = gfx_v9_0_is_idle,
4368         .wait_for_idle = gfx_v9_0_wait_for_idle,
4369         .soft_reset = gfx_v9_0_soft_reset,
4370         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4371         .set_powergating_state = gfx_v9_0_set_powergating_state,
4372         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4373 };
4374
4375 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4376         .type = AMDGPU_RING_TYPE_GFX,
4377         .align_mask = 0xff,
4378         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4379         .support_64bit_ptrs = true,
4380         .vmhub = AMDGPU_GFXHUB,
4381         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4382         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4383         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4384         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4385                 5 +  /* COND_EXEC */
4386                 7 +  /* PIPELINE_SYNC */
4387                 24 + /* VM_FLUSH */
4388                 8 +  /* FENCE for VM_FLUSH */
4389                 20 + /* GDS switch */
4390                 4 + /* double SWITCH_BUFFER,
4391                        the first COND_EXEC jump to the place just
4392                            prior to this double SWITCH_BUFFER  */
4393                 5 + /* COND_EXEC */
4394                 7 +      /*     HDP_flush */
4395                 4 +      /*     VGT_flush */
4396                 14 + /* CE_META */
4397                 31 + /* DE_META */
4398                 3 + /* CNTX_CTRL */
4399                 5 + /* HDP_INVL */
4400                 8 + 8 + /* FENCE x2 */
4401                 2, /* SWITCH_BUFFER */
4402         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4403         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4404         .emit_fence = gfx_v9_0_ring_emit_fence,
4405         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4406         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4407         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4408         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4409         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4410         .test_ring = gfx_v9_0_ring_test_ring,
4411         .test_ib = gfx_v9_0_ring_test_ib,
4412         .insert_nop = amdgpu_ring_insert_nop,
4413         .pad_ib = amdgpu_ring_generic_pad_ib,
4414         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4415         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4416         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4417         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4418         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4419 };
4420
4421 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4422         .type = AMDGPU_RING_TYPE_COMPUTE,
4423         .align_mask = 0xff,
4424         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4425         .support_64bit_ptrs = true,
4426         .vmhub = AMDGPU_GFXHUB,
4427         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4428         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4429         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4430         .emit_frame_size =
4431                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4432                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4433                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4434                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4435                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4436                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4437         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4438         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4439         .emit_fence = gfx_v9_0_ring_emit_fence,
4440         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4441         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4442         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4443         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4444         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4445         .test_ring = gfx_v9_0_ring_test_ring,
4446         .test_ib = gfx_v9_0_ring_test_ib,
4447         .insert_nop = amdgpu_ring_insert_nop,
4448         .pad_ib = amdgpu_ring_generic_pad_ib,
4449 };
4450
4451 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4452         .type = AMDGPU_RING_TYPE_KIQ,
4453         .align_mask = 0xff,
4454         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4455         .support_64bit_ptrs = true,
4456         .vmhub = AMDGPU_GFXHUB,
4457         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4458         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4459         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4460         .emit_frame_size =
4461                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4462                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4463                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4464                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4465                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4466                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4467         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4468         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4469         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4470         .test_ring = gfx_v9_0_ring_test_ring,
4471         .test_ib = gfx_v9_0_ring_test_ib,
4472         .insert_nop = amdgpu_ring_insert_nop,
4473         .pad_ib = amdgpu_ring_generic_pad_ib,
4474         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4475         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4476 };
4477
4478 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4479 {
4480         int i;
4481
4482         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4483
4484         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4485                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4486
4487         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4488                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4489 }
4490
4491 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4492         .set = gfx_v9_0_kiq_set_interrupt_state,
4493         .process = gfx_v9_0_kiq_irq,
4494 };
4495
4496 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4497         .set = gfx_v9_0_set_eop_interrupt_state,
4498         .process = gfx_v9_0_eop_irq,
4499 };
4500
4501 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4502         .set = gfx_v9_0_set_priv_reg_fault_state,
4503         .process = gfx_v9_0_priv_reg_irq,
4504 };
4505
4506 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4507         .set = gfx_v9_0_set_priv_inst_fault_state,
4508         .process = gfx_v9_0_priv_inst_irq,
4509 };
4510
4511 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4512 {
4513         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4514         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4515
4516         adev->gfx.priv_reg_irq.num_types = 1;
4517         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4518
4519         adev->gfx.priv_inst_irq.num_types = 1;
4520         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4521
4522         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4523         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4524 }
4525
4526 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4527 {
4528         switch (adev->asic_type) {
4529         case CHIP_VEGA10:
4530         case CHIP_RAVEN:
4531                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4532                 break;
4533         default:
4534                 break;
4535         }
4536 }
4537
4538 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4539 {
4540         /* init asci gds info */
4541         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4542         adev->gds.gws.total_size = 64;
4543         adev->gds.oa.total_size = 16;
4544
4545         if (adev->gds.mem.total_size == 64 * 1024) {
4546                 adev->gds.mem.gfx_partition_size = 4096;
4547                 adev->gds.mem.cs_partition_size = 4096;
4548
4549                 adev->gds.gws.gfx_partition_size = 4;
4550                 adev->gds.gws.cs_partition_size = 4;
4551
4552                 adev->gds.oa.gfx_partition_size = 4;
4553                 adev->gds.oa.cs_partition_size = 1;
4554         } else {
4555                 adev->gds.mem.gfx_partition_size = 1024;
4556                 adev->gds.mem.cs_partition_size = 1024;
4557
4558                 adev->gds.gws.gfx_partition_size = 16;
4559                 adev->gds.gws.cs_partition_size = 16;
4560
4561                 adev->gds.oa.gfx_partition_size = 4;
4562                 adev->gds.oa.cs_partition_size = 4;
4563         }
4564 }
4565
4566 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4567 {
4568         u32 data, mask;
4569
4570         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4571         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4572
4573         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4574         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4575
4576         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4577
4578         return (~data) & mask;
4579 }
4580
4581 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4582                                  struct amdgpu_cu_info *cu_info)
4583 {
4584         int i, j, k, counter, active_cu_number = 0;
4585         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4586
4587         if (!adev || !cu_info)
4588                 return -EINVAL;
4589
4590         memset(cu_info, 0, sizeof(*cu_info));
4591
4592         mutex_lock(&adev->grbm_idx_mutex);
4593         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4594                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4595                         mask = 1;
4596                         ao_bitmap = 0;
4597                         counter = 0;
4598                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4599                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4600                         cu_info->bitmap[i][j] = bitmap;
4601
4602                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4603                                 if (bitmap & mask) {
4604                                         if (counter < adev->gfx.config.max_cu_per_sh)
4605                                                 ao_bitmap |= mask;
4606                                         counter ++;
4607                                 }
4608                                 mask <<= 1;
4609                         }
4610                         active_cu_number += counter;
4611                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4612                 }
4613         }
4614         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4615         mutex_unlock(&adev->grbm_idx_mutex);
4616
4617         cu_info->number = active_cu_number;
4618         cu_info->ao_cu_mask = ao_cu_mask;
4619
4620         return 0;
4621 }
4622
4623 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4624 {
4625         .type = AMD_IP_BLOCK_TYPE_GFX,
4626         .major = 9,
4627         .minor = 0,
4628         .rev = 0,
4629         .funcs = &gfx_v9_0_ip_funcs,
4630 };