drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/kthread.h>
  27 #include <linux/pci.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_pm.h"
  33 #include "amdgpu_dm_debugfs.h"
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_rap.h"
  36 #include "amdgpu_securedisplay.h"
  37 #include "amdgpu_fw_attestation.h"
  38 #include "amdgpu_umr.h"
  39
  40 #include "amdgpu_reset.h"
  41 #include "amdgpu_psp_ta.h"
  42
  43 #if defined(CONFIG_DEBUG_FS)
  44
  45 /**
  46  * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
  47  *
  48  * @read: True if reading
  49  * @f: open file handle
  50  * @buf: User buffer to write/read to
  51  * @size: Number of bytes to write/read
  52  * @pos:  Offset to seek to
  53  *
  54  * This debugfs entry has special meaning on the offset being sought.
  55  * Various bits have different meanings:
  56  *
  57  * Bit 62:  Indicates a GRBM bank switch is needed
  58  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  59  *          zero)
  60  * Bits 24..33: The SE or ME selector if needed
  61  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  62  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  63  *
  64  * Bit 23:  Indicates that the PM power gating lock should be held
  65  *          This is necessary to read registers that might be
  66  *          unreliable during a power gating transistion.
  67  *
  68  * The lower bits are the BYTE offset of the register to read.  This
  69  * allows reading multiple registers in a single call and having
  70  * the returned size reflect that.
  71  */
  72 static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
  73                 char __user *buf, size_t size, loff_t *pos)
  74 {
  75         struct amdgpu_device *adev = file_inode(f)->i_private;
  76         ssize_t result = 0;
  77         int r;
  78         bool pm_pg_lock, use_bank, use_ring;
  79         unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
  80
  81         pm_pg_lock = use_bank = use_ring = false;
  82         instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
  83
  84         if (size & 0x3 || *pos & 0x3 ||
  85                         ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
  86                 return -EINVAL;
  87
  88         /* are we reading registers for which a PG lock is necessary? */
  89         pm_pg_lock = (*pos >> 23) & 1;
  90
  91         if (*pos & (1ULL << 62)) {
  92                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
  93                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
  94                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
  95
  96                 if (se_bank == 0x3FF)
  97                         se_bank = 0xFFFFFFFF;
  98                 if (sh_bank == 0x3FF)
  99                         sh_bank = 0xFFFFFFFF;
 100                 if (instance_bank == 0x3FF)
 101                         instance_bank = 0xFFFFFFFF;
 102                 use_bank = true;
 103         } else if (*pos & (1ULL << 61)) {
 104
 105                 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
 106                 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
 107                 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
 108                 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 109
 110                 use_ring = true;
 111         } else {
 112                 use_bank = use_ring = false;
 113         }
 114
 115         *pos &= (1UL << 22) - 1;
 116
 117         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 118         if (r < 0) {
 119                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 120                 return r;
 121         }
 122
 123         r = amdgpu_virt_enable_access_debugfs(adev);
 124         if (r < 0) {
 125                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 126                 return r;
 127         }
 128
 129         if (use_bank) {
 130                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
 131                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
 132                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 133                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 134                         amdgpu_virt_disable_access_debugfs(adev);
 135                         return -EINVAL;
 136                 }
 137                 mutex_lock(&adev->grbm_idx_mutex);
 138                 amdgpu_gfx_select_se_sh(adev, se_bank,
 139                                         sh_bank, instance_bank);
 140         } else if (use_ring) {
 141                 mutex_lock(&adev->srbm_mutex);
 142                 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
 143         }
 144
 145         if (pm_pg_lock)
 146                 mutex_lock(&adev->pm.mutex);
 147
 148         while (size) {
 149                 uint32_t value;
 150
 151                 if (read) {
 152                         value = RREG32(*pos >> 2);
 153                         r = put_user(value, (uint32_t *)buf);
 154                 } else {
 155                         r = get_user(value, (uint32_t *)buf);
 156                         if (!r)
 157                                 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
 158                 }
 159                 if (r) {
 160                         result = r;
 161                         goto end;
 162                 }
 163
 164                 result += 4;
 165                 buf += 4;
 166                 *pos += 4;
 167                 size -= 4;
 168         }
 169
 170 end:
 171         if (use_bank) {
 172                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 173                 mutex_unlock(&adev->grbm_idx_mutex);
 174         } else if (use_ring) {
 175                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 176                 mutex_unlock(&adev->srbm_mutex);
 177         }
 178
 179         if (pm_pg_lock)
 180                 mutex_unlock(&adev->pm.mutex);
 181
 182         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 183         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 184
 185         amdgpu_virt_disable_access_debugfs(adev);
 186         return result;
 187 }
 188
 189 /*
 190  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
 191  */
 192 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 193                                         size_t size, loff_t *pos)
 194 {
 195         return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 196 }
 197
 198 /*
 199  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
 200  */
 201 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 202                                          size_t size, loff_t *pos)
 203 {
 204         return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
 205 }
 206
 207 static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
 208 {
 209         struct amdgpu_debugfs_regs2_data *rd;
 210
 211         rd = kzalloc(sizeof *rd, GFP_KERNEL);
 212         if (!rd)
 213                 return -ENOMEM;
 214         rd->adev = file_inode(file)->i_private;
 215         file->private_data = rd;
 216         mutex_init(&rd->lock);
 217
 218         return 0;
 219 }
 220
 221 static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
 222 {
 223         struct amdgpu_debugfs_regs2_data *rd = file->private_data;
 224         mutex_destroy(&rd->lock);
 225         kfree(file->private_data);
 226         return 0;
 227 }
 228
 229 static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)
 230 {
 231         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 232         struct amdgpu_device *adev = rd->adev;
 233         ssize_t result = 0;
 234         int r;
 235         uint32_t value;
 236
 237         if (size & 0x3 || offset & 0x3)
 238                 return -EINVAL;
 239
 240         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 241         if (r < 0) {
 242                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 243                 return r;
 244         }
 245
 246         r = amdgpu_virt_enable_access_debugfs(adev);
 247         if (r < 0) {
 248                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 249                 return r;
 250         }
 251
 252         mutex_lock(&rd->lock);
 253
 254         if (rd->id.use_grbm) {
 255                 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
 256                     (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
 257                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 258                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 259                         amdgpu_virt_disable_access_debugfs(adev);
 260                         mutex_unlock(&rd->lock);
 261                         return -EINVAL;
 262                 }
 263                 mutex_lock(&adev->grbm_idx_mutex);
 264                 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
 265                                                                 rd->id.grbm.sh,
 266                                                                 rd->id.grbm.instance);
 267         }
 268
 269         if (rd->id.use_srbm) {
 270                 mutex_lock(&adev->srbm_mutex);
 271                 amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,
 272                                                                         rd->id.srbm.queue, rd->id.srbm.vmid);
 273         }
 274
 275         if (rd->id.pg_lock)
 276                 mutex_lock(&adev->pm.mutex);
 277
 278         while (size) {
 279                 if (!write_en) {
 280                         value = RREG32(offset >> 2);
 281                         r = put_user(value, (uint32_t *)buf);
 282                 } else {
 283                         r = get_user(value, (uint32_t *)buf);
 284                         if (!r)
 285                                 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value);
 286                 }
 287                 if (r) {
 288                         result = r;
 289                         goto end;
 290                 }
 291                 offset += 4;
 292                 size -= 4;
 293                 result += 4;
 294                 buf += 4;
 295         }
 296 end:
 297         if (rd->id.use_grbm) {
 298                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 299                 mutex_unlock(&adev->grbm_idx_mutex);
 300         }
 301
 302         if (rd->id.use_srbm) {
 303                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 304                 mutex_unlock(&adev->srbm_mutex);
 305         }
 306
 307         if (rd->id.pg_lock)
 308                 mutex_unlock(&adev->pm.mutex);
 309
 310         mutex_unlock(&rd->lock);
 311
 312         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 313         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 314
 315         amdgpu_virt_disable_access_debugfs(adev);
 316         return result;
 317 }
 318
 319 static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)
 320 {
 321         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 322         int r;
 323
 324         switch (cmd) {
 325         case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
 326                 mutex_lock(&rd->lock);
 327                 r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data, sizeof rd->id);
 328                 mutex_unlock(&rd->lock);
 329                 return r ? -EINVAL : 0;
 330         default:
 331                 return -EINVAL;
 332         }
 333         return 0;
 334 }
 335
 336 static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
 337 {
 338         return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);
 339 }
 340
 341 static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos)
 342 {
 343         return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);
 344 }
 345
 346
 347 /**
 348  * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
 349  *
 350  * @f: open file handle
 351  * @buf: User buffer to store read data in
 352  * @size: Number of bytes to read
 353  * @pos:  Offset to seek to
 354  *
 355  * The lower bits are the BYTE offset of the register to read.  This
 356  * allows reading multiple registers in a single call and having
 357  * the returned size reflect that.
 358  */
 359 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
 360                                         size_t size, loff_t *pos)
 361 {
 362         struct amdgpu_device *adev = file_inode(f)->i_private;
 363         ssize_t result = 0;
 364         int r;
 365
 366         if (size & 0x3 || *pos & 0x3)
 367                 return -EINVAL;
 368
 369         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 370         if (r < 0) {
 371                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 372                 return r;
 373         }
 374
 375         r = amdgpu_virt_enable_access_debugfs(adev);
 376         if (r < 0) {
 377                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 378                 return r;
 379         }
 380
 381         while (size) {
 382                 uint32_t value;
 383
 384                 value = RREG32_PCIE(*pos);
 385                 r = put_user(value, (uint32_t *)buf);
 386                 if (r)
 387                         goto out;
 388
 389                 result += 4;
 390                 buf += 4;
 391                 *pos += 4;
 392                 size -= 4;
 393         }
 394
 395         r = result;
 396 out:
 397         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 398         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 399         amdgpu_virt_disable_access_debugfs(adev);
 400         return r;
 401 }
 402
 403 /**
 404  * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
 405  *
 406  * @f: open file handle
 407  * @buf: User buffer to write data from
 408  * @size: Number of bytes to write
 409  * @pos:  Offset to seek to
 410  *
 411  * The lower bits are the BYTE offset of the register to write.  This
 412  * allows writing multiple registers in a single call and having
 413  * the returned size reflect that.
 414  */
 415 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
 416                                          size_t size, loff_t *pos)
 417 {
 418         struct amdgpu_device *adev = file_inode(f)->i_private;
 419         ssize_t result = 0;
 420         int r;
 421
 422         if (size & 0x3 || *pos & 0x3)
 423                 return -EINVAL;
 424
 425         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 426         if (r < 0) {
 427                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 428                 return r;
 429         }
 430
 431         r = amdgpu_virt_enable_access_debugfs(adev);
 432         if (r < 0) {
 433                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 434                 return r;
 435         }
 436
 437         while (size) {
 438                 uint32_t value;
 439
 440                 r = get_user(value, (uint32_t *)buf);
 441                 if (r)
 442                         goto out;
 443
 444                 WREG32_PCIE(*pos, value);
 445
 446                 result += 4;
 447                 buf += 4;
 448                 *pos += 4;
 449                 size -= 4;
 450         }
 451
 452         r = result;
 453 out:
 454         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 455         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 456         amdgpu_virt_disable_access_debugfs(adev);
 457         return r;
 458 }
 459
 460 /**
 461  * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
 462  *
 463  * @f: open file handle
 464  * @buf: User buffer to store read data in
 465  * @size: Number of bytes to read
 466  * @pos:  Offset to seek to
 467  *
 468  * The lower bits are the BYTE offset of the register to read.  This
 469  * allows reading multiple registers in a single call and having
 470  * the returned size reflect that.
 471  */
 472 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
 473                                         size_t size, loff_t *pos)
 474 {
 475         struct amdgpu_device *adev = file_inode(f)->i_private;
 476         ssize_t result = 0;
 477         int r;
 478
 479         if (size & 0x3 || *pos & 0x3)
 480                 return -EINVAL;
 481
 482         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 483         if (r < 0) {
 484                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 485                 return r;
 486         }
 487
 488         r = amdgpu_virt_enable_access_debugfs(adev);
 489         if (r < 0) {
 490                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 491                 return r;
 492         }
 493
 494         while (size) {
 495                 uint32_t value;
 496
 497                 value = RREG32_DIDT(*pos >> 2);
 498                 r = put_user(value, (uint32_t *)buf);
 499                 if (r)
 500                         goto out;
 501
 502                 result += 4;
 503                 buf += 4;
 504                 *pos += 4;
 505                 size -= 4;
 506         }
 507
 508         r = result;
 509 out:
 510         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 511         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 512         amdgpu_virt_disable_access_debugfs(adev);
 513         return r;
 514 }
 515
 516 /**
 517  * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
 518  *
 519  * @f: open file handle
 520  * @buf: User buffer to write data from
 521  * @size: Number of bytes to write
 522  * @pos:  Offset to seek to
 523  *
 524  * The lower bits are the BYTE offset of the register to write.  This
 525  * allows writing multiple registers in a single call and having
 526  * the returned size reflect that.
 527  */
 528 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
 529                                          size_t size, loff_t *pos)
 530 {
 531         struct amdgpu_device *adev = file_inode(f)->i_private;
 532         ssize_t result = 0;
 533         int r;
 534
 535         if (size & 0x3 || *pos & 0x3)
 536                 return -EINVAL;
 537
 538         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 539         if (r < 0) {
 540                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 541                 return r;
 542         }
 543
 544         r = amdgpu_virt_enable_access_debugfs(adev);
 545         if (r < 0) {
 546                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 547                 return r;
 548         }
 549
 550         while (size) {
 551                 uint32_t value;
 552
 553                 r = get_user(value, (uint32_t *)buf);
 554                 if (r)
 555                         goto out;
 556
 557                 WREG32_DIDT(*pos >> 2, value);
 558
 559                 result += 4;
 560                 buf += 4;
 561                 *pos += 4;
 562                 size -= 4;
 563         }
 564
 565         r = result;
 566 out:
 567         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 568         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 569         amdgpu_virt_disable_access_debugfs(adev);
 570         return r;
 571 }
 572
 573 /**
 574  * amdgpu_debugfs_regs_smc_read - Read from a SMC register
 575  *
 576  * @f: open file handle
 577  * @buf: User buffer to store read data in
 578  * @size: Number of bytes to read
 579  * @pos:  Offset to seek to
 580  *
 581  * The lower bits are the BYTE offset of the register to read.  This
 582  * allows reading multiple registers in a single call and having
 583  * the returned size reflect that.
 584  */
 585 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
 586                                         size_t size, loff_t *pos)
 587 {
 588         struct amdgpu_device *adev = file_inode(f)->i_private;
 589         ssize_t result = 0;
 590         int r;
 591
 592         if (size & 0x3 || *pos & 0x3)
 593                 return -EINVAL;
 594
 595         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 596         if (r < 0) {
 597                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 598                 return r;
 599         }
 600
 601         r = amdgpu_virt_enable_access_debugfs(adev);
 602         if (r < 0) {
 603                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 604                 return r;
 605         }
 606
 607         while (size) {
 608                 uint32_t value;
 609
 610                 value = RREG32_SMC(*pos);
 611                 r = put_user(value, (uint32_t *)buf);
 612                 if (r)
 613                         goto out;
 614
 615                 result += 4;
 616                 buf += 4;
 617                 *pos += 4;
 618                 size -= 4;
 619         }
 620
 621         r = result;
 622 out:
 623         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 624         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 625         amdgpu_virt_disable_access_debugfs(adev);
 626         return r;
 627 }
 628
 629 /**
 630  * amdgpu_debugfs_regs_smc_write - Write to a SMC register
 631  *
 632  * @f: open file handle
 633  * @buf: User buffer to write data from
 634  * @size: Number of bytes to write
 635  * @pos:  Offset to seek to
 636  *
 637  * The lower bits are the BYTE offset of the register to write.  This
 638  * allows writing multiple registers in a single call and having
 639  * the returned size reflect that.
 640  */
 641 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
 642                                          size_t size, loff_t *pos)
 643 {
 644         struct amdgpu_device *adev = file_inode(f)->i_private;
 645         ssize_t result = 0;
 646         int r;
 647
 648         if (size & 0x3 || *pos & 0x3)
 649                 return -EINVAL;
 650
 651         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 652         if (r < 0) {
 653                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 654                 return r;
 655         }
 656
 657         r = amdgpu_virt_enable_access_debugfs(adev);
 658         if (r < 0) {
 659                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 660                 return r;
 661         }
 662
 663         while (size) {
 664                 uint32_t value;
 665
 666                 r = get_user(value, (uint32_t *)buf);
 667                 if (r)
 668                         goto out;
 669
 670                 WREG32_SMC(*pos, value);
 671
 672                 result += 4;
 673                 buf += 4;
 674                 *pos += 4;
 675                 size -= 4;
 676         }
 677
 678         r = result;
 679 out:
 680         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 681         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 682         amdgpu_virt_disable_access_debugfs(adev);
 683         return r;
 684 }
 685
 686 /**
 687  * amdgpu_debugfs_gca_config_read - Read from gfx config data
 688  *
 689  * @f: open file handle
 690  * @buf: User buffer to store read data in
 691  * @size: Number of bytes to read
 692  * @pos:  Offset to seek to
 693  *
 694  * This file is used to access configuration data in a somewhat
 695  * stable fashion.  The format is a series of DWORDs with the first
 696  * indicating which revision it is.  New content is appended to the
 697  * end so that older software can still read the data.
 698  */
 699
 700 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
 701                                         size_t size, loff_t *pos)
 702 {
 703         struct amdgpu_device *adev = file_inode(f)->i_private;
 704         ssize_t result = 0;
 705         int r;
 706         uint32_t *config, no_regs = 0;
 707
 708         if (size & 0x3 || *pos & 0x3)
 709                 return -EINVAL;
 710
 711         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
 712         if (!config)
 713                 return -ENOMEM;
 714
 715         /* version, increment each time something is added */
 716         config[no_regs++] = 5;
 717         config[no_regs++] = adev->gfx.config.max_shader_engines;
 718         config[no_regs++] = adev->gfx.config.max_tile_pipes;
 719         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
 720         config[no_regs++] = adev->gfx.config.max_sh_per_se;
 721         config[no_regs++] = adev->gfx.config.max_backends_per_se;
 722         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
 723         config[no_regs++] = adev->gfx.config.max_gprs;
 724         config[no_regs++] = adev->gfx.config.max_gs_threads;
 725         config[no_regs++] = adev->gfx.config.max_hw_contexts;
 726         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
 727         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
 728         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
 729         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
 730         config[no_regs++] = adev->gfx.config.num_tile_pipes;
 731         config[no_regs++] = adev->gfx.config.backend_enable_mask;
 732         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
 733         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
 734         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
 735         config[no_regs++] = adev->gfx.config.num_gpus;
 736         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
 737         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
 738         config[no_regs++] = adev->gfx.config.gb_addr_config;
 739         config[no_regs++] = adev->gfx.config.num_rbs;
 740
 741         /* rev==1 */
 742         config[no_regs++] = adev->rev_id;
 743         config[no_regs++] = lower_32_bits(adev->pg_flags);
 744         config[no_regs++] = lower_32_bits(adev->cg_flags);
 745
 746         /* rev==2 */
 747         config[no_regs++] = adev->family;
 748         config[no_regs++] = adev->external_rev_id;
 749
 750         /* rev==3 */
 751         config[no_regs++] = adev->pdev->device;
 752         config[no_regs++] = adev->pdev->revision;
 753         config[no_regs++] = adev->pdev->subsystem_device;
 754         config[no_regs++] = adev->pdev->subsystem_vendor;
 755
 756         /* rev==4 APU flag */
 757         config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
 758
 759         /* rev==5 PG/CG flag upper 32bit */
 760         config[no_regs++] = upper_32_bits(adev->pg_flags);
 761         config[no_regs++] = upper_32_bits(adev->cg_flags);
 762
 763         while (size && (*pos < no_regs * 4)) {
 764                 uint32_t value;
 765
 766                 value = config[*pos >> 2];
 767                 r = put_user(value, (uint32_t *)buf);
 768                 if (r) {
 769                         kfree(config);
 770                         return r;
 771                 }
 772
 773                 result += 4;
 774                 buf += 4;
 775                 *pos += 4;
 776                 size -= 4;
 777         }
 778
 779         kfree(config);
 780         return result;
 781 }
 782
 783 /**
 784  * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
 785  *
 786  * @f: open file handle
 787  * @buf: User buffer to store read data in
 788  * @size: Number of bytes to read
 789  * @pos:  Offset to seek to
 790  *
 791  * The offset is treated as the BYTE address of one of the sensors
 792  * enumerated in amd/include/kgd_pp_interface.h under the
 793  * 'amd_pp_sensors' enumeration.  For instance to read the UVD VCLK
 794  * you would use the offset 3 * 4 = 12.
 795  */
 796 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 797                                         size_t size, loff_t *pos)
 798 {
 799         struct amdgpu_device *adev = file_inode(f)->i_private;
 800         int idx, x, outsize, r, valuesize;
 801         uint32_t values[16];
 802
 803         if (size & 3 || *pos & 0x3)
 804                 return -EINVAL;
 805
 806         if (!adev->pm.dpm_enabled)
 807                 return -EINVAL;
 808
 809         /* convert offset to sensor number */
 810         idx = *pos >> 2;
 811
 812         valuesize = sizeof(values);
 813
 814         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 815         if (r < 0) {
 816                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 817                 return r;
 818         }
 819
 820         r = amdgpu_virt_enable_access_debugfs(adev);
 821         if (r < 0) {
 822                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 823                 return r;
 824         }
 825
 826         r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
 827
 828         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 829         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 830
 831         if (r) {
 832                 amdgpu_virt_disable_access_debugfs(adev);
 833                 return r;
 834         }
 835
 836         if (size > valuesize) {
 837                 amdgpu_virt_disable_access_debugfs(adev);
 838                 return -EINVAL;
 839         }
 840
 841         outsize = 0;
 842         x = 0;
 843         if (!r) {
 844                 while (size) {
 845                         r = put_user(values[x++], (int32_t *)buf);
 846                         buf += 4;
 847                         size -= 4;
 848                         outsize += 4;
 849                 }
 850         }
 851
 852         amdgpu_virt_disable_access_debugfs(adev);
 853         return !r ? outsize : r;
 854 }
 855
 856 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
 857  *
 858  * @f: open file handle
 859  * @buf: User buffer to store read data in
 860  * @size: Number of bytes to read
 861  * @pos:  Offset to seek to
 862  *
 863  * The offset being sought changes which wave that the status data
 864  * will be returned for.  The bits are used as follows:
 865  *
 866  * Bits 0..6:   Byte offset into data
 867  * Bits 7..14:  SE selector
 868  * Bits 15..22: SH/SA selector
 869  * Bits 23..30: CU/{WGP+SIMD} selector
 870  * Bits 31..36: WAVE ID selector
 871  * Bits 37..44: SIMD ID selector
 872  *
 873  * The returned data begins with one DWORD of version information
 874  * Followed by WAVE STATUS registers relevant to the GFX IP version
 875  * being used.  See gfx_v8_0_read_wave_data() for an example output.
 876  */
 877 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 878                                         size_t size, loff_t *pos)
 879 {
 880         struct amdgpu_device *adev = f->f_inode->i_private;
 881         int r, x;
 882         ssize_t result = 0;
 883         uint32_t offset, se, sh, cu, wave, simd, data[32];
 884
 885         if (size & 3 || *pos & 3)
 886                 return -EINVAL;
 887
 888         /* decode offset */
 889         offset = (*pos & GENMASK_ULL(6, 0));
 890         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
 891         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
 892         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
 893         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
 894         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
 895
 896         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 897         if (r < 0) {
 898                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 899                 return r;
 900         }
 901
 902         r = amdgpu_virt_enable_access_debugfs(adev);
 903         if (r < 0) {
 904                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 905                 return r;
 906         }
 907
 908         /* switch to the specific se/sh/cu */
 909         mutex_lock(&adev->grbm_idx_mutex);
 910         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 911
 912         x = 0;
 913         if (adev->gfx.funcs->read_wave_data)
 914                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
 915
 916         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 917         mutex_unlock(&adev->grbm_idx_mutex);
 918
 919         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 920         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 921
 922         if (!x) {
 923                 amdgpu_virt_disable_access_debugfs(adev);
 924                 return -EINVAL;
 925         }
 926
 927         while (size && (offset < x * 4)) {
 928                 uint32_t value;
 929
 930                 value = data[offset >> 2];
 931                 r = put_user(value, (uint32_t *)buf);
 932                 if (r) {
 933                         amdgpu_virt_disable_access_debugfs(adev);
 934                         return r;
 935                 }
 936
 937                 result += 4;
 938                 buf += 4;
 939                 offset += 4;
 940                 size -= 4;
 941         }
 942
 943         amdgpu_virt_disable_access_debugfs(adev);
 944         return result;
 945 }
 946
 947 /** amdgpu_debugfs_gpr_read - Read wave gprs
 948  *
 949  * @f: open file handle
 950  * @buf: User buffer to store read data in
 951  * @size: Number of bytes to read
 952  * @pos:  Offset to seek to
 953  *
 954  * The offset being sought changes which wave that the status data
 955  * will be returned for.  The bits are used as follows:
 956  *
 957  * Bits 0..11:  Byte offset into data
 958  * Bits 12..19: SE selector
 959  * Bits 20..27: SH/SA selector
 960  * Bits 28..35: CU/{WGP+SIMD} selector
 961  * Bits 36..43: WAVE ID selector
 962  * Bits 37..44: SIMD ID selector
 963  * Bits 52..59: Thread selector
 964  * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
 965  *
 966  * The return data comes from the SGPR or VGPR register bank for
 967  * the selected operational unit.
 968  */
 969 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
 970                                         size_t size, loff_t *pos)
 971 {
 972         struct amdgpu_device *adev = f->f_inode->i_private;
 973         int r;
 974         ssize_t result = 0;
 975         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 976
 977         if (size > 4096 || size & 3 || *pos & 3)
 978                 return -EINVAL;
 979
 980         /* decode offset */
 981         offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
 982         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 983         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 984         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
 985         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
 986         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
 987         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
 988         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
 989
 990         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
 991         if (!data)
 992                 return -ENOMEM;
 993
 994         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 995         if (r < 0)
 996                 goto err;
 997
 998         r = amdgpu_virt_enable_access_debugfs(adev);
 999         if (r < 0)
1000                 goto err;
1001
1002         /* switch to the specific se/sh/cu */
1003         mutex_lock(&adev->grbm_idx_mutex);
1004         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
1005
1006         if (bank == 0) {
1007                 if (adev->gfx.funcs->read_wave_vgprs)
1008                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
1009         } else {
1010                 if (adev->gfx.funcs->read_wave_sgprs)
1011                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
1012         }
1013
1014         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1015         mutex_unlock(&adev->grbm_idx_mutex);
1016
1017         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1018         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1019
1020         while (size) {
1021                 uint32_t value;
1022
1023                 value = data[result >> 2];
1024                 r = put_user(value, (uint32_t *)buf);
1025                 if (r) {
1026                         amdgpu_virt_disable_access_debugfs(adev);
1027                         goto err;
1028                 }
1029
1030                 result += 4;
1031                 buf += 4;
1032                 size -= 4;
1033         }
1034
1035         kfree(data);
1036         amdgpu_virt_disable_access_debugfs(adev);
1037         return result;
1038
1039 err:
1040         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1041         kfree(data);
1042         return r;
1043 }
1044
1045 /**
1046  * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1047  *
1048  * @f: open file handle
1049  * @buf: User buffer to write data from
1050  * @size: Number of bytes to write
1051  * @pos:  Offset to seek to
1052  *
1053  * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1054  */
1055 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1056                                          size_t size, loff_t *pos)
1057 {
1058         struct amdgpu_device *adev = file_inode(f)->i_private;
1059         ssize_t result = 0;
1060         int r;
1061
1062         if (size & 0x3 || *pos & 0x3)
1063                 return -EINVAL;
1064
1065         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1066         if (r < 0) {
1067                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1068                 return r;
1069         }
1070
1071         while (size) {
1072                 uint32_t value;
1073
1074                 r = get_user(value, (uint32_t *)buf);
1075                 if (r)
1076                         goto out;
1077
1078                 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1079
1080                 result += 4;
1081                 buf += 4;
1082                 *pos += 4;
1083                 size -= 4;
1084         }
1085
1086         r = result;
1087 out:
1088         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1089         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1090
1091         return r;
1092 }
1093
1094
1095 /**
1096  * amdgpu_debugfs_gfxoff_read - read gfxoff status
1097  *
1098  * @f: open file handle
1099  * @buf: User buffer to store read data in
1100  * @size: Number of bytes to read
1101  * @pos:  Offset to seek to
1102  */
1103 static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1104                                          size_t size, loff_t *pos)
1105 {
1106         struct amdgpu_device *adev = file_inode(f)->i_private;
1107         ssize_t result = 0;
1108         int r;
1109
1110         if (size & 0x3 || *pos & 0x3)
1111                 return -EINVAL;
1112
1113         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1114         if (r < 0) {
1115                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1116                 return r;
1117         }
1118
1119         while (size) {
1120                 uint32_t value;
1121
1122                 r = amdgpu_get_gfx_off_status(adev, &value);
1123                 if (r)
1124                         goto out;
1125
1126                 r = put_user(value, (uint32_t *)buf);
1127                 if (r)
1128                         goto out;
1129
1130                 result += 4;
1131                 buf += 4;
1132                 *pos += 4;
1133                 size -= 4;
1134         }
1135
1136         r = result;
1137 out:
1138         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1139         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1140
1141         return r;
1142 }
1143
1144 static const struct file_operations amdgpu_debugfs_regs2_fops = {
1145         .owner = THIS_MODULE,
1146         .unlocked_ioctl = amdgpu_debugfs_regs2_ioctl,
1147         .read = amdgpu_debugfs_regs2_read,
1148         .write = amdgpu_debugfs_regs2_write,
1149         .open = amdgpu_debugfs_regs2_open,
1150         .release = amdgpu_debugfs_regs2_release,
1151         .llseek = default_llseek
1152 };
1153
1154 static const struct file_operations amdgpu_debugfs_regs_fops = {
1155         .owner = THIS_MODULE,
1156         .read = amdgpu_debugfs_regs_read,
1157         .write = amdgpu_debugfs_regs_write,
1158         .llseek = default_llseek
1159 };
1160 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1161         .owner = THIS_MODULE,
1162         .read = amdgpu_debugfs_regs_didt_read,
1163         .write = amdgpu_debugfs_regs_didt_write,
1164         .llseek = default_llseek
1165 };
1166 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1167         .owner = THIS_MODULE,
1168         .read = amdgpu_debugfs_regs_pcie_read,
1169         .write = amdgpu_debugfs_regs_pcie_write,
1170         .llseek = default_llseek
1171 };
1172 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1173         .owner = THIS_MODULE,
1174         .read = amdgpu_debugfs_regs_smc_read,
1175         .write = amdgpu_debugfs_regs_smc_write,
1176         .llseek = default_llseek
1177 };
1178
1179 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1180         .owner = THIS_MODULE,
1181         .read = amdgpu_debugfs_gca_config_read,
1182         .llseek = default_llseek
1183 };
1184
1185 static const struct file_operations amdgpu_debugfs_sensors_fops = {
1186         .owner = THIS_MODULE,
1187         .read = amdgpu_debugfs_sensor_read,
1188         .llseek = default_llseek
1189 };
1190
1191 static const struct file_operations amdgpu_debugfs_wave_fops = {
1192         .owner = THIS_MODULE,
1193         .read = amdgpu_debugfs_wave_read,
1194         .llseek = default_llseek
1195 };
1196 static const struct file_operations amdgpu_debugfs_gpr_fops = {
1197         .owner = THIS_MODULE,
1198         .read = amdgpu_debugfs_gpr_read,
1199         .llseek = default_llseek
1200 };
1201
1202 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1203         .owner = THIS_MODULE,
1204         .read = amdgpu_debugfs_gfxoff_read,
1205         .write = amdgpu_debugfs_gfxoff_write,
1206         .llseek = default_llseek
1207 };
1208
1209 static const struct file_operations *debugfs_regs[] = {
1210         &amdgpu_debugfs_regs_fops,
1211         &amdgpu_debugfs_regs2_fops,
1212         &amdgpu_debugfs_regs_didt_fops,
1213         &amdgpu_debugfs_regs_pcie_fops,
1214         &amdgpu_debugfs_regs_smc_fops,
1215         &amdgpu_debugfs_gca_config_fops,
1216         &amdgpu_debugfs_sensors_fops,
1217         &amdgpu_debugfs_wave_fops,
1218         &amdgpu_debugfs_gpr_fops,
1219         &amdgpu_debugfs_gfxoff_fops,
1220 };
1221
1222 static const char *debugfs_regs_names[] = {
1223         "amdgpu_regs",
1224         "amdgpu_regs2",
1225         "amdgpu_regs_didt",
1226         "amdgpu_regs_pcie",
1227         "amdgpu_regs_smc",
1228         "amdgpu_gca_config",
1229         "amdgpu_sensors",
1230         "amdgpu_wave",
1231         "amdgpu_gpr",
1232         "amdgpu_gfxoff",
1233 };
1234
1235 /**
1236  * amdgpu_debugfs_regs_init -   Initialize debugfs entries that provide
1237  *                              register access.
1238  *
1239  * @adev: The device to attach the debugfs entries to
1240  */
1241 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1242 {
1243         struct drm_minor *minor = adev_to_drm(adev)->primary;
1244         struct dentry *ent, *root = minor->debugfs_root;
1245         unsigned int i;
1246
1247         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1248                 ent = debugfs_create_file(debugfs_regs_names[i],
1249                                           S_IFREG | S_IRUGO, root,
1250                                           adev, debugfs_regs[i]);
1251                 if (!i && !IS_ERR_OR_NULL(ent))
1252                         i_size_write(ent->d_inode, adev->rmmio_size);
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1259 {
1260         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1261         struct drm_device *dev = adev_to_drm(adev);
1262         int r = 0, i;
1263
1264         r = pm_runtime_get_sync(dev->dev);
1265         if (r < 0) {
1266                 pm_runtime_put_autosuspend(dev->dev);
1267                 return r;
1268         }
1269
1270         /* Avoid accidently unparking the sched thread during GPU reset */
1271         r = down_write_killable(&adev->reset_domain->sem);
1272         if (r)
1273                 return r;
1274
1275         /* hold on the scheduler */
1276         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1277                 struct amdgpu_ring *ring = adev->rings[i];
1278
1279                 if (!ring || !ring->sched.thread)
1280                         continue;
1281                 kthread_park(ring->sched.thread);
1282         }
1283
1284         seq_printf(m, "run ib test:\n");
1285         r = amdgpu_ib_ring_tests(adev);
1286         if (r)
1287                 seq_printf(m, "ib ring tests failed (%d).\n", r);
1288         else
1289                 seq_printf(m, "ib ring tests passed.\n");
1290
1291         /* go on the scheduler */
1292         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1293                 struct amdgpu_ring *ring = adev->rings[i];
1294
1295                 if (!ring || !ring->sched.thread)
1296                         continue;
1297                 kthread_unpark(ring->sched.thread);
1298         }
1299
1300         up_write(&adev->reset_domain->sem);
1301
1302         pm_runtime_mark_last_busy(dev->dev);
1303         pm_runtime_put_autosuspend(dev->dev);
1304
1305         return 0;
1306 }
1307
1308 static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1309 {
1310         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1311         struct drm_device *dev = adev_to_drm(adev);
1312         int r;
1313
1314         r = pm_runtime_get_sync(dev->dev);
1315         if (r < 0) {
1316                 pm_runtime_put_autosuspend(dev->dev);
1317                 return r;
1318         }
1319
1320         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
1321
1322         pm_runtime_mark_last_busy(dev->dev);
1323         pm_runtime_put_autosuspend(dev->dev);
1324
1325         return 0;
1326 }
1327
1328
1329 static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1330 {
1331         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1332         struct drm_device *dev = adev_to_drm(adev);
1333         int r;
1334
1335         r = pm_runtime_get_sync(dev->dev);
1336         if (r < 0) {
1337                 pm_runtime_put_autosuspend(dev->dev);
1338                 return r;
1339         }
1340
1341         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
1342
1343         pm_runtime_mark_last_busy(dev->dev);
1344         pm_runtime_put_autosuspend(dev->dev);
1345
1346         return 0;
1347 }
1348
1349 static int amdgpu_debugfs_benchmark(void *data, u64 val)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1352         struct drm_device *dev = adev_to_drm(adev);
1353         int r;
1354
1355         r = pm_runtime_get_sync(dev->dev);
1356         if (r < 0) {
1357                 pm_runtime_put_autosuspend(dev->dev);
1358                 return r;
1359         }
1360
1361         r = amdgpu_benchmark(adev, val);
1362
1363         pm_runtime_mark_last_busy(dev->dev);
1364         pm_runtime_put_autosuspend(dev->dev);
1365
1366         return r;
1367 }
1368
1369 static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1370 {
1371         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1372         struct drm_device *dev = adev_to_drm(adev);
1373         struct drm_file *file;
1374         int r;
1375
1376         r = mutex_lock_interruptible(&dev->filelist_mutex);
1377         if (r)
1378                 return r;
1379
1380         list_for_each_entry(file, &dev->filelist, lhead) {
1381                 struct amdgpu_fpriv *fpriv = file->driver_priv;
1382                 struct amdgpu_vm *vm = &fpriv->vm;
1383
1384                 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1385                                 vm->task_info.pid, vm->task_info.process_name);
1386                 r = amdgpu_bo_reserve(vm->root.bo, true);
1387                 if (r)
1388                         break;
1389                 amdgpu_debugfs_vm_bo_info(vm, m);
1390                 amdgpu_bo_unreserve(vm->root.bo);
1391         }
1392
1393         mutex_unlock(&dev->filelist_mutex);
1394
1395         return r;
1396 }
1397
1398 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1399 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1400 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1401                          NULL, "%lld\n");
1402 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1403                          NULL, "%lld\n");
1404 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
1405                          "%lld\n");
1406
1407 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1408                                           struct dma_fence **fences)
1409 {
1410         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1411         uint32_t sync_seq, last_seq;
1412
1413         last_seq = atomic_read(&ring->fence_drv.last_seq);
1414         sync_seq = ring->fence_drv.sync_seq;
1415
1416         last_seq &= drv->num_fences_mask;
1417         sync_seq &= drv->num_fences_mask;
1418
1419         do {
1420                 struct dma_fence *fence, **ptr;
1421
1422                 ++last_seq;
1423                 last_seq &= drv->num_fences_mask;
1424                 ptr = &drv->fences[last_seq];
1425
1426                 fence = rcu_dereference_protected(*ptr, 1);
1427                 RCU_INIT_POINTER(*ptr, NULL);
1428
1429                 if (!fence)
1430                         continue;
1431
1432                 fences[last_seq] = fence;
1433
1434         } while (last_seq != sync_seq);
1435 }
1436
1437 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1438                                             int length)
1439 {
1440         int i;
1441         struct dma_fence *fence;
1442
1443         for (i = 0; i < length; i++) {
1444                 fence = fences[i];
1445                 if (!fence)
1446                         continue;
1447                 dma_fence_signal(fence);
1448                 dma_fence_put(fence);
1449         }
1450 }
1451
1452 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1453 {
1454         struct drm_sched_job *s_job;
1455         struct dma_fence *fence;
1456
1457         spin_lock(&sched->job_list_lock);
1458         list_for_each_entry(s_job, &sched->pending_list, list) {
1459                 fence = sched->ops->run_job(s_job);
1460                 dma_fence_put(fence);
1461         }
1462         spin_unlock(&sched->job_list_lock);
1463 }
1464
1465 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1466 {
1467         struct amdgpu_job *job;
1468         struct drm_sched_job *s_job, *tmp;
1469         uint32_t preempt_seq;
1470         struct dma_fence *fence, **ptr;
1471         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1472         struct drm_gpu_scheduler *sched = &ring->sched;
1473         bool preempted = true;
1474
1475         if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1476                 return;
1477
1478         preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1479         if (preempt_seq <= atomic_read(&drv->last_seq)) {
1480                 preempted = false;
1481                 goto no_preempt;
1482         }
1483
1484         preempt_seq &= drv->num_fences_mask;
1485         ptr = &drv->fences[preempt_seq];
1486         fence = rcu_dereference_protected(*ptr, 1);
1487
1488 no_preempt:
1489         spin_lock(&sched->job_list_lock);
1490         list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1491                 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1492                         /* remove job from ring_mirror_list */
1493                         list_del_init(&s_job->list);
1494                         sched->ops->free_job(s_job);
1495                         continue;
1496                 }
1497                 job = to_amdgpu_job(s_job);
1498                 if (preempted && (&job->hw_fence) == fence)
1499                         /* mark the job as preempted */
1500                         job->preemption_status |= AMDGPU_IB_PREEMPTED;
1501         }
1502         spin_unlock(&sched->job_list_lock);
1503 }
1504
1505 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1506 {
1507         int r, resched, length;
1508         struct amdgpu_ring *ring;
1509         struct dma_fence **fences = NULL;
1510         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1511
1512         if (val >= AMDGPU_MAX_RINGS)
1513                 return -EINVAL;
1514
1515         ring = adev->rings[val];
1516
1517         if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1518                 return -EINVAL;
1519
1520         /* the last preemption failed */
1521         if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1522                 return -EBUSY;
1523
1524         length = ring->fence_drv.num_fences_mask + 1;
1525         fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1526         if (!fences)
1527                 return -ENOMEM;
1528
1529         /* Avoid accidently unparking the sched thread during GPU reset */
1530         r = down_read_killable(&adev->reset_domain->sem);
1531         if (r)
1532                 goto pro_end;
1533
1534         /* stop the scheduler */
1535         kthread_park(ring->sched.thread);
1536
1537         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1538
1539         /* preempt the IB */
1540         r = amdgpu_ring_preempt_ib(ring);
1541         if (r) {
1542                 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1543                 goto failure;
1544         }
1545
1546         amdgpu_fence_process(ring);
1547
1548         if (atomic_read(&ring->fence_drv.last_seq) !=
1549             ring->fence_drv.sync_seq) {
1550                 DRM_INFO("ring %d was preempted\n", ring->idx);
1551
1552                 amdgpu_ib_preempt_mark_partial_job(ring);
1553
1554                 /* swap out the old fences */
1555                 amdgpu_ib_preempt_fences_swap(ring, fences);
1556
1557                 amdgpu_fence_driver_force_completion(ring);
1558
1559                 /* resubmit unfinished jobs */
1560                 amdgpu_ib_preempt_job_recovery(&ring->sched);
1561
1562                 /* wait for jobs finished */
1563                 amdgpu_fence_wait_empty(ring);
1564
1565                 /* signal the old fences */
1566                 amdgpu_ib_preempt_signal_fences(fences, length);
1567         }
1568
1569 failure:
1570         /* restart the scheduler */
1571         kthread_unpark(ring->sched.thread);
1572
1573         up_read(&adev->reset_domain->sem);
1574
1575         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1576
1577 pro_end:
1578         kfree(fences);
1579
1580         return r;
1581 }
1582
1583 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1584 {
1585         int ret = 0;
1586         uint32_t max_freq, min_freq;
1587         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1588
1589         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1590                 return -EINVAL;
1591
1592         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1593         if (ret < 0) {
1594                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1595                 return ret;
1596         }
1597
1598         ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1599         if (ret == -EOPNOTSUPP) {
1600                 ret = 0;
1601                 goto out;
1602         }
1603         if (ret || val > max_freq || val < min_freq) {
1604                 ret = -EINVAL;
1605                 goto out;
1606         }
1607
1608         ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1609         if (ret)
1610                 ret = -EINVAL;
1611
1612 out:
1613         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1614         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1615
1616         return ret;
1617 }
1618
1619 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1620                         amdgpu_debugfs_ib_preempt, "%llu\n");
1621
1622 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
1623                         amdgpu_debugfs_sclk_set, "%llu\n");
1624
1625 static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
1626                                 char __user *buf, size_t size, loff_t *pos)
1627 {
1628         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1629         char reg_offset[12];
1630         int i, ret, len = 0;
1631
1632         if (*pos)
1633                 return 0;
1634
1635         memset(reg_offset, 0, 12);
1636         ret = down_read_killable(&adev->reset_domain->sem);
1637         if (ret)
1638                 return ret;
1639
1640         for (i = 0; i < adev->num_regs; i++) {
1641                 sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
1642                 up_read(&adev->reset_domain->sem);
1643                 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
1644                         return -EFAULT;
1645
1646                 len += strlen(reg_offset);
1647                 ret = down_read_killable(&adev->reset_domain->sem);
1648                 if (ret)
1649                         return ret;
1650         }
1651
1652         up_read(&adev->reset_domain->sem);
1653         *pos += len;
1654
1655         return len;
1656 }
1657
1658 static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
1659                         const char __user *buf, size_t size, loff_t *pos)
1660 {
1661         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1662         char reg_offset[11];
1663         uint32_t *new, *tmp = NULL;
1664         int ret, i = 0, len = 0;
1665
1666         do {
1667                 memset(reg_offset, 0, 11);
1668                 if (copy_from_user(reg_offset, buf + len,
1669                                         min(10, ((int)size-len)))) {
1670                         ret = -EFAULT;
1671                         goto error_free;
1672                 }
1673
1674                 new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
1675                 if (!new) {
1676                         ret = -ENOMEM;
1677                         goto error_free;
1678                 }
1679                 tmp = new;
1680                 if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
1681                         ret = -EINVAL;
1682                         goto error_free;
1683                 }
1684
1685                 len += ret;
1686                 i++;
1687         } while (len < size);
1688
1689         new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
1690         if (!new) {
1691                 ret = -ENOMEM;
1692                 goto error_free;
1693         }
1694         ret = down_write_killable(&adev->reset_domain->sem);
1695         if (ret)
1696                 goto error_free;
1697
1698         swap(adev->reset_dump_reg_list, tmp);
1699         swap(adev->reset_dump_reg_value, new);
1700         adev->num_regs = i;
1701         up_write(&adev->reset_domain->sem);
1702         ret = size;
1703
1704 error_free:
1705         kfree(tmp);
1706         kfree(new);
1707         return ret;
1708 }
1709
1710 static const struct file_operations amdgpu_reset_dump_register_list = {
1711         .owner = THIS_MODULE,
1712         .read = amdgpu_reset_dump_register_list_read,
1713         .write = amdgpu_reset_dump_register_list_write,
1714         .llseek = default_llseek
1715 };
1716
1717 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1718 {
1719         struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
1720         struct dentry *ent;
1721         int r, i;
1722
1723         if (!debugfs_initialized())
1724                 return 0;
1725
1726         debugfs_create_x32("amdgpu_smu_debug", 0600, root,
1727                            &adev->pm.smu_debug_mask);
1728
1729         ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
1730                                   &fops_ib_preempt);
1731         if (IS_ERR(ent)) {
1732                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1733                 return PTR_ERR(ent);
1734         }
1735
1736         ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
1737                                   &fops_sclk_set);
1738         if (IS_ERR(ent)) {
1739                 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1740                 return PTR_ERR(ent);
1741         }
1742
1743         /* Register debugfs entries for amdgpu_ttm */
1744         amdgpu_ttm_debugfs_init(adev);
1745         amdgpu_debugfs_pm_init(adev);
1746         amdgpu_debugfs_sa_init(adev);
1747         amdgpu_debugfs_fence_init(adev);
1748         amdgpu_debugfs_gem_init(adev);
1749
1750         r = amdgpu_debugfs_regs_init(adev);
1751         if (r)
1752                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1753
1754         amdgpu_debugfs_firmware_init(adev);
1755         amdgpu_ta_if_debugfs_init(adev);
1756
1757 #if defined(CONFIG_DRM_AMD_DC)
1758         if (amdgpu_device_has_dc_support(adev))
1759                 dtn_debugfs_init(adev);
1760 #endif
1761
1762         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1763                 struct amdgpu_ring *ring = adev->rings[i];
1764
1765                 if (!ring)
1766                         continue;
1767
1768                 amdgpu_debugfs_ring_init(adev, ring);
1769         }
1770
1771         for ( i = 0; i < adev->vcn.num_vcn_inst; i++) {
1772                 if (!amdgpu_vcnfw_log)
1773                         break;
1774
1775                 if (adev->vcn.harvest_config & (1 << i))
1776                         continue;
1777
1778                 amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
1779         }
1780
1781         amdgpu_ras_debugfs_create_all(adev);
1782         amdgpu_rap_debugfs_init(adev);
1783         amdgpu_securedisplay_debugfs_init(adev);
1784         amdgpu_fw_attestation_debugfs_init(adev);
1785
1786         debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
1787                             &amdgpu_evict_vram_fops);
1788         debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
1789                             &amdgpu_evict_gtt_fops);
1790         debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
1791                             &amdgpu_debugfs_test_ib_fops);
1792         debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
1793                             &amdgpu_debugfs_vm_info_fops);
1794         debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
1795                             &amdgpu_benchmark_fops);
1796         debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
1797                             &amdgpu_reset_dump_register_list);
1798
1799         adev->debugfs_vbios_blob.data = adev->bios;
1800         adev->debugfs_vbios_blob.size = adev->bios_size;
1801         debugfs_create_blob("amdgpu_vbios", 0444, root,
1802                             &adev->debugfs_vbios_blob);
1803
1804         adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
1805         adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
1806         debugfs_create_blob("amdgpu_discovery", 0444, root,
1807                             &adev->debugfs_discovery_blob);
1808
1809         return 0;
1810 }
1811
1812 #else
1813 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1814 {
1815         return 0;
1816 }
1817 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1818 {
1819         return 0;
1820 }
1821 #endif