drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <drm/drm_drv.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42
  43 /*
  44  * Fences
  45  * Fences mark an event in the GPUs pipeline and are used
  46  * for GPU/CPU synchronization.  When the fence is written,
  47  * it is expected that all buffers associated with that fence
  48  * are no longer in use by the associated ring on the GPU and
  49  * that the the relevant GPU caches have been flushed.
  50  */
  51
  52 struct amdgpu_fence {
  53         struct dma_fence base;
  54
  55         /* RB, DMA, etc. */
  56         struct amdgpu_ring              *ring;
  57 };
  58
  59 static struct kmem_cache *amdgpu_fence_slab;
  60
  61 int amdgpu_fence_slab_init(void)
  62 {
  63         amdgpu_fence_slab = kmem_cache_create(
  64                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  65                 SLAB_HWCACHE_ALIGN, NULL);
  66         if (!amdgpu_fence_slab)
  67                 return -ENOMEM;
  68         return 0;
  69 }
  70
  71 void amdgpu_fence_slab_fini(void)
  72 {
  73         rcu_barrier();
  74         kmem_cache_destroy(amdgpu_fence_slab);
  75 }
  76 /*
  77  * Cast helper
  78  */
  79 static const struct dma_fence_ops amdgpu_fence_ops;
  80 static const struct dma_fence_ops amdgpu_job_fence_ops;
  81 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  82 {
  83         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  84
  85         if (__f->base.ops == &amdgpu_fence_ops ||
  86             __f->base.ops == &amdgpu_job_fence_ops)
  87                 return __f;
  88
  89         return NULL;
  90 }
  91
  92 /**
  93  * amdgpu_fence_write - write a fence value
  94  *
  95  * @ring: ring the fence is associated with
  96  * @seq: sequence number to write
  97  *
  98  * Writes a fence value to memory (all asics).
  99  */
 100 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
 101 {
 102         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 103
 104         if (drv->cpu_addr)
 105                 *drv->cpu_addr = cpu_to_le32(seq);
 106 }
 107
 108 /**
 109  * amdgpu_fence_read - read a fence value
 110  *
 111  * @ring: ring the fence is associated with
 112  *
 113  * Reads a fence value from memory (all asics).
 114  * Returns the value of the fence read from memory.
 115  */
 116 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 119         u32 seq = 0;
 120
 121         if (drv->cpu_addr)
 122                 seq = le32_to_cpu(*drv->cpu_addr);
 123         else
 124                 seq = atomic_read(&drv->last_seq);
 125
 126         return seq;
 127 }
 128
 129 /**
 130  * amdgpu_fence_emit - emit a fence on the requested ring
 131  *
 132  * @ring: ring the fence is associated with
 133  * @f: resulting fence object
 134  * @job: job the fence is embedded in
 135  * @flags: flags to pass into the subordinate .emit_fence() call
 136  *
 137  * Emits a fence command on the requested ring (all asics).
 138  * Returns 0 on success, -ENOMEM on failure.
 139  */
 140 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
 141                       unsigned flags)
 142 {
 143         struct amdgpu_device *adev = ring->adev;
 144         struct dma_fence *fence;
 145         struct amdgpu_fence *am_fence;
 146         struct dma_fence __rcu **ptr;
 147         uint32_t seq;
 148         int r;
 149
 150         if (job == NULL) {
 151                 /* create a sperate hw fence */
 152                 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
 153                 if (am_fence == NULL)
 154                         return -ENOMEM;
 155                 fence = &am_fence->base;
 156                 am_fence->ring = ring;
 157         } else {
 158                 /* take use of job-embedded fence */
 159                 fence = &job->hw_fence;
 160         }
 161
 162         seq = ++ring->fence_drv.sync_seq;
 163         if (job && job->job_run_counter) {
 164                 /* reinit seq for resubmitted jobs */
 165                 fence->seqno = seq;
 166         } else {
 167                 if (job)
 168                         dma_fence_init(fence, &amdgpu_job_fence_ops,
 169                                        &ring->fence_drv.lock,
 170                                        adev->fence_context + ring->idx, seq);
 171                 else
 172                         dma_fence_init(fence, &amdgpu_fence_ops,
 173                                        &ring->fence_drv.lock,
 174                                        adev->fence_context + ring->idx, seq);
 175         }
 176
 177         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 178                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 179         pm_runtime_get_noresume(adev_to_drm(adev)->dev);
 180         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 181         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 182                 struct dma_fence *old;
 183
 184                 rcu_read_lock();
 185                 old = dma_fence_get_rcu_safe(ptr);
 186                 rcu_read_unlock();
 187
 188                 if (old) {
 189                         r = dma_fence_wait(old, false);
 190                         dma_fence_put(old);
 191                         if (r)
 192                                 return r;
 193                 }
 194         }
 195
 196         /* This function can't be called concurrently anyway, otherwise
 197          * emitting the fence would mess up the hardware ring buffer.
 198          */
 199         rcu_assign_pointer(*ptr, dma_fence_get(fence));
 200
 201         *f = fence;
 202
 203         return 0;
 204 }
 205
 206 /**
 207  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 208  *
 209  * @ring: ring the fence is associated with
 210  * @s: resulting sequence number
 211  * @timeout: the timeout for waiting in usecs
 212  *
 213  * Emits a fence command on the requested ring (all asics).
 214  * Used For polling fence.
 215  * Returns 0 on success, -ENOMEM on failure.
 216  */
 217 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
 218                               uint32_t timeout)
 219 {
 220         uint32_t seq;
 221         signed long r;
 222
 223         if (!s)
 224                 return -EINVAL;
 225
 226         seq = ++ring->fence_drv.sync_seq;
 227         r = amdgpu_fence_wait_polling(ring,
 228                                       seq - ring->fence_drv.num_fences_mask,
 229                                       timeout);
 230         if (r < 1)
 231                 return -ETIMEDOUT;
 232
 233         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 234                                seq, 0);
 235
 236         *s = seq;
 237
 238         return 0;
 239 }
 240
 241 /**
 242  * amdgpu_fence_schedule_fallback - schedule fallback check
 243  *
 244  * @ring: pointer to struct amdgpu_ring
 245  *
 246  * Start a timer as fallback to our interrupts.
 247  */
 248 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 249 {
 250         mod_timer(&ring->fence_drv.fallback_timer,
 251                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 252 }
 253
 254 /**
 255  * amdgpu_fence_process - check for fence activity
 256  *
 257  * @ring: pointer to struct amdgpu_ring
 258  *
 259  * Checks the current fence value and calculates the last
 260  * signalled fence value. Wakes the fence queue if the
 261  * sequence number has increased.
 262  *
 263  * Returns true if fence was processed
 264  */
 265 bool amdgpu_fence_process(struct amdgpu_ring *ring)
 266 {
 267         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 268         struct amdgpu_device *adev = ring->adev;
 269         uint32_t seq, last_seq;
 270
 271         do {
 272                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 273                 seq = amdgpu_fence_read(ring);
 274
 275         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 276
 277         if (del_timer(&ring->fence_drv.fallback_timer) &&
 278             seq != ring->fence_drv.sync_seq)
 279                 amdgpu_fence_schedule_fallback(ring);
 280
 281         if (unlikely(seq == last_seq))
 282                 return false;
 283
 284         last_seq &= drv->num_fences_mask;
 285         seq &= drv->num_fences_mask;
 286
 287         do {
 288                 struct dma_fence *fence, **ptr;
 289
 290                 ++last_seq;
 291                 last_seq &= drv->num_fences_mask;
 292                 ptr = &drv->fences[last_seq];
 293
 294                 /* There is always exactly one thread signaling this fence slot */
 295                 fence = rcu_dereference_protected(*ptr, 1);
 296                 RCU_INIT_POINTER(*ptr, NULL);
 297
 298                 if (!fence)
 299                         continue;
 300
 301                 dma_fence_signal(fence);
 302                 dma_fence_put(fence);
 303                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 304                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 305         } while (last_seq != seq);
 306
 307         return true;
 308 }
 309
 310 /**
 311  * amdgpu_fence_fallback - fallback for hardware interrupts
 312  *
 313  * @t: timer context used to obtain the pointer to ring structure
 314  *
 315  * Checks for fence activity.
 316  */
 317 static void amdgpu_fence_fallback(struct timer_list *t)
 318 {
 319         struct amdgpu_ring *ring = from_timer(ring, t,
 320                                               fence_drv.fallback_timer);
 321
 322         if (amdgpu_fence_process(ring))
 323                 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
 324 }
 325
 326 /**
 327  * amdgpu_fence_wait_empty - wait for all fences to signal
 328  *
 329  * @ring: ring index the fence is associated with
 330  *
 331  * Wait for all fences on the requested ring to signal (all asics).
 332  * Returns 0 if the fences have passed, error for all other cases.
 333  */
 334 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 335 {
 336         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 337         struct dma_fence *fence, **ptr;
 338         int r;
 339
 340         if (!seq)
 341                 return 0;
 342
 343         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 344         rcu_read_lock();
 345         fence = rcu_dereference(*ptr);
 346         if (!fence || !dma_fence_get_rcu(fence)) {
 347                 rcu_read_unlock();
 348                 return 0;
 349         }
 350         rcu_read_unlock();
 351
 352         r = dma_fence_wait(fence, false);
 353         dma_fence_put(fence);
 354         return r;
 355 }
 356
 357 /**
 358  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 359  *
 360  * @ring: ring index the fence is associated with
 361  * @wait_seq: sequence number to wait
 362  * @timeout: the timeout for waiting in usecs
 363  *
 364  * Wait for all fences on the requested ring to signal (all asics).
 365  * Returns left time if no timeout, 0 or minus if timeout.
 366  */
 367 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 368                                       uint32_t wait_seq,
 369                                       signed long timeout)
 370 {
 371         uint32_t seq;
 372
 373         do {
 374                 seq = amdgpu_fence_read(ring);
 375                 udelay(5);
 376                 timeout -= 5;
 377         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 378
 379         return timeout > 0 ? timeout : 0;
 380 }
 381 /**
 382  * amdgpu_fence_count_emitted - get the count of emitted fences
 383  *
 384  * @ring: ring the fence is associated with
 385  *
 386  * Get the number of fences emitted on the requested ring (all asics).
 387  * Returns the number of emitted fences on the ring.  Used by the
 388  * dynpm code to ring track activity.
 389  */
 390 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 391 {
 392         uint64_t emitted;
 393
 394         /* We are not protected by ring lock when reading the last sequence
 395          * but it's ok to report slightly wrong fence count here.
 396          */
 397         amdgpu_fence_process(ring);
 398         emitted = 0x100000000ull;
 399         emitted -= atomic_read(&ring->fence_drv.last_seq);
 400         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 401         return lower_32_bits(emitted);
 402 }
 403
 404 /**
 405  * amdgpu_fence_driver_start_ring - make the fence driver
 406  * ready for use on the requested ring.
 407  *
 408  * @ring: ring to start the fence driver on
 409  * @irq_src: interrupt source to use for this ring
 410  * @irq_type: interrupt type to use for this ring
 411  *
 412  * Make the fence driver ready for processing (all asics).
 413  * Not all asics have all rings, so each asic will only
 414  * start the fence driver on the rings it has.
 415  * Returns 0 for success, errors for failure.
 416  */
 417 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 418                                    struct amdgpu_irq_src *irq_src,
 419                                    unsigned irq_type)
 420 {
 421         struct amdgpu_device *adev = ring->adev;
 422         uint64_t index;
 423
 424         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 425                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 426                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 427         } else {
 428                 /* put fence directly behind firmware */
 429                 index = ALIGN(adev->uvd.fw->size, 8);
 430                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 431                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 432         }
 433         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 434
 435         ring->fence_drv.irq_src = irq_src;
 436         ring->fence_drv.irq_type = irq_type;
 437         ring->fence_drv.initialized = true;
 438
 439         DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
 440                       ring->name, ring->fence_drv.gpu_addr);
 441         return 0;
 442 }
 443
 444 /**
 445  * amdgpu_fence_driver_init_ring - init the fence driver
 446  * for the requested ring.
 447  *
 448  * @ring: ring to init the fence driver on
 449  * @num_hw_submission: number of entries on the hardware queue
 450  * @sched_score: optional score atomic shared with other schedulers
 451  *
 452  * Init the fence driver for the requested ring (all asics).
 453  * Helper function for amdgpu_fence_driver_init().
 454  */
 455 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 456                                   unsigned num_hw_submission,
 457                                   atomic_t *sched_score)
 458 {
 459         struct amdgpu_device *adev = ring->adev;
 460         long timeout;
 461         int r;
 462
 463         if (!adev)
 464                 return -EINVAL;
 465
 466         if (!is_power_of_2(num_hw_submission))
 467                 return -EINVAL;
 468
 469         ring->fence_drv.cpu_addr = NULL;
 470         ring->fence_drv.gpu_addr = 0;
 471         ring->fence_drv.sync_seq = 0;
 472         atomic_set(&ring->fence_drv.last_seq, 0);
 473         ring->fence_drv.initialized = false;
 474
 475         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 476
 477         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 478         spin_lock_init(&ring->fence_drv.lock);
 479         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 480                                          GFP_KERNEL);
 481         if (!ring->fence_drv.fences)
 482                 return -ENOMEM;
 483
 484         /* No need to setup the GPU scheduler for rings that don't need it */
 485         if (ring->no_scheduler)
 486                 return 0;
 487
 488         switch (ring->funcs->type) {
 489         case AMDGPU_RING_TYPE_GFX:
 490                 timeout = adev->gfx_timeout;
 491                 break;
 492         case AMDGPU_RING_TYPE_COMPUTE:
 493                 timeout = adev->compute_timeout;
 494                 break;
 495         case AMDGPU_RING_TYPE_SDMA:
 496                 timeout = adev->sdma_timeout;
 497                 break;
 498         default:
 499                 timeout = adev->video_timeout;
 500                 break;
 501         }
 502
 503         r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 504                            num_hw_submission, amdgpu_job_hang_limit,
 505                            timeout, NULL, sched_score, ring->name);
 506         if (r) {
 507                 DRM_ERROR("Failed to create scheduler on ring %s.\n",
 508                           ring->name);
 509                 return r;
 510         }
 511
 512         return 0;
 513 }
 514
 515 /**
 516  * amdgpu_fence_driver_sw_init - init the fence driver
 517  * for all possible rings.
 518  *
 519  * @adev: amdgpu device pointer
 520  *
 521  * Init the fence driver for all possible rings (all asics).
 522  * Not all asics have all rings, so each asic will only
 523  * start the fence driver on the rings it has using
 524  * amdgpu_fence_driver_start_ring().
 525  * Returns 0 for success.
 526  */
 527 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
 528 {
 529         return 0;
 530 }
 531
 532 /**
 533  * amdgpu_fence_driver_hw_fini - tear down the fence driver
 534  * for all possible rings.
 535  *
 536  * @adev: amdgpu device pointer
 537  *
 538  * Tear down the fence driver for all possible rings (all asics).
 539  */
 540 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
 541 {
 542         int i, r;
 543
 544         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 545                 struct amdgpu_ring *ring = adev->rings[i];
 546
 547                 if (!ring || !ring->fence_drv.initialized)
 548                         continue;
 549
 550                 /* You can't wait for HW to signal if it's gone */
 551                 if (!drm_dev_is_unplugged(adev_to_drm(adev)))
 552                         r = amdgpu_fence_wait_empty(ring);
 553                 else
 554                         r = -ENODEV;
 555                 /* no need to trigger GPU reset as we are unloading */
 556                 if (r)
 557                         amdgpu_fence_driver_force_completion(ring);
 558
 559                 if (ring->fence_drv.irq_src)
 560                         amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 561                                        ring->fence_drv.irq_type);
 562
 563                 del_timer_sync(&ring->fence_drv.fallback_timer);
 564         }
 565 }
 566
 567 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
 568 {
 569         unsigned int i, j;
 570
 571         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 572                 struct amdgpu_ring *ring = adev->rings[i];
 573
 574                 if (!ring || !ring->fence_drv.initialized)
 575                         continue;
 576
 577                 if (!ring->no_scheduler)
 578                         drm_sched_fini(&ring->sched);
 579
 580                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 581                         dma_fence_put(ring->fence_drv.fences[j]);
 582                 kfree(ring->fence_drv.fences);
 583                 ring->fence_drv.fences = NULL;
 584                 ring->fence_drv.initialized = false;
 585         }
 586 }
 587
 588 /**
 589  * amdgpu_fence_driver_hw_init - enable the fence driver
 590  * for all possible rings.
 591  *
 592  * @adev: amdgpu device pointer
 593  *
 594  * Enable the fence driver for all possible rings (all asics).
 595  * Not all asics have all rings, so each asic will only
 596  * start the fence driver on the rings it has using
 597  * amdgpu_fence_driver_start_ring().
 598  * Returns 0 for success.
 599  */
 600 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
 601 {
 602         int i;
 603
 604         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 605                 struct amdgpu_ring *ring = adev->rings[i];
 606                 if (!ring || !ring->fence_drv.initialized)
 607                         continue;
 608
 609                 /* enable the interrupt */
 610                 if (ring->fence_drv.irq_src)
 611                         amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 612                                        ring->fence_drv.irq_type);
 613         }
 614 }
 615
 616 /**
 617  * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
 618  *
 619  * @ring: fence of the ring to be cleared
 620  *
 621  */
 622 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
 623 {
 624         int i;
 625         struct dma_fence *old, **ptr;
 626
 627         for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
 628                 ptr = &ring->fence_drv.fences[i];
 629                 old = rcu_dereference_protected(*ptr, 1);
 630                 if (old && old->ops == &amdgpu_job_fence_ops)
 631                         RCU_INIT_POINTER(*ptr, NULL);
 632         }
 633 }
 634
 635 /**
 636  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 637  *
 638  * @ring: fence of the ring to signal
 639  *
 640  */
 641 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 642 {
 643         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 644         amdgpu_fence_process(ring);
 645 }
 646
 647 /*
 648  * Common fence implementation
 649  */
 650
 651 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 652 {
 653         return "amdgpu";
 654 }
 655
 656 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 657 {
 658         return (const char *)to_amdgpu_fence(f)->ring->name;
 659 }
 660
 661 static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
 662 {
 663         struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 664
 665         return (const char *)to_amdgpu_ring(job->base.sched)->name;
 666 }
 667
 668 /**
 669  * amdgpu_fence_enable_signaling - enable signalling on fence
 670  * @f: fence
 671  *
 672  * This function is called with fence_queue lock held, and adds a callback
 673  * to fence_queue that checks if this fence is signaled, and if so it
 674  * signals the fence and removes itself.
 675  */
 676 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 677 {
 678         if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
 679                 amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
 680
 681         return true;
 682 }
 683
 684 /**
 685  * amdgpu_job_fence_enable_signaling - enable signalling on job fence
 686  * @f: fence
 687  *
 688  * This is the simliar function with amdgpu_fence_enable_signaling above, it
 689  * only handles the job embedded fence.
 690  */
 691 static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
 692 {
 693         struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 694
 695         if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
 696                 amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
 697
 698         return true;
 699 }
 700
 701 /**
 702  * amdgpu_fence_free - free up the fence memory
 703  *
 704  * @rcu: RCU callback head
 705  *
 706  * Free up the fence memory after the RCU grace period.
 707  */
 708 static void amdgpu_fence_free(struct rcu_head *rcu)
 709 {
 710         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 711
 712         /* free fence_slab if it's separated fence*/
 713         kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
 714 }
 715
 716 /**
 717  * amdgpu_job_fence_free - free up the job with embedded fence
 718  *
 719  * @rcu: RCU callback head
 720  *
 721  * Free up the job with embedded fence after the RCU grace period.
 722  */
 723 static void amdgpu_job_fence_free(struct rcu_head *rcu)
 724 {
 725         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 726
 727         /* free job if fence has a parent job */
 728         kfree(container_of(f, struct amdgpu_job, hw_fence));
 729 }
 730
 731 /**
 732  * amdgpu_fence_release - callback that fence can be freed
 733  *
 734  * @f: fence
 735  *
 736  * This function is called when the reference count becomes zero.
 737  * It just RCU schedules freeing up the fence.
 738  */
 739 static void amdgpu_fence_release(struct dma_fence *f)
 740 {
 741         call_rcu(&f->rcu, amdgpu_fence_free);
 742 }
 743
 744 /**
 745  * amdgpu_job_fence_release - callback that job embedded fence can be freed
 746  *
 747  * @f: fence
 748  *
 749  * This is the simliar function with amdgpu_fence_release above, it
 750  * only handles the job embedded fence.
 751  */
 752 static void amdgpu_job_fence_release(struct dma_fence *f)
 753 {
 754         call_rcu(&f->rcu, amdgpu_job_fence_free);
 755 }
 756
 757 static const struct dma_fence_ops amdgpu_fence_ops = {
 758         .get_driver_name = amdgpu_fence_get_driver_name,
 759         .get_timeline_name = amdgpu_fence_get_timeline_name,
 760         .enable_signaling = amdgpu_fence_enable_signaling,
 761         .release = amdgpu_fence_release,
 762 };
 763
 764 static const struct dma_fence_ops amdgpu_job_fence_ops = {
 765         .get_driver_name = amdgpu_fence_get_driver_name,
 766         .get_timeline_name = amdgpu_job_fence_get_timeline_name,
 767         .enable_signaling = amdgpu_job_fence_enable_signaling,
 768         .release = amdgpu_job_fence_release,
 769 };
 770
 771 /*
 772  * Fence debugfs
 773  */
 774 #if defined(CONFIG_DEBUG_FS)
 775 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
 776 {
 777         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
 778         int i;
 779
 780         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 781                 struct amdgpu_ring *ring = adev->rings[i];
 782                 if (!ring || !ring->fence_drv.initialized)
 783                         continue;
 784
 785                 amdgpu_fence_process(ring);
 786
 787                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 788                 seq_printf(m, "Last signaled fence          0x%08x\n",
 789                            atomic_read(&ring->fence_drv.last_seq));
 790                 seq_printf(m, "Last emitted                 0x%08x\n",
 791                            ring->fence_drv.sync_seq);
 792
 793                 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
 794                     ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
 795                         seq_printf(m, "Last signaled trailing fence 0x%08x\n",
 796                                    le32_to_cpu(*ring->trail_fence_cpu_addr));
 797                         seq_printf(m, "Last emitted                 0x%08x\n",
 798                                    ring->trail_seq);
 799                 }
 800
 801                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 802                         continue;
 803
 804                 /* set in CP_VMID_PREEMPT and preemption occurred */
 805                 seq_printf(m, "Last preempted               0x%08x\n",
 806                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 807                 /* set in CP_VMID_RESET and reset occurred */
 808                 seq_printf(m, "Last reset                   0x%08x\n",
 809                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 810                 /* Both preemption and reset occurred */
 811                 seq_printf(m, "Last both                    0x%08x\n",
 812                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 813         }
 814         return 0;
 815 }
 816
 817 /*
 818  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 819  *
 820  * Manually trigger a gpu reset at the next fence wait.
 821  */
 822 static int gpu_recover_get(void *data, u64 *val)
 823 {
 824         struct amdgpu_device *adev = (struct amdgpu_device *)data;
 825         struct drm_device *dev = adev_to_drm(adev);
 826         int r;
 827
 828         r = pm_runtime_get_sync(dev->dev);
 829         if (r < 0) {
 830                 pm_runtime_put_autosuspend(dev->dev);
 831                 return 0;
 832         }
 833
 834         *val = amdgpu_device_gpu_recover(adev, NULL);
 835
 836         pm_runtime_mark_last_busy(dev->dev);
 837         pm_runtime_put_autosuspend(dev->dev);
 838
 839         return 0;
 840 }
 841
 842 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 843 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 844                          "%lld\n");
 845
 846 #endif
 847
 848 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 849 {
 850 #if defined(CONFIG_DEBUG_FS)
 851         struct drm_minor *minor = adev_to_drm(adev)->primary;
 852         struct dentry *root = minor->debugfs_root;
 853
 854         debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 855                             &amdgpu_debugfs_fence_info_fops);
 856
 857         if (!amdgpu_sriov_vf(adev))
 858                 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
 859                                     &amdgpu_debugfs_gpu_recover_fops);
 860 #endif
 861 }
 862