drivers/gpu/drm/omapdrm/dss/venc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2009 Nokia Corporation
   4  * Author: Tomi Valkeinen <[email protected]>
   5  *
   6  * VENC settings from TI's DSS driver
   7  */
   8
   9 #define DSS_SUBSYS_NAME "VENC"
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/clk.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/of.h>
  24 #include <linux/of_graph.h>
  25 #include <linux/component.h>
  26 #include <linux/sys_soc.h>
  27
  28 #include <drm/drm_bridge.h>
  29
  30 #include "omapdss.h"
  31 #include "dss.h"
  32
  33 /* Venc registers */
  34 #define VENC_REV_ID                             0x00
  35 #define VENC_STATUS                             0x04
  36 #define VENC_F_CONTROL                          0x08
  37 #define VENC_VIDOUT_CTRL                        0x10
  38 #define VENC_SYNC_CTRL                          0x14
  39 #define VENC_LLEN                               0x1C
  40 #define VENC_FLENS                              0x20
  41 #define VENC_HFLTR_CTRL                         0x24
  42 #define VENC_CC_CARR_WSS_CARR                   0x28
  43 #define VENC_C_PHASE                            0x2C
  44 #define VENC_GAIN_U                             0x30
  45 #define VENC_GAIN_V                             0x34
  46 #define VENC_GAIN_Y                             0x38
  47 #define VENC_BLACK_LEVEL                        0x3C
  48 #define VENC_BLANK_LEVEL                        0x40
  49 #define VENC_X_COLOR                            0x44
  50 #define VENC_M_CONTROL                          0x48
  51 #define VENC_BSTAMP_WSS_DATA                    0x4C
  52 #define VENC_S_CARR                             0x50
  53 #define VENC_LINE21                             0x54
  54 #define VENC_LN_SEL                             0x58
  55 #define VENC_L21__WC_CTL                        0x5C
  56 #define VENC_HTRIGGER_VTRIGGER                  0x60
  57 #define VENC_SAVID__EAVID                       0x64
  58 #define VENC_FLEN__FAL                          0x68
  59 #define VENC_LAL__PHASE_RESET                   0x6C
  60 #define VENC_HS_INT_START_STOP_X                0x70
  61 #define VENC_HS_EXT_START_STOP_X                0x74
  62 #define VENC_VS_INT_START_X                     0x78
  63 #define VENC_VS_INT_STOP_X__VS_INT_START_Y      0x7C
  64 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X      0x80
  65 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y      0x84
  66 #define VENC_VS_EXT_STOP_Y                      0x88
  67 #define VENC_AVID_START_STOP_X                  0x90
  68 #define VENC_AVID_START_STOP_Y                  0x94
  69 #define VENC_FID_INT_START_X__FID_INT_START_Y   0xA0
  70 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X  0xA4
  71 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y  0xA8
  72 #define VENC_TVDETGP_INT_START_STOP_X           0xB0
  73 #define VENC_TVDETGP_INT_START_STOP_Y           0xB4
  74 #define VENC_GEN_CTRL                           0xB8
  75 #define VENC_OUTPUT_CONTROL                     0xC4
  76 #define VENC_OUTPUT_TEST                        0xC8
  77 #define VENC_DAC_B__DAC_C                       0xC8
  78
  79 struct venc_config {
  80         u32 f_control;
  81         u32 vidout_ctrl;
  82         u32 sync_ctrl;
  83         u32 llen;
  84         u32 flens;
  85         u32 hfltr_ctrl;
  86         u32 cc_carr_wss_carr;
  87         u32 c_phase;
  88         u32 gain_u;
  89         u32 gain_v;
  90         u32 gain_y;
  91         u32 black_level;
  92         u32 blank_level;
  93         u32 x_color;
  94         u32 m_control;
  95         u32 bstamp_wss_data;
  96         u32 s_carr;
  97         u32 line21;
  98         u32 ln_sel;
  99         u32 l21__wc_ctl;
 100         u32 htrigger_vtrigger;
 101         u32 savid__eavid;
 102         u32 flen__fal;
 103         u32 lal__phase_reset;
 104         u32 hs_int_start_stop_x;
 105         u32 hs_ext_start_stop_x;
 106         u32 vs_int_start_x;
 107         u32 vs_int_stop_x__vs_int_start_y;
 108         u32 vs_int_stop_y__vs_ext_start_x;
 109         u32 vs_ext_stop_x__vs_ext_start_y;
 110         u32 vs_ext_stop_y;
 111         u32 avid_start_stop_x;
 112         u32 avid_start_stop_y;
 113         u32 fid_int_start_x__fid_int_start_y;
 114         u32 fid_int_offset_y__fid_ext_start_x;
 115         u32 fid_ext_start_y__fid_ext_offset_y;
 116         u32 tvdetgp_int_start_stop_x;
 117         u32 tvdetgp_int_start_stop_y;
 118         u32 gen_ctrl;
 119 };
 120
 121 /* from TRM */
 122 static const struct venc_config venc_config_pal_trm = {
 123         .f_control                              = 0,
 124         .vidout_ctrl                            = 1,
 125         .sync_ctrl                              = 0x40,
 126         .llen                                   = 0x35F, /* 863 */
 127         .flens                                  = 0x270, /* 624 */
 128         .hfltr_ctrl                             = 0,
 129         .cc_carr_wss_carr                       = 0x2F7225ED,
 130         .c_phase                                = 0,
 131         .gain_u                                 = 0x111,
 132         .gain_v                                 = 0x181,
 133         .gain_y                                 = 0x140,
 134         .black_level                            = 0x3B,
 135         .blank_level                            = 0x3B,
 136         .x_color                                = 0x7,
 137         .m_control                              = 0x2,
 138         .bstamp_wss_data                        = 0x3F,
 139         .s_carr                                 = 0x2A098ACB,
 140         .line21                                 = 0,
 141         .ln_sel                                 = 0x01290015,
 142         .l21__wc_ctl                            = 0x0000F603,
 143         .htrigger_vtrigger                      = 0,
 144
 145         .savid__eavid                           = 0x06A70108,
 146         .flen__fal                              = 0x00180270,
 147         .lal__phase_reset                       = 0x00040135,
 148         .hs_int_start_stop_x                    = 0x00880358,
 149         .hs_ext_start_stop_x                    = 0x000F035F,
 150         .vs_int_start_x                         = 0x01A70000,
 151         .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
 152         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
 153         .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
 154         .vs_ext_stop_y                          = 0x00000025,
 155         .avid_start_stop_x                      = 0x03530083,
 156         .avid_start_stop_y                      = 0x026C002E,
 157         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 158         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 159         .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
 160
 161         .tvdetgp_int_start_stop_x               = 0x00140001,
 162         .tvdetgp_int_start_stop_y               = 0x00010001,
 163         .gen_ctrl                               = 0x00FF0000,
 164 };
 165
 166 /* from TRM */
 167 static const struct venc_config venc_config_ntsc_trm = {
 168         .f_control                              = 0,
 169         .vidout_ctrl                            = 1,
 170         .sync_ctrl                              = 0x8040,
 171         .llen                                   = 0x359,
 172         .flens                                  = 0x20C,
 173         .hfltr_ctrl                             = 0,
 174         .cc_carr_wss_carr                       = 0x043F2631,
 175         .c_phase                                = 0,
 176         .gain_u                                 = 0x102,
 177         .gain_v                                 = 0x16C,
 178         .gain_y                                 = 0x12F,
 179         .black_level                            = 0x43,
 180         .blank_level                            = 0x38,
 181         .x_color                                = 0x7,
 182         .m_control                              = 0x1,
 183         .bstamp_wss_data                        = 0x38,
 184         .s_carr                                 = 0x21F07C1F,
 185         .line21                                 = 0,
 186         .ln_sel                                 = 0x01310011,
 187         .l21__wc_ctl                            = 0x0000F003,
 188         .htrigger_vtrigger                      = 0,
 189
 190         .savid__eavid                           = 0x069300F4,
 191         .flen__fal                              = 0x0016020C,
 192         .lal__phase_reset                       = 0x00060107,
 193         .hs_int_start_stop_x                    = 0x008E0350,
 194         .hs_ext_start_stop_x                    = 0x000F0359,
 195         .vs_int_start_x                         = 0x01A00000,
 196         .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
 197         .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
 198         .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
 199         .vs_ext_stop_y                          = 0x00000006,
 200         .avid_start_stop_x                      = 0x03480078,
 201         .avid_start_stop_y                      = 0x02060024,
 202         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 203         .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
 204         .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
 205
 206         .tvdetgp_int_start_stop_x               = 0x00140001,
 207         .tvdetgp_int_start_stop_y               = 0x00010001,
 208         .gen_ctrl                               = 0x00F90000,
 209 };
 210
 211 static const struct venc_config venc_config_pal_bdghi = {
 212         .f_control                              = 0,
 213         .vidout_ctrl                            = 0,
 214         .sync_ctrl                              = 0,
 215         .hfltr_ctrl                             = 0,
 216         .x_color                                = 0,
 217         .line21                                 = 0,
 218         .ln_sel                                 = 21,
 219         .htrigger_vtrigger                      = 0,
 220         .tvdetgp_int_start_stop_x               = 0x00140001,
 221         .tvdetgp_int_start_stop_y               = 0x00010001,
 222         .gen_ctrl                               = 0x00FB0000,
 223
 224         .llen                                   = 864-1,
 225         .flens                                  = 625-1,
 226         .cc_carr_wss_carr                       = 0x2F7625ED,
 227         .c_phase                                = 0xDF,
 228         .gain_u                                 = 0x111,
 229         .gain_v                                 = 0x181,
 230         .gain_y                                 = 0x140,
 231         .black_level                            = 0x3e,
 232         .blank_level                            = 0x3e,
 233         .m_control                              = 0<<2 | 1<<1,
 234         .bstamp_wss_data                        = 0x42,
 235         .s_carr                                 = 0x2a098acb,
 236         .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
 237         .savid__eavid                           = 0x06A70108,
 238         .flen__fal                              = 23<<16 | 624<<0,
 239         .lal__phase_reset                       = 2<<17 | 310<<0,
 240         .hs_int_start_stop_x                    = 0x00920358,
 241         .hs_ext_start_stop_x                    = 0x000F035F,
 242         .vs_int_start_x                         = 0x1a7<<16,
 243         .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
 244         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
 245         .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
 246         .vs_ext_stop_y                          = 0x05,
 247         .avid_start_stop_x                      = 0x03530082,
 248         .avid_start_stop_y                      = 0x0270002E,
 249         .fid_int_start_x__fid_int_start_y       = 0x0005008A,
 250         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 251         .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
 252 };
 253
 254 enum venc_videomode {
 255         VENC_MODE_UNKNOWN,
 256         VENC_MODE_PAL,
 257         VENC_MODE_NTSC,
 258 };
 259
 260 static const struct drm_display_mode omap_dss_pal_mode = {
 261         .hdisplay       = 720,
 262         .hsync_start    = 732,
 263         .hsync_end      = 796,
 264         .htotal         = 864,
 265         .vdisplay       = 574,
 266         .vsync_start    = 579,
 267         .vsync_end      = 584,
 268         .vtotal         = 625,
 269         .clock          = 13500,
 270
 271         .flags          = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
 272                           DRM_MODE_FLAG_NVSYNC,
 273 };
 274
 275 static const struct drm_display_mode omap_dss_ntsc_mode = {
 276         .hdisplay       = 720,
 277         .hsync_start    = 736,
 278         .hsync_end      = 800,
 279         .htotal         = 858,
 280         .vdisplay       = 482,
 281         .vsync_start    = 488,
 282         .vsync_end      = 494,
 283         .vtotal         = 525,
 284         .clock          = 13500,
 285
 286         .flags          = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
 287                           DRM_MODE_FLAG_NVSYNC,
 288 };
 289
 290 struct venc_device {
 291         struct platform_device *pdev;
 292         void __iomem *base;
 293         struct regulator *vdda_dac_reg;
 294         struct dss_device *dss;
 295
 296         struct dss_debugfs_entry *debugfs;
 297
 298         struct clk      *tv_dac_clk;
 299
 300         const struct venc_config *config;
 301         enum omap_dss_venc_type type;
 302         bool invert_polarity;
 303         bool requires_tv_dac_clk;
 304
 305         struct omap_dss_device output;
 306         struct drm_bridge bridge;
 307 };
 308
 309 #define drm_bridge_to_venc(b) container_of(b, struct venc_device, bridge)
 310
 311 static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
 312 {
 313         __raw_writel(val, venc->base + idx);
 314 }
 315
 316 static inline u32 venc_read_reg(struct venc_device *venc, int idx)
 317 {
 318         u32 l = __raw_readl(venc->base + idx);
 319         return l;
 320 }
 321
 322 static void venc_write_config(struct venc_device *venc,
 323                               const struct venc_config *config)
 324 {
 325         DSSDBG("write venc conf\n");
 326
 327         venc_write_reg(venc, VENC_LLEN, config->llen);
 328         venc_write_reg(venc, VENC_FLENS, config->flens);
 329         venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
 330         venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
 331         venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
 332         venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
 333         venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
 334         venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
 335         venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
 336         venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
 337         venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
 338         venc_write_reg(venc, VENC_S_CARR, config->s_carr);
 339         venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
 340         venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
 341         venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
 342         venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
 343         venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
 344                        config->hs_int_start_stop_x);
 345         venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
 346                        config->hs_ext_start_stop_x);
 347         venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
 348         venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
 349                        config->vs_int_stop_x__vs_int_start_y);
 350         venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
 351                        config->vs_int_stop_y__vs_ext_start_x);
 352         venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
 353                        config->vs_ext_stop_x__vs_ext_start_y);
 354         venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
 355         venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
 356         venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
 357         venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
 358                        config->fid_int_start_x__fid_int_start_y);
 359         venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
 360                        config->fid_int_offset_y__fid_ext_start_x);
 361         venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
 362                        config->fid_ext_start_y__fid_ext_offset_y);
 363
 364         venc_write_reg(venc, VENC_DAC_B__DAC_C,
 365                        venc_read_reg(venc, VENC_DAC_B__DAC_C));
 366         venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
 367         venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
 368         venc_write_reg(venc, VENC_X_COLOR, config->x_color);
 369         venc_write_reg(venc, VENC_LINE21, config->line21);
 370         venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
 371         venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
 372         venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
 373                        config->tvdetgp_int_start_stop_x);
 374         venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
 375                        config->tvdetgp_int_start_stop_y);
 376         venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
 377         venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
 378         venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
 379 }
 380
 381 static void venc_reset(struct venc_device *venc)
 382 {
 383         int t = 1000;
 384
 385         venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
 386         while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
 387                 if (--t == 0) {
 388                         DSSERR("Failed to reset venc\n");
 389                         return;
 390                 }
 391         }
 392
 393 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
 394         /* the magical sleep that makes things work */
 395         /* XXX more info? What bug this circumvents? */
 396         msleep(20);
 397 #endif
 398 }
 399
 400 static int venc_runtime_get(struct venc_device *venc)
 401 {
 402         int r;
 403
 404         DSSDBG("venc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&venc->pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 static void venc_runtime_put(struct venc_device *venc)
 412 {
 413         int r;
 414
 415         DSSDBG("venc_runtime_put\n");
 416
 417         r = pm_runtime_put_sync(&venc->pdev->dev);
 418         WARN_ON(r < 0 && r != -ENOSYS);
 419 }
 420
 421 static int venc_power_on(struct venc_device *venc)
 422 {
 423         u32 l;
 424         int r;
 425
 426         r = venc_runtime_get(venc);
 427         if (r)
 428                 goto err0;
 429
 430         venc_reset(venc);
 431         venc_write_config(venc, venc->config);
 432
 433         dss_set_venc_output(venc->dss, venc->type);
 434         dss_set_dac_pwrdn_bgz(venc->dss, 1);
 435
 436         l = 0;
 437
 438         if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 439                 l |= 1 << 1;
 440         else /* S-Video */
 441                 l |= (1 << 0) | (1 << 2);
 442
 443         if (venc->invert_polarity == false)
 444                 l |= 1 << 3;
 445
 446         venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
 447
 448         r = regulator_enable(venc->vdda_dac_reg);
 449         if (r)
 450                 goto err1;
 451
 452         r = dss_mgr_enable(&venc->output);
 453         if (r)
 454                 goto err2;
 455
 456         return 0;
 457
 458 err2:
 459         regulator_disable(venc->vdda_dac_reg);
 460 err1:
 461         venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
 462         dss_set_dac_pwrdn_bgz(venc->dss, 0);
 463
 464         venc_runtime_put(venc);
 465 err0:
 466         return r;
 467 }
 468
 469 static void venc_power_off(struct venc_device *venc)
 470 {
 471         venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
 472         dss_set_dac_pwrdn_bgz(venc->dss, 0);
 473
 474         dss_mgr_disable(&venc->output);
 475
 476         regulator_disable(venc->vdda_dac_reg);
 477
 478         venc_runtime_put(venc);
 479 }
 480
 481 static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode)
 482 {
 483         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
 484                 return VENC_MODE_UNKNOWN;
 485
 486         if (mode->clock == omap_dss_pal_mode.clock &&
 487             mode->hdisplay == omap_dss_pal_mode.hdisplay &&
 488             mode->vdisplay == omap_dss_pal_mode.vdisplay)
 489                 return VENC_MODE_PAL;
 490
 491         if (mode->clock == omap_dss_ntsc_mode.clock &&
 492             mode->hdisplay == omap_dss_ntsc_mode.hdisplay &&
 493             mode->vdisplay == omap_dss_ntsc_mode.vdisplay)
 494                 return VENC_MODE_NTSC;
 495
 496         return VENC_MODE_UNKNOWN;
 497 }
 498
 499 static int venc_dump_regs(struct seq_file *s, void *p)
 500 {
 501         struct venc_device *venc = s->private;
 502
 503 #define DUMPREG(venc, r) \
 504         seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
 505
 506         if (venc_runtime_get(venc))
 507                 return 0;
 508
 509         DUMPREG(venc, VENC_F_CONTROL);
 510         DUMPREG(venc, VENC_VIDOUT_CTRL);
 511         DUMPREG(venc, VENC_SYNC_CTRL);
 512         DUMPREG(venc, VENC_LLEN);
 513         DUMPREG(venc, VENC_FLENS);
 514         DUMPREG(venc, VENC_HFLTR_CTRL);
 515         DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
 516         DUMPREG(venc, VENC_C_PHASE);
 517         DUMPREG(venc, VENC_GAIN_U);
 518         DUMPREG(venc, VENC_GAIN_V);
 519         DUMPREG(venc, VENC_GAIN_Y);
 520         DUMPREG(venc, VENC_BLACK_LEVEL);
 521         DUMPREG(venc, VENC_BLANK_LEVEL);
 522         DUMPREG(venc, VENC_X_COLOR);
 523         DUMPREG(venc, VENC_M_CONTROL);
 524         DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
 525         DUMPREG(venc, VENC_S_CARR);
 526         DUMPREG(venc, VENC_LINE21);
 527         DUMPREG(venc, VENC_LN_SEL);
 528         DUMPREG(venc, VENC_L21__WC_CTL);
 529         DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
 530         DUMPREG(venc, VENC_SAVID__EAVID);
 531         DUMPREG(venc, VENC_FLEN__FAL);
 532         DUMPREG(venc, VENC_LAL__PHASE_RESET);
 533         DUMPREG(venc, VENC_HS_INT_START_STOP_X);
 534         DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
 535         DUMPREG(venc, VENC_VS_INT_START_X);
 536         DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
 537         DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
 538         DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
 539         DUMPREG(venc, VENC_VS_EXT_STOP_Y);
 540         DUMPREG(venc, VENC_AVID_START_STOP_X);
 541         DUMPREG(venc, VENC_AVID_START_STOP_Y);
 542         DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
 543         DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
 544         DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
 545         DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
 546         DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
 547         DUMPREG(venc, VENC_GEN_CTRL);
 548         DUMPREG(venc, VENC_OUTPUT_CONTROL);
 549         DUMPREG(venc, VENC_OUTPUT_TEST);
 550
 551         venc_runtime_put(venc);
 552
 553 #undef DUMPREG
 554         return 0;
 555 }
 556
 557 static int venc_get_clocks(struct venc_device *venc)
 558 {
 559         struct clk *clk;
 560
 561         if (venc->requires_tv_dac_clk) {
 562                 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
 563                 if (IS_ERR(clk)) {
 564                         DSSERR("can't get tv_dac_clk\n");
 565                         return PTR_ERR(clk);
 566                 }
 567         } else {
 568                 clk = NULL;
 569         }
 570
 571         venc->tv_dac_clk = clk;
 572
 573         return 0;
 574 }
 575
 576 /* -----------------------------------------------------------------------------
 577  * DRM Bridge Operations
 578  */
 579
 580 static int venc_bridge_attach(struct drm_bridge *bridge,
 581                               enum drm_bridge_attach_flags flags)
 582 {
 583         struct venc_device *venc = drm_bridge_to_venc(bridge);
 584
 585         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
 586                 return -EINVAL;
 587
 588         return drm_bridge_attach(bridge->encoder, venc->output.next_bridge,
 589                                  bridge, flags);
 590 }
 591
 592 static enum drm_mode_status
 593 venc_bridge_mode_valid(struct drm_bridge *bridge,
 594                        const struct drm_display_mode *mode)
 595 {
 596         switch (venc_get_videomode(mode)) {
 597         case VENC_MODE_PAL:
 598         case VENC_MODE_NTSC:
 599                 return MODE_OK;
 600
 601         default:
 602                 return MODE_BAD;
 603         }
 604 }
 605
 606 static bool venc_bridge_mode_fixup(struct drm_bridge *bridge,
 607                                    const struct drm_display_mode *mode,
 608                                    struct drm_display_mode *adjusted_mode)
 609 {
 610         const struct drm_display_mode *venc_mode;
 611
 612         switch (venc_get_videomode(adjusted_mode)) {
 613         case VENC_MODE_PAL:
 614                 venc_mode = &omap_dss_pal_mode;
 615                 break;
 616
 617         case VENC_MODE_NTSC:
 618                 venc_mode = &omap_dss_ntsc_mode;
 619                 break;
 620
 621         default:
 622                 return false;
 623         }
 624
 625         drm_mode_copy(adjusted_mode, venc_mode);
 626         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 627         drm_mode_set_name(adjusted_mode);
 628
 629         return true;
 630 }
 631
 632 static void venc_bridge_mode_set(struct drm_bridge *bridge,
 633                                  const struct drm_display_mode *mode,
 634                                  const struct drm_display_mode *adjusted_mode)
 635 {
 636         struct venc_device *venc = drm_bridge_to_venc(bridge);
 637         enum venc_videomode venc_mode = venc_get_videomode(adjusted_mode);
 638
 639         switch (venc_mode) {
 640         default:
 641                 WARN_ON_ONCE(1);
 642                 /* Fall-through */
 643         case VENC_MODE_PAL:
 644                 venc->config = &venc_config_pal_trm;
 645                 break;
 646
 647         case VENC_MODE_NTSC:
 648                 venc->config = &venc_config_ntsc_trm;
 649                 break;
 650         }
 651
 652         dispc_set_tv_pclk(venc->dss->dispc, 13500000);
 653 }
 654
 655 static void venc_bridge_enable(struct drm_bridge *bridge)
 656 {
 657         struct venc_device *venc = drm_bridge_to_venc(bridge);
 658
 659         venc_power_on(venc);
 660 }
 661
 662 static void venc_bridge_disable(struct drm_bridge *bridge)
 663 {
 664         struct venc_device *venc = drm_bridge_to_venc(bridge);
 665
 666         venc_power_off(venc);
 667 }
 668
 669 static int venc_bridge_get_modes(struct drm_bridge *bridge,
 670                                  struct drm_connector *connector)
 671 {
 672         static const struct drm_display_mode *modes[] = {
 673                 &omap_dss_pal_mode,
 674                 &omap_dss_ntsc_mode,
 675         };
 676         unsigned int i;
 677
 678         for (i = 0; i < ARRAY_SIZE(modes); ++i) {
 679                 struct drm_display_mode *mode;
 680
 681                 mode = drm_mode_duplicate(connector->dev, modes[i]);
 682                 if (!mode)
 683                         return i;
 684
 685                 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 686                 drm_mode_set_name(mode);
 687                 drm_mode_probed_add(connector, mode);
 688         }
 689
 690         return ARRAY_SIZE(modes);
 691 }
 692
 693 static const struct drm_bridge_funcs venc_bridge_funcs = {
 694         .attach = venc_bridge_attach,
 695         .mode_valid = venc_bridge_mode_valid,
 696         .mode_fixup = venc_bridge_mode_fixup,
 697         .mode_set = venc_bridge_mode_set,
 698         .enable = venc_bridge_enable,
 699         .disable = venc_bridge_disable,
 700         .get_modes = venc_bridge_get_modes,
 701 };
 702
 703 static void venc_bridge_init(struct venc_device *venc)
 704 {
 705         venc->bridge.funcs = &venc_bridge_funcs;
 706         venc->bridge.of_node = venc->pdev->dev.of_node;
 707         venc->bridge.ops = DRM_BRIDGE_OP_MODES;
 708         venc->bridge.type = DRM_MODE_CONNECTOR_SVIDEO;
 709         venc->bridge.interlace_allowed = true;
 710
 711         drm_bridge_add(&venc->bridge);
 712 }
 713
 714 static void venc_bridge_cleanup(struct venc_device *venc)
 715 {
 716         drm_bridge_remove(&venc->bridge);
 717 }
 718
 719 /* -----------------------------------------------------------------------------
 720  * Component Bind & Unbind
 721  */
 722
 723 static int venc_bind(struct device *dev, struct device *master, void *data)
 724 {
 725         struct dss_device *dss = dss_get_device(master);
 726         struct venc_device *venc = dev_get_drvdata(dev);
 727         u8 rev_id;
 728         int r;
 729
 730         venc->dss = dss;
 731
 732         r = venc_runtime_get(venc);
 733         if (r)
 734                 return r;
 735
 736         rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
 737         dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
 738
 739         venc_runtime_put(venc);
 740
 741         venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
 742                                                 venc);
 743
 744         return 0;
 745 }
 746
 747 static void venc_unbind(struct device *dev, struct device *master, void *data)
 748 {
 749         struct venc_device *venc = dev_get_drvdata(dev);
 750
 751         dss_debugfs_remove_file(venc->debugfs);
 752 }
 753
 754 static const struct component_ops venc_component_ops = {
 755         .bind   = venc_bind,
 756         .unbind = venc_unbind,
 757 };
 758
 759 /* -----------------------------------------------------------------------------
 760  * Probe & Remove, Suspend & Resume
 761  */
 762
 763 static int venc_init_output(struct venc_device *venc)
 764 {
 765         struct omap_dss_device *out = &venc->output;
 766         int r;
 767
 768         venc_bridge_init(venc);
 769
 770         out->dev = &venc->pdev->dev;
 771         out->id = OMAP_DSS_OUTPUT_VENC;
 772         out->type = OMAP_DISPLAY_TYPE_VENC;
 773         out->name = "venc.0";
 774         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 775         out->owner = THIS_MODULE;
 776         out->of_port = 0;
 777         out->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
 778
 779         r = omapdss_device_init_output(out, &venc->bridge);
 780         if (r < 0) {
 781                 venc_bridge_cleanup(venc);
 782                 return r;
 783         }
 784
 785         omapdss_device_register(out);
 786
 787         return 0;
 788 }
 789
 790 static void venc_uninit_output(struct venc_device *venc)
 791 {
 792         omapdss_device_unregister(&venc->output);
 793         omapdss_device_cleanup_output(&venc->output);
 794
 795         venc_bridge_cleanup(venc);
 796 }
 797
 798 static int venc_probe_of(struct venc_device *venc)
 799 {
 800         struct device_node *node = venc->pdev->dev.of_node;
 801         struct device_node *ep;
 802         u32 channels;
 803         int r;
 804
 805         ep = of_graph_get_endpoint_by_regs(node, 0, 0);
 806         if (!ep)
 807                 return 0;
 808
 809         venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
 810
 811         r = of_property_read_u32(ep, "ti,channels", &channels);
 812         if (r) {
 813                 dev_err(&venc->pdev->dev,
 814                         "failed to read property 'ti,channels': %d\n", r);
 815                 goto err;
 816         }
 817
 818         switch (channels) {
 819         case 1:
 820                 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
 821                 break;
 822         case 2:
 823                 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
 824                 break;
 825         default:
 826                 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
 827                         channels);
 828                 r = -EINVAL;
 829                 goto err;
 830         }
 831
 832         of_node_put(ep);
 833
 834         return 0;
 835
 836 err:
 837         of_node_put(ep);
 838         return r;
 839 }
 840
 841 static const struct soc_device_attribute venc_soc_devices[] = {
 842         { .machine = "OMAP3[45]*" },
 843         { .machine = "AM35*" },
 844         { /* sentinel */ }
 845 };
 846
 847 static int venc_probe(struct platform_device *pdev)
 848 {
 849         struct venc_device *venc;
 850         struct resource *venc_mem;
 851         int r;
 852
 853         venc = kzalloc(sizeof(*venc), GFP_KERNEL);
 854         if (!venc)
 855                 return -ENOMEM;
 856
 857         venc->pdev = pdev;
 858
 859         platform_set_drvdata(pdev, venc);
 860
 861         /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
 862         if (soc_device_match(venc_soc_devices))
 863                 venc->requires_tv_dac_clk = true;
 864
 865         venc->config = &venc_config_pal_trm;
 866
 867         venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
 868         venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
 869         if (IS_ERR(venc->base)) {
 870                 r = PTR_ERR(venc->base);
 871                 goto err_free;
 872         }
 873
 874         venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
 875         if (IS_ERR(venc->vdda_dac_reg)) {
 876                 r = PTR_ERR(venc->vdda_dac_reg);
 877                 if (r != -EPROBE_DEFER)
 878                         DSSERR("can't get VDDA_DAC regulator\n");
 879                 goto err_free;
 880         }
 881
 882         r = venc_get_clocks(venc);
 883         if (r)
 884                 goto err_free;
 885
 886         r = venc_probe_of(venc);
 887         if (r)
 888                 goto err_free;
 889
 890         pm_runtime_enable(&pdev->dev);
 891
 892         r = venc_init_output(venc);
 893         if (r)
 894                 goto err_pm_disable;
 895
 896         r = component_add(&pdev->dev, &venc_component_ops);
 897         if (r)
 898                 goto err_uninit_output;
 899
 900         return 0;
 901
 902 err_uninit_output:
 903         venc_uninit_output(venc);
 904 err_pm_disable:
 905         pm_runtime_disable(&pdev->dev);
 906 err_free:
 907         kfree(venc);
 908         return r;
 909 }
 910
 911 static int venc_remove(struct platform_device *pdev)
 912 {
 913         struct venc_device *venc = platform_get_drvdata(pdev);
 914
 915         component_del(&pdev->dev, &venc_component_ops);
 916
 917         venc_uninit_output(venc);
 918
 919         pm_runtime_disable(&pdev->dev);
 920
 921         kfree(venc);
 922         return 0;
 923 }
 924
 925 static int venc_runtime_suspend(struct device *dev)
 926 {
 927         struct venc_device *venc = dev_get_drvdata(dev);
 928
 929         if (venc->tv_dac_clk)
 930                 clk_disable_unprepare(venc->tv_dac_clk);
 931
 932         return 0;
 933 }
 934
 935 static int venc_runtime_resume(struct device *dev)
 936 {
 937         struct venc_device *venc = dev_get_drvdata(dev);
 938
 939         if (venc->tv_dac_clk)
 940                 clk_prepare_enable(venc->tv_dac_clk);
 941
 942         return 0;
 943 }
 944
 945 static const struct dev_pm_ops venc_pm_ops = {
 946         .runtime_suspend = venc_runtime_suspend,
 947         .runtime_resume = venc_runtime_resume,
 948 };
 949
 950 static const struct of_device_id venc_of_match[] = {
 951         { .compatible = "ti,omap2-venc", },
 952         { .compatible = "ti,omap3-venc", },
 953         { .compatible = "ti,omap4-venc", },
 954         {},
 955 };
 956
 957 struct platform_driver omap_venchw_driver = {
 958         .probe          = venc_probe,
 959         .remove         = venc_remove,
 960         .driver         = {
 961                 .name   = "omapdss_venc",
 962                 .pm     = &venc_pm_ops,
 963                 .of_match_table = venc_of_match,
 964                 .suppress_bind_attrs = true,
 965         },
 966 };