drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  78
  79 static void intel_increase_pllclock(struct drm_device *dev,
  80                                     enum pipe pipe);
  81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  82
  83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  84                                 struct intel_crtc_config *pipe_config);
  85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  86                                    struct intel_crtc_config *pipe_config);
  87
  88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  89                           int x, int y, struct drm_framebuffer *old_fb);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc);
 103 static void chv_prepare_pll(struct intel_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6700000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, crtc, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 427                                                 int refclk)
 428 {
 429         struct drm_device *dev = crtc->dev;
 430         const intel_limit_t *limit;
 431
 432         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 433                 if (intel_is_dual_link_lvds(dev)) {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_dual_lvds;
 438                 } else {
 439                         if (refclk == 100000)
 440                                 limit = &intel_limits_ironlake_single_lvds_100m;
 441                         else
 442                                 limit = &intel_limits_ironlake_single_lvds;
 443                 }
 444         } else
 445                 limit = &intel_limits_ironlake_dac;
 446
 447         return limit;
 448 }
 449
 450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 451 {
 452         struct drm_device *dev = crtc->dev;
 453         const intel_limit_t *limit;
 454
 455         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 456                 if (intel_is_dual_link_lvds(dev))
 457                         limit = &intel_limits_g4x_dual_channel_lvds;
 458                 else
 459                         limit = &intel_limits_g4x_single_channel_lvds;
 460         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 461                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 462                 limit = &intel_limits_g4x_hdmi;
 463         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 464                 limit = &intel_limits_g4x_sdvo;
 465         } else /* The option is for other outputs */
 466                 limit = &intel_limits_i9xx_sdvo;
 467
 468         return limit;
 469 }
 470
 471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 472 {
 473         struct drm_device *dev = crtc->dev;
 474         const intel_limit_t *limit;
 475
 476         if (HAS_PCH_SPLIT(dev))
 477                 limit = intel_ironlake_limit(crtc, refclk);
 478         else if (IS_G4X(dev)) {
 479                 limit = intel_g4x_limit(crtc);
 480         } else if (IS_PINEVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 482                         limit = &intel_limits_pineview_lvds;
 483                 else
 484                         limit = &intel_limits_pineview_sdvo;
 485         } else if (IS_CHERRYVIEW(dev)) {
 486                 limit = &intel_limits_chv;
 487         } else if (IS_VALLEYVIEW(dev)) {
 488                 limit = &intel_limits_vlv;
 489         } else if (!IS_GEN2(dev)) {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i9xx_lvds;
 492                 else
 493                         limit = &intel_limits_i9xx_sdvo;
 494         } else {
 495                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 496                         limit = &intel_limits_i8xx_lvds;
 497                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 498                         limit = &intel_limits_i8xx_dvo;
 499                 else
 500                         limit = &intel_limits_i8xx_dac;
 501         }
 502         return limit;
 503 }
 504
 505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 506 static void pineview_clock(int refclk, intel_clock_t *clock)
 507 {
 508         clock->m = clock->m2 + 2;
 509         clock->p = clock->p1 * clock->p2;
 510         if (WARN_ON(clock->n == 0 || clock->p == 0))
 511                 return;
 512         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 513         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 514 }
 515
 516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 517 {
 518         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 519 }
 520
 521 static void i9xx_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = i9xx_dpll_compute_m(clock);
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static void chv_clock(int refclk, intel_clock_t *clock)
 532 {
 533         clock->m = clock->m1 * clock->m2;
 534         clock->p = clock->p1 * clock->p2;
 535         if (WARN_ON(clock->n == 0 || clock->p == 0))
 536                 return;
 537         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 538                         clock->n << 22);
 539         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 553                 INTELPllInvalid("n out of range\n");
 554         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 555                 INTELPllInvalid("p1 out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560
 561         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 562                 if (clock->m1 <= clock->m2)
 563                         INTELPllInvalid("m1 <= m2\n");
 564
 565         if (!IS_VALLEYVIEW(dev)) {
 566                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 567                         INTELPllInvalid("p out of range\n");
 568                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 569                         INTELPllInvalid("m out of range\n");
 570         }
 571
 572         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 573                 INTELPllInvalid("vco out of range\n");
 574         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 575          * connector, etc., rather than just a single range.
 576          */
 577         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 578                 INTELPllInvalid("dot out of range\n");
 579
 580         return true;
 581 }
 582
 583 static bool
 584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 585                     int target, int refclk, intel_clock_t *match_clock,
 586                     intel_clock_t *best_clock)
 587 {
 588         struct drm_device *dev = crtc->dev;
 589         intel_clock_t clock;
 590         int err = target;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 /*
 594                  * For LVDS just rely on its current settings for dual-channel.
 595                  * We haven't figured out how to reliably set up different
 596                  * single/dual channel state, if we even can.
 597                  */
 598                 if (intel_is_dual_link_lvds(dev))
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610
 611         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 612              clock.m1++) {
 613                 for (clock.m2 = limit->m2.min;
 614                      clock.m2 <= limit->m2.max; clock.m2++) {
 615                         if (clock.m2 >= clock.m1)
 616                                 break;
 617                         for (clock.n = limit->n.min;
 618                              clock.n <= limit->n.max; clock.n++) {
 619                                 for (clock.p1 = limit->p1.min;
 620                                         clock.p1 <= limit->p1.max; clock.p1++) {
 621                                         int this_err;
 622
 623                                         i9xx_clock(refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627                                         if (match_clock &&
 628                                             clock.p != match_clock->p)
 629                                                 continue;
 630
 631                                         this_err = abs(clock.dot - target);
 632                                         if (this_err < err) {
 633                                                 *best_clock = clock;
 634                                                 err = this_err;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640
 641         return (err != target);
 642 }
 643
 644 static bool
 645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 646                    int target, int refclk, intel_clock_t *match_clock,
 647                    intel_clock_t *best_clock)
 648 {
 649         struct drm_device *dev = crtc->dev;
 650         intel_clock_t clock;
 651         int err = target;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 /*
 655                  * For LVDS just rely on its current settings for dual-channel.
 656                  * We haven't figured out how to reliably set up different
 657                  * single/dual channel state, if we even can.
 658                  */
 659                 if (intel_is_dual_link_lvds(dev))
 660                         clock.p2 = limit->p2.p2_fast;
 661                 else
 662                         clock.p2 = limit->p2.p2_slow;
 663         } else {
 664                 if (target < limit->p2.dot_limit)
 665                         clock.p2 = limit->p2.p2_slow;
 666                 else
 667                         clock.p2 = limit->p2.p2_fast;
 668         }
 669
 670         memset(best_clock, 0, sizeof(*best_clock));
 671
 672         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 673              clock.m1++) {
 674                 for (clock.m2 = limit->m2.min;
 675                      clock.m2 <= limit->m2.max; clock.m2++) {
 676                         for (clock.n = limit->n.min;
 677                              clock.n <= limit->n.max; clock.n++) {
 678                                 for (clock.p1 = limit->p1.min;
 679                                         clock.p1 <= limit->p1.max; clock.p1++) {
 680                                         int this_err;
 681
 682                                         pineview_clock(refclk, &clock);
 683                                         if (!intel_PLL_is_valid(dev, limit,
 684                                                                 &clock))
 685                                                 continue;
 686                                         if (match_clock &&
 687                                             clock.p != match_clock->p)
 688                                                 continue;
 689
 690                                         this_err = abs(clock.dot - target);
 691                                         if (this_err < err) {
 692                                                 *best_clock = clock;
 693                                                 err = this_err;
 694                                         }
 695                                 }
 696                         }
 697                 }
 698         }
 699
 700         return (err != target);
 701 }
 702
 703 static bool
 704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                    int target, int refclk, intel_clock_t *match_clock,
 706                    intel_clock_t *best_clock)
 707 {
 708         struct drm_device *dev = crtc->dev;
 709         intel_clock_t clock;
 710         int max_n;
 711         bool found;
 712         /* approximately equals target * 0.00585 */
 713         int err_most = (target >> 8) + (target >> 9);
 714         found = false;
 715
 716         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requirement, prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirement, prefere larger m1,m2 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         i9xx_clock(refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745
 746                                         this_err = abs(clock.dot - target);
 747                                         if (this_err < err_most) {
 748                                                 *best_clock = clock;
 749                                                 err_most = this_err;
 750                                                 max_n = clock.n;
 751                                                 found = true;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757         return found;
 758 }
 759
 760 static bool
 761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                    int target, int refclk, intel_clock_t *match_clock,
 763                    intel_clock_t *best_clock)
 764 {
 765         struct drm_device *dev = crtc->dev;
 766         intel_clock_t clock;
 767         unsigned int bestppm = 1000000;
 768         /* min update 19.2 MHz */
 769         int max_n = min(limit->n.max, refclk / 19200);
 770         bool found = false;
 771
 772         target *= 5; /* fast clock */
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         /* based on hardware requirement, prefer smaller n to precision */
 777         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 778                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 779                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 780                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 781                                 clock.p = clock.p1 * clock.p2;
 782                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 783                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 784                                         unsigned int ppm, diff;
 785
 786                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 787                                                                      refclk * clock.m1);
 788
 789                                         vlv_clock(refclk, &clock);
 790
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794
 795                                         diff = abs(clock.dot - target);
 796                                         ppm = div_u64(1000000ULL * diff, target);
 797
 798                                         if (ppm < 100 && clock.p > best_clock->p) {
 799                                                 bestppm = 0;
 800                                                 *best_clock = clock;
 801                                                 found = true;
 802                                         }
 803
 804                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 805                                                 bestppm = ppm;
 806                                                 *best_clock = clock;
 807                                                 found = true;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813
 814         return found;
 815 }
 816
 817 static bool
 818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 819                    int target, int refclk, intel_clock_t *match_clock,
 820                    intel_clock_t *best_clock)
 821 {
 822         struct drm_device *dev = crtc->dev;
 823         intel_clock_t clock;
 824         uint64_t m2;
 825         int found = false;
 826
 827         memset(best_clock, 0, sizeof(*best_clock));
 828
 829         /*
 830          * Based on hardware doc, the n always set to 1, and m1 always
 831          * set to 2.  If requires to support 200Mhz refclk, we need to
 832          * revisit this because n may not 1 anymore.
 833          */
 834         clock.n = 1, clock.m1 = 2;
 835         target *= 5;    /* fast clock */
 836
 837         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 838                 for (clock.p2 = limit->p2.p2_fast;
 839                                 clock.p2 >= limit->p2.p2_slow;
 840                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 841
 842                         clock.p = clock.p1 * clock.p2;
 843
 844                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 845                                         clock.n) << 22, refclk * clock.m1);
 846
 847                         if (m2 > INT_MAX/clock.m1)
 848                                 continue;
 849
 850                         clock.m2 = m2;
 851
 852                         chv_clock(refclk, &clock);
 853
 854                         if (!intel_PLL_is_valid(dev, limit, &clock))
 855                                 continue;
 856
 857                         /* based on hardware requirement, prefer bigger p
 858                          */
 859                         if (clock.p > best_clock->p) {
 860                                 *best_clock = clock;
 861                                 found = true;
 862                         }
 863                 }
 864         }
 865
 866         return found;
 867 }
 868
 869 bool intel_crtc_active(struct drm_crtc *crtc)
 870 {
 871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 872
 873         /* Be paranoid as we can arrive here with only partial
 874          * state retrieved from the hardware during setup.
 875          *
 876          * We can ditch the adjusted_mode.crtc_clock check as soon
 877          * as Haswell has gained clock readout/fastboot support.
 878          *
 879          * We can ditch the crtc->primary->fb check as soon as we can
 880          * properly reconstruct framebuffers.
 881          */
 882         return intel_crtc->active && crtc->primary->fb &&
 883                 intel_crtc->config.adjusted_mode.crtc_clock;
 884 }
 885
 886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 887                                              enum pipe pipe)
 888 {
 889         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 891
 892         return intel_crtc->config.cpu_transcoder;
 893 }
 894
 895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 896 {
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 899
 900         frame = I915_READ(frame_reg);
 901
 902         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 903                 WARN(1, "vblank wait on pipe %c timed out\n",
 904                      pipe_name(pipe));
 905 }
 906
 907 /**
 908  * intel_wait_for_vblank - wait for vblank on a given pipe
 909  * @dev: drm device
 910  * @pipe: pipe to wait for
 911  *
 912  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 913  * mode setting code.
 914  */
 915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 916 {
 917         struct drm_i915_private *dev_priv = dev->dev_private;
 918         int pipestat_reg = PIPESTAT(pipe);
 919
 920         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 921                 g4x_wait_for_vblank(dev, pipe);
 922                 return;
 923         }
 924
 925         /* Clear existing vblank status. Note this will clear any other
 926          * sticky status fields as well.
 927          *
 928          * This races with i915_driver_irq_handler() with the result
 929          * that either function could miss a vblank event.  Here it is not
 930          * fatal, as we will either wait upon the next vblank interrupt or
 931          * timeout.  Generally speaking intel_wait_for_vblank() is only
 932          * called during modeset at which time the GPU should be idle and
 933          * should *not* be performing page flips and thus not waiting on
 934          * vblanks...
 935          * Currently, the result of us stealing a vblank from the irq
 936          * handler is that a single frame will be skipped during swapbuffers.
 937          */
 938         I915_WRITE(pipestat_reg,
 939                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 940
 941         /* Wait for vblank interrupt bit to set */
 942         if (wait_for(I915_READ(pipestat_reg) &
 943                      PIPE_VBLANK_INTERRUPT_STATUS,
 944                      50))
 945                 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
 946                               pipe_name(pipe));
 947 }
 948
 949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 reg = PIPEDSL(pipe);
 953         u32 line1, line2;
 954         u32 line_mask;
 955
 956         if (IS_GEN2(dev))
 957                 line_mask = DSL_LINEMASK_GEN2;
 958         else
 959                 line_mask = DSL_LINEMASK_GEN3;
 960
 961         line1 = I915_READ(reg) & line_mask;
 962         mdelay(5);
 963         line2 = I915_READ(reg) & line_mask;
 964
 965         return line1 == line2;
 966 }
 967
 968 /*
 969  * intel_wait_for_pipe_off - wait for pipe to turn off
 970  * @crtc: crtc whose pipe to wait for
 971  *
 972  * After disabling a pipe, we can't wait for vblank in the usual way,
 973  * spinning on the vblank interrupt status bit, since we won't actually
 974  * see an interrupt when the pipe is disabled.
 975  *
 976  * On Gen4 and above:
 977  *   wait for the pipe register state bit to turn off
 978  *
 979  * Otherwise:
 980  *   wait for the display line value to settle (it usually
 981  *   ends up stopping at the start of the next frame).
 982  *
 983  */
 984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 985 {
 986         struct drm_device *dev = crtc->base.dev;
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 989         enum pipe pipe = crtc->pipe;
 990
 991         if (INTEL_INFO(dev)->gen >= 4) {
 992                 int reg = PIPECONF(cpu_transcoder);
 993
 994                 /* Wait for the Pipe State to go off */
 995                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 996                              100))
 997                         WARN(1, "pipe_off wait timed out\n");
 998         } else {
 999                 /* Wait for the display line to settle */
1000                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001                         WARN(1, "pipe_off wait timed out\n");
1002         }
1003 }
1004
1005 /*
1006  * ibx_digital_port_connected - is the specified port connected?
1007  * @dev_priv: i915 private structure
1008  * @port: the port to test
1009  *
1010  * Returns true if @port is connected, false otherwise.
1011  */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013                                 struct intel_digital_port *port)
1014 {
1015         u32 bit;
1016
1017         if (HAS_PCH_IBX(dev_priv->dev)) {
1018                 switch (port->port) {
1019                 case PORT_B:
1020                         bit = SDE_PORTB_HOTPLUG;
1021                         break;
1022                 case PORT_C:
1023                         bit = SDE_PORTC_HOTPLUG;
1024                         break;
1025                 case PORT_D:
1026                         bit = SDE_PORTD_HOTPLUG;
1027                         break;
1028                 default:
1029                         return true;
1030                 }
1031         } else {
1032                 switch (port->port) {
1033                 case PORT_B:
1034                         bit = SDE_PORTB_HOTPLUG_CPT;
1035                         break;
1036                 case PORT_C:
1037                         bit = SDE_PORTC_HOTPLUG_CPT;
1038                         break;
1039                 case PORT_D:
1040                         bit = SDE_PORTD_HOTPLUG_CPT;
1041                         break;
1042                 default:
1043                         return true;
1044                 }
1045         }
1046
1047         return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057                 enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074         u32 val;
1075         bool cur_state;
1076
1077         mutex_lock(&dev_priv->dpio_lock);
1078         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079         mutex_unlock(&dev_priv->dpio_lock);
1080
1081         cur_state = val & DSI_PLL_VCO_EN;
1082         WARN(cur_state != state,
1083              "DSI PLL state assertion failure (expected %s, current %s)\n",
1084              state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094         if (crtc->config.shared_dpll < 0)
1095                 return NULL;
1096
1097         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102                         struct intel_shared_dpll *pll,
1103                         bool state)
1104 {
1105         bool cur_state;
1106         struct intel_dpll_hw_state hw_state;
1107
1108         if (WARN (!pll,
1109                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1110                 return;
1111
1112         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113         WARN(cur_state != state,
1114              "%s assertion failure (expected %s, current %s)\n",
1115              pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119                           enum pipe pipe, bool state)
1120 {
1121         int reg;
1122         u32 val;
1123         bool cur_state;
1124         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125                                                                       pipe);
1126
1127         if (HAS_DDI(dev_priv->dev)) {
1128                 /* DDI does not have a specific FDI_TX register */
1129                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132         } else {
1133                 reg = FDI_TX_CTL(pipe);
1134                 val = I915_READ(reg);
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139              state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_ENABLE);
1154         WARN(cur_state != state,
1155              "FDI RX state assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162                                       enum pipe pipe)
1163 {
1164         int reg;
1165         u32 val;
1166
1167         /* ILK FDI PLL is always enabled */
1168         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169                 return;
1170
1171         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172         if (HAS_DDI(dev_priv->dev))
1173                 return;
1174
1175         reg = FDI_TX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181                        enum pipe pipe, bool state)
1182 {
1183         int reg;
1184         u32 val;
1185         bool cur_state;
1186
1187         reg = FDI_RX_CTL(pipe);
1188         val = I915_READ(reg);
1189         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190         WARN(cur_state != state,
1191              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192              state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196                                   enum pipe pipe)
1197 {
1198         struct drm_device *dev = dev_priv->dev;
1199         int pp_reg;
1200         u32 val;
1201         enum pipe panel_pipe = PIPE_A;
1202         bool locked = true;
1203
1204         if (WARN_ON(HAS_DDI(dev)))
1205                 return;
1206
1207         if (HAS_PCH_SPLIT(dev)) {
1208                 u32 port_sel;
1209
1210                 pp_reg = PCH_PP_CONTROL;
1211                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215                         panel_pipe = PIPE_B;
1216                 /* XXX: else fix for eDP */
1217         } else if (IS_VALLEYVIEW(dev)) {
1218                 /* presumably write lock depends on pipe, not port select */
1219                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220                 panel_pipe = pipe;
1221         } else {
1222                 pp_reg = PP_CONTROL;
1223                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224                         panel_pipe = PIPE_B;
1225         }
1226
1227         val = I915_READ(pp_reg);
1228         if (!(val & PANEL_POWER_ON) ||
1229             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230                 locked = false;
1231
1232         WARN(panel_pipe == pipe && locked,
1233              "panel assertion failure, pipe %c regs locked\n",
1234              pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238                           enum pipe pipe, bool state)
1239 {
1240         struct drm_device *dev = dev_priv->dev;
1241         bool cur_state;
1242
1243         if (IS_845G(dev) || IS_I865G(dev))
1244                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245         else
1246                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248         WARN(cur_state != state,
1249              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256                  enum pipe pipe, bool state)
1257 {
1258         int reg;
1259         u32 val;
1260         bool cur_state;
1261         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262                                                                       pipe);
1263
1264         /* if we need the pipe quirk it must be always on */
1265         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267                 state = true;
1268
1269         if (!intel_display_power_enabled(dev_priv,
1270                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271                 cur_state = false;
1272         } else {
1273                 reg = PIPECONF(cpu_transcoder);
1274                 val = I915_READ(reg);
1275                 cur_state = !!(val & PIPECONF_ENABLE);
1276         }
1277
1278         WARN(cur_state != state,
1279              "pipe %c assertion failure (expected %s, current %s)\n",
1280              pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284                          enum plane plane, bool state)
1285 {
1286         int reg;
1287         u32 val;
1288         bool cur_state;
1289
1290         reg = DSPCNTR(plane);
1291         val = I915_READ(reg);
1292         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293         WARN(cur_state != state,
1294              "plane %c assertion failure (expected %s, current %s)\n",
1295              plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302                                    enum pipe pipe)
1303 {
1304         struct drm_device *dev = dev_priv->dev;
1305         int reg, i;
1306         u32 val;
1307         int cur_pipe;
1308
1309         /* Primary planes are fixed to pipes on gen4+ */
1310         if (INTEL_INFO(dev)->gen >= 4) {
1311                 reg = DSPCNTR(pipe);
1312                 val = I915_READ(reg);
1313                 WARN(val & DISPLAY_PLANE_ENABLE,
1314                      "plane %c assertion failure, should be disabled but not\n",
1315                      plane_name(pipe));
1316                 return;
1317         }
1318
1319         /* Need to check both planes against the pipe */
1320         for_each_pipe(dev_priv, i) {
1321                 reg = DSPCNTR(i);
1322                 val = I915_READ(reg);
1323                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324                         DISPPLANE_SEL_PIPE_SHIFT;
1325                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327                      plane_name(i), pipe_name(pipe));
1328         }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332                                     enum pipe pipe)
1333 {
1334         struct drm_device *dev = dev_priv->dev;
1335         int reg, sprite;
1336         u32 val;
1337
1338         if (IS_VALLEYVIEW(dev)) {
1339                 for_each_sprite(pipe, sprite) {
1340                         reg = SPCNTR(pipe, sprite);
1341                         val = I915_READ(reg);
1342                         WARN(val & SP_ENABLE,
1343                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                              sprite_name(pipe, sprite), pipe_name(pipe));
1345                 }
1346         } else if (INTEL_INFO(dev)->gen >= 7) {
1347                 reg = SPRCTL(pipe);
1348                 val = I915_READ(reg);
1349                 WARN(val & SPRITE_ENABLE,
1350                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351                      plane_name(pipe), pipe_name(pipe));
1352         } else if (INTEL_INFO(dev)->gen >= 5) {
1353                 reg = DVSCNTR(pipe);
1354                 val = I915_READ(reg);
1355                 WARN(val & DVS_ENABLE,
1356                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357                      plane_name(pipe), pipe_name(pipe));
1358         }
1359 }
1360
1361 static void assert_vblank_disabled(struct drm_crtc *crtc)
1362 {
1363         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1364                 drm_crtc_vblank_put(crtc);
1365 }
1366
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1368 {
1369         u32 val;
1370         bool enabled;
1371
1372         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1373
1374         val = I915_READ(PCH_DREF_CONTROL);
1375         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1376                             DREF_SUPERSPREAD_SOURCE_MASK));
1377         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1378 }
1379
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1381                                            enum pipe pipe)
1382 {
1383         int reg;
1384         u32 val;
1385         bool enabled;
1386
1387         reg = PCH_TRANSCONF(pipe);
1388         val = I915_READ(reg);
1389         enabled = !!(val & TRANS_ENABLE);
1390         WARN(enabled,
1391              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1392              pipe_name(pipe));
1393 }
1394
1395 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1396                             enum pipe pipe, u32 port_sel, u32 val)
1397 {
1398         if ((val & DP_PORT_EN) == 0)
1399                 return false;
1400
1401         if (HAS_PCH_CPT(dev_priv->dev)) {
1402                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1403                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1404                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1405                         return false;
1406         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1407                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1408                         return false;
1409         } else {
1410                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1411                         return false;
1412         }
1413         return true;
1414 }
1415
1416 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1417                               enum pipe pipe, u32 val)
1418 {
1419         if ((val & SDVO_ENABLE) == 0)
1420                 return false;
1421
1422         if (HAS_PCH_CPT(dev_priv->dev)) {
1423                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1424                         return false;
1425         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1426                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1427                         return false;
1428         } else {
1429                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1430                         return false;
1431         }
1432         return true;
1433 }
1434
1435 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1436                               enum pipe pipe, u32 val)
1437 {
1438         if ((val & LVDS_PORT_EN) == 0)
1439                 return false;
1440
1441         if (HAS_PCH_CPT(dev_priv->dev)) {
1442                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1443                         return false;
1444         } else {
1445                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1446                         return false;
1447         }
1448         return true;
1449 }
1450
1451 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1452                               enum pipe pipe, u32 val)
1453 {
1454         if ((val & ADPA_DAC_ENABLE) == 0)
1455                 return false;
1456         if (HAS_PCH_CPT(dev_priv->dev)) {
1457                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458                         return false;
1459         } else {
1460                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1467                                    enum pipe pipe, int reg, u32 port_sel)
1468 {
1469         u32 val = I915_READ(reg);
1470         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1471              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472              reg, pipe_name(pipe));
1473
1474         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1475              && (val & DP_PIPEB_SELECT),
1476              "IBX PCH dp port still using transcoder B\n");
1477 }
1478
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1480                                      enum pipe pipe, int reg)
1481 {
1482         u32 val = I915_READ(reg);
1483         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1484              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485              reg, pipe_name(pipe));
1486
1487         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1488              && (val & SDVO_PIPE_B_SELECT),
1489              "IBX PCH hdmi port still using transcoder B\n");
1490 }
1491
1492 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1493                                       enum pipe pipe)
1494 {
1495         int reg;
1496         u32 val;
1497
1498         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1499         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1500         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1501
1502         reg = PCH_ADPA;
1503         val = I915_READ(reg);
1504         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1505              "PCH VGA enabled on transcoder %c, should be disabled\n",
1506              pipe_name(pipe));
1507
1508         reg = PCH_LVDS;
1509         val = I915_READ(reg);
1510         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1511              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1512              pipe_name(pipe));
1513
1514         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1515         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1516         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1517 }
1518
1519 static void intel_init_dpio(struct drm_device *dev)
1520 {
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523         if (!IS_VALLEYVIEW(dev))
1524                 return;
1525
1526         /*
1527          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528          * CHV x1 PHY (DP/HDMI D)
1529          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1530          */
1531         if (IS_CHERRYVIEW(dev)) {
1532                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1533                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1534         } else {
1535                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1536         }
1537 }
1538
1539 static void vlv_enable_pll(struct intel_crtc *crtc)
1540 {
1541         struct drm_device *dev = crtc->base.dev;
1542         struct drm_i915_private *dev_priv = dev->dev_private;
1543         int reg = DPLL(crtc->pipe);
1544         u32 dpll = crtc->config.dpll_hw_state.dpll;
1545
1546         assert_pipe_disabled(dev_priv, crtc->pipe);
1547
1548         /* No really, not for ILK+ */
1549         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1550
1551         /* PLL is protected by panel, make sure we can write it */
1552         if (IS_MOBILE(dev_priv->dev))
1553                 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555         I915_WRITE(reg, dpll);
1556         POSTING_READ(reg);
1557         udelay(150);
1558
1559         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1560                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1561
1562         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1563         POSTING_READ(DPLL_MD(crtc->pipe));
1564
1565         /* We do this three times for luck */
1566         I915_WRITE(reg, dpll);
1567         POSTING_READ(reg);
1568         udelay(150); /* wait for warmup */
1569         I915_WRITE(reg, dpll);
1570         POSTING_READ(reg);
1571         udelay(150); /* wait for warmup */
1572         I915_WRITE(reg, dpll);
1573         POSTING_READ(reg);
1574         udelay(150); /* wait for warmup */
1575 }
1576
1577 static void chv_enable_pll(struct intel_crtc *crtc)
1578 {
1579         struct drm_device *dev = crtc->base.dev;
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         int pipe = crtc->pipe;
1582         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1583         u32 tmp;
1584
1585         assert_pipe_disabled(dev_priv, crtc->pipe);
1586
1587         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1588
1589         mutex_lock(&dev_priv->dpio_lock);
1590
1591         /* Enable back the 10bit clock to display controller */
1592         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1593         tmp |= DPIO_DCLKP_EN;
1594         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1595
1596         /*
1597          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1598          */
1599         udelay(1);
1600
1601         /* Enable PLL */
1602         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1603
1604         /* Check PLL is locked */
1605         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1606                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1607
1608         /* not sure when this should be written */
1609         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1610         POSTING_READ(DPLL_MD(pipe));
1611
1612         mutex_unlock(&dev_priv->dpio_lock);
1613 }
1614
1615 static void i9xx_enable_pll(struct intel_crtc *crtc)
1616 {
1617         struct drm_device *dev = crtc->base.dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         int reg = DPLL(crtc->pipe);
1620         u32 dpll = crtc->config.dpll_hw_state.dpll;
1621
1622         assert_pipe_disabled(dev_priv, crtc->pipe);
1623
1624         /* No really, not for ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1626
1627         /* PLL is protected by panel, make sure we can write it */
1628         if (IS_MOBILE(dev) && !IS_I830(dev))
1629                 assert_panel_unlocked(dev_priv, crtc->pipe);
1630
1631         I915_WRITE(reg, dpll);
1632
1633         /* Wait for the clocks to stabilize. */
1634         POSTING_READ(reg);
1635         udelay(150);
1636
1637         if (INTEL_INFO(dev)->gen >= 4) {
1638                 I915_WRITE(DPLL_MD(crtc->pipe),
1639                            crtc->config.dpll_hw_state.dpll_md);
1640         } else {
1641                 /* The pixel multiplier can only be updated once the
1642                  * DPLL is enabled and the clocks are stable.
1643                  *
1644                  * So write it again.
1645                  */
1646                 I915_WRITE(reg, dpll);
1647         }
1648
1649         /* We do this three times for luck */
1650         I915_WRITE(reg, dpll);
1651         POSTING_READ(reg);
1652         udelay(150); /* wait for warmup */
1653         I915_WRITE(reg, dpll);
1654         POSTING_READ(reg);
1655         udelay(150); /* wait for warmup */
1656         I915_WRITE(reg, dpll);
1657         POSTING_READ(reg);
1658         udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662  * i9xx_disable_pll - disable a PLL
1663  * @dev_priv: i915 private structure
1664  * @pipe: pipe PLL to disable
1665  *
1666  * Disable the PLL for @pipe, making sure the pipe is off first.
1667  *
1668  * Note!  This is for pre-ILK only.
1669  */
1670 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1671 {
1672         /* Don't disable pipe or pipe PLLs if needed */
1673         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1674             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1675                 return;
1676
1677         /* Make sure the pipe isn't still relying on us */
1678         assert_pipe_disabled(dev_priv, pipe);
1679
1680         I915_WRITE(DPLL(pipe), 0);
1681         POSTING_READ(DPLL(pipe));
1682 }
1683
1684 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1685 {
1686         u32 val = 0;
1687
1688         /* Make sure the pipe isn't still relying on us */
1689         assert_pipe_disabled(dev_priv, pipe);
1690
1691         /*
1692          * Leave integrated clock source and reference clock enabled for pipe B.
1693          * The latter is needed for VGA hotplug / manual detection.
1694          */
1695         if (pipe == PIPE_B)
1696                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1697         I915_WRITE(DPLL(pipe), val);
1698         POSTING_READ(DPLL(pipe));
1699
1700 }
1701
1702 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1703 {
1704         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1705         u32 val;
1706
1707         /* Make sure the pipe isn't still relying on us */
1708         assert_pipe_disabled(dev_priv, pipe);
1709
1710         /* Set PLL en = 0 */
1711         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1712         if (pipe != PIPE_A)
1713                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1714         I915_WRITE(DPLL(pipe), val);
1715         POSTING_READ(DPLL(pipe));
1716
1717         mutex_lock(&dev_priv->dpio_lock);
1718
1719         /* Disable 10bit clock to display controller */
1720         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1721         val &= ~DPIO_DCLKP_EN;
1722         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1723
1724         /* disable left/right clock distribution */
1725         if (pipe != PIPE_B) {
1726                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1727                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1728                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1729         } else {
1730                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1731                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1732                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1733         }
1734
1735         mutex_unlock(&dev_priv->dpio_lock);
1736 }
1737
1738 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1739                 struct intel_digital_port *dport)
1740 {
1741         u32 port_mask;
1742         int dpll_reg;
1743
1744         switch (dport->port) {
1745         case PORT_B:
1746                 port_mask = DPLL_PORTB_READY_MASK;
1747                 dpll_reg = DPLL(0);
1748                 break;
1749         case PORT_C:
1750                 port_mask = DPLL_PORTC_READY_MASK;
1751                 dpll_reg = DPLL(0);
1752                 break;
1753         case PORT_D:
1754                 port_mask = DPLL_PORTD_READY_MASK;
1755                 dpll_reg = DPIO_PHY_STATUS;
1756                 break;
1757         default:
1758                 BUG();
1759         }
1760
1761         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1762                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1763                      port_name(dport->port), I915_READ(dpll_reg));
1764 }
1765
1766 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1767 {
1768         struct drm_device *dev = crtc->base.dev;
1769         struct drm_i915_private *dev_priv = dev->dev_private;
1770         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1771
1772         if (WARN_ON(pll == NULL))
1773                 return;
1774
1775         WARN_ON(!pll->refcount);
1776         if (pll->active == 0) {
1777                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1778                 WARN_ON(pll->on);
1779                 assert_shared_dpll_disabled(dev_priv, pll);
1780
1781                 pll->mode_set(dev_priv, pll);
1782         }
1783 }
1784
1785 /**
1786  * intel_enable_shared_dpll - enable PCH PLL
1787  * @dev_priv: i915 private structure
1788  * @pipe: pipe PLL to enable
1789  *
1790  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1791  * drives the transcoder clock.
1792  */
1793 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1794 {
1795         struct drm_device *dev = crtc->base.dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1798
1799         if (WARN_ON(pll == NULL))
1800                 return;
1801
1802         if (WARN_ON(pll->refcount == 0))
1803                 return;
1804
1805         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1806                       pll->name, pll->active, pll->on,
1807                       crtc->base.base.id);
1808
1809         if (pll->active++) {
1810                 WARN_ON(!pll->on);
1811                 assert_shared_dpll_enabled(dev_priv, pll);
1812                 return;
1813         }
1814         WARN_ON(pll->on);
1815
1816         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1817
1818         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1819         pll->enable(dev_priv, pll);
1820         pll->on = true;
1821 }
1822
1823 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1824 {
1825         struct drm_device *dev = crtc->base.dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1828
1829         /* PCH only available on ILK+ */
1830         BUG_ON(INTEL_INFO(dev)->gen < 5);
1831         if (WARN_ON(pll == NULL))
1832                return;
1833
1834         if (WARN_ON(pll->refcount == 0))
1835                 return;
1836
1837         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1838                       pll->name, pll->active, pll->on,
1839                       crtc->base.base.id);
1840
1841         if (WARN_ON(pll->active == 0)) {
1842                 assert_shared_dpll_disabled(dev_priv, pll);
1843                 return;
1844         }
1845
1846         assert_shared_dpll_enabled(dev_priv, pll);
1847         WARN_ON(!pll->on);
1848         if (--pll->active)
1849                 return;
1850
1851         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1852         pll->disable(dev_priv, pll);
1853         pll->on = false;
1854
1855         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1856 }
1857
1858 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1859                                            enum pipe pipe)
1860 {
1861         struct drm_device *dev = dev_priv->dev;
1862         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1864         uint32_t reg, val, pipeconf_val;
1865
1866         /* PCH only available on ILK+ */
1867         BUG_ON(!HAS_PCH_SPLIT(dev));
1868
1869         /* Make sure PCH DPLL is enabled */
1870         assert_shared_dpll_enabled(dev_priv,
1871                                    intel_crtc_to_shared_dpll(intel_crtc));
1872
1873         /* FDI must be feeding us bits for PCH ports */
1874         assert_fdi_tx_enabled(dev_priv, pipe);
1875         assert_fdi_rx_enabled(dev_priv, pipe);
1876
1877         if (HAS_PCH_CPT(dev)) {
1878                 /* Workaround: Set the timing override bit before enabling the
1879                  * pch transcoder. */
1880                 reg = TRANS_CHICKEN2(pipe);
1881                 val = I915_READ(reg);
1882                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1883                 I915_WRITE(reg, val);
1884         }
1885
1886         reg = PCH_TRANSCONF(pipe);
1887         val = I915_READ(reg);
1888         pipeconf_val = I915_READ(PIPECONF(pipe));
1889
1890         if (HAS_PCH_IBX(dev_priv->dev)) {
1891                 /*
1892                  * make the BPC in transcoder be consistent with
1893                  * that in pipeconf reg.
1894                  */
1895                 val &= ~PIPECONF_BPC_MASK;
1896                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1897         }
1898
1899         val &= ~TRANS_INTERLACE_MASK;
1900         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1901                 if (HAS_PCH_IBX(dev_priv->dev) &&
1902                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1903                         val |= TRANS_LEGACY_INTERLACED_ILK;
1904                 else
1905                         val |= TRANS_INTERLACED;
1906         else
1907                 val |= TRANS_PROGRESSIVE;
1908
1909         I915_WRITE(reg, val | TRANS_ENABLE);
1910         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1911                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1912 }
1913
1914 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1915                                       enum transcoder cpu_transcoder)
1916 {
1917         u32 val, pipeconf_val;
1918
1919         /* PCH only available on ILK+ */
1920         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1921
1922         /* FDI must be feeding us bits for PCH ports */
1923         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1924         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1925
1926         /* Workaround: set timing override bit. */
1927         val = I915_READ(_TRANSA_CHICKEN2);
1928         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1929         I915_WRITE(_TRANSA_CHICKEN2, val);
1930
1931         val = TRANS_ENABLE;
1932         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1933
1934         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1935             PIPECONF_INTERLACED_ILK)
1936                 val |= TRANS_INTERLACED;
1937         else
1938                 val |= TRANS_PROGRESSIVE;
1939
1940         I915_WRITE(LPT_TRANSCONF, val);
1941         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1942                 DRM_ERROR("Failed to enable PCH transcoder\n");
1943 }
1944
1945 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1946                                             enum pipe pipe)
1947 {
1948         struct drm_device *dev = dev_priv->dev;
1949         uint32_t reg, val;
1950
1951         /* FDI relies on the transcoder */
1952         assert_fdi_tx_disabled(dev_priv, pipe);
1953         assert_fdi_rx_disabled(dev_priv, pipe);
1954
1955         /* Ports must be off as well */
1956         assert_pch_ports_disabled(dev_priv, pipe);
1957
1958         reg = PCH_TRANSCONF(pipe);
1959         val = I915_READ(reg);
1960         val &= ~TRANS_ENABLE;
1961         I915_WRITE(reg, val);
1962         /* wait for PCH transcoder off, transcoder state */
1963         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1964                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1965
1966         if (!HAS_PCH_IBX(dev)) {
1967                 /* Workaround: Clear the timing override chicken bit again. */
1968                 reg = TRANS_CHICKEN2(pipe);
1969                 val = I915_READ(reg);
1970                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1971                 I915_WRITE(reg, val);
1972         }
1973 }
1974
1975 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1976 {
1977         u32 val;
1978
1979         val = I915_READ(LPT_TRANSCONF);
1980         val &= ~TRANS_ENABLE;
1981         I915_WRITE(LPT_TRANSCONF, val);
1982         /* wait for PCH transcoder off, transcoder state */
1983         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1984                 DRM_ERROR("Failed to disable PCH transcoder\n");
1985
1986         /* Workaround: clear timing override bit. */
1987         val = I915_READ(_TRANSA_CHICKEN2);
1988         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1989         I915_WRITE(_TRANSA_CHICKEN2, val);
1990 }
1991
1992 /**
1993  * intel_enable_pipe - enable a pipe, asserting requirements
1994  * @crtc: crtc responsible for the pipe
1995  *
1996  * Enable @crtc's pipe, making sure that various hardware specific requirements
1997  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1998  */
1999 static void intel_enable_pipe(struct intel_crtc *crtc)
2000 {
2001         struct drm_device *dev = crtc->base.dev;
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003         enum pipe pipe = crtc->pipe;
2004         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2005                                                                       pipe);
2006         enum pipe pch_transcoder;
2007         int reg;
2008         u32 val;
2009
2010         assert_planes_disabled(dev_priv, pipe);
2011         assert_cursor_disabled(dev_priv, pipe);
2012         assert_sprites_disabled(dev_priv, pipe);
2013
2014         if (HAS_PCH_LPT(dev_priv->dev))
2015                 pch_transcoder = TRANSCODER_A;
2016         else
2017                 pch_transcoder = pipe;
2018
2019         /*
2020          * A pipe without a PLL won't actually be able to drive bits from
2021          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2022          * need the check.
2023          */
2024         if (!HAS_PCH_SPLIT(dev_priv->dev))
2025                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2026                         assert_dsi_pll_enabled(dev_priv);
2027                 else
2028                         assert_pll_enabled(dev_priv, pipe);
2029         else {
2030                 if (crtc->config.has_pch_encoder) {
2031                         /* if driving the PCH, we need FDI enabled */
2032                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2033                         assert_fdi_tx_pll_enabled(dev_priv,
2034                                                   (enum pipe) cpu_transcoder);
2035                 }
2036                 /* FIXME: assert CPU port conditions for SNB+ */
2037         }
2038
2039         reg = PIPECONF(cpu_transcoder);
2040         val = I915_READ(reg);
2041         if (val & PIPECONF_ENABLE) {
2042                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2043                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2044                 return;
2045         }
2046
2047         I915_WRITE(reg, val | PIPECONF_ENABLE);
2048         POSTING_READ(reg);
2049 }
2050
2051 /**
2052  * intel_disable_pipe - disable a pipe, asserting requirements
2053  * @crtc: crtc whose pipes is to be disabled
2054  *
2055  * Disable the pipe of @crtc, making sure that various hardware
2056  * specific requirements are met, if applicable, e.g. plane
2057  * disabled, panel fitter off, etc.
2058  *
2059  * Will wait until the pipe has shut down before returning.
2060  */
2061 static void intel_disable_pipe(struct intel_crtc *crtc)
2062 {
2063         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2064         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2065         enum pipe pipe = crtc->pipe;
2066         int reg;
2067         u32 val;
2068
2069         /*
2070          * Make sure planes won't keep trying to pump pixels to us,
2071          * or we might hang the display.
2072          */
2073         assert_planes_disabled(dev_priv, pipe);
2074         assert_cursor_disabled(dev_priv, pipe);
2075         assert_sprites_disabled(dev_priv, pipe);
2076
2077         reg = PIPECONF(cpu_transcoder);
2078         val = I915_READ(reg);
2079         if ((val & PIPECONF_ENABLE) == 0)
2080                 return;
2081
2082         /*
2083          * Double wide has implications for planes
2084          * so best keep it disabled when not needed.
2085          */
2086         if (crtc->config.double_wide)
2087                 val &= ~PIPECONF_DOUBLE_WIDE;
2088
2089         /* Don't disable pipe or pipe PLLs if needed */
2090         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2091             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2092                 val &= ~PIPECONF_ENABLE;
2093
2094         I915_WRITE(reg, val);
2095         if ((val & PIPECONF_ENABLE) == 0)
2096                 intel_wait_for_pipe_off(crtc);
2097 }
2098
2099 /*
2100  * Plane regs are double buffered, going from enabled->disabled needs a
2101  * trigger in order to latch.  The display address reg provides this.
2102  */
2103 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2104                                enum plane plane)
2105 {
2106         struct drm_device *dev = dev_priv->dev;
2107         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2108
2109         I915_WRITE(reg, I915_READ(reg));
2110         POSTING_READ(reg);
2111 }
2112
2113 /**
2114  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2115  * @plane:  plane to be enabled
2116  * @crtc: crtc for the plane
2117  *
2118  * Enable @plane on @crtc, making sure that the pipe is running first.
2119  */
2120 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2121                                           struct drm_crtc *crtc)
2122 {
2123         struct drm_device *dev = plane->dev;
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126
2127         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2129
2130         if (intel_crtc->primary_enabled)
2131                 return;
2132
2133         intel_crtc->primary_enabled = true;
2134
2135         dev_priv->display.update_primary_plane(crtc, plane->fb,
2136                                                crtc->x, crtc->y);
2137
2138         /*
2139          * BDW signals flip done immediately if the plane
2140          * is disabled, even if the plane enable is already
2141          * armed to occur at the next vblank :(
2142          */
2143         if (IS_BROADWELL(dev))
2144                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2145 }
2146
2147 /**
2148  * intel_disable_primary_hw_plane - disable the primary hardware plane
2149  * @plane: plane to be disabled
2150  * @crtc: crtc for the plane
2151  *
2152  * Disable @plane on @crtc, making sure that the pipe is running first.
2153  */
2154 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2155                                            struct drm_crtc *crtc)
2156 {
2157         struct drm_device *dev = plane->dev;
2158         struct drm_i915_private *dev_priv = dev->dev_private;
2159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160
2161         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2162
2163         if (!intel_crtc->primary_enabled)
2164                 return;
2165
2166         intel_crtc->primary_enabled = false;
2167
2168         dev_priv->display.update_primary_plane(crtc, plane->fb,
2169                                                crtc->x, crtc->y);
2170 }
2171
2172 static bool need_vtd_wa(struct drm_device *dev)
2173 {
2174 #ifdef CONFIG_INTEL_IOMMU
2175         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2176                 return true;
2177 #endif
2178         return false;
2179 }
2180
2181 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2182 {
2183         int tile_height;
2184
2185         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2186         return ALIGN(height, tile_height);
2187 }
2188
2189 int
2190 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2191                            struct drm_i915_gem_object *obj,
2192                            struct intel_engine_cs *pipelined)
2193 {
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         u32 alignment;
2196         int ret;
2197
2198         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2199
2200         switch (obj->tiling_mode) {
2201         case I915_TILING_NONE:
2202                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2203                         alignment = 128 * 1024;
2204                 else if (INTEL_INFO(dev)->gen >= 4)
2205                         alignment = 4 * 1024;
2206                 else
2207                         alignment = 64 * 1024;
2208                 break;
2209         case I915_TILING_X:
2210                 /* pin() will align the object as required by fence */
2211                 alignment = 0;
2212                 break;
2213         case I915_TILING_Y:
2214                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2215                 return -EINVAL;
2216         default:
2217                 BUG();
2218         }
2219
2220         /* Note that the w/a also requires 64 PTE of padding following the
2221          * bo. We currently fill all unused PTE with the shadow page and so
2222          * we should always have valid PTE following the scanout preventing
2223          * the VT-d warning.
2224          */
2225         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2226                 alignment = 256 * 1024;
2227
2228         /*
2229          * Global gtt pte registers are special registers which actually forward
2230          * writes to a chunk of system memory. Which means that there is no risk
2231          * that the register values disappear as soon as we call
2232          * intel_runtime_pm_put(), so it is correct to wrap only the
2233          * pin/unpin/fence and not more.
2234          */
2235         intel_runtime_pm_get(dev_priv);
2236
2237         dev_priv->mm.interruptible = false;
2238         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2239         if (ret)
2240                 goto err_interruptible;
2241
2242         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2243          * fence, whereas 965+ only requires a fence if using
2244          * framebuffer compression.  For simplicity, we always install
2245          * a fence as the cost is not that onerous.
2246          */
2247         ret = i915_gem_object_get_fence(obj);
2248         if (ret)
2249                 goto err_unpin;
2250
2251         i915_gem_object_pin_fence(obj);
2252
2253         dev_priv->mm.interruptible = true;
2254         intel_runtime_pm_put(dev_priv);
2255         return 0;
2256
2257 err_unpin:
2258         i915_gem_object_unpin_from_display_plane(obj);
2259 err_interruptible:
2260         dev_priv->mm.interruptible = true;
2261         intel_runtime_pm_put(dev_priv);
2262         return ret;
2263 }
2264
2265 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2266 {
2267         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2268
2269         i915_gem_object_unpin_fence(obj);
2270         i915_gem_object_unpin_from_display_plane(obj);
2271 }
2272
2273 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2274  * is assumed to be a power-of-two. */
2275 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2276                                              unsigned int tiling_mode,
2277                                              unsigned int cpp,
2278                                              unsigned int pitch)
2279 {
2280         if (tiling_mode != I915_TILING_NONE) {
2281                 unsigned int tile_rows, tiles;
2282
2283                 tile_rows = *y / 8;
2284                 *y %= 8;
2285
2286                 tiles = *x / (512/cpp);
2287                 *x %= 512/cpp;
2288
2289                 return tile_rows * pitch * 8 + tiles * 4096;
2290         } else {
2291                 unsigned int offset;
2292
2293                 offset = *y * pitch + *x * cpp;
2294                 *y = 0;
2295                 *x = (offset & 4095) / cpp;
2296                 return offset & -4096;
2297         }
2298 }
2299
2300 int intel_format_to_fourcc(int format)
2301 {
2302         switch (format) {
2303         case DISPPLANE_8BPP:
2304                 return DRM_FORMAT_C8;
2305         case DISPPLANE_BGRX555:
2306                 return DRM_FORMAT_XRGB1555;
2307         case DISPPLANE_BGRX565:
2308                 return DRM_FORMAT_RGB565;
2309         default:
2310         case DISPPLANE_BGRX888:
2311                 return DRM_FORMAT_XRGB8888;
2312         case DISPPLANE_RGBX888:
2313                 return DRM_FORMAT_XBGR8888;
2314         case DISPPLANE_BGRX101010:
2315                 return DRM_FORMAT_XRGB2101010;
2316         case DISPPLANE_RGBX101010:
2317                 return DRM_FORMAT_XBGR2101010;
2318         }
2319 }
2320
2321 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2322                                   struct intel_plane_config *plane_config)
2323 {
2324         struct drm_device *dev = crtc->base.dev;
2325         struct drm_i915_gem_object *obj = NULL;
2326         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2327         u32 base = plane_config->base;
2328
2329         if (plane_config->size == 0)
2330                 return false;
2331
2332         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2333                                                              plane_config->size);
2334         if (!obj)
2335                 return false;
2336
2337         if (plane_config->tiled) {
2338                 obj->tiling_mode = I915_TILING_X;
2339                 obj->stride = crtc->base.primary->fb->pitches[0];
2340         }
2341
2342         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2343         mode_cmd.width = crtc->base.primary->fb->width;
2344         mode_cmd.height = crtc->base.primary->fb->height;
2345         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2346
2347         mutex_lock(&dev->struct_mutex);
2348
2349         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2350                                    &mode_cmd, obj)) {
2351                 DRM_DEBUG_KMS("intel fb init failed\n");
2352                 goto out_unref_obj;
2353         }
2354
2355         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2356         mutex_unlock(&dev->struct_mutex);
2357
2358         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2359         return true;
2360
2361 out_unref_obj:
2362         drm_gem_object_unreference(&obj->base);
2363         mutex_unlock(&dev->struct_mutex);
2364         return false;
2365 }
2366
2367 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2368                                  struct intel_plane_config *plane_config)
2369 {
2370         struct drm_device *dev = intel_crtc->base.dev;
2371         struct drm_crtc *c;
2372         struct intel_crtc *i;
2373         struct drm_i915_gem_object *obj;
2374
2375         if (!intel_crtc->base.primary->fb)
2376                 return;
2377
2378         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2379                 return;
2380
2381         kfree(intel_crtc->base.primary->fb);
2382         intel_crtc->base.primary->fb = NULL;
2383
2384         /*
2385          * Failed to alloc the obj, check to see if we should share
2386          * an fb with another CRTC instead
2387          */
2388         for_each_crtc(dev, c) {
2389                 i = to_intel_crtc(c);
2390
2391                 if (c == &intel_crtc->base)
2392                         continue;
2393
2394                 if (!i->active)
2395                         continue;
2396
2397                 obj = intel_fb_obj(c->primary->fb);
2398                 if (obj == NULL)
2399                         continue;
2400
2401                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2402                         drm_framebuffer_reference(c->primary->fb);
2403                         intel_crtc->base.primary->fb = c->primary->fb;
2404                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2405                         break;
2406                 }
2407         }
2408 }
2409
2410 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2411                                       struct drm_framebuffer *fb,
2412                                       int x, int y)
2413 {
2414         struct drm_device *dev = crtc->dev;
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2417         struct drm_i915_gem_object *obj;
2418         int plane = intel_crtc->plane;
2419         unsigned long linear_offset;
2420         u32 dspcntr;
2421         u32 reg = DSPCNTR(plane);
2422         int pixel_size;
2423
2424         if (!intel_crtc->primary_enabled) {
2425                 I915_WRITE(reg, 0);
2426                 if (INTEL_INFO(dev)->gen >= 4)
2427                         I915_WRITE(DSPSURF(plane), 0);
2428                 else
2429                         I915_WRITE(DSPADDR(plane), 0);
2430                 POSTING_READ(reg);
2431                 return;
2432         }
2433
2434         obj = intel_fb_obj(fb);
2435         if (WARN_ON(obj == NULL))
2436                 return;
2437
2438         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2439
2440         dspcntr = DISPPLANE_GAMMA_ENABLE;
2441
2442         dspcntr |= DISPLAY_PLANE_ENABLE;
2443
2444         if (INTEL_INFO(dev)->gen < 4) {
2445                 if (intel_crtc->pipe == PIPE_B)
2446                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2447
2448                 /* pipesrc and dspsize control the size that is scaled from,
2449                  * which should always be the user's requested size.
2450                  */
2451                 I915_WRITE(DSPSIZE(plane),
2452                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2453                            (intel_crtc->config.pipe_src_w - 1));
2454                 I915_WRITE(DSPPOS(plane), 0);
2455         }
2456
2457         switch (fb->pixel_format) {
2458         case DRM_FORMAT_C8:
2459                 dspcntr |= DISPPLANE_8BPP;
2460                 break;
2461         case DRM_FORMAT_XRGB1555:
2462         case DRM_FORMAT_ARGB1555:
2463                 dspcntr |= DISPPLANE_BGRX555;
2464                 break;
2465         case DRM_FORMAT_RGB565:
2466                 dspcntr |= DISPPLANE_BGRX565;
2467                 break;
2468         case DRM_FORMAT_XRGB8888:
2469         case DRM_FORMAT_ARGB8888:
2470                 dspcntr |= DISPPLANE_BGRX888;
2471                 break;
2472         case DRM_FORMAT_XBGR8888:
2473         case DRM_FORMAT_ABGR8888:
2474                 dspcntr |= DISPPLANE_RGBX888;
2475                 break;
2476         case DRM_FORMAT_XRGB2101010:
2477         case DRM_FORMAT_ARGB2101010:
2478                 dspcntr |= DISPPLANE_BGRX101010;
2479                 break;
2480         case DRM_FORMAT_XBGR2101010:
2481         case DRM_FORMAT_ABGR2101010:
2482                 dspcntr |= DISPPLANE_RGBX101010;
2483                 break;
2484         default:
2485                 BUG();
2486         }
2487
2488         if (INTEL_INFO(dev)->gen >= 4 &&
2489             obj->tiling_mode != I915_TILING_NONE)
2490                 dspcntr |= DISPPLANE_TILED;
2491
2492         if (IS_G4X(dev))
2493                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2494
2495         linear_offset = y * fb->pitches[0] + x * pixel_size;
2496
2497         if (INTEL_INFO(dev)->gen >= 4) {
2498                 intel_crtc->dspaddr_offset =
2499                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2500                                                        pixel_size,
2501                                                        fb->pitches[0]);
2502                 linear_offset -= intel_crtc->dspaddr_offset;
2503         } else {
2504                 intel_crtc->dspaddr_offset = linear_offset;
2505         }
2506
2507         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2508                 dspcntr |= DISPPLANE_ROTATE_180;
2509
2510                 x += (intel_crtc->config.pipe_src_w - 1);
2511                 y += (intel_crtc->config.pipe_src_h - 1);
2512
2513                 /* Finding the last pixel of the last line of the display
2514                 data and adding to linear_offset*/
2515                 linear_offset +=
2516                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2517                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2518         }
2519
2520         I915_WRITE(reg, dspcntr);
2521
2522         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2523                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2524                       fb->pitches[0]);
2525         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2526         if (INTEL_INFO(dev)->gen >= 4) {
2527                 I915_WRITE(DSPSURF(plane),
2528                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2529                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2530                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2531         } else
2532                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2533         POSTING_READ(reg);
2534 }
2535
2536 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2537                                           struct drm_framebuffer *fb,
2538                                           int x, int y)
2539 {
2540         struct drm_device *dev = crtc->dev;
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543         struct drm_i915_gem_object *obj;
2544         int plane = intel_crtc->plane;
2545         unsigned long linear_offset;
2546         u32 dspcntr;
2547         u32 reg = DSPCNTR(plane);
2548         int pixel_size;
2549
2550         if (!intel_crtc->primary_enabled) {
2551                 I915_WRITE(reg, 0);
2552                 I915_WRITE(DSPSURF(plane), 0);
2553                 POSTING_READ(reg);
2554                 return;
2555         }
2556
2557         obj = intel_fb_obj(fb);
2558         if (WARN_ON(obj == NULL))
2559                 return;
2560
2561         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2562
2563         dspcntr = DISPPLANE_GAMMA_ENABLE;
2564
2565         dspcntr |= DISPLAY_PLANE_ENABLE;
2566
2567         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2568                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2569
2570         switch (fb->pixel_format) {
2571         case DRM_FORMAT_C8:
2572                 dspcntr |= DISPPLANE_8BPP;
2573                 break;
2574         case DRM_FORMAT_RGB565:
2575                 dspcntr |= DISPPLANE_BGRX565;
2576                 break;
2577         case DRM_FORMAT_XRGB8888:
2578         case DRM_FORMAT_ARGB8888:
2579                 dspcntr |= DISPPLANE_BGRX888;
2580                 break;
2581         case DRM_FORMAT_XBGR8888:
2582         case DRM_FORMAT_ABGR8888:
2583                 dspcntr |= DISPPLANE_RGBX888;
2584                 break;
2585         case DRM_FORMAT_XRGB2101010:
2586         case DRM_FORMAT_ARGB2101010:
2587                 dspcntr |= DISPPLANE_BGRX101010;
2588                 break;
2589         case DRM_FORMAT_XBGR2101010:
2590         case DRM_FORMAT_ABGR2101010:
2591                 dspcntr |= DISPPLANE_RGBX101010;
2592                 break;
2593         default:
2594                 BUG();
2595         }
2596
2597         if (obj->tiling_mode != I915_TILING_NONE)
2598                 dspcntr |= DISPPLANE_TILED;
2599
2600         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2601                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2602
2603         linear_offset = y * fb->pitches[0] + x * pixel_size;
2604         intel_crtc->dspaddr_offset =
2605                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2606                                                pixel_size,
2607                                                fb->pitches[0]);
2608         linear_offset -= intel_crtc->dspaddr_offset;
2609         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2610                 dspcntr |= DISPPLANE_ROTATE_180;
2611
2612                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2613                         x += (intel_crtc->config.pipe_src_w - 1);
2614                         y += (intel_crtc->config.pipe_src_h - 1);
2615
2616                         /* Finding the last pixel of the last line of the display
2617                         data and adding to linear_offset*/
2618                         linear_offset +=
2619                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2620                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2621                 }
2622         }
2623
2624         I915_WRITE(reg, dspcntr);
2625
2626         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2627                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2628                       fb->pitches[0]);
2629         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2630         I915_WRITE(DSPSURF(plane),
2631                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2632         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2633                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2634         } else {
2635                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2636                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2637         }
2638         POSTING_READ(reg);
2639 }
2640
2641 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2642 static int
2643 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2644                            int x, int y, enum mode_set_atomic state)
2645 {
2646         struct drm_device *dev = crtc->dev;
2647         struct drm_i915_private *dev_priv = dev->dev_private;
2648
2649         if (dev_priv->display.disable_fbc)
2650                 dev_priv->display.disable_fbc(dev);
2651         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2652
2653         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2654
2655         return 0;
2656 }
2657
2658 void intel_display_handle_reset(struct drm_device *dev)
2659 {
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661         struct drm_crtc *crtc;
2662
2663         /*
2664          * Flips in the rings have been nuked by the reset,
2665          * so complete all pending flips so that user space
2666          * will get its events and not get stuck.
2667          *
2668          * Also update the base address of all primary
2669          * planes to the the last fb to make sure we're
2670          * showing the correct fb after a reset.
2671          *
2672          * Need to make two loops over the crtcs so that we
2673          * don't try to grab a crtc mutex before the
2674          * pending_flip_queue really got woken up.
2675          */
2676
2677         for_each_crtc(dev, crtc) {
2678                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679                 enum plane plane = intel_crtc->plane;
2680
2681                 intel_prepare_page_flip(dev, plane);
2682                 intel_finish_page_flip_plane(dev, plane);
2683         }
2684
2685         for_each_crtc(dev, crtc) {
2686                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687
2688                 drm_modeset_lock(&crtc->mutex, NULL);
2689                 /*
2690                  * FIXME: Once we have proper support for primary planes (and
2691                  * disabling them without disabling the entire crtc) allow again
2692                  * a NULL crtc->primary->fb.
2693                  */
2694                 if (intel_crtc->active && crtc->primary->fb)
2695                         dev_priv->display.update_primary_plane(crtc,
2696                                                                crtc->primary->fb,
2697                                                                crtc->x,
2698                                                                crtc->y);
2699                 drm_modeset_unlock(&crtc->mutex);
2700         }
2701 }
2702
2703 static int
2704 intel_finish_fb(struct drm_framebuffer *old_fb)
2705 {
2706         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2707         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2708         bool was_interruptible = dev_priv->mm.interruptible;
2709         int ret;
2710
2711         /* Big Hammer, we also need to ensure that any pending
2712          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2713          * current scanout is retired before unpinning the old
2714          * framebuffer.
2715          *
2716          * This should only fail upon a hung GPU, in which case we
2717          * can safely continue.
2718          */
2719         dev_priv->mm.interruptible = false;
2720         ret = i915_gem_object_finish_gpu(obj);
2721         dev_priv->mm.interruptible = was_interruptible;
2722
2723         return ret;
2724 }
2725
2726 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2727 {
2728         struct drm_device *dev = crtc->dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731         unsigned long flags;
2732         bool pending;
2733
2734         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2735             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2736                 return false;
2737
2738         spin_lock_irqsave(&dev->event_lock, flags);
2739         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2740         spin_unlock_irqrestore(&dev->event_lock, flags);
2741
2742         return pending;
2743 }
2744
2745 static int
2746 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2747                     struct drm_framebuffer *fb)
2748 {
2749         struct drm_device *dev = crtc->dev;
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2752         enum pipe pipe = intel_crtc->pipe;
2753         struct drm_framebuffer *old_fb = crtc->primary->fb;
2754         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2755         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2756         int ret;
2757
2758         if (intel_crtc_has_pending_flip(crtc)) {
2759                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2760                 return -EBUSY;
2761         }
2762
2763         /* no fb bound */
2764         if (!fb) {
2765                 DRM_ERROR("No FB bound\n");
2766                 return 0;
2767         }
2768
2769         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2770                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2771                           plane_name(intel_crtc->plane),
2772                           INTEL_INFO(dev)->num_pipes);
2773                 return -EINVAL;
2774         }
2775
2776         mutex_lock(&dev->struct_mutex);
2777         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2778         if (ret == 0)
2779                 i915_gem_track_fb(old_obj, obj,
2780                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2781         mutex_unlock(&dev->struct_mutex);
2782         if (ret != 0) {
2783                 DRM_ERROR("pin & fence failed\n");
2784                 return ret;
2785         }
2786
2787         /*
2788          * Update pipe size and adjust fitter if needed: the reason for this is
2789          * that in compute_mode_changes we check the native mode (not the pfit
2790          * mode) to see if we can flip rather than do a full mode set. In the
2791          * fastboot case, we'll flip, but if we don't update the pipesrc and
2792          * pfit state, we'll end up with a big fb scanned out into the wrong
2793          * sized surface.
2794          *
2795          * To fix this properly, we need to hoist the checks up into
2796          * compute_mode_changes (or above), check the actual pfit state and
2797          * whether the platform allows pfit disable with pipe active, and only
2798          * then update the pipesrc and pfit state, even on the flip path.
2799          */
2800         if (i915.fastboot) {
2801                 const struct drm_display_mode *adjusted_mode =
2802                         &intel_crtc->config.adjusted_mode;
2803
2804                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2805                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2806                            (adjusted_mode->crtc_vdisplay - 1));
2807                 if (!intel_crtc->config.pch_pfit.enabled &&
2808                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2809                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2810                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2811                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2812                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2813                 }
2814                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2815                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2816         }
2817
2818         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2819
2820         if (intel_crtc->active)
2821                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2822
2823         crtc->primary->fb = fb;
2824         crtc->x = x;
2825         crtc->y = y;
2826
2827         if (old_fb) {
2828                 if (intel_crtc->active && old_fb != fb)
2829                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2830                 mutex_lock(&dev->struct_mutex);
2831                 intel_unpin_fb_obj(old_obj);
2832                 mutex_unlock(&dev->struct_mutex);
2833         }
2834
2835         mutex_lock(&dev->struct_mutex);
2836         intel_update_fbc(dev);
2837         mutex_unlock(&dev->struct_mutex);
2838
2839         return 0;
2840 }
2841
2842 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2843 {
2844         struct drm_device *dev = crtc->dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2847         int pipe = intel_crtc->pipe;
2848         u32 reg, temp;
2849
2850         /* enable normal train */
2851         reg = FDI_TX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         if (IS_IVYBRIDGE(dev)) {
2854                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2855                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2856         } else {
2857                 temp &= ~FDI_LINK_TRAIN_NONE;
2858                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2859         }
2860         I915_WRITE(reg, temp);
2861
2862         reg = FDI_RX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         if (HAS_PCH_CPT(dev)) {
2865                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2866                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2867         } else {
2868                 temp &= ~FDI_LINK_TRAIN_NONE;
2869                 temp |= FDI_LINK_TRAIN_NONE;
2870         }
2871         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2872
2873         /* wait one idle pattern time */
2874         POSTING_READ(reg);
2875         udelay(1000);
2876
2877         /* IVB wants error correction enabled */
2878         if (IS_IVYBRIDGE(dev))
2879                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2880                            FDI_FE_ERRC_ENABLE);
2881 }
2882
2883 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2884 {
2885         return crtc->base.enabled && crtc->active &&
2886                 crtc->config.has_pch_encoder;
2887 }
2888
2889 static void ivb_modeset_global_resources(struct drm_device *dev)
2890 {
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         struct intel_crtc *pipe_B_crtc =
2893                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2894         struct intel_crtc *pipe_C_crtc =
2895                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2896         uint32_t temp;
2897
2898         /*
2899          * When everything is off disable fdi C so that we could enable fdi B
2900          * with all lanes. Note that we don't care about enabled pipes without
2901          * an enabled pch encoder.
2902          */
2903         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2904             !pipe_has_enabled_pch(pipe_C_crtc)) {
2905                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2906                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2907
2908                 temp = I915_READ(SOUTH_CHICKEN1);
2909                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2910                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2911                 I915_WRITE(SOUTH_CHICKEN1, temp);
2912         }
2913 }
2914
2915 /* The FDI link training functions for ILK/Ibexpeak. */
2916 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2917 {
2918         struct drm_device *dev = crtc->dev;
2919         struct drm_i915_private *dev_priv = dev->dev_private;
2920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2921         int pipe = intel_crtc->pipe;
2922         u32 reg, temp, tries;
2923
2924         /* FDI needs bits from pipe first */
2925         assert_pipe_enabled(dev_priv, pipe);
2926
2927         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2928            for train result */
2929         reg = FDI_RX_IMR(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_RX_SYMBOL_LOCK;
2932         temp &= ~FDI_RX_BIT_LOCK;
2933         I915_WRITE(reg, temp);
2934         I915_READ(reg);
2935         udelay(150);
2936
2937         /* enable CPU FDI TX and PCH FDI RX */
2938         reg = FDI_TX_CTL(pipe);
2939         temp = I915_READ(reg);
2940         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2941         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2942         temp &= ~FDI_LINK_TRAIN_NONE;
2943         temp |= FDI_LINK_TRAIN_PATTERN_1;
2944         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2945
2946         reg = FDI_RX_CTL(pipe);
2947         temp = I915_READ(reg);
2948         temp &= ~FDI_LINK_TRAIN_NONE;
2949         temp |= FDI_LINK_TRAIN_PATTERN_1;
2950         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2951
2952         POSTING_READ(reg);
2953         udelay(150);
2954
2955         /* Ironlake workaround, enable clock pointer after FDI enable*/
2956         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2957         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2958                    FDI_RX_PHASE_SYNC_POINTER_EN);
2959
2960         reg = FDI_RX_IIR(pipe);
2961         for (tries = 0; tries < 5; tries++) {
2962                 temp = I915_READ(reg);
2963                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2964
2965                 if ((temp & FDI_RX_BIT_LOCK)) {
2966                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2967                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2968                         break;
2969                 }
2970         }
2971         if (tries == 5)
2972                 DRM_ERROR("FDI train 1 fail!\n");
2973
2974         /* Train 2 */
2975         reg = FDI_TX_CTL(pipe);
2976         temp = I915_READ(reg);
2977         temp &= ~FDI_LINK_TRAIN_NONE;
2978         temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         I915_WRITE(reg, temp);
2980
2981         reg = FDI_RX_CTL(pipe);
2982         temp = I915_READ(reg);
2983         temp &= ~FDI_LINK_TRAIN_NONE;
2984         temp |= FDI_LINK_TRAIN_PATTERN_2;
2985         I915_WRITE(reg, temp);
2986
2987         POSTING_READ(reg);
2988         udelay(150);
2989
2990         reg = FDI_RX_IIR(pipe);
2991         for (tries = 0; tries < 5; tries++) {
2992                 temp = I915_READ(reg);
2993                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2994
2995                 if (temp & FDI_RX_SYMBOL_LOCK) {
2996                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2997                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2998                         break;
2999                 }
3000         }
3001         if (tries == 5)
3002                 DRM_ERROR("FDI train 2 fail!\n");
3003
3004         DRM_DEBUG_KMS("FDI train done\n");
3005
3006 }
3007
3008 static const int snb_b_fdi_train_param[] = {
3009         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3010         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3011         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3012         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3013 };
3014
3015 /* The FDI link training functions for SNB/Cougarpoint. */
3016 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3017 {
3018         struct drm_device *dev = crtc->dev;
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021         int pipe = intel_crtc->pipe;
3022         u32 reg, temp, i, retry;
3023
3024         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025            for train result */
3026         reg = FDI_RX_IMR(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~FDI_RX_SYMBOL_LOCK;
3029         temp &= ~FDI_RX_BIT_LOCK;
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         /* enable CPU FDI TX and PCH FDI RX */
3036         reg = FDI_TX_CTL(pipe);
3037         temp = I915_READ(reg);
3038         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3039         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3040         temp &= ~FDI_LINK_TRAIN_NONE;
3041         temp |= FDI_LINK_TRAIN_PATTERN_1;
3042         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3043         /* SNB-B */
3044         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3045         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3046
3047         I915_WRITE(FDI_RX_MISC(pipe),
3048                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3049
3050         reg = FDI_RX_CTL(pipe);
3051         temp = I915_READ(reg);
3052         if (HAS_PCH_CPT(dev)) {
3053                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3054                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3055         } else {
3056                 temp &= ~FDI_LINK_TRAIN_NONE;
3057                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3058         }
3059         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3060
3061         POSTING_READ(reg);
3062         udelay(150);
3063
3064         for (i = 0; i < 4; i++) {
3065                 reg = FDI_TX_CTL(pipe);
3066                 temp = I915_READ(reg);
3067                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3068                 temp |= snb_b_fdi_train_param[i];
3069                 I915_WRITE(reg, temp);
3070
3071                 POSTING_READ(reg);
3072                 udelay(500);
3073
3074                 for (retry = 0; retry < 5; retry++) {
3075                         reg = FDI_RX_IIR(pipe);
3076                         temp = I915_READ(reg);
3077                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3078                         if (temp & FDI_RX_BIT_LOCK) {
3079                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3080                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3081                                 break;
3082                         }
3083                         udelay(50);
3084                 }
3085                 if (retry < 5)
3086                         break;
3087         }
3088         if (i == 4)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         if (IS_GEN6(dev)) {
3097                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3098                 /* SNB-B */
3099                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3100         }
3101         I915_WRITE(reg, temp);
3102
3103         reg = FDI_RX_CTL(pipe);
3104         temp = I915_READ(reg);
3105         if (HAS_PCH_CPT(dev)) {
3106                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3107                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3108         } else {
3109                 temp &= ~FDI_LINK_TRAIN_NONE;
3110                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3111         }
3112         I915_WRITE(reg, temp);
3113
3114         POSTING_READ(reg);
3115         udelay(150);
3116
3117         for (i = 0; i < 4; i++) {
3118                 reg = FDI_TX_CTL(pipe);
3119                 temp = I915_READ(reg);
3120                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3121                 temp |= snb_b_fdi_train_param[i];
3122                 I915_WRITE(reg, temp);
3123
3124                 POSTING_READ(reg);
3125                 udelay(500);
3126
3127                 for (retry = 0; retry < 5; retry++) {
3128                         reg = FDI_RX_IIR(pipe);
3129                         temp = I915_READ(reg);
3130                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3131                         if (temp & FDI_RX_SYMBOL_LOCK) {
3132                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3133                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3134                                 break;
3135                         }
3136                         udelay(50);
3137                 }
3138                 if (retry < 5)
3139                         break;
3140         }
3141         if (i == 4)
3142                 DRM_ERROR("FDI train 2 fail!\n");
3143
3144         DRM_DEBUG_KMS("FDI train done.\n");
3145 }
3146
3147 /* Manual link training for Ivy Bridge A0 parts */
3148 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3149 {
3150         struct drm_device *dev = crtc->dev;
3151         struct drm_i915_private *dev_priv = dev->dev_private;
3152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153         int pipe = intel_crtc->pipe;
3154         u32 reg, temp, i, j;
3155
3156         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3157            for train result */
3158         reg = FDI_RX_IMR(pipe);
3159         temp = I915_READ(reg);
3160         temp &= ~FDI_RX_SYMBOL_LOCK;
3161         temp &= ~FDI_RX_BIT_LOCK;
3162         I915_WRITE(reg, temp);
3163
3164         POSTING_READ(reg);
3165         udelay(150);
3166
3167         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3168                       I915_READ(FDI_RX_IIR(pipe)));
3169
3170         /* Try each vswing and preemphasis setting twice before moving on */
3171         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3172                 /* disable first in case we need to retry */
3173                 reg = FDI_TX_CTL(pipe);
3174                 temp = I915_READ(reg);
3175                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3176                 temp &= ~FDI_TX_ENABLE;
3177                 I915_WRITE(reg, temp);
3178
3179                 reg = FDI_RX_CTL(pipe);
3180                 temp = I915_READ(reg);
3181                 temp &= ~FDI_LINK_TRAIN_AUTO;
3182                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3183                 temp &= ~FDI_RX_ENABLE;
3184                 I915_WRITE(reg, temp);
3185
3186                 /* enable CPU FDI TX and PCH FDI RX */
3187                 reg = FDI_TX_CTL(pipe);
3188                 temp = I915_READ(reg);
3189                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3190                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3191                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3192                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3193                 temp |= snb_b_fdi_train_param[j/2];
3194                 temp |= FDI_COMPOSITE_SYNC;
3195                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3196
3197                 I915_WRITE(FDI_RX_MISC(pipe),
3198                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3199
3200                 reg = FDI_RX_CTL(pipe);
3201                 temp = I915_READ(reg);
3202                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3203                 temp |= FDI_COMPOSITE_SYNC;
3204                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3205
3206                 POSTING_READ(reg);
3207                 udelay(1); /* should be 0.5us */
3208
3209                 for (i = 0; i < 4; i++) {
3210                         reg = FDI_RX_IIR(pipe);
3211                         temp = I915_READ(reg);
3212                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3213
3214                         if (temp & FDI_RX_BIT_LOCK ||
3215                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3216                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3217                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3218                                               i);
3219                                 break;
3220                         }
3221                         udelay(1); /* should be 0.5us */
3222                 }
3223                 if (i == 4) {
3224                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3225                         continue;
3226                 }
3227
3228                 /* Train 2 */
3229                 reg = FDI_TX_CTL(pipe);
3230                 temp = I915_READ(reg);
3231                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3232                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3233                 I915_WRITE(reg, temp);
3234
3235                 reg = FDI_RX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3238                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(2); /* should be 1.5us */
3243
3244                 for (i = 0; i < 4; i++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248
3249                         if (temp & FDI_RX_SYMBOL_LOCK ||
3250                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3251                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3252                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3253                                               i);
3254                                 goto train_done;
3255                         }
3256                         udelay(2); /* should be 1.5us */
3257                 }
3258                 if (i == 4)
3259                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3260         }
3261
3262 train_done:
3263         DRM_DEBUG_KMS("FDI train done.\n");
3264 }
3265
3266 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3267 {
3268         struct drm_device *dev = intel_crtc->base.dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp;
3272
3273
3274         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3275         reg = FDI_RX_CTL(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3278         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3279         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3280         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3281
3282         POSTING_READ(reg);
3283         udelay(200);
3284
3285         /* Switch from Rawclk to PCDclk */
3286         temp = I915_READ(reg);
3287         I915_WRITE(reg, temp | FDI_PCDCLK);
3288
3289         POSTING_READ(reg);
3290         udelay(200);
3291
3292         /* Enable CPU FDI TX PLL, always on for Ironlake */
3293         reg = FDI_TX_CTL(pipe);
3294         temp = I915_READ(reg);
3295         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3296                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3297
3298                 POSTING_READ(reg);
3299                 udelay(100);
3300         }
3301 }
3302
3303 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3304 {
3305         struct drm_device *dev = intel_crtc->base.dev;
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         int pipe = intel_crtc->pipe;
3308         u32 reg, temp;
3309
3310         /* Switch from PCDclk to Rawclk */
3311         reg = FDI_RX_CTL(pipe);
3312         temp = I915_READ(reg);
3313         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3314
3315         /* Disable CPU FDI TX PLL */
3316         reg = FDI_TX_CTL(pipe);
3317         temp = I915_READ(reg);
3318         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3319
3320         POSTING_READ(reg);
3321         udelay(100);
3322
3323         reg = FDI_RX_CTL(pipe);
3324         temp = I915_READ(reg);
3325         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3326
3327         /* Wait for the clocks to turn off. */
3328         POSTING_READ(reg);
3329         udelay(100);
3330 }
3331
3332 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int pipe = intel_crtc->pipe;
3338         u32 reg, temp;
3339
3340         /* disable CPU FDI tx and PCH FDI rx */
3341         reg = FDI_TX_CTL(pipe);
3342         temp = I915_READ(reg);
3343         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3344         POSTING_READ(reg);
3345
3346         reg = FDI_RX_CTL(pipe);
3347         temp = I915_READ(reg);
3348         temp &= ~(0x7 << 16);
3349         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3350         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3351
3352         POSTING_READ(reg);
3353         udelay(100);
3354
3355         /* Ironlake workaround, disable clock pointer after downing FDI */
3356         if (HAS_PCH_IBX(dev))
3357                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3358
3359         /* still set train pattern 1 */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         temp &= ~FDI_LINK_TRAIN_NONE;
3363         temp |= FDI_LINK_TRAIN_PATTERN_1;
3364         I915_WRITE(reg, temp);
3365
3366         reg = FDI_RX_CTL(pipe);
3367         temp = I915_READ(reg);
3368         if (HAS_PCH_CPT(dev)) {
3369                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3370                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3371         } else {
3372                 temp &= ~FDI_LINK_TRAIN_NONE;
3373                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3374         }
3375         /* BPC in FDI rx is consistent with that in PIPECONF */
3376         temp &= ~(0x07 << 16);
3377         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3378         I915_WRITE(reg, temp);
3379
3380         POSTING_READ(reg);
3381         udelay(100);
3382 }
3383
3384 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3385 {
3386         struct intel_crtc *crtc;
3387
3388         /* Note that we don't need to be called with mode_config.lock here
3389          * as our list of CRTC objects is static for the lifetime of the
3390          * device and so cannot disappear as we iterate. Similarly, we can
3391          * happily treat the predicates as racy, atomic checks as userspace
3392          * cannot claim and pin a new fb without at least acquring the
3393          * struct_mutex and so serialising with us.
3394          */
3395         for_each_intel_crtc(dev, crtc) {
3396                 if (atomic_read(&crtc->unpin_work_count) == 0)
3397                         continue;
3398
3399                 if (crtc->unpin_work)
3400                         intel_wait_for_vblank(dev, crtc->pipe);
3401
3402                 return true;
3403         }
3404
3405         return false;
3406 }
3407
3408 static void page_flip_completed(struct intel_crtc *intel_crtc)
3409 {
3410         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3411         struct intel_unpin_work *work = intel_crtc->unpin_work;
3412
3413         /* ensure that the unpin work is consistent wrt ->pending. */
3414         smp_rmb();
3415         intel_crtc->unpin_work = NULL;
3416
3417         if (work->event)
3418                 drm_send_vblank_event(intel_crtc->base.dev,
3419                                       intel_crtc->pipe,
3420                                       work->event);
3421
3422         drm_crtc_vblank_put(&intel_crtc->base);
3423
3424         wake_up_all(&dev_priv->pending_flip_queue);
3425         queue_work(dev_priv->wq, &work->work);
3426
3427         trace_i915_flip_complete(intel_crtc->plane,
3428                                  work->pending_flip_obj);
3429 }
3430
3431 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435
3436         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3437         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3438                                        !intel_crtc_has_pending_flip(crtc),
3439                                        60*HZ) == 0)) {
3440                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3441                 unsigned long flags;
3442
3443                 spin_lock_irqsave(&dev->event_lock, flags);
3444                 if (intel_crtc->unpin_work) {
3445                         WARN_ONCE(1, "Removing stuck page flip\n");
3446                         page_flip_completed(intel_crtc);
3447                 }
3448                 spin_unlock_irqrestore(&dev->event_lock, flags);
3449         }
3450
3451         if (crtc->primary->fb) {
3452                 mutex_lock(&dev->struct_mutex);
3453                 intel_finish_fb(crtc->primary->fb);
3454                 mutex_unlock(&dev->struct_mutex);
3455         }
3456 }
3457
3458 /* Program iCLKIP clock to the desired frequency */
3459 static void lpt_program_iclkip(struct drm_crtc *crtc)
3460 {
3461         struct drm_device *dev = crtc->dev;
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3464         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3465         u32 temp;
3466
3467         mutex_lock(&dev_priv->dpio_lock);
3468
3469         /* It is necessary to ungate the pixclk gate prior to programming
3470          * the divisors, and gate it back when it is done.
3471          */
3472         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3473
3474         /* Disable SSCCTL */
3475         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3476                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3477                                 SBI_SSCCTL_DISABLE,
3478                         SBI_ICLK);
3479
3480         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3481         if (clock == 20000) {
3482                 auxdiv = 1;
3483                 divsel = 0x41;
3484                 phaseinc = 0x20;
3485         } else {
3486                 /* The iCLK virtual clock root frequency is in MHz,
3487                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3488                  * divisors, it is necessary to divide one by another, so we
3489                  * convert the virtual clock precision to KHz here for higher
3490                  * precision.
3491                  */
3492                 u32 iclk_virtual_root_freq = 172800 * 1000;
3493                 u32 iclk_pi_range = 64;
3494                 u32 desired_divisor, msb_divisor_value, pi_value;
3495
3496                 desired_divisor = (iclk_virtual_root_freq / clock);
3497                 msb_divisor_value = desired_divisor / iclk_pi_range;
3498                 pi_value = desired_divisor % iclk_pi_range;
3499
3500                 auxdiv = 0;
3501                 divsel = msb_divisor_value - 2;
3502                 phaseinc = pi_value;
3503         }
3504
3505         /* This should not happen with any sane values */
3506         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3507                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3508         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3509                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3510
3511         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3512                         clock,
3513                         auxdiv,
3514                         divsel,
3515                         phasedir,
3516                         phaseinc);
3517
3518         /* Program SSCDIVINTPHASE6 */
3519         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3520         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3521         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3522         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3523         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3524         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3525         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3526         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3527
3528         /* Program SSCAUXDIV */
3529         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3530         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3531         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3532         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3533
3534         /* Enable modulator and associated divider */
3535         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3536         temp &= ~SBI_SSCCTL_DISABLE;
3537         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3538
3539         /* Wait for initialization time */
3540         udelay(24);
3541
3542         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3543
3544         mutex_unlock(&dev_priv->dpio_lock);
3545 }
3546
3547 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3548                                                 enum pipe pch_transcoder)
3549 {
3550         struct drm_device *dev = crtc->base.dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3553
3554         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3555                    I915_READ(HTOTAL(cpu_transcoder)));
3556         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3557                    I915_READ(HBLANK(cpu_transcoder)));
3558         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3559                    I915_READ(HSYNC(cpu_transcoder)));
3560
3561         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3562                    I915_READ(VTOTAL(cpu_transcoder)));
3563         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3564                    I915_READ(VBLANK(cpu_transcoder)));
3565         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3566                    I915_READ(VSYNC(cpu_transcoder)));
3567         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3568                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3569 }
3570
3571 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3572 {
3573         struct drm_i915_private *dev_priv = dev->dev_private;
3574         uint32_t temp;
3575
3576         temp = I915_READ(SOUTH_CHICKEN1);
3577         if (temp & FDI_BC_BIFURCATION_SELECT)
3578                 return;
3579
3580         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3581         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3582
3583         temp |= FDI_BC_BIFURCATION_SELECT;
3584         DRM_DEBUG_KMS("enabling fdi C rx\n");
3585         I915_WRITE(SOUTH_CHICKEN1, temp);
3586         POSTING_READ(SOUTH_CHICKEN1);
3587 }
3588
3589 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3590 {
3591         struct drm_device *dev = intel_crtc->base.dev;
3592         struct drm_i915_private *dev_priv = dev->dev_private;
3593
3594         switch (intel_crtc->pipe) {
3595         case PIPE_A:
3596                 break;
3597         case PIPE_B:
3598                 if (intel_crtc->config.fdi_lanes > 2)
3599                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3600                 else
3601                         cpt_enable_fdi_bc_bifurcation(dev);
3602
3603                 break;
3604         case PIPE_C:
3605                 cpt_enable_fdi_bc_bifurcation(dev);
3606
3607                 break;
3608         default:
3609                 BUG();
3610         }
3611 }
3612
3613 /*
3614  * Enable PCH resources required for PCH ports:
3615  *   - PCH PLLs
3616  *   - FDI training & RX/TX
3617  *   - update transcoder timings
3618  *   - DP transcoding bits
3619  *   - transcoder
3620  */
3621 static void ironlake_pch_enable(struct drm_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626         int pipe = intel_crtc->pipe;
3627         u32 reg, temp;
3628
3629         assert_pch_transcoder_disabled(dev_priv, pipe);
3630
3631         if (IS_IVYBRIDGE(dev))
3632                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3633
3634         /* Write the TU size bits before fdi link training, so that error
3635          * detection works. */
3636         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3637                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3638
3639         /* For PCH output, training FDI link */
3640         dev_priv->display.fdi_link_train(crtc);
3641
3642         /* We need to program the right clock selection before writing the pixel
3643          * mutliplier into the DPLL. */
3644         if (HAS_PCH_CPT(dev)) {
3645                 u32 sel;
3646
3647                 temp = I915_READ(PCH_DPLL_SEL);
3648                 temp |= TRANS_DPLL_ENABLE(pipe);
3649                 sel = TRANS_DPLLB_SEL(pipe);
3650                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3651                         temp |= sel;
3652                 else
3653                         temp &= ~sel;
3654                 I915_WRITE(PCH_DPLL_SEL, temp);
3655         }
3656
3657         /* XXX: pch pll's can be enabled any time before we enable the PCH
3658          * transcoder, and we actually should do this to not upset any PCH
3659          * transcoder that already use the clock when we share it.
3660          *
3661          * Note that enable_shared_dpll tries to do the right thing, but
3662          * get_shared_dpll unconditionally resets the pll - we need that to have
3663          * the right LVDS enable sequence. */
3664         intel_enable_shared_dpll(intel_crtc);
3665
3666         /* set transcoder timing, panel must allow it */
3667         assert_panel_unlocked(dev_priv, pipe);
3668         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3669
3670         intel_fdi_normal_train(crtc);
3671
3672         /* For PCH DP, enable TRANS_DP_CTL */
3673         if (HAS_PCH_CPT(dev) &&
3674             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3675              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3676                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3677                 reg = TRANS_DP_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3680                           TRANS_DP_SYNC_MASK |
3681                           TRANS_DP_BPC_MASK);
3682                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3683                          TRANS_DP_ENH_FRAMING);
3684                 temp |= bpc << 9; /* same format but at 11:9 */
3685
3686                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3687                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3688                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3689                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3690
3691                 switch (intel_trans_dp_port_sel(crtc)) {
3692                 case PCH_DP_B:
3693                         temp |= TRANS_DP_PORT_SEL_B;
3694                         break;
3695                 case PCH_DP_C:
3696                         temp |= TRANS_DP_PORT_SEL_C;
3697                         break;
3698                 case PCH_DP_D:
3699                         temp |= TRANS_DP_PORT_SEL_D;
3700                         break;
3701                 default:
3702                         BUG();
3703                 }
3704
3705                 I915_WRITE(reg, temp);
3706         }
3707
3708         ironlake_enable_pch_transcoder(dev_priv, pipe);
3709 }
3710
3711 static void lpt_pch_enable(struct drm_crtc *crtc)
3712 {
3713         struct drm_device *dev = crtc->dev;
3714         struct drm_i915_private *dev_priv = dev->dev_private;
3715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3717
3718         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3719
3720         lpt_program_iclkip(crtc);
3721
3722         /* Set transcoder timing. */
3723         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3724
3725         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3726 }
3727
3728 void intel_put_shared_dpll(struct intel_crtc *crtc)
3729 {
3730         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3731
3732         if (pll == NULL)
3733                 return;
3734
3735         if (pll->refcount == 0) {
3736                 WARN(1, "bad %s refcount\n", pll->name);
3737                 return;
3738         }
3739
3740         if (--pll->refcount == 0) {
3741                 WARN_ON(pll->on);
3742                 WARN_ON(pll->active);
3743         }
3744
3745         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3746 }
3747
3748 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3749 {
3750         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3751         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3752         enum intel_dpll_id i;
3753
3754         if (pll) {
3755                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3756                               crtc->base.base.id, pll->name);
3757                 intel_put_shared_dpll(crtc);
3758         }
3759
3760         if (HAS_PCH_IBX(dev_priv->dev)) {
3761                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3762                 i = (enum intel_dpll_id) crtc->pipe;
3763                 pll = &dev_priv->shared_dplls[i];
3764
3765                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3766                               crtc->base.base.id, pll->name);
3767
3768                 WARN_ON(pll->refcount);
3769
3770                 goto found;
3771         }
3772
3773         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3774                 pll = &dev_priv->shared_dplls[i];
3775
3776                 /* Only want to check enabled timings first */
3777                 if (pll->refcount == 0)
3778                         continue;
3779
3780                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3781                            sizeof(pll->hw_state)) == 0) {
3782                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3783                                       crtc->base.base.id,
3784                                       pll->name, pll->refcount, pll->active);
3785
3786                         goto found;
3787                 }
3788         }
3789
3790         /* Ok no matching timings, maybe there's a free one? */
3791         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3792                 pll = &dev_priv->shared_dplls[i];
3793                 if (pll->refcount == 0) {
3794                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3795                                       crtc->base.base.id, pll->name);
3796                         goto found;
3797                 }
3798         }
3799
3800         return NULL;
3801
3802 found:
3803         if (pll->refcount == 0)
3804                 pll->hw_state = crtc->config.dpll_hw_state;
3805
3806         crtc->config.shared_dpll = i;
3807         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3808                          pipe_name(crtc->pipe));
3809
3810         pll->refcount++;
3811
3812         return pll;
3813 }
3814
3815 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3816 {
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         int dslreg = PIPEDSL(pipe);
3819         u32 temp;
3820
3821         temp = I915_READ(dslreg);
3822         udelay(500);
3823         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3824                 if (wait_for(I915_READ(dslreg) != temp, 5))
3825                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3826         }
3827 }
3828
3829 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3830 {
3831         struct drm_device *dev = crtc->base.dev;
3832         struct drm_i915_private *dev_priv = dev->dev_private;
3833         int pipe = crtc->pipe;
3834
3835         if (crtc->config.pch_pfit.enabled) {
3836                 /* Force use of hard-coded filter coefficients
3837                  * as some pre-programmed values are broken,
3838                  * e.g. x201.
3839                  */
3840                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3841                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3842                                                  PF_PIPE_SEL_IVB(pipe));
3843                 else
3844                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3845                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3846                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3847         }
3848 }
3849
3850 static void intel_enable_planes(struct drm_crtc *crtc)
3851 {
3852         struct drm_device *dev = crtc->dev;
3853         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3854         struct drm_plane *plane;
3855         struct intel_plane *intel_plane;
3856
3857         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3858                 intel_plane = to_intel_plane(plane);
3859                 if (intel_plane->pipe == pipe)
3860                         intel_plane_restore(&intel_plane->base);
3861         }
3862 }
3863
3864 static void intel_disable_planes(struct drm_crtc *crtc)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3868         struct drm_plane *plane;
3869         struct intel_plane *intel_plane;
3870
3871         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3872                 intel_plane = to_intel_plane(plane);
3873                 if (intel_plane->pipe == pipe)
3874                         intel_plane_disable(&intel_plane->base);
3875         }
3876 }
3877
3878 void hsw_enable_ips(struct intel_crtc *crtc)
3879 {
3880         struct drm_device *dev = crtc->base.dev;
3881         struct drm_i915_private *dev_priv = dev->dev_private;
3882
3883         if (!crtc->config.ips_enabled)
3884                 return;
3885
3886         /* We can only enable IPS after we enable a plane and wait for a vblank */
3887         intel_wait_for_vblank(dev, crtc->pipe);
3888
3889         assert_plane_enabled(dev_priv, crtc->plane);
3890         if (IS_BROADWELL(dev)) {
3891                 mutex_lock(&dev_priv->rps.hw_lock);
3892                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3893                 mutex_unlock(&dev_priv->rps.hw_lock);
3894                 /* Quoting Art Runyan: "its not safe to expect any particular
3895                  * value in IPS_CTL bit 31 after enabling IPS through the
3896                  * mailbox." Moreover, the mailbox may return a bogus state,
3897                  * so we need to just enable it and continue on.
3898                  */
3899         } else {
3900                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3901                 /* The bit only becomes 1 in the next vblank, so this wait here
3902                  * is essentially intel_wait_for_vblank. If we don't have this
3903                  * and don't wait for vblanks until the end of crtc_enable, then
3904                  * the HW state readout code will complain that the expected
3905                  * IPS_CTL value is not the one we read. */
3906                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3907                         DRM_ERROR("Timed out waiting for IPS enable\n");
3908         }
3909 }
3910
3911 void hsw_disable_ips(struct intel_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->base.dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915
3916         if (!crtc->config.ips_enabled)
3917                 return;
3918
3919         assert_plane_enabled(dev_priv, crtc->plane);
3920         if (IS_BROADWELL(dev)) {
3921                 mutex_lock(&dev_priv->rps.hw_lock);
3922                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3923                 mutex_unlock(&dev_priv->rps.hw_lock);
3924                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3925                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3926                         DRM_ERROR("Timed out waiting for IPS disable\n");
3927         } else {
3928                 I915_WRITE(IPS_CTL, 0);
3929                 POSTING_READ(IPS_CTL);
3930         }
3931
3932         /* We need to wait for a vblank before we can disable the plane. */
3933         intel_wait_for_vblank(dev, crtc->pipe);
3934 }
3935
3936 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3937 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3938 {
3939         struct drm_device *dev = crtc->dev;
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942         enum pipe pipe = intel_crtc->pipe;
3943         int palreg = PALETTE(pipe);
3944         int i;
3945         bool reenable_ips = false;
3946
3947         /* The clocks have to be on to load the palette. */
3948         if (!crtc->enabled || !intel_crtc->active)
3949                 return;
3950
3951         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3952                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3953                         assert_dsi_pll_enabled(dev_priv);
3954                 else
3955                         assert_pll_enabled(dev_priv, pipe);
3956         }
3957
3958         /* use legacy palette for Ironlake */
3959         if (!HAS_GMCH_DISPLAY(dev))
3960                 palreg = LGC_PALETTE(pipe);
3961
3962         /* Workaround : Do not read or write the pipe palette/gamma data while
3963          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3964          */
3965         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3966             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3967              GAMMA_MODE_MODE_SPLIT)) {
3968                 hsw_disable_ips(intel_crtc);
3969                 reenable_ips = true;
3970         }
3971
3972         for (i = 0; i < 256; i++) {
3973                 I915_WRITE(palreg + 4 * i,
3974                            (intel_crtc->lut_r[i] << 16) |
3975                            (intel_crtc->lut_g[i] << 8) |
3976                            intel_crtc->lut_b[i]);
3977         }
3978
3979         if (reenable_ips)
3980                 hsw_enable_ips(intel_crtc);
3981 }
3982
3983 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3984 {
3985         if (!enable && intel_crtc->overlay) {
3986                 struct drm_device *dev = intel_crtc->base.dev;
3987                 struct drm_i915_private *dev_priv = dev->dev_private;
3988
3989                 mutex_lock(&dev->struct_mutex);
3990                 dev_priv->mm.interruptible = false;
3991                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3992                 dev_priv->mm.interruptible = true;
3993                 mutex_unlock(&dev->struct_mutex);
3994         }
3995
3996         /* Let userspace switch the overlay on again. In most cases userspace
3997          * has to recompute where to put it anyway.
3998          */
3999 }
4000
4001 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4002 {
4003         struct drm_device *dev = crtc->dev;
4004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4005         int pipe = intel_crtc->pipe;
4006
4007         assert_vblank_disabled(crtc);
4008
4009         drm_vblank_on(dev, pipe);
4010
4011         intel_enable_primary_hw_plane(crtc->primary, crtc);
4012         intel_enable_planes(crtc);
4013         intel_crtc_update_cursor(crtc, true);
4014         intel_crtc_dpms_overlay(intel_crtc, true);
4015
4016         hsw_enable_ips(intel_crtc);
4017
4018         mutex_lock(&dev->struct_mutex);
4019         intel_update_fbc(dev);
4020         mutex_unlock(&dev->struct_mutex);
4021
4022         /*
4023          * FIXME: Once we grow proper nuclear flip support out of this we need
4024          * to compute the mask of flip planes precisely. For the time being
4025          * consider this a flip from a NULL plane.
4026          */
4027         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4028 }
4029
4030 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4031 {
4032         struct drm_device *dev = crtc->dev;
4033         struct drm_i915_private *dev_priv = dev->dev_private;
4034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4035         int pipe = intel_crtc->pipe;
4036         int plane = intel_crtc->plane;
4037
4038         intel_crtc_wait_for_pending_flips(crtc);
4039
4040         if (dev_priv->fbc.plane == plane)
4041                 intel_disable_fbc(dev);
4042
4043         hsw_disable_ips(intel_crtc);
4044
4045         intel_crtc_dpms_overlay(intel_crtc, false);
4046         intel_crtc_update_cursor(crtc, false);
4047         intel_disable_planes(crtc);
4048         intel_disable_primary_hw_plane(crtc->primary, crtc);
4049
4050         /*
4051          * FIXME: Once we grow proper nuclear flip support out of this we need
4052          * to compute the mask of flip planes precisely. For the time being
4053          * consider this a flip to a NULL plane.
4054          */
4055         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4056
4057         drm_vblank_off(dev, pipe);
4058
4059         assert_vblank_disabled(crtc);
4060 }
4061
4062 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4063 {
4064         struct drm_device *dev = crtc->dev;
4065         struct drm_i915_private *dev_priv = dev->dev_private;
4066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4067         struct intel_encoder *encoder;
4068         int pipe = intel_crtc->pipe;
4069
4070         WARN_ON(!crtc->enabled);
4071
4072         if (intel_crtc->active)
4073                 return;
4074
4075         if (intel_crtc->config.has_pch_encoder)
4076                 intel_prepare_shared_dpll(intel_crtc);
4077
4078         if (intel_crtc->config.has_dp_encoder)
4079                 intel_dp_set_m_n(intel_crtc);
4080
4081         intel_set_pipe_timings(intel_crtc);
4082
4083         if (intel_crtc->config.has_pch_encoder) {
4084                 intel_cpu_transcoder_set_m_n(intel_crtc,
4085                                      &intel_crtc->config.fdi_m_n, NULL);
4086         }
4087
4088         ironlake_set_pipeconf(crtc);
4089
4090         intel_crtc->active = true;
4091
4092         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4093         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4094
4095         for_each_encoder_on_crtc(dev, crtc, encoder)
4096                 if (encoder->pre_enable)
4097                         encoder->pre_enable(encoder);
4098
4099         if (intel_crtc->config.has_pch_encoder) {
4100                 /* Note: FDI PLL enabling _must_ be done before we enable the
4101                  * cpu pipes, hence this is separate from all the other fdi/pch
4102                  * enabling. */
4103                 ironlake_fdi_pll_enable(intel_crtc);
4104         } else {
4105                 assert_fdi_tx_disabled(dev_priv, pipe);
4106                 assert_fdi_rx_disabled(dev_priv, pipe);
4107         }
4108
4109         ironlake_pfit_enable(intel_crtc);
4110
4111         /*
4112          * On ILK+ LUT must be loaded before the pipe is running but with
4113          * clocks enabled
4114          */
4115         intel_crtc_load_lut(crtc);
4116
4117         intel_update_watermarks(crtc);
4118         intel_enable_pipe(intel_crtc);
4119
4120         if (intel_crtc->config.has_pch_encoder)
4121                 ironlake_pch_enable(crtc);
4122
4123         for_each_encoder_on_crtc(dev, crtc, encoder)
4124                 encoder->enable(encoder);
4125
4126         if (HAS_PCH_CPT(dev))
4127                 cpt_verify_modeset(dev, intel_crtc->pipe);
4128
4129         intel_crtc_enable_planes(crtc);
4130 }
4131
4132 /* IPS only exists on ULT machines and is tied to pipe A. */
4133 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4134 {
4135         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4136 }
4137
4138 /*
4139  * This implements the workaround described in the "notes" section of the mode
4140  * set sequence documentation. When going from no pipes or single pipe to
4141  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4142  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4143  */
4144 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4145 {
4146         struct drm_device *dev = crtc->base.dev;
4147         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4148
4149         /* We want to get the other_active_crtc only if there's only 1 other
4150          * active crtc. */
4151         for_each_intel_crtc(dev, crtc_it) {
4152                 if (!crtc_it->active || crtc_it == crtc)
4153                         continue;
4154
4155                 if (other_active_crtc)
4156                         return;
4157
4158                 other_active_crtc = crtc_it;
4159         }
4160         if (!other_active_crtc)
4161                 return;
4162
4163         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4164         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4165 }
4166
4167 static void haswell_crtc_enable(struct drm_crtc *crtc)
4168 {
4169         struct drm_device *dev = crtc->dev;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172         struct intel_encoder *encoder;
4173         int pipe = intel_crtc->pipe;
4174
4175         WARN_ON(!crtc->enabled);
4176
4177         if (intel_crtc->active)
4178                 return;
4179
4180         if (intel_crtc_to_shared_dpll(intel_crtc))
4181                 intel_enable_shared_dpll(intel_crtc);
4182
4183         if (intel_crtc->config.has_dp_encoder)
4184                 intel_dp_set_m_n(intel_crtc);
4185
4186         intel_set_pipe_timings(intel_crtc);
4187
4188         if (intel_crtc->config.has_pch_encoder) {
4189                 intel_cpu_transcoder_set_m_n(intel_crtc,
4190                                      &intel_crtc->config.fdi_m_n, NULL);
4191         }
4192
4193         haswell_set_pipeconf(crtc);
4194
4195         intel_set_pipe_csc(crtc);
4196
4197         intel_crtc->active = true;
4198
4199         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4200         for_each_encoder_on_crtc(dev, crtc, encoder)
4201                 if (encoder->pre_enable)
4202                         encoder->pre_enable(encoder);
4203
4204         if (intel_crtc->config.has_pch_encoder) {
4205                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4206                 dev_priv->display.fdi_link_train(crtc);
4207         }
4208
4209         intel_ddi_enable_pipe_clock(intel_crtc);
4210
4211         ironlake_pfit_enable(intel_crtc);
4212
4213         /*
4214          * On ILK+ LUT must be loaded before the pipe is running but with
4215          * clocks enabled
4216          */
4217         intel_crtc_load_lut(crtc);
4218
4219         intel_ddi_set_pipe_settings(crtc);
4220         intel_ddi_enable_transcoder_func(crtc);
4221
4222         intel_update_watermarks(crtc);
4223         intel_enable_pipe(intel_crtc);
4224
4225         if (intel_crtc->config.has_pch_encoder)
4226                 lpt_pch_enable(crtc);
4227
4228         if (intel_crtc->config.dp_encoder_is_mst)
4229                 intel_ddi_set_vc_payload_alloc(crtc, true);
4230
4231         for_each_encoder_on_crtc(dev, crtc, encoder) {
4232                 encoder->enable(encoder);
4233                 intel_opregion_notify_encoder(encoder, true);
4234         }
4235
4236         /* If we change the relative order between pipe/planes enabling, we need
4237          * to change the workaround. */
4238         haswell_mode_set_planes_workaround(intel_crtc);
4239         intel_crtc_enable_planes(crtc);
4240 }
4241
4242 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4243 {
4244         struct drm_device *dev = crtc->base.dev;
4245         struct drm_i915_private *dev_priv = dev->dev_private;
4246         int pipe = crtc->pipe;
4247
4248         /* To avoid upsetting the power well on haswell only disable the pfit if
4249          * it's in use. The hw state code will make sure we get this right. */
4250         if (crtc->config.pch_pfit.enabled) {
4251                 I915_WRITE(PF_CTL(pipe), 0);
4252                 I915_WRITE(PF_WIN_POS(pipe), 0);
4253                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4254         }
4255 }
4256
4257 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4258 {
4259         struct drm_device *dev = crtc->dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262         struct intel_encoder *encoder;
4263         int pipe = intel_crtc->pipe;
4264         u32 reg, temp;
4265
4266         if (!intel_crtc->active)
4267                 return;
4268
4269         intel_crtc_disable_planes(crtc);
4270
4271         for_each_encoder_on_crtc(dev, crtc, encoder)
4272                 encoder->disable(encoder);
4273
4274         if (intel_crtc->config.has_pch_encoder)
4275                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4276
4277         intel_disable_pipe(intel_crtc);
4278
4279         ironlake_pfit_disable(intel_crtc);
4280
4281         for_each_encoder_on_crtc(dev, crtc, encoder)
4282                 if (encoder->post_disable)
4283                         encoder->post_disable(encoder);
4284
4285         if (intel_crtc->config.has_pch_encoder) {
4286                 ironlake_fdi_disable(crtc);
4287
4288                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4289                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4290
4291                 if (HAS_PCH_CPT(dev)) {
4292                         /* disable TRANS_DP_CTL */
4293                         reg = TRANS_DP_CTL(pipe);
4294                         temp = I915_READ(reg);
4295                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4296                                   TRANS_DP_PORT_SEL_MASK);
4297                         temp |= TRANS_DP_PORT_SEL_NONE;
4298                         I915_WRITE(reg, temp);
4299
4300                         /* disable DPLL_SEL */
4301                         temp = I915_READ(PCH_DPLL_SEL);
4302                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4303                         I915_WRITE(PCH_DPLL_SEL, temp);
4304                 }
4305
4306                 /* disable PCH DPLL */
4307                 intel_disable_shared_dpll(intel_crtc);
4308
4309                 ironlake_fdi_pll_disable(intel_crtc);
4310         }
4311
4312         intel_crtc->active = false;
4313         intel_update_watermarks(crtc);
4314
4315         mutex_lock(&dev->struct_mutex);
4316         intel_update_fbc(dev);
4317         mutex_unlock(&dev->struct_mutex);
4318 }
4319
4320 static void haswell_crtc_disable(struct drm_crtc *crtc)
4321 {
4322         struct drm_device *dev = crtc->dev;
4323         struct drm_i915_private *dev_priv = dev->dev_private;
4324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325         struct intel_encoder *encoder;
4326         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4327
4328         if (!intel_crtc->active)
4329                 return;
4330
4331         intel_crtc_disable_planes(crtc);
4332
4333         for_each_encoder_on_crtc(dev, crtc, encoder) {
4334                 intel_opregion_notify_encoder(encoder, false);
4335                 encoder->disable(encoder);
4336         }
4337
4338         if (intel_crtc->config.has_pch_encoder)
4339                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4340         intel_disable_pipe(intel_crtc);
4341
4342         if (intel_crtc->config.dp_encoder_is_mst)
4343                 intel_ddi_set_vc_payload_alloc(crtc, false);
4344
4345         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4346
4347         ironlake_pfit_disable(intel_crtc);
4348
4349         intel_ddi_disable_pipe_clock(intel_crtc);
4350
4351         if (intel_crtc->config.has_pch_encoder) {
4352                 lpt_disable_pch_transcoder(dev_priv);
4353                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4354                 intel_ddi_fdi_disable(crtc);
4355         }
4356
4357         for_each_encoder_on_crtc(dev, crtc, encoder)
4358                 if (encoder->post_disable)
4359                         encoder->post_disable(encoder);
4360
4361         intel_crtc->active = false;
4362         intel_update_watermarks(crtc);
4363
4364         mutex_lock(&dev->struct_mutex);
4365         intel_update_fbc(dev);
4366         mutex_unlock(&dev->struct_mutex);
4367
4368         if (intel_crtc_to_shared_dpll(intel_crtc))
4369                 intel_disable_shared_dpll(intel_crtc);
4370 }
4371
4372 static void ironlake_crtc_off(struct drm_crtc *crtc)
4373 {
4374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4375         intel_put_shared_dpll(intel_crtc);
4376 }
4377
4378
4379 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4380 {
4381         struct drm_device *dev = crtc->base.dev;
4382         struct drm_i915_private *dev_priv = dev->dev_private;
4383         struct intel_crtc_config *pipe_config = &crtc->config;
4384
4385         if (!crtc->config.gmch_pfit.control)
4386                 return;
4387
4388         /*
4389          * The panel fitter should only be adjusted whilst the pipe is disabled,
4390          * according to register description and PRM.
4391          */
4392         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4393         assert_pipe_disabled(dev_priv, crtc->pipe);
4394
4395         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4396         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4397
4398         /* Border color in case we don't scale up to the full screen. Black by
4399          * default, change to something else for debugging. */
4400         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4401 }
4402
4403 static enum intel_display_power_domain port_to_power_domain(enum port port)
4404 {
4405         switch (port) {
4406         case PORT_A:
4407                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4408         case PORT_B:
4409                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4410         case PORT_C:
4411                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4412         case PORT_D:
4413                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4414         default:
4415                 WARN_ON_ONCE(1);
4416                 return POWER_DOMAIN_PORT_OTHER;
4417         }
4418 }
4419
4420 #define for_each_power_domain(domain, mask)                             \
4421         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4422                 if ((1 << (domain)) & (mask))
4423
4424 enum intel_display_power_domain
4425 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4426 {
4427         struct drm_device *dev = intel_encoder->base.dev;
4428         struct intel_digital_port *intel_dig_port;
4429
4430         switch (intel_encoder->type) {
4431         case INTEL_OUTPUT_UNKNOWN:
4432                 /* Only DDI platforms should ever use this output type */
4433                 WARN_ON_ONCE(!HAS_DDI(dev));
4434         case INTEL_OUTPUT_DISPLAYPORT:
4435         case INTEL_OUTPUT_HDMI:
4436         case INTEL_OUTPUT_EDP:
4437                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4438                 return port_to_power_domain(intel_dig_port->port);
4439         case INTEL_OUTPUT_DP_MST:
4440                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4441                 return port_to_power_domain(intel_dig_port->port);
4442         case INTEL_OUTPUT_ANALOG:
4443                 return POWER_DOMAIN_PORT_CRT;
4444         case INTEL_OUTPUT_DSI:
4445                 return POWER_DOMAIN_PORT_DSI;
4446         default:
4447                 return POWER_DOMAIN_PORT_OTHER;
4448         }
4449 }
4450
4451 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4452 {
4453         struct drm_device *dev = crtc->dev;
4454         struct intel_encoder *intel_encoder;
4455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4456         enum pipe pipe = intel_crtc->pipe;
4457         unsigned long mask;
4458         enum transcoder transcoder;
4459
4460         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4461
4462         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4463         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4464         if (intel_crtc->config.pch_pfit.enabled ||
4465             intel_crtc->config.pch_pfit.force_thru)
4466                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4467
4468         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4469                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4470
4471         return mask;
4472 }
4473
4474 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4475                                   bool enable)
4476 {
4477         if (dev_priv->power_domains.init_power_on == enable)
4478                 return;
4479
4480         if (enable)
4481                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4482         else
4483                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4484
4485         dev_priv->power_domains.init_power_on = enable;
4486 }
4487
4488 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4489 {
4490         struct drm_i915_private *dev_priv = dev->dev_private;
4491         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4492         struct intel_crtc *crtc;
4493
4494         /*
4495          * First get all needed power domains, then put all unneeded, to avoid
4496          * any unnecessary toggling of the power wells.
4497          */
4498         for_each_intel_crtc(dev, crtc) {
4499                 enum intel_display_power_domain domain;
4500
4501                 if (!crtc->base.enabled)
4502                         continue;
4503
4504                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4505
4506                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4507                         intel_display_power_get(dev_priv, domain);
4508         }
4509
4510         for_each_intel_crtc(dev, crtc) {
4511                 enum intel_display_power_domain domain;
4512
4513                 for_each_power_domain(domain, crtc->enabled_power_domains)
4514                         intel_display_power_put(dev_priv, domain);
4515
4516                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4517         }
4518
4519         intel_display_set_init_power(dev_priv, false);
4520 }
4521
4522 /* returns HPLL frequency in kHz */
4523 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4524 {
4525         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4526
4527         /* Obtain SKU information */
4528         mutex_lock(&dev_priv->dpio_lock);
4529         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4530                 CCK_FUSE_HPLL_FREQ_MASK;
4531         mutex_unlock(&dev_priv->dpio_lock);
4532
4533         return vco_freq[hpll_freq] * 1000;
4534 }
4535
4536 static void vlv_update_cdclk(struct drm_device *dev)
4537 {
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539
4540         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4541         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4542                          dev_priv->vlv_cdclk_freq);
4543
4544         /*
4545          * Program the gmbus_freq based on the cdclk frequency.
4546          * BSpec erroneously claims we should aim for 4MHz, but
4547          * in fact 1MHz is the correct frequency.
4548          */
4549         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4550 }
4551
4552 /* Adjust CDclk dividers to allow high res or save power if possible */
4553 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4554 {
4555         struct drm_i915_private *dev_priv = dev->dev_private;
4556         u32 val, cmd;
4557
4558         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4559
4560         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4561                 cmd = 2;
4562         else if (cdclk == 266667)
4563                 cmd = 1;
4564         else
4565                 cmd = 0;
4566
4567         mutex_lock(&dev_priv->rps.hw_lock);
4568         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4569         val &= ~DSPFREQGUAR_MASK;
4570         val |= (cmd << DSPFREQGUAR_SHIFT);
4571         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4572         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4573                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4574                      50)) {
4575                 DRM_ERROR("timed out waiting for CDclk change\n");
4576         }
4577         mutex_unlock(&dev_priv->rps.hw_lock);
4578
4579         if (cdclk == 400000) {
4580                 u32 divider, vco;
4581
4582                 vco = valleyview_get_vco(dev_priv);
4583                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4584
4585                 mutex_lock(&dev_priv->dpio_lock);
4586                 /* adjust cdclk divider */
4587                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4588                 val &= ~DISPLAY_FREQUENCY_VALUES;
4589                 val |= divider;
4590                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4591
4592                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4593                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4594                              50))
4595                         DRM_ERROR("timed out waiting for CDclk change\n");
4596                 mutex_unlock(&dev_priv->dpio_lock);
4597         }
4598
4599         mutex_lock(&dev_priv->dpio_lock);
4600         /* adjust self-refresh exit latency value */
4601         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4602         val &= ~0x7f;
4603
4604         /*
4605          * For high bandwidth configs, we set a higher latency in the bunit
4606          * so that the core display fetch happens in time to avoid underruns.
4607          */
4608         if (cdclk == 400000)
4609                 val |= 4500 / 250; /* 4.5 usec */
4610         else
4611                 val |= 3000 / 250; /* 3.0 usec */
4612         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4613         mutex_unlock(&dev_priv->dpio_lock);
4614
4615         vlv_update_cdclk(dev);
4616 }
4617
4618 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4619 {
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621         u32 val, cmd;
4622
4623         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4624
4625         switch (cdclk) {
4626         case 400000:
4627                 cmd = 3;
4628                 break;
4629         case 333333:
4630         case 320000:
4631                 cmd = 2;
4632                 break;
4633         case 266667:
4634                 cmd = 1;
4635                 break;
4636         case 200000:
4637                 cmd = 0;
4638                 break;
4639         default:
4640                 WARN_ON(1);
4641                 return;
4642         }
4643
4644         mutex_lock(&dev_priv->rps.hw_lock);
4645         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4646         val &= ~DSPFREQGUAR_MASK_CHV;
4647         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4648         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4649         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4650                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4651                      50)) {
4652                 DRM_ERROR("timed out waiting for CDclk change\n");
4653         }
4654         mutex_unlock(&dev_priv->rps.hw_lock);
4655
4656         vlv_update_cdclk(dev);
4657 }
4658
4659 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4660                                  int max_pixclk)
4661 {
4662         int vco = valleyview_get_vco(dev_priv);
4663         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4664
4665         /* FIXME: Punit isn't quite ready yet */
4666         if (IS_CHERRYVIEW(dev_priv->dev))
4667                 return 400000;
4668
4669         /*
4670          * Really only a few cases to deal with, as only 4 CDclks are supported:
4671          *   200MHz
4672          *   267MHz
4673          *   320/333MHz (depends on HPLL freq)
4674          *   400MHz
4675          * So we check to see whether we're above 90% of the lower bin and
4676          * adjust if needed.
4677          *
4678          * We seem to get an unstable or solid color picture at 200MHz.
4679          * Not sure what's wrong. For now use 200MHz only when all pipes
4680          * are off.
4681          */
4682         if (max_pixclk > freq_320*9/10)
4683                 return 400000;
4684         else if (max_pixclk > 266667*9/10)
4685                 return freq_320;
4686         else if (max_pixclk > 0)
4687                 return 266667;
4688         else
4689                 return 200000;
4690 }
4691
4692 /* compute the max pixel clock for new configuration */
4693 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4694 {
4695         struct drm_device *dev = dev_priv->dev;
4696         struct intel_crtc *intel_crtc;
4697         int max_pixclk = 0;
4698
4699         for_each_intel_crtc(dev, intel_crtc) {
4700                 if (intel_crtc->new_enabled)
4701                         max_pixclk = max(max_pixclk,
4702                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4703         }
4704
4705         return max_pixclk;
4706 }
4707
4708 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4709                                             unsigned *prepare_pipes)
4710 {
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712         struct intel_crtc *intel_crtc;
4713         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4714
4715         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4716             dev_priv->vlv_cdclk_freq)
4717                 return;
4718
4719         /* disable/enable all currently active pipes while we change cdclk */
4720         for_each_intel_crtc(dev, intel_crtc)
4721                 if (intel_crtc->base.enabled)
4722                         *prepare_pipes |= (1 << intel_crtc->pipe);
4723 }
4724
4725 static void valleyview_modeset_global_resources(struct drm_device *dev)
4726 {
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4729         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4730
4731         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4732                 if (IS_CHERRYVIEW(dev))
4733                         cherryview_set_cdclk(dev, req_cdclk);
4734                 else
4735                         valleyview_set_cdclk(dev, req_cdclk);
4736         }
4737
4738         modeset_update_crtc_power_domains(dev);
4739 }
4740
4741 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4742 {
4743         struct drm_device *dev = crtc->dev;
4744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745         struct intel_encoder *encoder;
4746         int pipe = intel_crtc->pipe;
4747         bool is_dsi;
4748
4749         WARN_ON(!crtc->enabled);
4750
4751         if (intel_crtc->active)
4752                 return;
4753
4754         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4755
4756         if (!is_dsi) {
4757                 if (IS_CHERRYVIEW(dev))
4758                         chv_prepare_pll(intel_crtc);
4759                 else
4760                         vlv_prepare_pll(intel_crtc);
4761         }
4762
4763         if (intel_crtc->config.has_dp_encoder)
4764                 intel_dp_set_m_n(intel_crtc);
4765
4766         intel_set_pipe_timings(intel_crtc);
4767
4768         i9xx_set_pipeconf(intel_crtc);
4769
4770         intel_crtc->active = true;
4771
4772         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4773
4774         for_each_encoder_on_crtc(dev, crtc, encoder)
4775                 if (encoder->pre_pll_enable)
4776                         encoder->pre_pll_enable(encoder);
4777
4778         if (!is_dsi) {
4779                 if (IS_CHERRYVIEW(dev))
4780                         chv_enable_pll(intel_crtc);
4781                 else
4782                         vlv_enable_pll(intel_crtc);
4783         }
4784
4785         for_each_encoder_on_crtc(dev, crtc, encoder)
4786                 if (encoder->pre_enable)
4787                         encoder->pre_enable(encoder);
4788
4789         i9xx_pfit_enable(intel_crtc);
4790
4791         intel_crtc_load_lut(crtc);
4792
4793         intel_update_watermarks(crtc);
4794         intel_enable_pipe(intel_crtc);
4795
4796         for_each_encoder_on_crtc(dev, crtc, encoder)
4797                 encoder->enable(encoder);
4798
4799         intel_crtc_enable_planes(crtc);
4800
4801         /* Underruns don't raise interrupts, so check manually. */
4802         i9xx_check_fifo_underruns(dev);
4803 }
4804
4805 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4806 {
4807         struct drm_device *dev = crtc->base.dev;
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809
4810         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4811         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4812 }
4813
4814 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4815 {
4816         struct drm_device *dev = crtc->dev;
4817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4818         struct intel_encoder *encoder;
4819         int pipe = intel_crtc->pipe;
4820
4821         WARN_ON(!crtc->enabled);
4822
4823         if (intel_crtc->active)
4824                 return;
4825
4826         i9xx_set_pll_dividers(intel_crtc);
4827
4828         if (intel_crtc->config.has_dp_encoder)
4829                 intel_dp_set_m_n(intel_crtc);
4830
4831         intel_set_pipe_timings(intel_crtc);
4832
4833         i9xx_set_pipeconf(intel_crtc);
4834
4835         intel_crtc->active = true;
4836
4837         if (!IS_GEN2(dev))
4838                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4839
4840         for_each_encoder_on_crtc(dev, crtc, encoder)
4841                 if (encoder->pre_enable)
4842                         encoder->pre_enable(encoder);
4843
4844         i9xx_enable_pll(intel_crtc);
4845
4846         i9xx_pfit_enable(intel_crtc);
4847
4848         intel_crtc_load_lut(crtc);
4849
4850         intel_update_watermarks(crtc);
4851         intel_enable_pipe(intel_crtc);
4852
4853         for_each_encoder_on_crtc(dev, crtc, encoder)
4854                 encoder->enable(encoder);
4855
4856         intel_crtc_enable_planes(crtc);
4857
4858         /*
4859          * Gen2 reports pipe underruns whenever all planes are disabled.
4860          * So don't enable underrun reporting before at least some planes
4861          * are enabled.
4862          * FIXME: Need to fix the logic to work when we turn off all planes
4863          * but leave the pipe running.
4864          */
4865         if (IS_GEN2(dev))
4866                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4867
4868         /* Underruns don't raise interrupts, so check manually. */
4869         i9xx_check_fifo_underruns(dev);
4870 }
4871
4872 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4873 {
4874         struct drm_device *dev = crtc->base.dev;
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876
4877         if (!crtc->config.gmch_pfit.control)
4878                 return;
4879
4880         assert_pipe_disabled(dev_priv, crtc->pipe);
4881
4882         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4883                          I915_READ(PFIT_CONTROL));
4884         I915_WRITE(PFIT_CONTROL, 0);
4885 }
4886
4887 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4888 {
4889         struct drm_device *dev = crtc->dev;
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4892         struct intel_encoder *encoder;
4893         int pipe = intel_crtc->pipe;
4894
4895         if (!intel_crtc->active)
4896                 return;
4897
4898         /*
4899          * Gen2 reports pipe underruns whenever all planes are disabled.
4900          * So diasble underrun reporting before all the planes get disabled.
4901          * FIXME: Need to fix the logic to work when we turn off all planes
4902          * but leave the pipe running.
4903          */
4904         if (IS_GEN2(dev))
4905                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4906
4907         /*
4908          * Vblank time updates from the shadow to live plane control register
4909          * are blocked if the memory self-refresh mode is active at that
4910          * moment. So to make sure the plane gets truly disabled, disable
4911          * first the self-refresh mode. The self-refresh enable bit in turn
4912          * will be checked/applied by the HW only at the next frame start
4913          * event which is after the vblank start event, so we need to have a
4914          * wait-for-vblank between disabling the plane and the pipe.
4915          */
4916         intel_set_memory_cxsr(dev_priv, false);
4917         intel_crtc_disable_planes(crtc);
4918
4919         for_each_encoder_on_crtc(dev, crtc, encoder)
4920                 encoder->disable(encoder);
4921
4922         /*
4923          * On gen2 planes are double buffered but the pipe isn't, so we must
4924          * wait for planes to fully turn off before disabling the pipe.
4925          * We also need to wait on all gmch platforms because of the
4926          * self-refresh mode constraint explained above.
4927          */
4928         intel_wait_for_vblank(dev, pipe);
4929
4930         intel_disable_pipe(intel_crtc);
4931
4932         i9xx_pfit_disable(intel_crtc);
4933
4934         for_each_encoder_on_crtc(dev, crtc, encoder)
4935                 if (encoder->post_disable)
4936                         encoder->post_disable(encoder);
4937
4938         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4939                 if (IS_CHERRYVIEW(dev))
4940                         chv_disable_pll(dev_priv, pipe);
4941                 else if (IS_VALLEYVIEW(dev))
4942                         vlv_disable_pll(dev_priv, pipe);
4943                 else
4944                         i9xx_disable_pll(dev_priv, pipe);
4945         }
4946
4947         if (!IS_GEN2(dev))
4948                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4949
4950         intel_crtc->active = false;
4951         intel_update_watermarks(crtc);
4952
4953         mutex_lock(&dev->struct_mutex);
4954         intel_update_fbc(dev);
4955         mutex_unlock(&dev->struct_mutex);
4956 }
4957
4958 static void i9xx_crtc_off(struct drm_crtc *crtc)
4959 {
4960 }
4961
4962 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4963                                     bool enabled)
4964 {
4965         struct drm_device *dev = crtc->dev;
4966         struct drm_i915_master_private *master_priv;
4967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4968         int pipe = intel_crtc->pipe;
4969
4970         if (!dev->primary->master)
4971                 return;
4972
4973         master_priv = dev->primary->master->driver_priv;
4974         if (!master_priv->sarea_priv)
4975                 return;
4976
4977         switch (pipe) {
4978         case 0:
4979                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4980                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4981                 break;
4982         case 1:
4983                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4984                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4985                 break;
4986         default:
4987                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4988                 break;
4989         }
4990 }
4991
4992 /* Master function to enable/disable CRTC and corresponding power wells */
4993 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998         enum intel_display_power_domain domain;
4999         unsigned long domains;
5000
5001         if (enable) {
5002                 if (!intel_crtc->active) {
5003                         domains = get_crtc_power_domains(crtc);
5004                         for_each_power_domain(domain, domains)
5005                                 intel_display_power_get(dev_priv, domain);
5006                         intel_crtc->enabled_power_domains = domains;
5007
5008                         dev_priv->display.crtc_enable(crtc);
5009                 }
5010         } else {
5011                 if (intel_crtc->active) {
5012                         dev_priv->display.crtc_disable(crtc);
5013
5014                         domains = intel_crtc->enabled_power_domains;
5015                         for_each_power_domain(domain, domains)
5016                                 intel_display_power_put(dev_priv, domain);
5017                         intel_crtc->enabled_power_domains = 0;
5018                 }
5019         }
5020 }
5021
5022 /**
5023  * Sets the power management mode of the pipe and plane.
5024  */
5025 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5026 {
5027         struct drm_device *dev = crtc->dev;
5028         struct intel_encoder *intel_encoder;
5029         bool enable = false;
5030
5031         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5032                 enable |= intel_encoder->connectors_active;
5033
5034         intel_crtc_control(crtc, enable);
5035
5036         intel_crtc_update_sarea(crtc, enable);
5037 }
5038
5039 static void intel_crtc_disable(struct drm_crtc *crtc)
5040 {
5041         struct drm_device *dev = crtc->dev;
5042         struct drm_connector *connector;
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5045         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5046
5047         /* crtc should still be enabled when we disable it. */
5048         WARN_ON(!crtc->enabled);
5049
5050         dev_priv->display.crtc_disable(crtc);
5051         intel_crtc_update_sarea(crtc, false);
5052         dev_priv->display.off(crtc);
5053
5054         if (crtc->primary->fb) {
5055                 mutex_lock(&dev->struct_mutex);
5056                 intel_unpin_fb_obj(old_obj);
5057                 i915_gem_track_fb(old_obj, NULL,
5058                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5059                 mutex_unlock(&dev->struct_mutex);
5060                 crtc->primary->fb = NULL;
5061         }
5062
5063         /* Update computed state. */
5064         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5065                 if (!connector->encoder || !connector->encoder->crtc)
5066                         continue;
5067
5068                 if (connector->encoder->crtc != crtc)
5069                         continue;
5070
5071                 connector->dpms = DRM_MODE_DPMS_OFF;
5072                 to_intel_encoder(connector->encoder)->connectors_active = false;
5073         }
5074 }
5075
5076 void intel_encoder_destroy(struct drm_encoder *encoder)
5077 {
5078         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5079
5080         drm_encoder_cleanup(encoder);
5081         kfree(intel_encoder);
5082 }
5083
5084 /* Simple dpms helper for encoders with just one connector, no cloning and only
5085  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5086  * state of the entire output pipe. */
5087 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5088 {
5089         if (mode == DRM_MODE_DPMS_ON) {
5090                 encoder->connectors_active = true;
5091
5092                 intel_crtc_update_dpms(encoder->base.crtc);
5093         } else {
5094                 encoder->connectors_active = false;
5095
5096                 intel_crtc_update_dpms(encoder->base.crtc);
5097         }
5098 }
5099
5100 /* Cross check the actual hw state with our own modeset state tracking (and it's
5101  * internal consistency). */
5102 static void intel_connector_check_state(struct intel_connector *connector)
5103 {
5104         if (connector->get_hw_state(connector)) {
5105                 struct intel_encoder *encoder = connector->encoder;
5106                 struct drm_crtc *crtc;
5107                 bool encoder_enabled;
5108                 enum pipe pipe;
5109
5110                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5111                               connector->base.base.id,
5112                               connector->base.name);
5113
5114                 /* there is no real hw state for MST connectors */
5115                 if (connector->mst_port)
5116                         return;
5117
5118                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5119                      "wrong connector dpms state\n");
5120                 WARN(connector->base.encoder != &encoder->base,
5121                      "active connector not linked to encoder\n");
5122
5123                 if (encoder) {
5124                         WARN(!encoder->connectors_active,
5125                              "encoder->connectors_active not set\n");
5126
5127                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5128                         WARN(!encoder_enabled, "encoder not enabled\n");
5129                         if (WARN_ON(!encoder->base.crtc))
5130                                 return;
5131
5132                         crtc = encoder->base.crtc;
5133
5134                         WARN(!crtc->enabled, "crtc not enabled\n");
5135                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5136                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5137                              "encoder active on the wrong pipe\n");
5138                 }
5139         }
5140 }
5141
5142 /* Even simpler default implementation, if there's really no special case to
5143  * consider. */
5144 void intel_connector_dpms(struct drm_connector *connector, int mode)
5145 {
5146         /* All the simple cases only support two dpms states. */
5147         if (mode != DRM_MODE_DPMS_ON)
5148                 mode = DRM_MODE_DPMS_OFF;
5149
5150         if (mode == connector->dpms)
5151                 return;
5152
5153         connector->dpms = mode;
5154
5155         /* Only need to change hw state when actually enabled */
5156         if (connector->encoder)
5157                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5158
5159         intel_modeset_check_state(connector->dev);
5160 }
5161
5162 /* Simple connector->get_hw_state implementation for encoders that support only
5163  * one connector and no cloning and hence the encoder state determines the state
5164  * of the connector. */
5165 bool intel_connector_get_hw_state(struct intel_connector *connector)
5166 {
5167         enum pipe pipe = 0;
5168         struct intel_encoder *encoder = connector->encoder;
5169
5170         return encoder->get_hw_state(encoder, &pipe);
5171 }
5172
5173 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5174                                      struct intel_crtc_config *pipe_config)
5175 {
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct intel_crtc *pipe_B_crtc =
5178                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5179
5180         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5181                       pipe_name(pipe), pipe_config->fdi_lanes);
5182         if (pipe_config->fdi_lanes > 4) {
5183                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5184                               pipe_name(pipe), pipe_config->fdi_lanes);
5185                 return false;
5186         }
5187
5188         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5189                 if (pipe_config->fdi_lanes > 2) {
5190                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5191                                       pipe_config->fdi_lanes);
5192                         return false;
5193                 } else {
5194                         return true;
5195                 }
5196         }
5197
5198         if (INTEL_INFO(dev)->num_pipes == 2)
5199                 return true;
5200
5201         /* Ivybridge 3 pipe is really complicated */
5202         switch (pipe) {
5203         case PIPE_A:
5204                 return true;
5205         case PIPE_B:
5206                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5207                     pipe_config->fdi_lanes > 2) {
5208                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5209                                       pipe_name(pipe), pipe_config->fdi_lanes);
5210                         return false;
5211                 }
5212                 return true;
5213         case PIPE_C:
5214                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5215                     pipe_B_crtc->config.fdi_lanes <= 2) {
5216                         if (pipe_config->fdi_lanes > 2) {
5217                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5218                                               pipe_name(pipe), pipe_config->fdi_lanes);
5219                                 return false;
5220                         }
5221                 } else {
5222                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5223                         return false;
5224                 }
5225                 return true;
5226         default:
5227                 BUG();
5228         }
5229 }
5230
5231 #define RETRY 1
5232 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5233                                        struct intel_crtc_config *pipe_config)
5234 {
5235         struct drm_device *dev = intel_crtc->base.dev;
5236         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5237         int lane, link_bw, fdi_dotclock;
5238         bool setup_ok, needs_recompute = false;
5239
5240 retry:
5241         /* FDI is a binary signal running at ~2.7GHz, encoding
5242          * each output octet as 10 bits. The actual frequency
5243          * is stored as a divider into a 100MHz clock, and the
5244          * mode pixel clock is stored in units of 1KHz.
5245          * Hence the bw of each lane in terms of the mode signal
5246          * is:
5247          */
5248         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5249
5250         fdi_dotclock = adjusted_mode->crtc_clock;
5251
5252         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5253                                            pipe_config->pipe_bpp);
5254
5255         pipe_config->fdi_lanes = lane;
5256
5257         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5258                                link_bw, &pipe_config->fdi_m_n);
5259
5260         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5261                                             intel_crtc->pipe, pipe_config);
5262         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5263                 pipe_config->pipe_bpp -= 2*3;
5264                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5265                               pipe_config->pipe_bpp);
5266                 needs_recompute = true;
5267                 pipe_config->bw_constrained = true;
5268
5269                 goto retry;
5270         }
5271
5272         if (needs_recompute)
5273                 return RETRY;
5274
5275         return setup_ok ? 0 : -EINVAL;
5276 }
5277
5278 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5279                                    struct intel_crtc_config *pipe_config)
5280 {
5281         pipe_config->ips_enabled = i915.enable_ips &&
5282                                    hsw_crtc_supports_ips(crtc) &&
5283                                    pipe_config->pipe_bpp <= 24;
5284 }
5285
5286 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5287                                      struct intel_crtc_config *pipe_config)
5288 {
5289         struct drm_device *dev = crtc->base.dev;
5290         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5291
5292         /* FIXME should check pixel clock limits on all platforms */
5293         if (INTEL_INFO(dev)->gen < 4) {
5294                 struct drm_i915_private *dev_priv = dev->dev_private;
5295                 int clock_limit =
5296                         dev_priv->display.get_display_clock_speed(dev);
5297
5298                 /*
5299                  * Enable pixel doubling when the dot clock
5300                  * is > 90% of the (display) core speed.
5301                  *
5302                  * GDG double wide on either pipe,
5303                  * otherwise pipe A only.
5304                  */
5305                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5306                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5307                         clock_limit *= 2;
5308                         pipe_config->double_wide = true;
5309                 }
5310
5311                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5312                         return -EINVAL;
5313         }
5314
5315         /*
5316          * Pipe horizontal size must be even in:
5317          * - DVO ganged mode
5318          * - LVDS dual channel mode
5319          * - Double wide pipe
5320          */
5321         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5322              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5323                 pipe_config->pipe_src_w &= ~1;
5324
5325         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5326          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5327          */
5328         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5329                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5330                 return -EINVAL;
5331
5332         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5333                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5334         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5335                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5336                  * for lvds. */
5337                 pipe_config->pipe_bpp = 8*3;
5338         }
5339
5340         if (HAS_IPS(dev))
5341                 hsw_compute_ips_config(crtc, pipe_config);
5342
5343         /*
5344          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5345          * old clock survives for now.
5346          */
5347         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5348                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5349
5350         if (pipe_config->has_pch_encoder)
5351                 return ironlake_fdi_compute_config(crtc, pipe_config);
5352
5353         return 0;
5354 }
5355
5356 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5357 {
5358         struct drm_i915_private *dev_priv = dev->dev_private;
5359         int vco = valleyview_get_vco(dev_priv);
5360         u32 val;
5361         int divider;
5362
5363         /* FIXME: Punit isn't quite ready yet */
5364         if (IS_CHERRYVIEW(dev))
5365                 return 400000;
5366
5367         mutex_lock(&dev_priv->dpio_lock);
5368         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5369         mutex_unlock(&dev_priv->dpio_lock);
5370
5371         divider = val & DISPLAY_FREQUENCY_VALUES;
5372
5373         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5374              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5375              "cdclk change in progress\n");
5376
5377         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5378 }
5379
5380 static int i945_get_display_clock_speed(struct drm_device *dev)
5381 {
5382         return 400000;
5383 }
5384
5385 static int i915_get_display_clock_speed(struct drm_device *dev)
5386 {
5387         return 333000;
5388 }
5389
5390 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5391 {
5392         return 200000;
5393 }
5394
5395 static int pnv_get_display_clock_speed(struct drm_device *dev)
5396 {
5397         u16 gcfgc = 0;
5398
5399         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5400
5401         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5402         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5403                 return 267000;
5404         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5405                 return 333000;
5406         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5407                 return 444000;
5408         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5409                 return 200000;
5410         default:
5411                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5412         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5413                 return 133000;
5414         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5415                 return 167000;
5416         }
5417 }
5418
5419 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5420 {
5421         u16 gcfgc = 0;
5422
5423         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5424
5425         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5426                 return 133000;
5427         else {
5428                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5429                 case GC_DISPLAY_CLOCK_333_MHZ:
5430                         return 333000;
5431                 default:
5432                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5433                         return 190000;
5434                 }
5435         }
5436 }
5437
5438 static int i865_get_display_clock_speed(struct drm_device *dev)
5439 {
5440         return 266000;
5441 }
5442
5443 static int i855_get_display_clock_speed(struct drm_device *dev)
5444 {
5445         u16 hpllcc = 0;
5446         /* Assume that the hardware is in the high speed state.  This
5447          * should be the default.
5448          */
5449         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5450         case GC_CLOCK_133_200:
5451         case GC_CLOCK_100_200:
5452                 return 200000;
5453         case GC_CLOCK_166_250:
5454                 return 250000;
5455         case GC_CLOCK_100_133:
5456                 return 133000;
5457         }
5458
5459         /* Shouldn't happen */
5460         return 0;
5461 }
5462
5463 static int i830_get_display_clock_speed(struct drm_device *dev)
5464 {
5465         return 133000;
5466 }
5467
5468 static void
5469 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5470 {
5471         while (*num > DATA_LINK_M_N_MASK ||
5472                *den > DATA_LINK_M_N_MASK) {
5473                 *num >>= 1;
5474                 *den >>= 1;
5475         }
5476 }
5477
5478 static void compute_m_n(unsigned int m, unsigned int n,
5479                         uint32_t *ret_m, uint32_t *ret_n)
5480 {
5481         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5482         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5483         intel_reduce_m_n_ratio(ret_m, ret_n);
5484 }
5485
5486 void
5487 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5488                        int pixel_clock, int link_clock,
5489                        struct intel_link_m_n *m_n)
5490 {
5491         m_n->tu = 64;
5492
5493         compute_m_n(bits_per_pixel * pixel_clock,
5494                     link_clock * nlanes * 8,
5495                     &m_n->gmch_m, &m_n->gmch_n);
5496
5497         compute_m_n(pixel_clock, link_clock,
5498                     &m_n->link_m, &m_n->link_n);
5499 }
5500
5501 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5502 {
5503         if (i915.panel_use_ssc >= 0)
5504                 return i915.panel_use_ssc != 0;
5505         return dev_priv->vbt.lvds_use_ssc
5506                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5507 }
5508
5509 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5510 {
5511         struct drm_device *dev = crtc->dev;
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         int refclk;
5514
5515         if (IS_VALLEYVIEW(dev)) {
5516                 refclk = 100000;
5517         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5518             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5519                 refclk = dev_priv->vbt.lvds_ssc_freq;
5520                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5521         } else if (!IS_GEN2(dev)) {
5522                 refclk = 96000;
5523         } else {
5524                 refclk = 48000;
5525         }
5526
5527         return refclk;
5528 }
5529
5530 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5531 {
5532         return (1 << dpll->n) << 16 | dpll->m2;
5533 }
5534
5535 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5536 {
5537         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5538 }
5539
5540 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5541                                      intel_clock_t *reduced_clock)
5542 {
5543         struct drm_device *dev = crtc->base.dev;
5544         u32 fp, fp2 = 0;
5545
5546         if (IS_PINEVIEW(dev)) {
5547                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5548                 if (reduced_clock)
5549                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5550         } else {
5551                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5552                 if (reduced_clock)
5553                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5554         }
5555
5556         crtc->config.dpll_hw_state.fp0 = fp;
5557
5558         crtc->lowfreq_avail = false;
5559         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5560             reduced_clock && i915.powersave) {
5561                 crtc->config.dpll_hw_state.fp1 = fp2;
5562                 crtc->lowfreq_avail = true;
5563         } else {
5564                 crtc->config.dpll_hw_state.fp1 = fp;
5565         }
5566 }
5567
5568 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5569                 pipe)
5570 {
5571         u32 reg_val;
5572
5573         /*
5574          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5575          * and set it to a reasonable value instead.
5576          */
5577         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5578         reg_val &= 0xffffff00;
5579         reg_val |= 0x00000030;
5580         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5581
5582         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5583         reg_val &= 0x8cffffff;
5584         reg_val = 0x8c000000;
5585         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5586
5587         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5588         reg_val &= 0xffffff00;
5589         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5590
5591         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5592         reg_val &= 0x00ffffff;
5593         reg_val |= 0xb0000000;
5594         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5595 }
5596
5597 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5598                                          struct intel_link_m_n *m_n)
5599 {
5600         struct drm_device *dev = crtc->base.dev;
5601         struct drm_i915_private *dev_priv = dev->dev_private;
5602         int pipe = crtc->pipe;
5603
5604         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5605         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5606         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5607         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5608 }
5609
5610 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5611                                          struct intel_link_m_n *m_n,
5612                                          struct intel_link_m_n *m2_n2)
5613 {
5614         struct drm_device *dev = crtc->base.dev;
5615         struct drm_i915_private *dev_priv = dev->dev_private;
5616         int pipe = crtc->pipe;
5617         enum transcoder transcoder = crtc->config.cpu_transcoder;
5618
5619         if (INTEL_INFO(dev)->gen >= 5) {
5620                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5621                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5622                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5623                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5624                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5625                  * for gen < 8) and if DRRS is supported (to make sure the
5626                  * registers are not unnecessarily accessed).
5627                  */
5628                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5629                         crtc->config.has_drrs) {
5630                         I915_WRITE(PIPE_DATA_M2(transcoder),
5631                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5632                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5633                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5634                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5635                 }
5636         } else {
5637                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5638                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5639                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5640                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5641         }
5642 }
5643
5644 void intel_dp_set_m_n(struct intel_crtc *crtc)
5645 {
5646         if (crtc->config.has_pch_encoder)
5647                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5648         else
5649                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5650                                                    &crtc->config.dp_m2_n2);
5651 }
5652
5653 static void vlv_update_pll(struct intel_crtc *crtc)
5654 {
5655         u32 dpll, dpll_md;
5656
5657         /*
5658          * Enable DPIO clock input. We should never disable the reference
5659          * clock for pipe B, since VGA hotplug / manual detection depends
5660          * on it.
5661          */
5662         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5663                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5664         /* We should never disable this, set it here for state tracking */
5665         if (crtc->pipe == PIPE_B)
5666                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5667         dpll |= DPLL_VCO_ENABLE;
5668         crtc->config.dpll_hw_state.dpll = dpll;
5669
5670         dpll_md = (crtc->config.pixel_multiplier - 1)
5671                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5672         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5673 }
5674
5675 static void vlv_prepare_pll(struct intel_crtc *crtc)
5676 {
5677         struct drm_device *dev = crtc->base.dev;
5678         struct drm_i915_private *dev_priv = dev->dev_private;
5679         int pipe = crtc->pipe;
5680         u32 mdiv;
5681         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5682         u32 coreclk, reg_val;
5683
5684         mutex_lock(&dev_priv->dpio_lock);
5685
5686         bestn = crtc->config.dpll.n;
5687         bestm1 = crtc->config.dpll.m1;
5688         bestm2 = crtc->config.dpll.m2;
5689         bestp1 = crtc->config.dpll.p1;
5690         bestp2 = crtc->config.dpll.p2;
5691
5692         /* See eDP HDMI DPIO driver vbios notes doc */
5693
5694         /* PLL B needs special handling */
5695         if (pipe == PIPE_B)
5696                 vlv_pllb_recal_opamp(dev_priv, pipe);
5697
5698         /* Set up Tx target for periodic Rcomp update */
5699         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5700
5701         /* Disable target IRef on PLL */
5702         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5703         reg_val &= 0x00ffffff;
5704         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5705
5706         /* Disable fast lock */
5707         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5708
5709         /* Set idtafcrecal before PLL is enabled */
5710         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5711         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5712         mdiv |= ((bestn << DPIO_N_SHIFT));
5713         mdiv |= (1 << DPIO_K_SHIFT);
5714
5715         /*
5716          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5717          * but we don't support that).
5718          * Note: don't use the DAC post divider as it seems unstable.
5719          */
5720         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5721         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5722
5723         mdiv |= DPIO_ENABLE_CALIBRATION;
5724         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5725
5726         /* Set HBR and RBR LPF coefficients */
5727         if (crtc->config.port_clock == 162000 ||
5728             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5729             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5730                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5731                                  0x009f0003);
5732         else
5733                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5734                                  0x00d0000f);
5735
5736         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5737             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5738                 /* Use SSC source */
5739                 if (pipe == PIPE_A)
5740                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5741                                          0x0df40000);
5742                 else
5743                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5744                                          0x0df70000);
5745         } else { /* HDMI or VGA */
5746                 /* Use bend source */
5747                 if (pipe == PIPE_A)
5748                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5749                                          0x0df70000);
5750                 else
5751                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5752                                          0x0df40000);
5753         }
5754
5755         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5756         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5757         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5758             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5759                 coreclk |= 0x01000000;
5760         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5761
5762         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5763         mutex_unlock(&dev_priv->dpio_lock);
5764 }
5765
5766 static void chv_update_pll(struct intel_crtc *crtc)
5767 {
5768         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5769                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5770                 DPLL_VCO_ENABLE;
5771         if (crtc->pipe != PIPE_A)
5772                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5773
5774         crtc->config.dpll_hw_state.dpll_md =
5775                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5776 }
5777
5778 static void chv_prepare_pll(struct intel_crtc *crtc)
5779 {
5780         struct drm_device *dev = crtc->base.dev;
5781         struct drm_i915_private *dev_priv = dev->dev_private;
5782         int pipe = crtc->pipe;
5783         int dpll_reg = DPLL(crtc->pipe);
5784         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5785         u32 loopfilter, intcoeff;
5786         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5787         int refclk;
5788
5789         bestn = crtc->config.dpll.n;
5790         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5791         bestm1 = crtc->config.dpll.m1;
5792         bestm2 = crtc->config.dpll.m2 >> 22;
5793         bestp1 = crtc->config.dpll.p1;
5794         bestp2 = crtc->config.dpll.p2;
5795
5796         /*
5797          * Enable Refclk and SSC
5798          */
5799         I915_WRITE(dpll_reg,
5800                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5801
5802         mutex_lock(&dev_priv->dpio_lock);
5803
5804         /* p1 and p2 divider */
5805         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5806                         5 << DPIO_CHV_S1_DIV_SHIFT |
5807                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5808                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5809                         1 << DPIO_CHV_K_DIV_SHIFT);
5810
5811         /* Feedback post-divider - m2 */
5812         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5813
5814         /* Feedback refclk divider - n and m1 */
5815         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5816                         DPIO_CHV_M1_DIV_BY_2 |
5817                         1 << DPIO_CHV_N_DIV_SHIFT);
5818
5819         /* M2 fraction division */
5820         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5821
5822         /* M2 fraction division enable */
5823         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5824                        DPIO_CHV_FRAC_DIV_EN |
5825                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5826
5827         /* Loop filter */
5828         refclk = i9xx_get_refclk(&crtc->base, 0);
5829         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5830                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5831         if (refclk == 100000)
5832                 intcoeff = 11;
5833         else if (refclk == 38400)
5834                 intcoeff = 10;
5835         else
5836                 intcoeff = 9;
5837         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5838         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5839
5840         /* AFC Recal */
5841         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5842                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5843                         DPIO_AFC_RECAL);
5844
5845         mutex_unlock(&dev_priv->dpio_lock);
5846 }
5847
5848 static void i9xx_update_pll(struct intel_crtc *crtc,
5849                             intel_clock_t *reduced_clock,
5850                             int num_connectors)
5851 {
5852         struct drm_device *dev = crtc->base.dev;
5853         struct drm_i915_private *dev_priv = dev->dev_private;
5854         u32 dpll;
5855         bool is_sdvo;
5856         struct dpll *clock = &crtc->config.dpll;
5857
5858         i9xx_update_pll_dividers(crtc, reduced_clock);
5859
5860         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5861                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5862
5863         dpll = DPLL_VGA_MODE_DIS;
5864
5865         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5866                 dpll |= DPLLB_MODE_LVDS;
5867         else
5868                 dpll |= DPLLB_MODE_DAC_SERIAL;
5869
5870         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5871                 dpll |= (crtc->config.pixel_multiplier - 1)
5872                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5873         }
5874
5875         if (is_sdvo)
5876                 dpll |= DPLL_SDVO_HIGH_SPEED;
5877
5878         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5879                 dpll |= DPLL_SDVO_HIGH_SPEED;
5880
5881         /* compute bitmask from p1 value */
5882         if (IS_PINEVIEW(dev))
5883                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5884         else {
5885                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5886                 if (IS_G4X(dev) && reduced_clock)
5887                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5888         }
5889         switch (clock->p2) {
5890         case 5:
5891                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5892                 break;
5893         case 7:
5894                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5895                 break;
5896         case 10:
5897                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5898                 break;
5899         case 14:
5900                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5901                 break;
5902         }
5903         if (INTEL_INFO(dev)->gen >= 4)
5904                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5905
5906         if (crtc->config.sdvo_tv_clock)
5907                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5908         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5909                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5910                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5911         else
5912                 dpll |= PLL_REF_INPUT_DREFCLK;
5913
5914         dpll |= DPLL_VCO_ENABLE;
5915         crtc->config.dpll_hw_state.dpll = dpll;
5916
5917         if (INTEL_INFO(dev)->gen >= 4) {
5918                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5919                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5920                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5921         }
5922 }
5923
5924 static void i8xx_update_pll(struct intel_crtc *crtc,
5925                             intel_clock_t *reduced_clock,
5926                             int num_connectors)
5927 {
5928         struct drm_device *dev = crtc->base.dev;
5929         struct drm_i915_private *dev_priv = dev->dev_private;
5930         u32 dpll;
5931         struct dpll *clock = &crtc->config.dpll;
5932
5933         i9xx_update_pll_dividers(crtc, reduced_clock);
5934
5935         dpll = DPLL_VGA_MODE_DIS;
5936
5937         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5938                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5939         } else {
5940                 if (clock->p1 == 2)
5941                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5942                 else
5943                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5944                 if (clock->p2 == 4)
5945                         dpll |= PLL_P2_DIVIDE_BY_4;
5946         }
5947
5948         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5949                 dpll |= DPLL_DVO_2X_MODE;
5950
5951         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5952                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5953                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5954         else
5955                 dpll |= PLL_REF_INPUT_DREFCLK;
5956
5957         dpll |= DPLL_VCO_ENABLE;
5958         crtc->config.dpll_hw_state.dpll = dpll;
5959 }
5960
5961 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5962 {
5963         struct drm_device *dev = intel_crtc->base.dev;
5964         struct drm_i915_private *dev_priv = dev->dev_private;
5965         enum pipe pipe = intel_crtc->pipe;
5966         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5967         struct drm_display_mode *adjusted_mode =
5968                 &intel_crtc->config.adjusted_mode;
5969         uint32_t crtc_vtotal, crtc_vblank_end;
5970         int vsyncshift = 0;
5971
5972         /* We need to be careful not to changed the adjusted mode, for otherwise
5973          * the hw state checker will get angry at the mismatch. */
5974         crtc_vtotal = adjusted_mode->crtc_vtotal;
5975         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5976
5977         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5978                 /* the chip adds 2 halflines automatically */
5979                 crtc_vtotal -= 1;
5980                 crtc_vblank_end -= 1;
5981
5982                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5983                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5984                 else
5985                         vsyncshift = adjusted_mode->crtc_hsync_start -
5986                                 adjusted_mode->crtc_htotal / 2;
5987                 if (vsyncshift < 0)
5988                         vsyncshift += adjusted_mode->crtc_htotal;
5989         }
5990
5991         if (INTEL_INFO(dev)->gen > 3)
5992                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5993
5994         I915_WRITE(HTOTAL(cpu_transcoder),
5995                    (adjusted_mode->crtc_hdisplay - 1) |
5996                    ((adjusted_mode->crtc_htotal - 1) << 16));
5997         I915_WRITE(HBLANK(cpu_transcoder),
5998                    (adjusted_mode->crtc_hblank_start - 1) |
5999                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6000         I915_WRITE(HSYNC(cpu_transcoder),
6001                    (adjusted_mode->crtc_hsync_start - 1) |
6002                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6003
6004         I915_WRITE(VTOTAL(cpu_transcoder),
6005                    (adjusted_mode->crtc_vdisplay - 1) |
6006                    ((crtc_vtotal - 1) << 16));
6007         I915_WRITE(VBLANK(cpu_transcoder),
6008                    (adjusted_mode->crtc_vblank_start - 1) |
6009                    ((crtc_vblank_end - 1) << 16));
6010         I915_WRITE(VSYNC(cpu_transcoder),
6011                    (adjusted_mode->crtc_vsync_start - 1) |
6012                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6013
6014         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6015          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6016          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6017          * bits. */
6018         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6019             (pipe == PIPE_B || pipe == PIPE_C))
6020                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6021
6022         /* pipesrc controls the size that is scaled from, which should
6023          * always be the user's requested size.
6024          */
6025         I915_WRITE(PIPESRC(pipe),
6026                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6027                    (intel_crtc->config.pipe_src_h - 1));
6028 }
6029
6030 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6031                                    struct intel_crtc_config *pipe_config)
6032 {
6033         struct drm_device *dev = crtc->base.dev;
6034         struct drm_i915_private *dev_priv = dev->dev_private;
6035         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6036         uint32_t tmp;
6037
6038         tmp = I915_READ(HTOTAL(cpu_transcoder));
6039         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6040         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6041         tmp = I915_READ(HBLANK(cpu_transcoder));
6042         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6043         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6044         tmp = I915_READ(HSYNC(cpu_transcoder));
6045         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6046         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6047
6048         tmp = I915_READ(VTOTAL(cpu_transcoder));
6049         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6050         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6051         tmp = I915_READ(VBLANK(cpu_transcoder));
6052         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6053         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6054         tmp = I915_READ(VSYNC(cpu_transcoder));
6055         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6056         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6057
6058         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6059                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6060                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6061                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6062         }
6063
6064         tmp = I915_READ(PIPESRC(crtc->pipe));
6065         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6066         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6067
6068         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6069         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6070 }
6071
6072 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6073                                  struct intel_crtc_config *pipe_config)
6074 {
6075         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6076         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6077         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6078         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6079
6080         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6081         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6082         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6083         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6084
6085         mode->flags = pipe_config->adjusted_mode.flags;
6086
6087         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6088         mode->flags |= pipe_config->adjusted_mode.flags;
6089 }
6090
6091 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6092 {
6093         struct drm_device *dev = intel_crtc->base.dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         uint32_t pipeconf;
6096
6097         pipeconf = 0;
6098
6099         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6100             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6101                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6102
6103         if (intel_crtc->config.double_wide)
6104                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6105
6106         /* only g4x and later have fancy bpc/dither controls */
6107         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6108                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6109                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6110                         pipeconf |= PIPECONF_DITHER_EN |
6111                                     PIPECONF_DITHER_TYPE_SP;
6112
6113                 switch (intel_crtc->config.pipe_bpp) {
6114                 case 18:
6115                         pipeconf |= PIPECONF_6BPC;
6116                         break;
6117                 case 24:
6118                         pipeconf |= PIPECONF_8BPC;
6119                         break;
6120                 case 30:
6121                         pipeconf |= PIPECONF_10BPC;
6122                         break;
6123                 default:
6124                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6125                         BUG();
6126                 }
6127         }
6128
6129         if (HAS_PIPE_CXSR(dev)) {
6130                 if (intel_crtc->lowfreq_avail) {
6131                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6132                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6133                 } else {
6134                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6135                 }
6136         }
6137
6138         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6139                 if (INTEL_INFO(dev)->gen < 4 ||
6140                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6141                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6142                 else
6143                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6144         } else
6145                 pipeconf |= PIPECONF_PROGRESSIVE;
6146
6147         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6148                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6149
6150         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6151         POSTING_READ(PIPECONF(intel_crtc->pipe));
6152 }
6153
6154 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6155                               int x, int y,
6156                               struct drm_framebuffer *fb)
6157 {
6158         struct drm_device *dev = crtc->dev;
6159         struct drm_i915_private *dev_priv = dev->dev_private;
6160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6161         int refclk, num_connectors = 0;
6162         intel_clock_t clock, reduced_clock;
6163         bool ok, has_reduced_clock = false;
6164         bool is_lvds = false, is_dsi = false;
6165         struct intel_encoder *encoder;
6166         const intel_limit_t *limit;
6167
6168         for_each_encoder_on_crtc(dev, crtc, encoder) {
6169                 switch (encoder->type) {
6170                 case INTEL_OUTPUT_LVDS:
6171                         is_lvds = true;
6172                         break;
6173                 case INTEL_OUTPUT_DSI:
6174                         is_dsi = true;
6175                         break;
6176                 }
6177
6178                 num_connectors++;
6179         }
6180
6181         if (is_dsi)
6182                 return 0;
6183
6184         if (!intel_crtc->config.clock_set) {
6185                 refclk = i9xx_get_refclk(crtc, num_connectors);
6186
6187                 /*
6188                  * Returns a set of divisors for the desired target clock with
6189                  * the given refclk, or FALSE.  The returned values represent
6190                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6191                  * 2) / p1 / p2.
6192                  */
6193                 limit = intel_limit(crtc, refclk);
6194                 ok = dev_priv->display.find_dpll(limit, crtc,
6195                                                  intel_crtc->config.port_clock,
6196                                                  refclk, NULL, &clock);
6197                 if (!ok) {
6198                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6199                         return -EINVAL;
6200                 }
6201
6202                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6203                         /*
6204                          * Ensure we match the reduced clock's P to the target
6205                          * clock.  If the clocks don't match, we can't switch
6206                          * the display clock by using the FP0/FP1. In such case
6207                          * we will disable the LVDS downclock feature.
6208                          */
6209                         has_reduced_clock =
6210                                 dev_priv->display.find_dpll(limit, crtc,
6211                                                             dev_priv->lvds_downclock,
6212                                                             refclk, &clock,
6213                                                             &reduced_clock);
6214                 }
6215                 /* Compat-code for transition, will disappear. */
6216                 intel_crtc->config.dpll.n = clock.n;
6217                 intel_crtc->config.dpll.m1 = clock.m1;
6218                 intel_crtc->config.dpll.m2 = clock.m2;
6219                 intel_crtc->config.dpll.p1 = clock.p1;
6220                 intel_crtc->config.dpll.p2 = clock.p2;
6221         }
6222
6223         if (IS_GEN2(dev)) {
6224                 i8xx_update_pll(intel_crtc,
6225                                 has_reduced_clock ? &reduced_clock : NULL,
6226                                 num_connectors);
6227         } else if (IS_CHERRYVIEW(dev)) {
6228                 chv_update_pll(intel_crtc);
6229         } else if (IS_VALLEYVIEW(dev)) {
6230                 vlv_update_pll(intel_crtc);
6231         } else {
6232                 i9xx_update_pll(intel_crtc,
6233                                 has_reduced_clock ? &reduced_clock : NULL,
6234                                 num_connectors);
6235         }
6236
6237         return 0;
6238 }
6239
6240 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6241                                  struct intel_crtc_config *pipe_config)
6242 {
6243         struct drm_device *dev = crtc->base.dev;
6244         struct drm_i915_private *dev_priv = dev->dev_private;
6245         uint32_t tmp;
6246
6247         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6248                 return;
6249
6250         tmp = I915_READ(PFIT_CONTROL);
6251         if (!(tmp & PFIT_ENABLE))
6252                 return;
6253
6254         /* Check whether the pfit is attached to our pipe. */
6255         if (INTEL_INFO(dev)->gen < 4) {
6256                 if (crtc->pipe != PIPE_B)
6257                         return;
6258         } else {
6259                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6260                         return;
6261         }
6262
6263         pipe_config->gmch_pfit.control = tmp;
6264         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6265         if (INTEL_INFO(dev)->gen < 5)
6266                 pipe_config->gmch_pfit.lvds_border_bits =
6267                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6268 }
6269
6270 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6271                                struct intel_crtc_config *pipe_config)
6272 {
6273         struct drm_device *dev = crtc->base.dev;
6274         struct drm_i915_private *dev_priv = dev->dev_private;
6275         int pipe = pipe_config->cpu_transcoder;
6276         intel_clock_t clock;
6277         u32 mdiv;
6278         int refclk = 100000;
6279
6280         /* In case of MIPI DPLL will not even be used */
6281         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6282                 return;
6283
6284         mutex_lock(&dev_priv->dpio_lock);
6285         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6286         mutex_unlock(&dev_priv->dpio_lock);
6287
6288         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6289         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6290         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6291         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6292         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6293
6294         vlv_clock(refclk, &clock);
6295
6296         /* clock.dot is the fast clock */
6297         pipe_config->port_clock = clock.dot / 5;
6298 }
6299
6300 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6301                                   struct intel_plane_config *plane_config)
6302 {
6303         struct drm_device *dev = crtc->base.dev;
6304         struct drm_i915_private *dev_priv = dev->dev_private;
6305         u32 val, base, offset;
6306         int pipe = crtc->pipe, plane = crtc->plane;
6307         int fourcc, pixel_format;
6308         int aligned_height;
6309
6310         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6311         if (!crtc->base.primary->fb) {
6312                 DRM_DEBUG_KMS("failed to alloc fb\n");
6313                 return;
6314         }
6315
6316         val = I915_READ(DSPCNTR(plane));
6317
6318         if (INTEL_INFO(dev)->gen >= 4)
6319                 if (val & DISPPLANE_TILED)
6320                         plane_config->tiled = true;
6321
6322         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6323         fourcc = intel_format_to_fourcc(pixel_format);
6324         crtc->base.primary->fb->pixel_format = fourcc;
6325         crtc->base.primary->fb->bits_per_pixel =
6326                 drm_format_plane_cpp(fourcc, 0) * 8;
6327
6328         if (INTEL_INFO(dev)->gen >= 4) {
6329                 if (plane_config->tiled)
6330                         offset = I915_READ(DSPTILEOFF(plane));
6331                 else
6332                         offset = I915_READ(DSPLINOFF(plane));
6333                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6334         } else {
6335                 base = I915_READ(DSPADDR(plane));
6336         }
6337         plane_config->base = base;
6338
6339         val = I915_READ(PIPESRC(pipe));
6340         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6341         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6342
6343         val = I915_READ(DSPSTRIDE(pipe));
6344         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6345
6346         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6347                                             plane_config->tiled);
6348
6349         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6350                                         aligned_height);
6351
6352         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6353                       pipe, plane, crtc->base.primary->fb->width,
6354                       crtc->base.primary->fb->height,
6355                       crtc->base.primary->fb->bits_per_pixel, base,
6356                       crtc->base.primary->fb->pitches[0],
6357                       plane_config->size);
6358
6359 }
6360
6361 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6362                                struct intel_crtc_config *pipe_config)
6363 {
6364         struct drm_device *dev = crtc->base.dev;
6365         struct drm_i915_private *dev_priv = dev->dev_private;
6366         int pipe = pipe_config->cpu_transcoder;
6367         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6368         intel_clock_t clock;
6369         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6370         int refclk = 100000;
6371
6372         mutex_lock(&dev_priv->dpio_lock);
6373         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6374         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6375         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6376         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6377         mutex_unlock(&dev_priv->dpio_lock);
6378
6379         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6380         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6381         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6382         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6383         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6384
6385         chv_clock(refclk, &clock);
6386
6387         /* clock.dot is the fast clock */
6388         pipe_config->port_clock = clock.dot / 5;
6389 }
6390
6391 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6392                                  struct intel_crtc_config *pipe_config)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         uint32_t tmp;
6397
6398         if (!intel_display_power_enabled(dev_priv,
6399                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6400                 return false;
6401
6402         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6403         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6404
6405         tmp = I915_READ(PIPECONF(crtc->pipe));
6406         if (!(tmp & PIPECONF_ENABLE))
6407                 return false;
6408
6409         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6410                 switch (tmp & PIPECONF_BPC_MASK) {
6411                 case PIPECONF_6BPC:
6412                         pipe_config->pipe_bpp = 18;
6413                         break;
6414                 case PIPECONF_8BPC:
6415                         pipe_config->pipe_bpp = 24;
6416                         break;
6417                 case PIPECONF_10BPC:
6418                         pipe_config->pipe_bpp = 30;
6419                         break;
6420                 default:
6421                         break;
6422                 }
6423         }
6424
6425         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6426                 pipe_config->limited_color_range = true;
6427
6428         if (INTEL_INFO(dev)->gen < 4)
6429                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6430
6431         intel_get_pipe_timings(crtc, pipe_config);
6432
6433         i9xx_get_pfit_config(crtc, pipe_config);
6434
6435         if (INTEL_INFO(dev)->gen >= 4) {
6436                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6437                 pipe_config->pixel_multiplier =
6438                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6439                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6440                 pipe_config->dpll_hw_state.dpll_md = tmp;
6441         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6442                 tmp = I915_READ(DPLL(crtc->pipe));
6443                 pipe_config->pixel_multiplier =
6444                         ((tmp & SDVO_MULTIPLIER_MASK)
6445                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6446         } else {
6447                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6448                  * port and will be fixed up in the encoder->get_config
6449                  * function. */
6450                 pipe_config->pixel_multiplier = 1;
6451         }
6452         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6453         if (!IS_VALLEYVIEW(dev)) {
6454                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6455                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6456         } else {
6457                 /* Mask out read-only status bits. */
6458                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6459                                                      DPLL_PORTC_READY_MASK |
6460                                                      DPLL_PORTB_READY_MASK);
6461         }
6462
6463         if (IS_CHERRYVIEW(dev))
6464                 chv_crtc_clock_get(crtc, pipe_config);
6465         else if (IS_VALLEYVIEW(dev))
6466                 vlv_crtc_clock_get(crtc, pipe_config);
6467         else
6468                 i9xx_crtc_clock_get(crtc, pipe_config);
6469
6470         return true;
6471 }
6472
6473 static void ironlake_init_pch_refclk(struct drm_device *dev)
6474 {
6475         struct drm_i915_private *dev_priv = dev->dev_private;
6476         struct intel_encoder *encoder;
6477         u32 val, final;
6478         bool has_lvds = false;
6479         bool has_cpu_edp = false;
6480         bool has_panel = false;
6481         bool has_ck505 = false;
6482         bool can_ssc = false;
6483
6484         /* We need to take the global config into account */
6485         for_each_intel_encoder(dev, encoder) {
6486                 switch (encoder->type) {
6487                 case INTEL_OUTPUT_LVDS:
6488                         has_panel = true;
6489                         has_lvds = true;
6490                         break;
6491                 case INTEL_OUTPUT_EDP:
6492                         has_panel = true;
6493                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6494                                 has_cpu_edp = true;
6495                         break;
6496                 }
6497         }
6498
6499         if (HAS_PCH_IBX(dev)) {
6500                 has_ck505 = dev_priv->vbt.display_clock_mode;
6501                 can_ssc = has_ck505;
6502         } else {
6503                 has_ck505 = false;
6504                 can_ssc = true;
6505         }
6506
6507         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6508                       has_panel, has_lvds, has_ck505);
6509
6510         /* Ironlake: try to setup display ref clock before DPLL
6511          * enabling. This is only under driver's control after
6512          * PCH B stepping, previous chipset stepping should be
6513          * ignoring this setting.
6514          */
6515         val = I915_READ(PCH_DREF_CONTROL);
6516
6517         /* As we must carefully and slowly disable/enable each source in turn,
6518          * compute the final state we want first and check if we need to
6519          * make any changes at all.
6520          */
6521         final = val;
6522         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6523         if (has_ck505)
6524                 final |= DREF_NONSPREAD_CK505_ENABLE;
6525         else
6526                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6527
6528         final &= ~DREF_SSC_SOURCE_MASK;
6529         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6530         final &= ~DREF_SSC1_ENABLE;
6531
6532         if (has_panel) {
6533                 final |= DREF_SSC_SOURCE_ENABLE;
6534
6535                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6536                         final |= DREF_SSC1_ENABLE;
6537
6538                 if (has_cpu_edp) {
6539                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6540                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6541                         else
6542                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6543                 } else
6544                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6545         } else {
6546                 final |= DREF_SSC_SOURCE_DISABLE;
6547                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6548         }
6549
6550         if (final == val)
6551                 return;
6552
6553         /* Always enable nonspread source */
6554         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6555
6556         if (has_ck505)
6557                 val |= DREF_NONSPREAD_CK505_ENABLE;
6558         else
6559                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6560
6561         if (has_panel) {
6562                 val &= ~DREF_SSC_SOURCE_MASK;
6563                 val |= DREF_SSC_SOURCE_ENABLE;
6564
6565                 /* SSC must be turned on before enabling the CPU output  */
6566                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6567                         DRM_DEBUG_KMS("Using SSC on panel\n");
6568                         val |= DREF_SSC1_ENABLE;
6569                 } else
6570                         val &= ~DREF_SSC1_ENABLE;
6571
6572                 /* Get SSC going before enabling the outputs */
6573                 I915_WRITE(PCH_DREF_CONTROL, val);
6574                 POSTING_READ(PCH_DREF_CONTROL);
6575                 udelay(200);
6576
6577                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6578
6579                 /* Enable CPU source on CPU attached eDP */
6580                 if (has_cpu_edp) {
6581                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6582                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6583                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6584                         } else
6585                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6586                 } else
6587                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6588
6589                 I915_WRITE(PCH_DREF_CONTROL, val);
6590                 POSTING_READ(PCH_DREF_CONTROL);
6591                 udelay(200);
6592         } else {
6593                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6594
6595                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6596
6597                 /* Turn off CPU output */
6598                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6599
6600                 I915_WRITE(PCH_DREF_CONTROL, val);
6601                 POSTING_READ(PCH_DREF_CONTROL);
6602                 udelay(200);
6603
6604                 /* Turn off the SSC source */
6605                 val &= ~DREF_SSC_SOURCE_MASK;
6606                 val |= DREF_SSC_SOURCE_DISABLE;
6607
6608                 /* Turn off SSC1 */
6609                 val &= ~DREF_SSC1_ENABLE;
6610
6611                 I915_WRITE(PCH_DREF_CONTROL, val);
6612                 POSTING_READ(PCH_DREF_CONTROL);
6613                 udelay(200);
6614         }
6615
6616         BUG_ON(val != final);
6617 }
6618
6619 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6620 {
6621         uint32_t tmp;
6622
6623         tmp = I915_READ(SOUTH_CHICKEN2);
6624         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6625         I915_WRITE(SOUTH_CHICKEN2, tmp);
6626
6627         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6628                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6629                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6630
6631         tmp = I915_READ(SOUTH_CHICKEN2);
6632         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6633         I915_WRITE(SOUTH_CHICKEN2, tmp);
6634
6635         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6636                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6637                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6638 }
6639
6640 /* WaMPhyProgramming:hsw */
6641 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6642 {
6643         uint32_t tmp;
6644
6645         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6646         tmp &= ~(0xFF << 24);
6647         tmp |= (0x12 << 24);
6648         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6649
6650         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6651         tmp |= (1 << 11);
6652         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6653
6654         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6655         tmp |= (1 << 11);
6656         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6657
6658         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6659         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6660         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6661
6662         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6663         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6664         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6665
6666         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6667         tmp &= ~(7 << 13);
6668         tmp |= (5 << 13);
6669         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6670
6671         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6672         tmp &= ~(7 << 13);
6673         tmp |= (5 << 13);
6674         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6675
6676         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6677         tmp &= ~0xFF;
6678         tmp |= 0x1C;
6679         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6680
6681         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6682         tmp &= ~0xFF;
6683         tmp |= 0x1C;
6684         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6685
6686         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6687         tmp &= ~(0xFF << 16);
6688         tmp |= (0x1C << 16);
6689         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6690
6691         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6692         tmp &= ~(0xFF << 16);
6693         tmp |= (0x1C << 16);
6694         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6695
6696         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6697         tmp |= (1 << 27);
6698         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6699
6700         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6701         tmp |= (1 << 27);
6702         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6703
6704         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6705         tmp &= ~(0xF << 28);
6706         tmp |= (4 << 28);
6707         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6708
6709         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6710         tmp &= ~(0xF << 28);
6711         tmp |= (4 << 28);
6712         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6713 }
6714
6715 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6716  * Programming" based on the parameters passed:
6717  * - Sequence to enable CLKOUT_DP
6718  * - Sequence to enable CLKOUT_DP without spread
6719  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6720  */
6721 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6722                                  bool with_fdi)
6723 {
6724         struct drm_i915_private *dev_priv = dev->dev_private;
6725         uint32_t reg, tmp;
6726
6727         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6728                 with_spread = true;
6729         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6730                  with_fdi, "LP PCH doesn't have FDI\n"))
6731                 with_fdi = false;
6732
6733         mutex_lock(&dev_priv->dpio_lock);
6734
6735         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6736         tmp &= ~SBI_SSCCTL_DISABLE;
6737         tmp |= SBI_SSCCTL_PATHALT;
6738         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6739
6740         udelay(24);
6741
6742         if (with_spread) {
6743                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6744                 tmp &= ~SBI_SSCCTL_PATHALT;
6745                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6746
6747                 if (with_fdi) {
6748                         lpt_reset_fdi_mphy(dev_priv);
6749                         lpt_program_fdi_mphy(dev_priv);
6750                 }
6751         }
6752
6753         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6754                SBI_GEN0 : SBI_DBUFF0;
6755         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6756         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6757         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6758
6759         mutex_unlock(&dev_priv->dpio_lock);
6760 }
6761
6762 /* Sequence to disable CLKOUT_DP */
6763 static void lpt_disable_clkout_dp(struct drm_device *dev)
6764 {
6765         struct drm_i915_private *dev_priv = dev->dev_private;
6766         uint32_t reg, tmp;
6767
6768         mutex_lock(&dev_priv->dpio_lock);
6769
6770         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6771                SBI_GEN0 : SBI_DBUFF0;
6772         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6773         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6774         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6775
6776         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6777         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6778                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6779                         tmp |= SBI_SSCCTL_PATHALT;
6780                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6781                         udelay(32);
6782                 }
6783                 tmp |= SBI_SSCCTL_DISABLE;
6784                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6785         }
6786
6787         mutex_unlock(&dev_priv->dpio_lock);
6788 }
6789
6790 static void lpt_init_pch_refclk(struct drm_device *dev)
6791 {
6792         struct intel_encoder *encoder;
6793         bool has_vga = false;
6794
6795         for_each_intel_encoder(dev, encoder) {
6796                 switch (encoder->type) {
6797                 case INTEL_OUTPUT_ANALOG:
6798                         has_vga = true;
6799                         break;
6800                 }
6801         }
6802
6803         if (has_vga)
6804                 lpt_enable_clkout_dp(dev, true, true);
6805         else
6806                 lpt_disable_clkout_dp(dev);
6807 }
6808
6809 /*
6810  * Initialize reference clocks when the driver loads
6811  */
6812 void intel_init_pch_refclk(struct drm_device *dev)
6813 {
6814         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6815                 ironlake_init_pch_refclk(dev);
6816         else if (HAS_PCH_LPT(dev))
6817                 lpt_init_pch_refclk(dev);
6818 }
6819
6820 static int ironlake_get_refclk(struct drm_crtc *crtc)
6821 {
6822         struct drm_device *dev = crtc->dev;
6823         struct drm_i915_private *dev_priv = dev->dev_private;
6824         struct intel_encoder *encoder;
6825         int num_connectors = 0;
6826         bool is_lvds = false;
6827
6828         for_each_encoder_on_crtc(dev, crtc, encoder) {
6829                 switch (encoder->type) {
6830                 case INTEL_OUTPUT_LVDS:
6831                         is_lvds = true;
6832                         break;
6833                 }
6834                 num_connectors++;
6835         }
6836
6837         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6838                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6839                               dev_priv->vbt.lvds_ssc_freq);
6840                 return dev_priv->vbt.lvds_ssc_freq;
6841         }
6842
6843         return 120000;
6844 }
6845
6846 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6847 {
6848         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6850         int pipe = intel_crtc->pipe;
6851         uint32_t val;
6852
6853         val = 0;
6854
6855         switch (intel_crtc->config.pipe_bpp) {
6856         case 18:
6857                 val |= PIPECONF_6BPC;
6858                 break;
6859         case 24:
6860                 val |= PIPECONF_8BPC;
6861                 break;
6862         case 30:
6863                 val |= PIPECONF_10BPC;
6864                 break;
6865         case 36:
6866                 val |= PIPECONF_12BPC;
6867                 break;
6868         default:
6869                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6870                 BUG();
6871         }
6872
6873         if (intel_crtc->config.dither)
6874                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6875
6876         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6877                 val |= PIPECONF_INTERLACED_ILK;
6878         else
6879                 val |= PIPECONF_PROGRESSIVE;
6880
6881         if (intel_crtc->config.limited_color_range)
6882                 val |= PIPECONF_COLOR_RANGE_SELECT;
6883
6884         I915_WRITE(PIPECONF(pipe), val);
6885         POSTING_READ(PIPECONF(pipe));
6886 }
6887
6888 /*
6889  * Set up the pipe CSC unit.
6890  *
6891  * Currently only full range RGB to limited range RGB conversion
6892  * is supported, but eventually this should handle various
6893  * RGB<->YCbCr scenarios as well.
6894  */
6895 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6896 {
6897         struct drm_device *dev = crtc->dev;
6898         struct drm_i915_private *dev_priv = dev->dev_private;
6899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6900         int pipe = intel_crtc->pipe;
6901         uint16_t coeff = 0x7800; /* 1.0 */
6902
6903         /*
6904          * TODO: Check what kind of values actually come out of the pipe
6905          * with these coeff/postoff values and adjust to get the best
6906          * accuracy. Perhaps we even need to take the bpc value into
6907          * consideration.
6908          */
6909
6910         if (intel_crtc->config.limited_color_range)
6911                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6912
6913         /*
6914          * GY/GU and RY/RU should be the other way around according
6915          * to BSpec, but reality doesn't agree. Just set them up in
6916          * a way that results in the correct picture.
6917          */
6918         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6919         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6920
6921         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6922         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6923
6924         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6925         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6926
6927         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6928         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6929         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6930
6931         if (INTEL_INFO(dev)->gen > 6) {
6932                 uint16_t postoff = 0;
6933
6934                 if (intel_crtc->config.limited_color_range)
6935                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6936
6937                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6938                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6939                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6940
6941                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6942         } else {
6943                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6944
6945                 if (intel_crtc->config.limited_color_range)
6946                         mode |= CSC_BLACK_SCREEN_OFFSET;
6947
6948                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6949         }
6950 }
6951
6952 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6953 {
6954         struct drm_device *dev = crtc->dev;
6955         struct drm_i915_private *dev_priv = dev->dev_private;
6956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957         enum pipe pipe = intel_crtc->pipe;
6958         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6959         uint32_t val;
6960
6961         val = 0;
6962
6963         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6964                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6965
6966         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6967                 val |= PIPECONF_INTERLACED_ILK;
6968         else
6969                 val |= PIPECONF_PROGRESSIVE;
6970
6971         I915_WRITE(PIPECONF(cpu_transcoder), val);
6972         POSTING_READ(PIPECONF(cpu_transcoder));
6973
6974         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6975         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6976
6977         if (IS_BROADWELL(dev)) {
6978                 val = 0;
6979
6980                 switch (intel_crtc->config.pipe_bpp) {
6981                 case 18:
6982                         val |= PIPEMISC_DITHER_6_BPC;
6983                         break;
6984                 case 24:
6985                         val |= PIPEMISC_DITHER_8_BPC;
6986                         break;
6987                 case 30:
6988                         val |= PIPEMISC_DITHER_10_BPC;
6989                         break;
6990                 case 36:
6991                         val |= PIPEMISC_DITHER_12_BPC;
6992                         break;
6993                 default:
6994                         /* Case prevented by pipe_config_set_bpp. */
6995                         BUG();
6996                 }
6997
6998                 if (intel_crtc->config.dither)
6999                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7000
7001                 I915_WRITE(PIPEMISC(pipe), val);
7002         }
7003 }
7004
7005 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7006                                     intel_clock_t *clock,
7007                                     bool *has_reduced_clock,
7008                                     intel_clock_t *reduced_clock)
7009 {
7010         struct drm_device *dev = crtc->dev;
7011         struct drm_i915_private *dev_priv = dev->dev_private;
7012         struct intel_encoder *intel_encoder;
7013         int refclk;
7014         const intel_limit_t *limit;
7015         bool ret, is_lvds = false;
7016
7017         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7018                 switch (intel_encoder->type) {
7019                 case INTEL_OUTPUT_LVDS:
7020                         is_lvds = true;
7021                         break;
7022                 }
7023         }
7024
7025         refclk = ironlake_get_refclk(crtc);
7026
7027         /*
7028          * Returns a set of divisors for the desired target clock with the given
7029          * refclk, or FALSE.  The returned values represent the clock equation:
7030          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7031          */
7032         limit = intel_limit(crtc, refclk);
7033         ret = dev_priv->display.find_dpll(limit, crtc,
7034                                           to_intel_crtc(crtc)->config.port_clock,
7035                                           refclk, NULL, clock);
7036         if (!ret)
7037                 return false;
7038
7039         if (is_lvds && dev_priv->lvds_downclock_avail) {
7040                 /*
7041                  * Ensure we match the reduced clock's P to the target clock.
7042                  * If the clocks don't match, we can't switch the display clock
7043                  * by using the FP0/FP1. In such case we will disable the LVDS
7044                  * downclock feature.
7045                 */
7046                 *has_reduced_clock =
7047                         dev_priv->display.find_dpll(limit, crtc,
7048                                                     dev_priv->lvds_downclock,
7049                                                     refclk, clock,
7050                                                     reduced_clock);
7051         }
7052
7053         return true;
7054 }
7055
7056 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7057 {
7058         /*
7059          * Account for spread spectrum to avoid
7060          * oversubscribing the link. Max center spread
7061          * is 2.5%; use 5% for safety's sake.
7062          */
7063         u32 bps = target_clock * bpp * 21 / 20;
7064         return DIV_ROUND_UP(bps, link_bw * 8);
7065 }
7066
7067 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7068 {
7069         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7070 }
7071
7072 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7073                                       u32 *fp,
7074                                       intel_clock_t *reduced_clock, u32 *fp2)
7075 {
7076         struct drm_crtc *crtc = &intel_crtc->base;
7077         struct drm_device *dev = crtc->dev;
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         struct intel_encoder *intel_encoder;
7080         uint32_t dpll;
7081         int factor, num_connectors = 0;
7082         bool is_lvds = false, is_sdvo = false;
7083
7084         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7085                 switch (intel_encoder->type) {
7086                 case INTEL_OUTPUT_LVDS:
7087                         is_lvds = true;
7088                         break;
7089                 case INTEL_OUTPUT_SDVO:
7090                 case INTEL_OUTPUT_HDMI:
7091                         is_sdvo = true;
7092                         break;
7093                 }
7094
7095                 num_connectors++;
7096         }
7097
7098         /* Enable autotuning of the PLL clock (if permissible) */
7099         factor = 21;
7100         if (is_lvds) {
7101                 if ((intel_panel_use_ssc(dev_priv) &&
7102                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7103                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7104                         factor = 25;
7105         } else if (intel_crtc->config.sdvo_tv_clock)
7106                 factor = 20;
7107
7108         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7109                 *fp |= FP_CB_TUNE;
7110
7111         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7112                 *fp2 |= FP_CB_TUNE;
7113
7114         dpll = 0;
7115
7116         if (is_lvds)
7117                 dpll |= DPLLB_MODE_LVDS;
7118         else
7119                 dpll |= DPLLB_MODE_DAC_SERIAL;
7120
7121         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7122                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7123
7124         if (is_sdvo)
7125                 dpll |= DPLL_SDVO_HIGH_SPEED;
7126         if (intel_crtc->config.has_dp_encoder)
7127                 dpll |= DPLL_SDVO_HIGH_SPEED;
7128
7129         /* compute bitmask from p1 value */
7130         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7131         /* also FPA1 */
7132         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7133
7134         switch (intel_crtc->config.dpll.p2) {
7135         case 5:
7136                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7137                 break;
7138         case 7:
7139                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7140                 break;
7141         case 10:
7142                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7143                 break;
7144         case 14:
7145                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7146                 break;
7147         }
7148
7149         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7150                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7151         else
7152                 dpll |= PLL_REF_INPUT_DREFCLK;
7153
7154         return dpll | DPLL_VCO_ENABLE;
7155 }
7156
7157 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7158                                   int x, int y,
7159                                   struct drm_framebuffer *fb)
7160 {
7161         struct drm_device *dev = crtc->dev;
7162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7163         int num_connectors = 0;
7164         intel_clock_t clock, reduced_clock;
7165         u32 dpll = 0, fp = 0, fp2 = 0;
7166         bool ok, has_reduced_clock = false;
7167         bool is_lvds = false;
7168         struct intel_encoder *encoder;
7169         struct intel_shared_dpll *pll;
7170
7171         for_each_encoder_on_crtc(dev, crtc, encoder) {
7172                 switch (encoder->type) {
7173                 case INTEL_OUTPUT_LVDS:
7174                         is_lvds = true;
7175                         break;
7176                 }
7177
7178                 num_connectors++;
7179         }
7180
7181         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7182              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7183
7184         ok = ironlake_compute_clocks(crtc, &clock,
7185                                      &has_reduced_clock, &reduced_clock);
7186         if (!ok && !intel_crtc->config.clock_set) {
7187                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7188                 return -EINVAL;
7189         }
7190         /* Compat-code for transition, will disappear. */
7191         if (!intel_crtc->config.clock_set) {
7192                 intel_crtc->config.dpll.n = clock.n;
7193                 intel_crtc->config.dpll.m1 = clock.m1;
7194                 intel_crtc->config.dpll.m2 = clock.m2;
7195                 intel_crtc->config.dpll.p1 = clock.p1;
7196                 intel_crtc->config.dpll.p2 = clock.p2;
7197         }
7198
7199         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7200         if (intel_crtc->config.has_pch_encoder) {
7201                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7202                 if (has_reduced_clock)
7203                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7204
7205                 dpll = ironlake_compute_dpll(intel_crtc,
7206                                              &fp, &reduced_clock,
7207                                              has_reduced_clock ? &fp2 : NULL);
7208
7209                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7210                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7211                 if (has_reduced_clock)
7212                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7213                 else
7214                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7215
7216                 pll = intel_get_shared_dpll(intel_crtc);
7217                 if (pll == NULL) {
7218                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7219                                          pipe_name(intel_crtc->pipe));
7220                         return -EINVAL;
7221                 }
7222         } else
7223                 intel_put_shared_dpll(intel_crtc);
7224
7225         if (is_lvds && has_reduced_clock && i915.powersave)
7226                 intel_crtc->lowfreq_avail = true;
7227         else
7228                 intel_crtc->lowfreq_avail = false;
7229
7230         return 0;
7231 }
7232
7233 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7234                                          struct intel_link_m_n *m_n)
7235 {
7236         struct drm_device *dev = crtc->base.dev;
7237         struct drm_i915_private *dev_priv = dev->dev_private;
7238         enum pipe pipe = crtc->pipe;
7239
7240         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7241         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7242         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7243                 & ~TU_SIZE_MASK;
7244         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7245         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7246                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7247 }
7248
7249 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7250                                          enum transcoder transcoder,
7251                                          struct intel_link_m_n *m_n,
7252                                          struct intel_link_m_n *m2_n2)
7253 {
7254         struct drm_device *dev = crtc->base.dev;
7255         struct drm_i915_private *dev_priv = dev->dev_private;
7256         enum pipe pipe = crtc->pipe;
7257
7258         if (INTEL_INFO(dev)->gen >= 5) {
7259                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7260                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7261                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7262                         & ~TU_SIZE_MASK;
7263                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7264                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7265                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7266                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7267                  * gen < 8) and if DRRS is supported (to make sure the
7268                  * registers are not unnecessarily read).
7269                  */
7270                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7271                         crtc->config.has_drrs) {
7272                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7273                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7274                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7275                                         & ~TU_SIZE_MASK;
7276                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7277                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7278                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7279                 }
7280         } else {
7281                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7282                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7283                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7284                         & ~TU_SIZE_MASK;
7285                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7286                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7287                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7288         }
7289 }
7290
7291 void intel_dp_get_m_n(struct intel_crtc *crtc,
7292                       struct intel_crtc_config *pipe_config)
7293 {
7294         if (crtc->config.has_pch_encoder)
7295                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7296         else
7297                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7298                                              &pipe_config->dp_m_n,
7299                                              &pipe_config->dp_m2_n2);
7300 }
7301
7302 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7303                                         struct intel_crtc_config *pipe_config)
7304 {
7305         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7306                                      &pipe_config->fdi_m_n, NULL);
7307 }
7308
7309 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7310                                      struct intel_crtc_config *pipe_config)
7311 {
7312         struct drm_device *dev = crtc->base.dev;
7313         struct drm_i915_private *dev_priv = dev->dev_private;
7314         uint32_t tmp;
7315
7316         tmp = I915_READ(PF_CTL(crtc->pipe));
7317
7318         if (tmp & PF_ENABLE) {
7319                 pipe_config->pch_pfit.enabled = true;
7320                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7321                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7322
7323                 /* We currently do not free assignements of panel fitters on
7324                  * ivb/hsw (since we don't use the higher upscaling modes which
7325                  * differentiates them) so just WARN about this case for now. */
7326                 if (IS_GEN7(dev)) {
7327                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7328                                 PF_PIPE_SEL_IVB(crtc->pipe));
7329                 }
7330         }
7331 }
7332
7333 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7334                                       struct intel_plane_config *plane_config)
7335 {
7336         struct drm_device *dev = crtc->base.dev;
7337         struct drm_i915_private *dev_priv = dev->dev_private;
7338         u32 val, base, offset;
7339         int pipe = crtc->pipe, plane = crtc->plane;
7340         int fourcc, pixel_format;
7341         int aligned_height;
7342
7343         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7344         if (!crtc->base.primary->fb) {
7345                 DRM_DEBUG_KMS("failed to alloc fb\n");
7346                 return;
7347         }
7348
7349         val = I915_READ(DSPCNTR(plane));
7350
7351         if (INTEL_INFO(dev)->gen >= 4)
7352                 if (val & DISPPLANE_TILED)
7353                         plane_config->tiled = true;
7354
7355         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7356         fourcc = intel_format_to_fourcc(pixel_format);
7357         crtc->base.primary->fb->pixel_format = fourcc;
7358         crtc->base.primary->fb->bits_per_pixel =
7359                 drm_format_plane_cpp(fourcc, 0) * 8;
7360
7361         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7362         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7363                 offset = I915_READ(DSPOFFSET(plane));
7364         } else {
7365                 if (plane_config->tiled)
7366                         offset = I915_READ(DSPTILEOFF(plane));
7367                 else
7368                         offset = I915_READ(DSPLINOFF(plane));
7369         }
7370         plane_config->base = base;
7371
7372         val = I915_READ(PIPESRC(pipe));
7373         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7374         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7375
7376         val = I915_READ(DSPSTRIDE(pipe));
7377         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7378
7379         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7380                                             plane_config->tiled);
7381
7382         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7383                                         aligned_height);
7384
7385         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7386                       pipe, plane, crtc->base.primary->fb->width,
7387                       crtc->base.primary->fb->height,
7388                       crtc->base.primary->fb->bits_per_pixel, base,
7389                       crtc->base.primary->fb->pitches[0],
7390                       plane_config->size);
7391 }
7392
7393 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7394                                      struct intel_crtc_config *pipe_config)
7395 {
7396         struct drm_device *dev = crtc->base.dev;
7397         struct drm_i915_private *dev_priv = dev->dev_private;
7398         uint32_t tmp;
7399
7400         if (!intel_display_power_enabled(dev_priv,
7401                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7402                 return false;
7403
7404         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7405         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7406
7407         tmp = I915_READ(PIPECONF(crtc->pipe));
7408         if (!(tmp & PIPECONF_ENABLE))
7409                 return false;
7410
7411         switch (tmp & PIPECONF_BPC_MASK) {
7412         case PIPECONF_6BPC:
7413                 pipe_config->pipe_bpp = 18;
7414                 break;
7415         case PIPECONF_8BPC:
7416                 pipe_config->pipe_bpp = 24;
7417                 break;
7418         case PIPECONF_10BPC:
7419                 pipe_config->pipe_bpp = 30;
7420                 break;
7421         case PIPECONF_12BPC:
7422                 pipe_config->pipe_bpp = 36;
7423                 break;
7424         default:
7425                 break;
7426         }
7427
7428         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7429                 pipe_config->limited_color_range = true;
7430
7431         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7432                 struct intel_shared_dpll *pll;
7433
7434                 pipe_config->has_pch_encoder = true;
7435
7436                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7437                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7438                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7439
7440                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7441
7442                 if (HAS_PCH_IBX(dev_priv->dev)) {
7443                         pipe_config->shared_dpll =
7444                                 (enum intel_dpll_id) crtc->pipe;
7445                 } else {
7446                         tmp = I915_READ(PCH_DPLL_SEL);
7447                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7448                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7449                         else
7450                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7451                 }
7452
7453                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7454
7455                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7456                                            &pipe_config->dpll_hw_state));
7457
7458                 tmp = pipe_config->dpll_hw_state.dpll;
7459                 pipe_config->pixel_multiplier =
7460                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7461                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7462
7463                 ironlake_pch_clock_get(crtc, pipe_config);
7464         } else {
7465                 pipe_config->pixel_multiplier = 1;
7466         }
7467
7468         intel_get_pipe_timings(crtc, pipe_config);
7469
7470         ironlake_get_pfit_config(crtc, pipe_config);
7471
7472         return true;
7473 }
7474
7475 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7476 {
7477         struct drm_device *dev = dev_priv->dev;
7478         struct intel_crtc *crtc;
7479
7480         for_each_intel_crtc(dev, crtc)
7481                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7482                      pipe_name(crtc->pipe));
7483
7484         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7485         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7486         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7487         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7488         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7489         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7490              "CPU PWM1 enabled\n");
7491         if (IS_HASWELL(dev))
7492                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7493                      "CPU PWM2 enabled\n");
7494         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7495              "PCH PWM1 enabled\n");
7496         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7497              "Utility pin enabled\n");
7498         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7499
7500         /*
7501          * In theory we can still leave IRQs enabled, as long as only the HPD
7502          * interrupts remain enabled. We used to check for that, but since it's
7503          * gen-specific and since we only disable LCPLL after we fully disable
7504          * the interrupts, the check below should be enough.
7505          */
7506         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7507 }
7508
7509 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7510 {
7511         struct drm_device *dev = dev_priv->dev;
7512
7513         if (IS_HASWELL(dev))
7514                 return I915_READ(D_COMP_HSW);
7515         else
7516                 return I915_READ(D_COMP_BDW);
7517 }
7518
7519 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7520 {
7521         struct drm_device *dev = dev_priv->dev;
7522
7523         if (IS_HASWELL(dev)) {
7524                 mutex_lock(&dev_priv->rps.hw_lock);
7525                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7526                                             val))
7527                         DRM_ERROR("Failed to write to D_COMP\n");
7528                 mutex_unlock(&dev_priv->rps.hw_lock);
7529         } else {
7530                 I915_WRITE(D_COMP_BDW, val);
7531                 POSTING_READ(D_COMP_BDW);
7532         }
7533 }
7534
7535 /*
7536  * This function implements pieces of two sequences from BSpec:
7537  * - Sequence for display software to disable LCPLL
7538  * - Sequence for display software to allow package C8+
7539  * The steps implemented here are just the steps that actually touch the LCPLL
7540  * register. Callers should take care of disabling all the display engine
7541  * functions, doing the mode unset, fixing interrupts, etc.
7542  */
7543 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7544                               bool switch_to_fclk, bool allow_power_down)
7545 {
7546         uint32_t val;
7547
7548         assert_can_disable_lcpll(dev_priv);
7549
7550         val = I915_READ(LCPLL_CTL);
7551
7552         if (switch_to_fclk) {
7553                 val |= LCPLL_CD_SOURCE_FCLK;
7554                 I915_WRITE(LCPLL_CTL, val);
7555
7556                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7557                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7558                         DRM_ERROR("Switching to FCLK failed\n");
7559
7560                 val = I915_READ(LCPLL_CTL);
7561         }
7562
7563         val |= LCPLL_PLL_DISABLE;
7564         I915_WRITE(LCPLL_CTL, val);
7565         POSTING_READ(LCPLL_CTL);
7566
7567         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7568                 DRM_ERROR("LCPLL still locked\n");
7569
7570         val = hsw_read_dcomp(dev_priv);
7571         val |= D_COMP_COMP_DISABLE;
7572         hsw_write_dcomp(dev_priv, val);
7573         ndelay(100);
7574
7575         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7576                      1))
7577                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7578
7579         if (allow_power_down) {
7580                 val = I915_READ(LCPLL_CTL);
7581                 val |= LCPLL_POWER_DOWN_ALLOW;
7582                 I915_WRITE(LCPLL_CTL, val);
7583                 POSTING_READ(LCPLL_CTL);
7584         }
7585 }
7586
7587 /*
7588  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7589  * source.
7590  */
7591 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7592 {
7593         uint32_t val;
7594         unsigned long irqflags;
7595
7596         val = I915_READ(LCPLL_CTL);
7597
7598         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7599                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7600                 return;
7601
7602         /*
7603          * Make sure we're not on PC8 state before disabling PC8, otherwise
7604          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7605          *
7606          * The other problem is that hsw_restore_lcpll() is called as part of
7607          * the runtime PM resume sequence, so we can't just call
7608          * gen6_gt_force_wake_get() because that function calls
7609          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7610          * while we are on the resume sequence. So to solve this problem we have
7611          * to call special forcewake code that doesn't touch runtime PM and
7612          * doesn't enable the forcewake delayed work.
7613          */
7614         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7615         if (dev_priv->uncore.forcewake_count++ == 0)
7616                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7617         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7618
7619         if (val & LCPLL_POWER_DOWN_ALLOW) {
7620                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7621                 I915_WRITE(LCPLL_CTL, val);
7622                 POSTING_READ(LCPLL_CTL);
7623         }
7624
7625         val = hsw_read_dcomp(dev_priv);
7626         val |= D_COMP_COMP_FORCE;
7627         val &= ~D_COMP_COMP_DISABLE;
7628         hsw_write_dcomp(dev_priv, val);
7629
7630         val = I915_READ(LCPLL_CTL);
7631         val &= ~LCPLL_PLL_DISABLE;
7632         I915_WRITE(LCPLL_CTL, val);
7633
7634         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7635                 DRM_ERROR("LCPLL not locked yet\n");
7636
7637         if (val & LCPLL_CD_SOURCE_FCLK) {
7638                 val = I915_READ(LCPLL_CTL);
7639                 val &= ~LCPLL_CD_SOURCE_FCLK;
7640                 I915_WRITE(LCPLL_CTL, val);
7641
7642                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7643                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7644                         DRM_ERROR("Switching back to LCPLL failed\n");
7645         }
7646
7647         /* See the big comment above. */
7648         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7649         if (--dev_priv->uncore.forcewake_count == 0)
7650                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7651         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7652 }
7653
7654 /*
7655  * Package states C8 and deeper are really deep PC states that can only be
7656  * reached when all the devices on the system allow it, so even if the graphics
7657  * device allows PC8+, it doesn't mean the system will actually get to these
7658  * states. Our driver only allows PC8+ when going into runtime PM.
7659  *
7660  * The requirements for PC8+ are that all the outputs are disabled, the power
7661  * well is disabled and most interrupts are disabled, and these are also
7662  * requirements for runtime PM. When these conditions are met, we manually do
7663  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7664  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7665  * hang the machine.
7666  *
7667  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7668  * the state of some registers, so when we come back from PC8+ we need to
7669  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7670  * need to take care of the registers kept by RC6. Notice that this happens even
7671  * if we don't put the device in PCI D3 state (which is what currently happens
7672  * because of the runtime PM support).
7673  *
7674  * For more, read "Display Sequences for Package C8" on the hardware
7675  * documentation.
7676  */
7677 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7678 {
7679         struct drm_device *dev = dev_priv->dev;
7680         uint32_t val;
7681
7682         DRM_DEBUG_KMS("Enabling package C8+\n");
7683
7684         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7685                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7686                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7687                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7688         }
7689
7690         lpt_disable_clkout_dp(dev);
7691         hsw_disable_lcpll(dev_priv, true, true);
7692 }
7693
7694 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7695 {
7696         struct drm_device *dev = dev_priv->dev;
7697         uint32_t val;
7698
7699         DRM_DEBUG_KMS("Disabling package C8+\n");
7700
7701         hsw_restore_lcpll(dev_priv);
7702         lpt_init_pch_refclk(dev);
7703
7704         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7705                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7706                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7707                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7708         }
7709
7710         intel_prepare_ddi(dev);
7711 }
7712
7713 static void snb_modeset_global_resources(struct drm_device *dev)
7714 {
7715         modeset_update_crtc_power_domains(dev);
7716 }
7717
7718 static void haswell_modeset_global_resources(struct drm_device *dev)
7719 {
7720         modeset_update_crtc_power_domains(dev);
7721 }
7722
7723 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7724                                  int x, int y,
7725                                  struct drm_framebuffer *fb)
7726 {
7727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7728
7729         if (!intel_ddi_pll_select(intel_crtc))
7730                 return -EINVAL;
7731
7732         intel_crtc->lowfreq_avail = false;
7733
7734         return 0;
7735 }
7736
7737 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7738                                 enum port port,
7739                                 struct intel_crtc_config *pipe_config)
7740 {
7741         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7742
7743         switch (pipe_config->ddi_pll_sel) {
7744         case PORT_CLK_SEL_WRPLL1:
7745                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7746                 break;
7747         case PORT_CLK_SEL_WRPLL2:
7748                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7749                 break;
7750         }
7751 }
7752
7753 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7754                                        struct intel_crtc_config *pipe_config)
7755 {
7756         struct drm_device *dev = crtc->base.dev;
7757         struct drm_i915_private *dev_priv = dev->dev_private;
7758         struct intel_shared_dpll *pll;
7759         enum port port;
7760         uint32_t tmp;
7761
7762         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7763
7764         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7765
7766         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7767
7768         if (pipe_config->shared_dpll >= 0) {
7769                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7770
7771                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7772                                            &pipe_config->dpll_hw_state));
7773         }
7774
7775         /*
7776          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7777          * DDI E. So just check whether this pipe is wired to DDI E and whether
7778          * the PCH transcoder is on.
7779          */
7780         if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7781                 pipe_config->has_pch_encoder = true;
7782
7783                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7784                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7785                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7786
7787                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7788         }
7789 }
7790
7791 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7792                                     struct intel_crtc_config *pipe_config)
7793 {
7794         struct drm_device *dev = crtc->base.dev;
7795         struct drm_i915_private *dev_priv = dev->dev_private;
7796         enum intel_display_power_domain pfit_domain;
7797         uint32_t tmp;
7798
7799         if (!intel_display_power_enabled(dev_priv,
7800                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7801                 return false;
7802
7803         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7804         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7805
7806         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7807         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7808                 enum pipe trans_edp_pipe;
7809                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7810                 default:
7811                         WARN(1, "unknown pipe linked to edp transcoder\n");
7812                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7813                 case TRANS_DDI_EDP_INPUT_A_ON:
7814                         trans_edp_pipe = PIPE_A;
7815                         break;
7816                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7817                         trans_edp_pipe = PIPE_B;
7818                         break;
7819                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7820                         trans_edp_pipe = PIPE_C;
7821                         break;
7822                 }
7823
7824                 if (trans_edp_pipe == crtc->pipe)
7825                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7826         }
7827
7828         if (!intel_display_power_enabled(dev_priv,
7829                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7830                 return false;
7831
7832         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7833         if (!(tmp & PIPECONF_ENABLE))
7834                 return false;
7835
7836         haswell_get_ddi_port_state(crtc, pipe_config);
7837
7838         intel_get_pipe_timings(crtc, pipe_config);
7839
7840         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7841         if (intel_display_power_enabled(dev_priv, pfit_domain))
7842                 ironlake_get_pfit_config(crtc, pipe_config);
7843
7844         if (IS_HASWELL(dev))
7845                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7846                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7847
7848         pipe_config->pixel_multiplier = 1;
7849
7850         return true;
7851 }
7852
7853 static struct {
7854         int clock;
7855         u32 config;
7856 } hdmi_audio_clock[] = {
7857         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7858         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7859         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7860         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7861         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7862         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7863         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7864         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7865         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7866         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7867 };
7868
7869 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7870 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7871 {
7872         int i;
7873
7874         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7875                 if (mode->clock == hdmi_audio_clock[i].clock)
7876                         break;
7877         }
7878
7879         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7880                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7881                 i = 1;
7882         }
7883
7884         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7885                       hdmi_audio_clock[i].clock,
7886                       hdmi_audio_clock[i].config);
7887
7888         return hdmi_audio_clock[i].config;
7889 }
7890
7891 static bool intel_eld_uptodate(struct drm_connector *connector,
7892                                int reg_eldv, uint32_t bits_eldv,
7893                                int reg_elda, uint32_t bits_elda,
7894                                int reg_edid)
7895 {
7896         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7897         uint8_t *eld = connector->eld;
7898         uint32_t i;
7899
7900         i = I915_READ(reg_eldv);
7901         i &= bits_eldv;
7902
7903         if (!eld[0])
7904                 return !i;
7905
7906         if (!i)
7907                 return false;
7908
7909         i = I915_READ(reg_elda);
7910         i &= ~bits_elda;
7911         I915_WRITE(reg_elda, i);
7912
7913         for (i = 0; i < eld[2]; i++)
7914                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7915                         return false;
7916
7917         return true;
7918 }
7919
7920 static void g4x_write_eld(struct drm_connector *connector,
7921                           struct drm_crtc *crtc,
7922                           struct drm_display_mode *mode)
7923 {
7924         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7925         uint8_t *eld = connector->eld;
7926         uint32_t eldv;
7927         uint32_t len;
7928         uint32_t i;
7929
7930         i = I915_READ(G4X_AUD_VID_DID);
7931
7932         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7933                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7934         else
7935                 eldv = G4X_ELDV_DEVCTG;
7936
7937         if (intel_eld_uptodate(connector,
7938                                G4X_AUD_CNTL_ST, eldv,
7939                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7940                                G4X_HDMIW_HDMIEDID))
7941                 return;
7942
7943         i = I915_READ(G4X_AUD_CNTL_ST);
7944         i &= ~(eldv | G4X_ELD_ADDR);
7945         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7946         I915_WRITE(G4X_AUD_CNTL_ST, i);
7947
7948         if (!eld[0])
7949                 return;
7950
7951         len = min_t(uint8_t, eld[2], len);
7952         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7953         for (i = 0; i < len; i++)
7954                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7955
7956         i = I915_READ(G4X_AUD_CNTL_ST);
7957         i |= eldv;
7958         I915_WRITE(G4X_AUD_CNTL_ST, i);
7959 }
7960
7961 static void haswell_write_eld(struct drm_connector *connector,
7962                               struct drm_crtc *crtc,
7963                               struct drm_display_mode *mode)
7964 {
7965         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7966         uint8_t *eld = connector->eld;
7967         uint32_t eldv;
7968         uint32_t i;
7969         int len;
7970         int pipe = to_intel_crtc(crtc)->pipe;
7971         int tmp;
7972
7973         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7974         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7975         int aud_config = HSW_AUD_CFG(pipe);
7976         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7977
7978         /* Audio output enable */
7979         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7980         tmp = I915_READ(aud_cntrl_st2);
7981         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7982         I915_WRITE(aud_cntrl_st2, tmp);
7983         POSTING_READ(aud_cntrl_st2);
7984
7985         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7986
7987         /* Set ELD valid state */
7988         tmp = I915_READ(aud_cntrl_st2);
7989         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7990         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7991         I915_WRITE(aud_cntrl_st2, tmp);
7992         tmp = I915_READ(aud_cntrl_st2);
7993         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7994
7995         /* Enable HDMI mode */
7996         tmp = I915_READ(aud_config);
7997         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7998         /* clear N_programing_enable and N_value_index */
7999         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8000         I915_WRITE(aud_config, tmp);
8001
8002         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8003
8004         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8005
8006         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8007                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8008                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8009                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8010         } else {
8011                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8012         }
8013
8014         if (intel_eld_uptodate(connector,
8015                                aud_cntrl_st2, eldv,
8016                                aud_cntl_st, IBX_ELD_ADDRESS,
8017                                hdmiw_hdmiedid))
8018                 return;
8019
8020         i = I915_READ(aud_cntrl_st2);
8021         i &= ~eldv;
8022         I915_WRITE(aud_cntrl_st2, i);
8023
8024         if (!eld[0])
8025                 return;
8026
8027         i = I915_READ(aud_cntl_st);
8028         i &= ~IBX_ELD_ADDRESS;
8029         I915_WRITE(aud_cntl_st, i);
8030         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
8031         DRM_DEBUG_DRIVER("port num:%d\n", i);
8032
8033         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8034         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8035         for (i = 0; i < len; i++)
8036                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8037
8038         i = I915_READ(aud_cntrl_st2);
8039         i |= eldv;
8040         I915_WRITE(aud_cntrl_st2, i);
8041
8042 }
8043
8044 static void ironlake_write_eld(struct drm_connector *connector,
8045                                struct drm_crtc *crtc,
8046                                struct drm_display_mode *mode)
8047 {
8048         struct drm_i915_private *dev_priv = connector->dev->dev_private;
8049         uint8_t *eld = connector->eld;
8050         uint32_t eldv;
8051         uint32_t i;
8052         int len;
8053         int hdmiw_hdmiedid;
8054         int aud_config;
8055         int aud_cntl_st;
8056         int aud_cntrl_st2;
8057         int pipe = to_intel_crtc(crtc)->pipe;
8058
8059         if (HAS_PCH_IBX(connector->dev)) {
8060                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8061                 aud_config = IBX_AUD_CFG(pipe);
8062                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8063                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8064         } else if (IS_VALLEYVIEW(connector->dev)) {
8065                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8066                 aud_config = VLV_AUD_CFG(pipe);
8067                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8068                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8069         } else {
8070                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8071                 aud_config = CPT_AUD_CFG(pipe);
8072                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8073                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8074         }
8075
8076         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8077
8078         if (IS_VALLEYVIEW(connector->dev))  {
8079                 struct intel_encoder *intel_encoder;
8080                 struct intel_digital_port *intel_dig_port;
8081
8082                 intel_encoder = intel_attached_encoder(connector);
8083                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8084                 i = intel_dig_port->port;
8085         } else {
8086                 i = I915_READ(aud_cntl_st);
8087                 i = (i >> 29) & DIP_PORT_SEL_MASK;
8088                 /* DIP_Port_Select, 0x1 = PortB */
8089         }
8090
8091         if (!i) {
8092                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8093                 /* operate blindly on all ports */
8094                 eldv = IBX_ELD_VALIDB;
8095                 eldv |= IBX_ELD_VALIDB << 4;
8096                 eldv |= IBX_ELD_VALIDB << 8;
8097         } else {
8098                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8099                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8100         }
8101
8102         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8103                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8104                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
8105                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8106         } else {
8107                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8108         }
8109
8110         if (intel_eld_uptodate(connector,
8111                                aud_cntrl_st2, eldv,
8112                                aud_cntl_st, IBX_ELD_ADDRESS,
8113                                hdmiw_hdmiedid))
8114                 return;
8115
8116         i = I915_READ(aud_cntrl_st2);
8117         i &= ~eldv;
8118         I915_WRITE(aud_cntrl_st2, i);
8119
8120         if (!eld[0])
8121                 return;
8122
8123         i = I915_READ(aud_cntl_st);
8124         i &= ~IBX_ELD_ADDRESS;
8125         I915_WRITE(aud_cntl_st, i);
8126
8127         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
8128         DRM_DEBUG_DRIVER("ELD size %d\n", len);
8129         for (i = 0; i < len; i++)
8130                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8131
8132         i = I915_READ(aud_cntrl_st2);
8133         i |= eldv;
8134         I915_WRITE(aud_cntrl_st2, i);
8135 }
8136
8137 void intel_write_eld(struct drm_encoder *encoder,
8138                      struct drm_display_mode *mode)
8139 {
8140         struct drm_crtc *crtc = encoder->crtc;
8141         struct drm_connector *connector;
8142         struct drm_device *dev = encoder->dev;
8143         struct drm_i915_private *dev_priv = dev->dev_private;
8144
8145         connector = drm_select_eld(encoder, mode);
8146         if (!connector)
8147                 return;
8148
8149         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8150                          connector->base.id,
8151                          connector->name,
8152                          connector->encoder->base.id,
8153                          connector->encoder->name);
8154
8155         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8156
8157         if (dev_priv->display.write_eld)
8158                 dev_priv->display.write_eld(connector, crtc, mode);
8159 }
8160
8161 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8162 {
8163         struct drm_device *dev = crtc->dev;
8164         struct drm_i915_private *dev_priv = dev->dev_private;
8165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8166         uint32_t cntl = 0, size = 0;
8167
8168         if (base) {
8169                 unsigned int width = intel_crtc->cursor_width;
8170                 unsigned int height = intel_crtc->cursor_height;
8171                 unsigned int stride = roundup_pow_of_two(width) * 4;
8172
8173                 switch (stride) {
8174                 default:
8175                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8176                                   width, stride);
8177                         stride = 256;
8178                         /* fallthrough */
8179                 case 256:
8180                 case 512:
8181                 case 1024:
8182                 case 2048:
8183                         break;
8184                 }
8185
8186                 cntl |= CURSOR_ENABLE |
8187                         CURSOR_GAMMA_ENABLE |
8188                         CURSOR_FORMAT_ARGB |
8189                         CURSOR_STRIDE(stride);
8190
8191                 size = (height << 12) | width;
8192         }
8193
8194         if (intel_crtc->cursor_cntl != 0 &&
8195             (intel_crtc->cursor_base != base ||
8196              intel_crtc->cursor_size != size ||
8197              intel_crtc->cursor_cntl != cntl)) {
8198                 /* On these chipsets we can only modify the base/size/stride
8199                  * whilst the cursor is disabled.
8200                  */
8201                 I915_WRITE(_CURACNTR, 0);
8202                 POSTING_READ(_CURACNTR);
8203                 intel_crtc->cursor_cntl = 0;
8204         }
8205
8206         if (intel_crtc->cursor_base != base)
8207                 I915_WRITE(_CURABASE, base);
8208
8209         if (intel_crtc->cursor_size != size) {
8210                 I915_WRITE(CURSIZE, size);
8211                 intel_crtc->cursor_size = size;
8212         }
8213
8214         if (intel_crtc->cursor_cntl != cntl) {
8215                 I915_WRITE(_CURACNTR, cntl);
8216                 POSTING_READ(_CURACNTR);
8217                 intel_crtc->cursor_cntl = cntl;
8218         }
8219 }
8220
8221 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8222 {
8223         struct drm_device *dev = crtc->dev;
8224         struct drm_i915_private *dev_priv = dev->dev_private;
8225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8226         int pipe = intel_crtc->pipe;
8227         uint32_t cntl;
8228
8229         cntl = 0;
8230         if (base) {
8231                 cntl = MCURSOR_GAMMA_ENABLE;
8232                 switch (intel_crtc->cursor_width) {
8233                         case 64:
8234                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8235                                 break;
8236                         case 128:
8237                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8238                                 break;
8239                         case 256:
8240                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8241                                 break;
8242                         default:
8243                                 WARN_ON(1);
8244                                 return;
8245                 }
8246                 cntl |= pipe << 28; /* Connect to correct pipe */
8247         }
8248         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8249                 cntl |= CURSOR_PIPE_CSC_ENABLE;
8250
8251         if (intel_crtc->cursor_cntl != cntl) {
8252                 I915_WRITE(CURCNTR(pipe), cntl);
8253                 POSTING_READ(CURCNTR(pipe));
8254                 intel_crtc->cursor_cntl = cntl;
8255         }
8256
8257         /* and commit changes on next vblank */
8258         I915_WRITE(CURBASE(pipe), base);
8259         POSTING_READ(CURBASE(pipe));
8260 }
8261
8262 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8263 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8264                                      bool on)
8265 {
8266         struct drm_device *dev = crtc->dev;
8267         struct drm_i915_private *dev_priv = dev->dev_private;
8268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8269         int pipe = intel_crtc->pipe;
8270         int x = crtc->cursor_x;
8271         int y = crtc->cursor_y;
8272         u32 base = 0, pos = 0;
8273
8274         if (on)
8275                 base = intel_crtc->cursor_addr;
8276
8277         if (x >= intel_crtc->config.pipe_src_w)
8278                 base = 0;
8279
8280         if (y >= intel_crtc->config.pipe_src_h)
8281                 base = 0;
8282
8283         if (x < 0) {
8284                 if (x + intel_crtc->cursor_width <= 0)
8285                         base = 0;
8286
8287                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8288                 x = -x;
8289         }
8290         pos |= x << CURSOR_X_SHIFT;
8291
8292         if (y < 0) {
8293                 if (y + intel_crtc->cursor_height <= 0)
8294                         base = 0;
8295
8296                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8297                 y = -y;
8298         }
8299         pos |= y << CURSOR_Y_SHIFT;
8300
8301         if (base == 0 && intel_crtc->cursor_base == 0)
8302                 return;
8303
8304         I915_WRITE(CURPOS(pipe), pos);
8305
8306         if (IS_845G(dev) || IS_I865G(dev))
8307                 i845_update_cursor(crtc, base);
8308         else
8309                 i9xx_update_cursor(crtc, base);
8310         intel_crtc->cursor_base = base;
8311 }
8312
8313 static bool cursor_size_ok(struct drm_device *dev,
8314                            uint32_t width, uint32_t height)
8315 {
8316         if (width == 0 || height == 0)
8317                 return false;
8318
8319         /*
8320          * 845g/865g are special in that they are only limited by
8321          * the width of their cursors, the height is arbitrary up to
8322          * the precision of the register. Everything else requires
8323          * square cursors, limited to a few power-of-two sizes.
8324          */
8325         if (IS_845G(dev) || IS_I865G(dev)) {
8326                 if ((width & 63) != 0)
8327                         return false;
8328
8329                 if (width > (IS_845G(dev) ? 64 : 512))
8330                         return false;
8331
8332                 if (height > 1023)
8333                         return false;
8334         } else {
8335                 switch (width | height) {
8336                 case 256:
8337                 case 128:
8338                         if (IS_GEN2(dev))
8339                                 return false;
8340                 case 64:
8341                         break;
8342                 default:
8343                         return false;
8344                 }
8345         }
8346
8347         return true;
8348 }
8349
8350 /*
8351  * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8352  *
8353  * Note that the object's reference will be consumed if the update fails.  If
8354  * the update succeeds, the reference of the old object (if any) will be
8355  * consumed.
8356  */
8357 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8358                                      struct drm_i915_gem_object *obj,
8359                                      uint32_t width, uint32_t height)
8360 {
8361         struct drm_device *dev = crtc->dev;
8362         struct drm_i915_private *dev_priv = dev->dev_private;
8363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8364         enum pipe pipe = intel_crtc->pipe;
8365         unsigned old_width, stride;
8366         uint32_t addr;
8367         int ret;
8368
8369         /* if we want to turn off the cursor ignore width and height */
8370         if (!obj) {
8371                 DRM_DEBUG_KMS("cursor off\n");
8372                 addr = 0;
8373                 mutex_lock(&dev->struct_mutex);
8374                 goto finish;
8375         }
8376
8377         /* Check for which cursor types we support */
8378         if (!cursor_size_ok(dev, width, height)) {
8379                 DRM_DEBUG("Cursor dimension not supported\n");
8380                 return -EINVAL;
8381         }
8382
8383         stride = roundup_pow_of_two(width) * 4;
8384         if (obj->base.size < stride * height) {
8385                 DRM_DEBUG_KMS("buffer is too small\n");
8386                 ret = -ENOMEM;
8387                 goto fail;
8388         }
8389
8390         /* we only need to pin inside GTT if cursor is non-phy */
8391         mutex_lock(&dev->struct_mutex);
8392         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8393                 unsigned alignment;
8394
8395                 if (obj->tiling_mode) {
8396                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8397                         ret = -EINVAL;
8398                         goto fail_locked;
8399                 }
8400
8401                 /*
8402                  * Global gtt pte registers are special registers which actually
8403                  * forward writes to a chunk of system memory. Which means that
8404                  * there is no risk that the register values disappear as soon
8405                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8406                  * only the pin/unpin/fence and not more.
8407                  */
8408                 intel_runtime_pm_get(dev_priv);
8409
8410                 /* Note that the w/a also requires 2 PTE of padding following
8411                  * the bo. We currently fill all unused PTE with the shadow
8412                  * page and so we should always have valid PTE following the
8413                  * cursor preventing the VT-d warning.
8414                  */
8415                 alignment = 0;
8416                 if (need_vtd_wa(dev))
8417                         alignment = 64*1024;
8418
8419                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8420                 if (ret) {
8421                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8422                         intel_runtime_pm_put(dev_priv);
8423                         goto fail_locked;
8424                 }
8425
8426                 ret = i915_gem_object_put_fence(obj);
8427                 if (ret) {
8428                         DRM_DEBUG_KMS("failed to release fence for cursor");
8429                         intel_runtime_pm_put(dev_priv);
8430                         goto fail_unpin;
8431                 }
8432
8433                 addr = i915_gem_obj_ggtt_offset(obj);
8434
8435                 intel_runtime_pm_put(dev_priv);
8436         } else {
8437                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8438                 ret = i915_gem_object_attach_phys(obj, align);
8439                 if (ret) {
8440                         DRM_DEBUG_KMS("failed to attach phys object\n");
8441                         goto fail_locked;
8442                 }
8443                 addr = obj->phys_handle->busaddr;
8444         }
8445
8446  finish:
8447         if (intel_crtc->cursor_bo) {
8448                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8449                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8450         }
8451
8452         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8453                           INTEL_FRONTBUFFER_CURSOR(pipe));
8454         mutex_unlock(&dev->struct_mutex);
8455
8456         old_width = intel_crtc->cursor_width;
8457
8458         intel_crtc->cursor_addr = addr;
8459         intel_crtc->cursor_bo = obj;
8460         intel_crtc->cursor_width = width;
8461         intel_crtc->cursor_height = height;
8462
8463         if (intel_crtc->active) {
8464                 if (old_width != width)
8465                         intel_update_watermarks(crtc);
8466                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8467         }
8468
8469         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8470
8471         return 0;
8472 fail_unpin:
8473         i915_gem_object_unpin_from_display_plane(obj);
8474 fail_locked:
8475         mutex_unlock(&dev->struct_mutex);
8476 fail:
8477         drm_gem_object_unreference_unlocked(&obj->base);
8478         return ret;
8479 }
8480
8481 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8482                                  u16 *blue, uint32_t start, uint32_t size)
8483 {
8484         int end = (start + size > 256) ? 256 : start + size, i;
8485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8486
8487         for (i = start; i < end; i++) {
8488                 intel_crtc->lut_r[i] = red[i] >> 8;
8489                 intel_crtc->lut_g[i] = green[i] >> 8;
8490                 intel_crtc->lut_b[i] = blue[i] >> 8;
8491         }
8492
8493         intel_crtc_load_lut(crtc);
8494 }
8495
8496 /* VESA 640x480x72Hz mode to set on the pipe */
8497 static struct drm_display_mode load_detect_mode = {
8498         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8499                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8500 };
8501
8502 struct drm_framebuffer *
8503 __intel_framebuffer_create(struct drm_device *dev,
8504                            struct drm_mode_fb_cmd2 *mode_cmd,
8505                            struct drm_i915_gem_object *obj)
8506 {
8507         struct intel_framebuffer *intel_fb;
8508         int ret;
8509
8510         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8511         if (!intel_fb) {
8512                 drm_gem_object_unreference_unlocked(&obj->base);
8513                 return ERR_PTR(-ENOMEM);
8514         }
8515
8516         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8517         if (ret)
8518                 goto err;
8519
8520         return &intel_fb->base;
8521 err:
8522         drm_gem_object_unreference_unlocked(&obj->base);
8523         kfree(intel_fb);
8524
8525         return ERR_PTR(ret);
8526 }
8527
8528 static struct drm_framebuffer *
8529 intel_framebuffer_create(struct drm_device *dev,
8530                          struct drm_mode_fb_cmd2 *mode_cmd,
8531                          struct drm_i915_gem_object *obj)
8532 {
8533         struct drm_framebuffer *fb;
8534         int ret;
8535
8536         ret = i915_mutex_lock_interruptible(dev);
8537         if (ret)
8538                 return ERR_PTR(ret);
8539         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8540         mutex_unlock(&dev->struct_mutex);
8541
8542         return fb;
8543 }
8544
8545 static u32
8546 intel_framebuffer_pitch_for_width(int width, int bpp)
8547 {
8548         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8549         return ALIGN(pitch, 64);
8550 }
8551
8552 static u32
8553 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8554 {
8555         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8556         return PAGE_ALIGN(pitch * mode->vdisplay);
8557 }
8558
8559 static struct drm_framebuffer *
8560 intel_framebuffer_create_for_mode(struct drm_device *dev,
8561                                   struct drm_display_mode *mode,
8562                                   int depth, int bpp)
8563 {
8564         struct drm_i915_gem_object *obj;
8565         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8566
8567         obj = i915_gem_alloc_object(dev,
8568                                     intel_framebuffer_size_for_mode(mode, bpp));
8569         if (obj == NULL)
8570                 return ERR_PTR(-ENOMEM);
8571
8572         mode_cmd.width = mode->hdisplay;
8573         mode_cmd.height = mode->vdisplay;
8574         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8575                                                                 bpp);
8576         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8577
8578         return intel_framebuffer_create(dev, &mode_cmd, obj);
8579 }
8580
8581 static struct drm_framebuffer *
8582 mode_fits_in_fbdev(struct drm_device *dev,
8583                    struct drm_display_mode *mode)
8584 {
8585 #ifdef CONFIG_DRM_I915_FBDEV
8586         struct drm_i915_private *dev_priv = dev->dev_private;
8587         struct drm_i915_gem_object *obj;
8588         struct drm_framebuffer *fb;
8589
8590         if (!dev_priv->fbdev)
8591                 return NULL;
8592
8593         if (!dev_priv->fbdev->fb)
8594                 return NULL;
8595
8596         obj = dev_priv->fbdev->fb->obj;
8597         BUG_ON(!obj);
8598
8599         fb = &dev_priv->fbdev->fb->base;
8600         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8601                                                                fb->bits_per_pixel))
8602                 return NULL;
8603
8604         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8605                 return NULL;
8606
8607         return fb;
8608 #else
8609         return NULL;
8610 #endif
8611 }
8612
8613 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8614                                 struct drm_display_mode *mode,
8615                                 struct intel_load_detect_pipe *old,
8616                                 struct drm_modeset_acquire_ctx *ctx)
8617 {
8618         struct intel_crtc *intel_crtc;
8619         struct intel_encoder *intel_encoder =
8620                 intel_attached_encoder(connector);
8621         struct drm_crtc *possible_crtc;
8622         struct drm_encoder *encoder = &intel_encoder->base;
8623         struct drm_crtc *crtc = NULL;
8624         struct drm_device *dev = encoder->dev;
8625         struct drm_framebuffer *fb;
8626         struct drm_mode_config *config = &dev->mode_config;
8627         int ret, i = -1;
8628
8629         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8630                       connector->base.id, connector->name,
8631                       encoder->base.id, encoder->name);
8632
8633 retry:
8634         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8635         if (ret)
8636                 goto fail_unlock;
8637
8638         /*
8639          * Algorithm gets a little messy:
8640          *
8641          *   - if the connector already has an assigned crtc, use it (but make
8642          *     sure it's on first)
8643          *
8644          *   - try to find the first unused crtc that can drive this connector,
8645          *     and use that if we find one
8646          */
8647
8648         /* See if we already have a CRTC for this connector */
8649         if (encoder->crtc) {
8650                 crtc = encoder->crtc;
8651
8652                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8653                 if (ret)
8654                         goto fail_unlock;
8655
8656                 old->dpms_mode = connector->dpms;
8657                 old->load_detect_temp = false;
8658
8659                 /* Make sure the crtc and connector are running */
8660                 if (connector->dpms != DRM_MODE_DPMS_ON)
8661                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8662
8663                 return true;
8664         }
8665
8666         /* Find an unused one (if possible) */
8667         for_each_crtc(dev, possible_crtc) {
8668                 i++;
8669                 if (!(encoder->possible_crtcs & (1 << i)))
8670                         continue;
8671                 if (possible_crtc->enabled)
8672                         continue;
8673                 /* This can occur when applying the pipe A quirk on resume. */
8674                 if (to_intel_crtc(possible_crtc)->new_enabled)
8675                         continue;
8676
8677                 crtc = possible_crtc;
8678                 break;
8679         }
8680
8681         /*
8682          * If we didn't find an unused CRTC, don't use any.
8683          */
8684         if (!crtc) {
8685                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8686                 goto fail_unlock;
8687         }
8688
8689         ret = drm_modeset_lock(&crtc->mutex, ctx);
8690         if (ret)
8691                 goto fail_unlock;
8692         intel_encoder->new_crtc = to_intel_crtc(crtc);
8693         to_intel_connector(connector)->new_encoder = intel_encoder;
8694
8695         intel_crtc = to_intel_crtc(crtc);
8696         intel_crtc->new_enabled = true;
8697         intel_crtc->new_config = &intel_crtc->config;
8698         old->dpms_mode = connector->dpms;
8699         old->load_detect_temp = true;
8700         old->release_fb = NULL;
8701
8702         if (!mode)
8703                 mode = &load_detect_mode;
8704
8705         /* We need a framebuffer large enough to accommodate all accesses
8706          * that the plane may generate whilst we perform load detection.
8707          * We can not rely on the fbcon either being present (we get called
8708          * during its initialisation to detect all boot displays, or it may
8709          * not even exist) or that it is large enough to satisfy the
8710          * requested mode.
8711          */
8712         fb = mode_fits_in_fbdev(dev, mode);
8713         if (fb == NULL) {
8714                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8715                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8716                 old->release_fb = fb;
8717         } else
8718                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8719         if (IS_ERR(fb)) {
8720                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8721                 goto fail;
8722         }
8723
8724         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8725                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8726                 if (old->release_fb)
8727                         old->release_fb->funcs->destroy(old->release_fb);
8728                 goto fail;
8729         }
8730
8731         /* let the connector get through one full cycle before testing */
8732         intel_wait_for_vblank(dev, intel_crtc->pipe);
8733         return true;
8734
8735  fail:
8736         intel_crtc->new_enabled = crtc->enabled;
8737         if (intel_crtc->new_enabled)
8738                 intel_crtc->new_config = &intel_crtc->config;
8739         else
8740                 intel_crtc->new_config = NULL;
8741 fail_unlock:
8742         if (ret == -EDEADLK) {
8743                 drm_modeset_backoff(ctx);
8744                 goto retry;
8745         }
8746
8747         return false;
8748 }
8749
8750 void intel_release_load_detect_pipe(struct drm_connector *connector,
8751                                     struct intel_load_detect_pipe *old)
8752 {
8753         struct intel_encoder *intel_encoder =
8754                 intel_attached_encoder(connector);
8755         struct drm_encoder *encoder = &intel_encoder->base;
8756         struct drm_crtc *crtc = encoder->crtc;
8757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8758
8759         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8760                       connector->base.id, connector->name,
8761                       encoder->base.id, encoder->name);
8762
8763         if (old->load_detect_temp) {
8764                 to_intel_connector(connector)->new_encoder = NULL;
8765                 intel_encoder->new_crtc = NULL;
8766                 intel_crtc->new_enabled = false;
8767                 intel_crtc->new_config = NULL;
8768                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8769
8770                 if (old->release_fb) {
8771                         drm_framebuffer_unregister_private(old->release_fb);
8772                         drm_framebuffer_unreference(old->release_fb);
8773                 }
8774
8775                 return;
8776         }
8777
8778         /* Switch crtc and encoder back off if necessary */
8779         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8780                 connector->funcs->dpms(connector, old->dpms_mode);
8781 }
8782
8783 static int i9xx_pll_refclk(struct drm_device *dev,
8784                            const struct intel_crtc_config *pipe_config)
8785 {
8786         struct drm_i915_private *dev_priv = dev->dev_private;
8787         u32 dpll = pipe_config->dpll_hw_state.dpll;
8788
8789         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8790                 return dev_priv->vbt.lvds_ssc_freq;
8791         else if (HAS_PCH_SPLIT(dev))
8792                 return 120000;
8793         else if (!IS_GEN2(dev))
8794                 return 96000;
8795         else
8796                 return 48000;
8797 }
8798
8799 /* Returns the clock of the currently programmed mode of the given pipe. */
8800 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8801                                 struct intel_crtc_config *pipe_config)
8802 {
8803         struct drm_device *dev = crtc->base.dev;
8804         struct drm_i915_private *dev_priv = dev->dev_private;
8805         int pipe = pipe_config->cpu_transcoder;
8806         u32 dpll = pipe_config->dpll_hw_state.dpll;
8807         u32 fp;
8808         intel_clock_t clock;
8809         int refclk = i9xx_pll_refclk(dev, pipe_config);
8810
8811         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8812                 fp = pipe_config->dpll_hw_state.fp0;
8813         else
8814                 fp = pipe_config->dpll_hw_state.fp1;
8815
8816         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8817         if (IS_PINEVIEW(dev)) {
8818                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8819                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8820         } else {
8821                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8822                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8823         }
8824
8825         if (!IS_GEN2(dev)) {
8826                 if (IS_PINEVIEW(dev))
8827                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8828                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8829                 else
8830                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8831                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8832
8833                 switch (dpll & DPLL_MODE_MASK) {
8834                 case DPLLB_MODE_DAC_SERIAL:
8835                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8836                                 5 : 10;
8837                         break;
8838                 case DPLLB_MODE_LVDS:
8839                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8840                                 7 : 14;
8841                         break;
8842                 default:
8843                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8844                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8845                         return;
8846                 }
8847
8848                 if (IS_PINEVIEW(dev))
8849                         pineview_clock(refclk, &clock);
8850                 else
8851                         i9xx_clock(refclk, &clock);
8852         } else {
8853                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8854                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8855
8856                 if (is_lvds) {
8857                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8858                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8859
8860                         if (lvds & LVDS_CLKB_POWER_UP)
8861                                 clock.p2 = 7;
8862                         else
8863                                 clock.p2 = 14;
8864                 } else {
8865                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8866                                 clock.p1 = 2;
8867                         else {
8868                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8869                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8870                         }
8871                         if (dpll & PLL_P2_DIVIDE_BY_4)
8872                                 clock.p2 = 4;
8873                         else
8874                                 clock.p2 = 2;
8875                 }
8876
8877                 i9xx_clock(refclk, &clock);
8878         }
8879
8880         /*
8881          * This value includes pixel_multiplier. We will use
8882          * port_clock to compute adjusted_mode.crtc_clock in the
8883          * encoder's get_config() function.
8884          */
8885         pipe_config->port_clock = clock.dot;
8886 }
8887
8888 int intel_dotclock_calculate(int link_freq,
8889                              const struct intel_link_m_n *m_n)
8890 {
8891         /*
8892          * The calculation for the data clock is:
8893          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8894          * But we want to avoid losing precison if possible, so:
8895          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8896          *
8897          * and the link clock is simpler:
8898          * link_clock = (m * link_clock) / n
8899          */
8900
8901         if (!m_n->link_n)
8902                 return 0;
8903
8904         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8905 }
8906
8907 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8908                                    struct intel_crtc_config *pipe_config)
8909 {
8910         struct drm_device *dev = crtc->base.dev;
8911
8912         /* read out port_clock from the DPLL */
8913         i9xx_crtc_clock_get(crtc, pipe_config);
8914
8915         /*
8916          * This value does not include pixel_multiplier.
8917          * We will check that port_clock and adjusted_mode.crtc_clock
8918          * agree once we know their relationship in the encoder's
8919          * get_config() function.
8920          */
8921         pipe_config->adjusted_mode.crtc_clock =
8922                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8923                                          &pipe_config->fdi_m_n);
8924 }
8925
8926 /** Returns the currently programmed mode of the given pipe. */
8927 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8928                                              struct drm_crtc *crtc)
8929 {
8930         struct drm_i915_private *dev_priv = dev->dev_private;
8931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8932         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8933         struct drm_display_mode *mode;
8934         struct intel_crtc_config pipe_config;
8935         int htot = I915_READ(HTOTAL(cpu_transcoder));
8936         int hsync = I915_READ(HSYNC(cpu_transcoder));
8937         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8938         int vsync = I915_READ(VSYNC(cpu_transcoder));
8939         enum pipe pipe = intel_crtc->pipe;
8940
8941         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8942         if (!mode)
8943                 return NULL;
8944
8945         /*
8946          * Construct a pipe_config sufficient for getting the clock info
8947          * back out of crtc_clock_get.
8948          *
8949          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8950          * to use a real value here instead.
8951          */
8952         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8953         pipe_config.pixel_multiplier = 1;
8954         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8955         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8956         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8957         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8958
8959         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8960         mode->hdisplay = (htot & 0xffff) + 1;
8961         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8962         mode->hsync_start = (hsync & 0xffff) + 1;
8963         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8964         mode->vdisplay = (vtot & 0xffff) + 1;
8965         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8966         mode->vsync_start = (vsync & 0xffff) + 1;
8967         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8968
8969         drm_mode_set_name(mode);
8970
8971         return mode;
8972 }
8973
8974 static void intel_increase_pllclock(struct drm_device *dev,
8975                                     enum pipe pipe)
8976 {
8977         struct drm_i915_private *dev_priv = dev->dev_private;
8978         int dpll_reg = DPLL(pipe);
8979         int dpll;
8980
8981         if (!HAS_GMCH_DISPLAY(dev))
8982                 return;
8983
8984         if (!dev_priv->lvds_downclock_avail)
8985                 return;
8986
8987         dpll = I915_READ(dpll_reg);
8988         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8989                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8990
8991                 assert_panel_unlocked(dev_priv, pipe);
8992
8993                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8994                 I915_WRITE(dpll_reg, dpll);
8995                 intel_wait_for_vblank(dev, pipe);
8996
8997                 dpll = I915_READ(dpll_reg);
8998                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8999                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9000         }
9001 }
9002
9003 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9004 {
9005         struct drm_device *dev = crtc->dev;
9006         struct drm_i915_private *dev_priv = dev->dev_private;
9007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9008
9009         if (!HAS_GMCH_DISPLAY(dev))
9010                 return;
9011
9012         if (!dev_priv->lvds_downclock_avail)
9013                 return;
9014
9015         /*
9016          * Since this is called by a timer, we should never get here in
9017          * the manual case.
9018          */
9019         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9020                 int pipe = intel_crtc->pipe;
9021                 int dpll_reg = DPLL(pipe);
9022                 int dpll;
9023
9024                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9025
9026                 assert_panel_unlocked(dev_priv, pipe);
9027
9028                 dpll = I915_READ(dpll_reg);
9029                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9030                 I915_WRITE(dpll_reg, dpll);
9031                 intel_wait_for_vblank(dev, pipe);
9032                 dpll = I915_READ(dpll_reg);
9033                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9034                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9035         }
9036
9037 }
9038
9039 void intel_mark_busy(struct drm_device *dev)
9040 {
9041         struct drm_i915_private *dev_priv = dev->dev_private;
9042
9043         if (dev_priv->mm.busy)
9044                 return;
9045
9046         intel_runtime_pm_get(dev_priv);
9047         i915_update_gfx_val(dev_priv);
9048         dev_priv->mm.busy = true;
9049 }
9050
9051 void intel_mark_idle(struct drm_device *dev)
9052 {
9053         struct drm_i915_private *dev_priv = dev->dev_private;
9054         struct drm_crtc *crtc;
9055
9056         if (!dev_priv->mm.busy)
9057                 return;
9058
9059         dev_priv->mm.busy = false;
9060
9061         if (!i915.powersave)
9062                 goto out;
9063
9064         for_each_crtc(dev, crtc) {
9065                 if (!crtc->primary->fb)
9066                         continue;
9067
9068                 intel_decrease_pllclock(crtc);
9069         }
9070
9071         if (INTEL_INFO(dev)->gen >= 6)
9072                 gen6_rps_idle(dev->dev_private);
9073
9074 out:
9075         intel_runtime_pm_put(dev_priv);
9076 }
9077
9078
9079 /**
9080  * intel_mark_fb_busy - mark given planes as busy
9081  * @dev: DRM device
9082  * @frontbuffer_bits: bits for the affected planes
9083  * @ring: optional ring for asynchronous commands
9084  *
9085  * This function gets called every time the screen contents change. It can be
9086  * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9087  */
9088 static void intel_mark_fb_busy(struct drm_device *dev,
9089                                unsigned frontbuffer_bits,
9090                                struct intel_engine_cs *ring)
9091 {
9092         struct drm_i915_private *dev_priv = dev->dev_private;
9093         enum pipe pipe;
9094
9095         if (!i915.powersave)
9096                 return;
9097
9098         for_each_pipe(dev_priv, pipe) {
9099                 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9100                         continue;
9101
9102                 intel_increase_pllclock(dev, pipe);
9103                 if (ring && intel_fbc_enabled(dev))
9104                         ring->fbc_dirty = true;
9105         }
9106 }
9107
9108 /**
9109  * intel_fb_obj_invalidate - invalidate frontbuffer object
9110  * @obj: GEM object to invalidate
9111  * @ring: set for asynchronous rendering
9112  *
9113  * This function gets called every time rendering on the given object starts and
9114  * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9115  * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9116  * until the rendering completes or a flip on this frontbuffer plane is
9117  * scheduled.
9118  */
9119 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9120                              struct intel_engine_cs *ring)
9121 {
9122         struct drm_device *dev = obj->base.dev;
9123         struct drm_i915_private *dev_priv = dev->dev_private;
9124
9125         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9126
9127         if (!obj->frontbuffer_bits)
9128                 return;
9129
9130         if (ring) {
9131                 mutex_lock(&dev_priv->fb_tracking.lock);
9132                 dev_priv->fb_tracking.busy_bits
9133                         |= obj->frontbuffer_bits;
9134                 dev_priv->fb_tracking.flip_bits
9135                         &= ~obj->frontbuffer_bits;
9136                 mutex_unlock(&dev_priv->fb_tracking.lock);
9137         }
9138
9139         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9140
9141         intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9142 }
9143
9144 /**
9145  * intel_frontbuffer_flush - flush frontbuffer
9146  * @dev: DRM device
9147  * @frontbuffer_bits: frontbuffer plane tracking bits
9148  *
9149  * This function gets called every time rendering on the given planes has
9150  * completed and frontbuffer caching can be started again. Flushes will get
9151  * delayed if they're blocked by some oustanding asynchronous rendering.
9152  *
9153  * Can be called without any locks held.
9154  */
9155 void intel_frontbuffer_flush(struct drm_device *dev,
9156                              unsigned frontbuffer_bits)
9157 {
9158         struct drm_i915_private *dev_priv = dev->dev_private;
9159
9160         /* Delay flushing when rings are still busy.*/
9161         mutex_lock(&dev_priv->fb_tracking.lock);
9162         frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9163         mutex_unlock(&dev_priv->fb_tracking.lock);
9164
9165         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9166
9167         intel_edp_psr_flush(dev, frontbuffer_bits);
9168
9169         /*
9170          * FIXME: Unconditional fbc flushing here is a rather gross hack and
9171          * needs to be reworked into a proper frontbuffer tracking scheme like
9172          * psr employs.
9173          */
9174         if (IS_BROADWELL(dev))
9175                 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9176 }
9177
9178 /**
9179  * intel_fb_obj_flush - flush frontbuffer object
9180  * @obj: GEM object to flush
9181  * @retire: set when retiring asynchronous rendering
9182  *
9183  * This function gets called every time rendering on the given object has
9184  * completed and frontbuffer caching can be started again. If @retire is true
9185  * then any delayed flushes will be unblocked.
9186  */
9187 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9188                         bool retire)
9189 {
9190         struct drm_device *dev = obj->base.dev;
9191         struct drm_i915_private *dev_priv = dev->dev_private;
9192         unsigned frontbuffer_bits;
9193
9194         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9195
9196         if (!obj->frontbuffer_bits)
9197                 return;
9198
9199         frontbuffer_bits = obj->frontbuffer_bits;
9200
9201         if (retire) {
9202                 mutex_lock(&dev_priv->fb_tracking.lock);
9203                 /* Filter out new bits since rendering started. */
9204                 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9205
9206                 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9207                 mutex_unlock(&dev_priv->fb_tracking.lock);
9208         }
9209
9210         intel_frontbuffer_flush(dev, frontbuffer_bits);
9211 }
9212
9213 /**
9214  * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9215  * @dev: DRM device
9216  * @frontbuffer_bits: frontbuffer plane tracking bits
9217  *
9218  * This function gets called after scheduling a flip on @obj. The actual
9219  * frontbuffer flushing will be delayed until completion is signalled with
9220  * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9221  * flush will be cancelled.
9222  *
9223  * Can be called without any locks held.
9224  */
9225 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9226                                     unsigned frontbuffer_bits)
9227 {
9228         struct drm_i915_private *dev_priv = dev->dev_private;
9229
9230         mutex_lock(&dev_priv->fb_tracking.lock);
9231         dev_priv->fb_tracking.flip_bits
9232                 |= frontbuffer_bits;
9233         mutex_unlock(&dev_priv->fb_tracking.lock);
9234 }
9235
9236 /**
9237  * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9238  * @dev: DRM device
9239  * @frontbuffer_bits: frontbuffer plane tracking bits
9240  *
9241  * This function gets called after the flip has been latched and will complete
9242  * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9243  *
9244  * Can be called without any locks held.
9245  */
9246 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9247                                      unsigned frontbuffer_bits)
9248 {
9249         struct drm_i915_private *dev_priv = dev->dev_private;
9250
9251         mutex_lock(&dev_priv->fb_tracking.lock);
9252         /* Mask any cancelled flips. */
9253         frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9254         dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9255         mutex_unlock(&dev_priv->fb_tracking.lock);
9256
9257         intel_frontbuffer_flush(dev, frontbuffer_bits);
9258 }
9259
9260 static void intel_crtc_destroy(struct drm_crtc *crtc)
9261 {
9262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9263         struct drm_device *dev = crtc->dev;
9264         struct intel_unpin_work *work;
9265         unsigned long flags;
9266
9267         spin_lock_irqsave(&dev->event_lock, flags);
9268         work = intel_crtc->unpin_work;
9269         intel_crtc->unpin_work = NULL;
9270         spin_unlock_irqrestore(&dev->event_lock, flags);
9271
9272         if (work) {
9273                 cancel_work_sync(&work->work);
9274                 kfree(work);
9275         }
9276
9277         drm_crtc_cleanup(crtc);
9278
9279         kfree(intel_crtc);
9280 }
9281
9282 static void intel_unpin_work_fn(struct work_struct *__work)
9283 {
9284         struct intel_unpin_work *work =
9285                 container_of(__work, struct intel_unpin_work, work);
9286         struct drm_device *dev = work->crtc->dev;
9287         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9288
9289         mutex_lock(&dev->struct_mutex);
9290         intel_unpin_fb_obj(work->old_fb_obj);
9291         drm_gem_object_unreference(&work->pending_flip_obj->base);
9292         drm_gem_object_unreference(&work->old_fb_obj->base);
9293
9294         intel_update_fbc(dev);
9295         mutex_unlock(&dev->struct_mutex);
9296
9297         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9298
9299         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9300         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9301
9302         kfree(work);
9303 }
9304
9305 static void do_intel_finish_page_flip(struct drm_device *dev,
9306                                       struct drm_crtc *crtc)
9307 {
9308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9309         struct intel_unpin_work *work;
9310         unsigned long flags;
9311
9312         /* Ignore early vblank irqs */
9313         if (intel_crtc == NULL)
9314                 return;
9315
9316         spin_lock_irqsave(&dev->event_lock, flags);
9317         work = intel_crtc->unpin_work;
9318
9319         /* Ensure we don't miss a work->pending update ... */
9320         smp_rmb();
9321
9322         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9323                 spin_unlock_irqrestore(&dev->event_lock, flags);
9324                 return;
9325         }
9326
9327         page_flip_completed(intel_crtc);
9328
9329         spin_unlock_irqrestore(&dev->event_lock, flags);
9330 }
9331
9332 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9333 {
9334         struct drm_i915_private *dev_priv = dev->dev_private;
9335         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9336
9337         do_intel_finish_page_flip(dev, crtc);
9338 }
9339
9340 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9341 {
9342         struct drm_i915_private *dev_priv = dev->dev_private;
9343         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9344
9345         do_intel_finish_page_flip(dev, crtc);
9346 }
9347
9348 /* Is 'a' after or equal to 'b'? */
9349 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9350 {
9351         return !((a - b) & 0x80000000);
9352 }
9353
9354 static bool page_flip_finished(struct intel_crtc *crtc)
9355 {
9356         struct drm_device *dev = crtc->base.dev;
9357         struct drm_i915_private *dev_priv = dev->dev_private;
9358
9359         /*
9360          * The relevant registers doen't exist on pre-ctg.
9361          * As the flip done interrupt doesn't trigger for mmio
9362          * flips on gmch platforms, a flip count check isn't
9363          * really needed there. But since ctg has the registers,
9364          * include it in the check anyway.
9365          */
9366         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9367                 return true;
9368
9369         /*
9370          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9371          * used the same base address. In that case the mmio flip might
9372          * have completed, but the CS hasn't even executed the flip yet.
9373          *
9374          * A flip count check isn't enough as the CS might have updated
9375          * the base address just after start of vblank, but before we
9376          * managed to process the interrupt. This means we'd complete the
9377          * CS flip too soon.
9378          *
9379          * Combining both checks should get us a good enough result. It may
9380          * still happen that the CS flip has been executed, but has not
9381          * yet actually completed. But in case the base address is the same
9382          * anyway, we don't really care.
9383          */
9384         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9385                 crtc->unpin_work->gtt_offset &&
9386                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9387                                     crtc->unpin_work->flip_count);
9388 }
9389
9390 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9391 {
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         struct intel_crtc *intel_crtc =
9394                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9395         unsigned long flags;
9396
9397         /* NB: An MMIO update of the plane base pointer will also
9398          * generate a page-flip completion irq, i.e. every modeset
9399          * is also accompanied by a spurious intel_prepare_page_flip().
9400          */
9401         spin_lock_irqsave(&dev->event_lock, flags);
9402         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9403                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9404         spin_unlock_irqrestore(&dev->event_lock, flags);
9405 }
9406
9407 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9408 {
9409         /* Ensure that the work item is consistent when activating it ... */
9410         smp_wmb();
9411         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9412         /* and that it is marked active as soon as the irq could fire. */
9413         smp_wmb();
9414 }
9415
9416 static int intel_gen2_queue_flip(struct drm_device *dev,
9417                                  struct drm_crtc *crtc,
9418                                  struct drm_framebuffer *fb,
9419                                  struct drm_i915_gem_object *obj,
9420                                  struct intel_engine_cs *ring,
9421                                  uint32_t flags)
9422 {
9423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9424         u32 flip_mask;
9425         int ret;
9426
9427         ret = intel_ring_begin(ring, 6);
9428         if (ret)
9429                 return ret;
9430
9431         /* Can't queue multiple flips, so wait for the previous
9432          * one to finish before executing the next.
9433          */
9434         if (intel_crtc->plane)
9435                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9436         else
9437                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9438         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9439         intel_ring_emit(ring, MI_NOOP);
9440         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9441                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9442         intel_ring_emit(ring, fb->pitches[0]);
9443         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9444         intel_ring_emit(ring, 0); /* aux display base address, unused */
9445
9446         intel_mark_page_flip_active(intel_crtc);
9447         __intel_ring_advance(ring);
9448         return 0;
9449 }
9450
9451 static int intel_gen3_queue_flip(struct drm_device *dev,
9452                                  struct drm_crtc *crtc,
9453                                  struct drm_framebuffer *fb,
9454                                  struct drm_i915_gem_object *obj,
9455                                  struct intel_engine_cs *ring,
9456                                  uint32_t flags)
9457 {
9458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9459         u32 flip_mask;
9460         int ret;
9461
9462         ret = intel_ring_begin(ring, 6);
9463         if (ret)
9464                 return ret;
9465
9466         if (intel_crtc->plane)
9467                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9468         else
9469                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9470         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9471         intel_ring_emit(ring, MI_NOOP);
9472         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9473                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9474         intel_ring_emit(ring, fb->pitches[0]);
9475         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9476         intel_ring_emit(ring, MI_NOOP);
9477
9478         intel_mark_page_flip_active(intel_crtc);
9479         __intel_ring_advance(ring);
9480         return 0;
9481 }
9482
9483 static int intel_gen4_queue_flip(struct drm_device *dev,
9484                                  struct drm_crtc *crtc,
9485                                  struct drm_framebuffer *fb,
9486                                  struct drm_i915_gem_object *obj,
9487                                  struct intel_engine_cs *ring,
9488                                  uint32_t flags)
9489 {
9490         struct drm_i915_private *dev_priv = dev->dev_private;
9491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9492         uint32_t pf, pipesrc;
9493         int ret;
9494
9495         ret = intel_ring_begin(ring, 4);
9496         if (ret)
9497                 return ret;
9498
9499         /* i965+ uses the linear or tiled offsets from the
9500          * Display Registers (which do not change across a page-flip)
9501          * so we need only reprogram the base address.
9502          */
9503         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9504                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9505         intel_ring_emit(ring, fb->pitches[0]);
9506         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9507                         obj->tiling_mode);
9508
9509         /* XXX Enabling the panel-fitter across page-flip is so far
9510          * untested on non-native modes, so ignore it for now.
9511          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9512          */
9513         pf = 0;
9514         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9515         intel_ring_emit(ring, pf | pipesrc);
9516
9517         intel_mark_page_flip_active(intel_crtc);
9518         __intel_ring_advance(ring);
9519         return 0;
9520 }
9521
9522 static int intel_gen6_queue_flip(struct drm_device *dev,
9523                                  struct drm_crtc *crtc,
9524                                  struct drm_framebuffer *fb,
9525                                  struct drm_i915_gem_object *obj,
9526                                  struct intel_engine_cs *ring,
9527                                  uint32_t flags)
9528 {
9529         struct drm_i915_private *dev_priv = dev->dev_private;
9530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9531         uint32_t pf, pipesrc;
9532         int ret;
9533
9534         ret = intel_ring_begin(ring, 4);
9535         if (ret)
9536                 return ret;
9537
9538         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9539                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9540         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9541         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9542
9543         /* Contrary to the suggestions in the documentation,
9544          * "Enable Panel Fitter" does not seem to be required when page
9545          * flipping with a non-native mode, and worse causes a normal
9546          * modeset to fail.
9547          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9548          */
9549         pf = 0;
9550         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9551         intel_ring_emit(ring, pf | pipesrc);
9552
9553         intel_mark_page_flip_active(intel_crtc);
9554         __intel_ring_advance(ring);
9555         return 0;
9556 }
9557
9558 static int intel_gen7_queue_flip(struct drm_device *dev,
9559                                  struct drm_crtc *crtc,
9560                                  struct drm_framebuffer *fb,
9561                                  struct drm_i915_gem_object *obj,
9562                                  struct intel_engine_cs *ring,
9563                                  uint32_t flags)
9564 {
9565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9566         uint32_t plane_bit = 0;
9567         int len, ret;
9568
9569         switch (intel_crtc->plane) {
9570         case PLANE_A:
9571                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9572                 break;
9573         case PLANE_B:
9574                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9575                 break;
9576         case PLANE_C:
9577                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9578                 break;
9579         default:
9580                 WARN_ONCE(1, "unknown plane in flip command\n");
9581                 return -ENODEV;
9582         }
9583
9584         len = 4;
9585         if (ring->id == RCS) {
9586                 len += 6;
9587                 /*
9588                  * On Gen 8, SRM is now taking an extra dword to accommodate
9589                  * 48bits addresses, and we need a NOOP for the batch size to
9590                  * stay even.
9591                  */
9592                 if (IS_GEN8(dev))
9593                         len += 2;
9594         }
9595
9596         /*
9597          * BSpec MI_DISPLAY_FLIP for IVB:
9598          * "The full packet must be contained within the same cache line."
9599          *
9600          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9601          * cacheline, if we ever start emitting more commands before
9602          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9603          * then do the cacheline alignment, and finally emit the
9604          * MI_DISPLAY_FLIP.
9605          */
9606         ret = intel_ring_cacheline_align(ring);
9607         if (ret)
9608                 return ret;
9609
9610         ret = intel_ring_begin(ring, len);
9611         if (ret)
9612                 return ret;
9613
9614         /* Unmask the flip-done completion message. Note that the bspec says that
9615          * we should do this for both the BCS and RCS, and that we must not unmask
9616          * more than one flip event at any time (or ensure that one flip message
9617          * can be sent by waiting for flip-done prior to queueing new flips).
9618          * Experimentation says that BCS works despite DERRMR masking all
9619          * flip-done completion events and that unmasking all planes at once
9620          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9621          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9622          */
9623         if (ring->id == RCS) {
9624                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9625                 intel_ring_emit(ring, DERRMR);
9626                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9627                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9628                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9629                 if (IS_GEN8(dev))
9630                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9631                                               MI_SRM_LRM_GLOBAL_GTT);
9632                 else
9633                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9634                                               MI_SRM_LRM_GLOBAL_GTT);
9635                 intel_ring_emit(ring, DERRMR);
9636                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9637                 if (IS_GEN8(dev)) {
9638                         intel_ring_emit(ring, 0);
9639                         intel_ring_emit(ring, MI_NOOP);
9640                 }
9641         }
9642
9643         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9644         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9645         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9646         intel_ring_emit(ring, (MI_NOOP));
9647
9648         intel_mark_page_flip_active(intel_crtc);
9649         __intel_ring_advance(ring);
9650         return 0;
9651 }
9652
9653 static bool use_mmio_flip(struct intel_engine_cs *ring,
9654                           struct drm_i915_gem_object *obj)
9655 {
9656         /*
9657          * This is not being used for older platforms, because
9658          * non-availability of flip done interrupt forces us to use
9659          * CS flips. Older platforms derive flip done using some clever
9660          * tricks involving the flip_pending status bits and vblank irqs.
9661          * So using MMIO flips there would disrupt this mechanism.
9662          */
9663
9664         if (ring == NULL)
9665                 return true;
9666
9667         if (INTEL_INFO(ring->dev)->gen < 5)
9668                 return false;
9669
9670         if (i915.use_mmio_flip < 0)
9671                 return false;
9672         else if (i915.use_mmio_flip > 0)
9673                 return true;
9674         else if (i915.enable_execlists)
9675                 return true;
9676         else
9677                 return ring != obj->ring;
9678 }
9679
9680 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9681 {
9682         struct drm_device *dev = intel_crtc->base.dev;
9683         struct drm_i915_private *dev_priv = dev->dev_private;
9684         struct intel_framebuffer *intel_fb =
9685                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9686         struct drm_i915_gem_object *obj = intel_fb->obj;
9687         u32 dspcntr;
9688         u32 reg;
9689
9690         intel_mark_page_flip_active(intel_crtc);
9691
9692         reg = DSPCNTR(intel_crtc->plane);
9693         dspcntr = I915_READ(reg);
9694
9695         if (INTEL_INFO(dev)->gen >= 4) {
9696                 if (obj->tiling_mode != I915_TILING_NONE)
9697                         dspcntr |= DISPPLANE_TILED;
9698                 else
9699                         dspcntr &= ~DISPPLANE_TILED;
9700         }
9701         I915_WRITE(reg, dspcntr);
9702
9703         I915_WRITE(DSPSURF(intel_crtc->plane),
9704                    intel_crtc->unpin_work->gtt_offset);
9705         POSTING_READ(DSPSURF(intel_crtc->plane));
9706 }
9707
9708 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9709 {
9710         struct intel_engine_cs *ring;
9711         int ret;
9712
9713         lockdep_assert_held(&obj->base.dev->struct_mutex);
9714
9715         if (!obj->last_write_seqno)
9716                 return 0;
9717
9718         ring = obj->ring;
9719
9720         if (i915_seqno_passed(ring->get_seqno(ring, true),
9721                               obj->last_write_seqno))
9722                 return 0;
9723
9724         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9725         if (ret)
9726                 return ret;
9727
9728         if (WARN_ON(!ring->irq_get(ring)))
9729                 return 0;
9730
9731         return 1;
9732 }
9733
9734 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9735 {
9736         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9737         struct intel_crtc *intel_crtc;
9738         unsigned long irq_flags;
9739         u32 seqno;
9740
9741         seqno = ring->get_seqno(ring, false);
9742
9743         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9744         for_each_intel_crtc(ring->dev, intel_crtc) {
9745                 struct intel_mmio_flip *mmio_flip;
9746
9747                 mmio_flip = &intel_crtc->mmio_flip;
9748                 if (mmio_flip->seqno == 0)
9749                         continue;
9750
9751                 if (ring->id != mmio_flip->ring_id)
9752                         continue;
9753
9754                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9755                         intel_do_mmio_flip(intel_crtc);
9756                         mmio_flip->seqno = 0;
9757                         ring->irq_put(ring);
9758                 }
9759         }
9760         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9761 }
9762
9763 static int intel_queue_mmio_flip(struct drm_device *dev,
9764                                  struct drm_crtc *crtc,
9765                                  struct drm_framebuffer *fb,
9766                                  struct drm_i915_gem_object *obj,
9767                                  struct intel_engine_cs *ring,
9768                                  uint32_t flags)
9769 {
9770         struct drm_i915_private *dev_priv = dev->dev_private;
9771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9772         unsigned long irq_flags;
9773         int ret;
9774
9775         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9776                 return -EBUSY;
9777
9778         ret = intel_postpone_flip(obj);
9779         if (ret < 0)
9780                 return ret;
9781         if (ret == 0) {
9782                 intel_do_mmio_flip(intel_crtc);
9783                 return 0;
9784         }
9785
9786         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9787         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9788         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9789         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9790
9791         /*
9792          * Double check to catch cases where irq fired before
9793          * mmio flip data was ready
9794          */
9795         intel_notify_mmio_flip(obj->ring);
9796         return 0;
9797 }
9798
9799 static int intel_default_queue_flip(struct drm_device *dev,
9800                                     struct drm_crtc *crtc,
9801                                     struct drm_framebuffer *fb,
9802                                     struct drm_i915_gem_object *obj,
9803                                     struct intel_engine_cs *ring,
9804                                     uint32_t flags)
9805 {
9806         return -ENODEV;
9807 }
9808
9809 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9810                                          struct drm_crtc *crtc)
9811 {
9812         struct drm_i915_private *dev_priv = dev->dev_private;
9813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9814         struct intel_unpin_work *work = intel_crtc->unpin_work;
9815         u32 addr;
9816
9817         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9818                 return true;
9819
9820         if (!work->enable_stall_check)
9821                 return false;
9822
9823         if (work->flip_ready_vblank == 0) {
9824                 if (work->flip_queued_ring &&
9825                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9826                                        work->flip_queued_seqno))
9827                         return false;
9828
9829                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9830         }
9831
9832         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9833                 return false;
9834
9835         /* Potential stall - if we see that the flip has happened,
9836          * assume a missed interrupt. */
9837         if (INTEL_INFO(dev)->gen >= 4)
9838                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9839         else
9840                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9841
9842         /* There is a potential issue here with a false positive after a flip
9843          * to the same address. We could address this by checking for a
9844          * non-incrementing frame counter.
9845          */
9846         return addr == work->gtt_offset;
9847 }
9848
9849 void intel_check_page_flip(struct drm_device *dev, int pipe)
9850 {
9851         struct drm_i915_private *dev_priv = dev->dev_private;
9852         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9854         unsigned long flags;
9855
9856         if (crtc == NULL)
9857                 return;
9858
9859         spin_lock_irqsave(&dev->event_lock, flags);
9860         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9861                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9862                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9863                 page_flip_completed(intel_crtc);
9864         }
9865         spin_unlock_irqrestore(&dev->event_lock, flags);
9866 }
9867
9868 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9869                                 struct drm_framebuffer *fb,
9870                                 struct drm_pending_vblank_event *event,
9871                                 uint32_t page_flip_flags)
9872 {
9873         struct drm_device *dev = crtc->dev;
9874         struct drm_i915_private *dev_priv = dev->dev_private;
9875         struct drm_framebuffer *old_fb = crtc->primary->fb;
9876         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9878         enum pipe pipe = intel_crtc->pipe;
9879         struct intel_unpin_work *work;
9880         struct intel_engine_cs *ring;
9881         unsigned long flags;
9882         int ret;
9883
9884         //trigger software GT busyness calculation
9885         gen8_flip_interrupt(dev);
9886
9887         /*
9888          * drm_mode_page_flip_ioctl() should already catch this, but double
9889          * check to be safe.  In the future we may enable pageflipping from
9890          * a disabled primary plane.
9891          */
9892         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9893                 return -EBUSY;
9894
9895         /* Can't change pixel format via MI display flips. */
9896         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9897                 return -EINVAL;
9898
9899         /*
9900          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9901          * Note that pitch changes could also affect these register.
9902          */
9903         if (INTEL_INFO(dev)->gen > 3 &&
9904             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9905              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9906                 return -EINVAL;
9907
9908         if (i915_terminally_wedged(&dev_priv->gpu_error))
9909                 goto out_hang;
9910
9911         work = kzalloc(sizeof(*work), GFP_KERNEL);
9912         if (work == NULL)
9913                 return -ENOMEM;
9914
9915         work->event = event;
9916         work->crtc = crtc;
9917         work->old_fb_obj = intel_fb_obj(old_fb);
9918         INIT_WORK(&work->work, intel_unpin_work_fn);
9919
9920         ret = drm_crtc_vblank_get(crtc);
9921         if (ret)
9922                 goto free_work;
9923
9924         /* We borrow the event spin lock for protecting unpin_work */
9925         spin_lock_irqsave(&dev->event_lock, flags);
9926         if (intel_crtc->unpin_work) {
9927                 /* Before declaring the flip queue wedged, check if
9928                  * the hardware completed the operation behind our backs.
9929                  */
9930                 if (__intel_pageflip_stall_check(dev, crtc)) {
9931                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9932                         page_flip_completed(intel_crtc);
9933                 } else {
9934                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9935                         spin_unlock_irqrestore(&dev->event_lock, flags);
9936
9937                         drm_crtc_vblank_put(crtc);
9938                         kfree(work);
9939                         return -EBUSY;
9940                 }
9941         }
9942         intel_crtc->unpin_work = work;
9943         spin_unlock_irqrestore(&dev->event_lock, flags);
9944
9945         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9946                 flush_workqueue(dev_priv->wq);
9947
9948         ret = i915_mutex_lock_interruptible(dev);
9949         if (ret)
9950                 goto cleanup;
9951
9952         /* Reference the objects for the scheduled work. */
9953         drm_gem_object_reference(&work->old_fb_obj->base);
9954         drm_gem_object_reference(&obj->base);
9955
9956         crtc->primary->fb = fb;
9957
9958         work->pending_flip_obj = obj;
9959
9960         atomic_inc(&intel_crtc->unpin_work_count);
9961         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9962
9963         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9964                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9965
9966         if (IS_VALLEYVIEW(dev)) {
9967                 ring = &dev_priv->ring[BCS];
9968                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9969                         /* vlv: DISPLAY_FLIP fails to change tiling */
9970                         ring = NULL;
9971         } else if (IS_IVYBRIDGE(dev)) {
9972                 ring = &dev_priv->ring[BCS];
9973         } else if (INTEL_INFO(dev)->gen >= 7) {
9974                 ring = obj->ring;
9975                 if (ring == NULL || ring->id != RCS)
9976                         ring = &dev_priv->ring[BCS];
9977         } else {
9978                 ring = &dev_priv->ring[RCS];
9979         }
9980
9981         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9982         if (ret)
9983                 goto cleanup_pending;
9984
9985         work->gtt_offset =
9986                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9987
9988         if (use_mmio_flip(ring, obj)) {
9989                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9990                                             page_flip_flags);
9991                 if (ret)
9992                         goto cleanup_unpin;
9993
9994                 work->flip_queued_seqno = obj->last_write_seqno;
9995                 work->flip_queued_ring = obj->ring;
9996         } else {
9997                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9998                                                    page_flip_flags);
9999                 if (ret)
10000                         goto cleanup_unpin;
10001
10002                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10003                 work->flip_queued_ring = ring;
10004         }
10005
10006         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10007         work->enable_stall_check = true;
10008
10009         i915_gem_track_fb(work->old_fb_obj, obj,
10010                           INTEL_FRONTBUFFER_PRIMARY(pipe));
10011
10012         intel_disable_fbc(dev);
10013         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10014         mutex_unlock(&dev->struct_mutex);
10015
10016         trace_i915_flip_request(intel_crtc->plane, obj);
10017
10018         return 0;
10019
10020 cleanup_unpin:
10021         intel_unpin_fb_obj(obj);
10022 cleanup_pending:
10023         atomic_dec(&intel_crtc->unpin_work_count);
10024         crtc->primary->fb = old_fb;
10025         drm_gem_object_unreference(&work->old_fb_obj->base);
10026         drm_gem_object_unreference(&obj->base);
10027         mutex_unlock(&dev->struct_mutex);
10028
10029 cleanup:
10030         spin_lock_irqsave(&dev->event_lock, flags);
10031         intel_crtc->unpin_work = NULL;
10032         spin_unlock_irqrestore(&dev->event_lock, flags);
10033
10034         drm_crtc_vblank_put(crtc);
10035 free_work:
10036         kfree(work);
10037
10038         if (ret == -EIO) {
10039 out_hang:
10040                 intel_crtc_wait_for_pending_flips(crtc);
10041                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10042                 if (ret == 0 && event)
10043                         drm_send_vblank_event(dev, pipe, event);
10044         }
10045         return ret;
10046 }
10047
10048 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10049         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10050         .load_lut = intel_crtc_load_lut,
10051 };
10052
10053 /**
10054  * intel_modeset_update_staged_output_state
10055  *
10056  * Updates the staged output configuration state, e.g. after we've read out the
10057  * current hw state.
10058  */
10059 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10060 {
10061         struct intel_crtc *crtc;
10062         struct intel_encoder *encoder;
10063         struct intel_connector *connector;
10064
10065         list_for_each_entry(connector, &dev->mode_config.connector_list,
10066                             base.head) {
10067                 connector->new_encoder =
10068                         to_intel_encoder(connector->base.encoder);
10069         }
10070
10071         for_each_intel_encoder(dev, encoder) {
10072                 encoder->new_crtc =
10073                         to_intel_crtc(encoder->base.crtc);
10074         }
10075
10076         for_each_intel_crtc(dev, crtc) {
10077                 crtc->new_enabled = crtc->base.enabled;
10078
10079                 if (crtc->new_enabled)
10080                         crtc->new_config = &crtc->config;
10081                 else
10082                         crtc->new_config = NULL;
10083         }
10084 }
10085
10086 /**
10087  * intel_modeset_commit_output_state
10088  *
10089  * This function copies the stage display pipe configuration to the real one.
10090  */
10091 static void intel_modeset_commit_output_state(struct drm_device *dev)
10092 {
10093         struct intel_crtc *crtc;
10094         struct intel_encoder *encoder;
10095         struct intel_connector *connector;
10096
10097         list_for_each_entry(connector, &dev->mode_config.connector_list,
10098                             base.head) {
10099                 connector->base.encoder = &connector->new_encoder->base;
10100         }
10101
10102         for_each_intel_encoder(dev, encoder) {
10103                 encoder->base.crtc = &encoder->new_crtc->base;
10104         }
10105
10106         for_each_intel_crtc(dev, crtc) {
10107                 crtc->base.enabled = crtc->new_enabled;
10108         }
10109 }
10110
10111 static void
10112 connected_sink_compute_bpp(struct intel_connector *connector,
10113                            struct intel_crtc_config *pipe_config)
10114 {
10115         int bpp = pipe_config->pipe_bpp;
10116
10117         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10118                 connector->base.base.id,
10119                 connector->base.name);
10120
10121         /* Don't use an invalid EDID bpc value */
10122         if (connector->base.display_info.bpc &&
10123             connector->base.display_info.bpc * 3 < bpp) {
10124                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10125                               bpp, connector->base.display_info.bpc*3);
10126                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10127         }
10128
10129         /* Clamp bpp to 8 on screens without EDID 1.4 */
10130         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10131                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10132                               bpp);
10133                 pipe_config->pipe_bpp = 24;
10134         }
10135 }
10136
10137 static int
10138 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10139                           struct drm_framebuffer *fb,
10140                           struct intel_crtc_config *pipe_config)
10141 {
10142         struct drm_device *dev = crtc->base.dev;
10143         struct intel_connector *connector;
10144         int bpp;
10145
10146         switch (fb->pixel_format) {
10147         case DRM_FORMAT_C8:
10148                 bpp = 8*3; /* since we go through a colormap */
10149                 break;
10150         case DRM_FORMAT_XRGB1555:
10151         case DRM_FORMAT_ARGB1555:
10152                 /* checked in intel_framebuffer_init already */
10153                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10154                         return -EINVAL;
10155         case DRM_FORMAT_RGB565:
10156                 bpp = 6*3; /* min is 18bpp */
10157                 break;
10158         case DRM_FORMAT_XBGR8888:
10159         case DRM_FORMAT_ABGR8888:
10160                 /* checked in intel_framebuffer_init already */
10161                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10162                         return -EINVAL;
10163         case DRM_FORMAT_XRGB8888:
10164         case DRM_FORMAT_ARGB8888:
10165                 bpp = 8*3;
10166                 break;
10167         case DRM_FORMAT_XRGB2101010:
10168         case DRM_FORMAT_ARGB2101010:
10169         case DRM_FORMAT_XBGR2101010:
10170         case DRM_FORMAT_ABGR2101010:
10171                 /* checked in intel_framebuffer_init already */
10172                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10173                         return -EINVAL;
10174                 bpp = 10*3;
10175                 break;
10176         /* TODO: gen4+ supports 16 bpc floating point, too. */
10177         default:
10178                 DRM_DEBUG_KMS("unsupported depth\n");
10179                 return -EINVAL;
10180         }
10181
10182         pipe_config->pipe_bpp = bpp;
10183
10184         /* Clamp display bpp to EDID value */
10185         list_for_each_entry(connector, &dev->mode_config.connector_list,
10186                             base.head) {
10187                 if (!connector->new_encoder ||
10188                     connector->new_encoder->new_crtc != crtc)
10189                         continue;
10190
10191                 connected_sink_compute_bpp(connector, pipe_config);
10192         }
10193
10194         return bpp;
10195 }
10196
10197 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10198 {
10199         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10200                         "type: 0x%x flags: 0x%x\n",
10201                 mode->crtc_clock,
10202                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10203                 mode->crtc_hsync_end, mode->crtc_htotal,
10204                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10205                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10206 }
10207
10208 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10209                                    struct intel_crtc_config *pipe_config,
10210                                    const char *context)
10211 {
10212         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10213                       context, pipe_name(crtc->pipe));
10214
10215         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10216         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10217                       pipe_config->pipe_bpp, pipe_config->dither);
10218         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10219                       pipe_config->has_pch_encoder,
10220                       pipe_config->fdi_lanes,
10221                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10222                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10223                       pipe_config->fdi_m_n.tu);
10224         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10225                       pipe_config->has_dp_encoder,
10226                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10227                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10228                       pipe_config->dp_m_n.tu);
10229
10230         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10231                       pipe_config->has_dp_encoder,
10232                       pipe_config->dp_m2_n2.gmch_m,
10233                       pipe_config->dp_m2_n2.gmch_n,
10234                       pipe_config->dp_m2_n2.link_m,
10235                       pipe_config->dp_m2_n2.link_n,
10236                       pipe_config->dp_m2_n2.tu);
10237
10238         DRM_DEBUG_KMS("requested mode:\n");
10239         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10240         DRM_DEBUG_KMS("adjusted mode:\n");
10241         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10242         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10243         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10244         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10245                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10246         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10247                       pipe_config->gmch_pfit.control,
10248                       pipe_config->gmch_pfit.pgm_ratios,
10249                       pipe_config->gmch_pfit.lvds_border_bits);
10250         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10251                       pipe_config->pch_pfit.pos,
10252                       pipe_config->pch_pfit.size,
10253                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10254         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10255         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10256 }
10257
10258 static bool encoders_cloneable(const struct intel_encoder *a,
10259                                const struct intel_encoder *b)
10260 {
10261         /* masks could be asymmetric, so check both ways */
10262         return a == b || (a->cloneable & (1 << b->type) &&
10263                           b->cloneable & (1 << a->type));
10264 }
10265
10266 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10267                                          struct intel_encoder *encoder)
10268 {
10269         struct drm_device *dev = crtc->base.dev;
10270         struct intel_encoder *source_encoder;
10271
10272         for_each_intel_encoder(dev, source_encoder) {
10273                 if (source_encoder->new_crtc != crtc)
10274                         continue;
10275
10276                 if (!encoders_cloneable(encoder, source_encoder))
10277                         return false;
10278         }
10279
10280         return true;
10281 }
10282
10283 static bool check_encoder_cloning(struct intel_crtc *crtc)
10284 {
10285         struct drm_device *dev = crtc->base.dev;
10286         struct intel_encoder *encoder;
10287
10288         for_each_intel_encoder(dev, encoder) {
10289                 if (encoder->new_crtc != crtc)
10290                         continue;
10291
10292                 if (!check_single_encoder_cloning(crtc, encoder))
10293                         return false;
10294         }
10295
10296         return true;
10297 }
10298
10299 static struct intel_crtc_config *
10300 intel_modeset_pipe_config(struct drm_crtc *crtc,
10301                           struct drm_framebuffer *fb,
10302                           struct drm_display_mode *mode)
10303 {
10304         struct drm_device *dev = crtc->dev;
10305         struct intel_encoder *encoder;
10306         struct intel_crtc_config *pipe_config;
10307         int plane_bpp, ret = -EINVAL;
10308         bool retry = true;
10309
10310         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10311                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10312                 return ERR_PTR(-EINVAL);
10313         }
10314
10315         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10316         if (!pipe_config)
10317                 return ERR_PTR(-ENOMEM);
10318
10319         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10320         drm_mode_copy(&pipe_config->requested_mode, mode);
10321
10322         pipe_config->cpu_transcoder =
10323                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10324         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10325
10326         /*
10327          * Sanitize sync polarity flags based on requested ones. If neither
10328          * positive or negative polarity is requested, treat this as meaning
10329          * negative polarity.
10330          */
10331         if (!(pipe_config->adjusted_mode.flags &
10332               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10333                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10334
10335         if (!(pipe_config->adjusted_mode.flags &
10336               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10337                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10338
10339         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10340          * plane pixel format and any sink constraints into account. Returns the
10341          * source plane bpp so that dithering can be selected on mismatches
10342          * after encoders and crtc also have had their say. */
10343         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10344                                               fb, pipe_config);
10345         if (plane_bpp < 0)
10346                 goto fail;
10347
10348         /*
10349          * Determine the real pipe dimensions. Note that stereo modes can
10350          * increase the actual pipe size due to the frame doubling and
10351          * insertion of additional space for blanks between the frame. This
10352          * is stored in the crtc timings. We use the requested mode to do this
10353          * computation to clearly distinguish it from the adjusted mode, which
10354          * can be changed by the connectors in the below retry loop.
10355          */
10356         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10357         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10358         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10359
10360 encoder_retry:
10361         /* Ensure the port clock defaults are reset when retrying. */
10362         pipe_config->port_clock = 0;
10363         pipe_config->pixel_multiplier = 1;
10364
10365         /* Fill in default crtc timings, allow encoders to overwrite them. */
10366         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10367
10368         /* Pass our mode to the connectors and the CRTC to give them a chance to
10369          * adjust it according to limitations or connector properties, and also
10370          * a chance to reject the mode entirely.
10371          */
10372         for_each_intel_encoder(dev, encoder) {
10373
10374                 if (&encoder->new_crtc->base != crtc)
10375                         continue;
10376
10377                 if (!(encoder->compute_config(encoder, pipe_config))) {
10378                         DRM_DEBUG_KMS("Encoder config failure\n");
10379                         goto fail;
10380                 }
10381         }
10382
10383         /* Set default port clock if not overwritten by the encoder. Needs to be
10384          * done afterwards in case the encoder adjusts the mode. */
10385         if (!pipe_config->port_clock)
10386                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10387                         * pipe_config->pixel_multiplier;
10388
10389         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10390         if (ret < 0) {
10391                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10392                 goto fail;
10393         }
10394
10395         if (ret == RETRY) {
10396                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10397                         ret = -EINVAL;
10398                         goto fail;
10399                 }
10400
10401                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10402                 retry = false;
10403                 goto encoder_retry;
10404         }
10405
10406         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10407         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10408                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10409
10410         return pipe_config;
10411 fail:
10412         kfree(pipe_config);
10413         return ERR_PTR(ret);
10414 }
10415
10416 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10417  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10418 static void
10419 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10420                              unsigned *prepare_pipes, unsigned *disable_pipes)
10421 {
10422         struct intel_crtc *intel_crtc;
10423         struct drm_device *dev = crtc->dev;
10424         struct intel_encoder *encoder;
10425         struct intel_connector *connector;
10426         struct drm_crtc *tmp_crtc;
10427
10428         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10429
10430         /* Check which crtcs have changed outputs connected to them, these need
10431          * to be part of the prepare_pipes mask. We don't (yet) support global
10432          * modeset across multiple crtcs, so modeset_pipes will only have one
10433          * bit set at most. */
10434         list_for_each_entry(connector, &dev->mode_config.connector_list,
10435                             base.head) {
10436                 if (connector->base.encoder == &connector->new_encoder->base)
10437                         continue;
10438
10439                 if (connector->base.encoder) {
10440                         tmp_crtc = connector->base.encoder->crtc;
10441
10442                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10443                 }
10444
10445                 if (connector->new_encoder)
10446                         *prepare_pipes |=
10447                                 1 << connector->new_encoder->new_crtc->pipe;
10448         }
10449
10450         for_each_intel_encoder(dev, encoder) {
10451                 if (encoder->base.crtc == &encoder->new_crtc->base)
10452                         continue;
10453
10454                 if (encoder->base.crtc) {
10455                         tmp_crtc = encoder->base.crtc;
10456
10457                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10458                 }
10459
10460                 if (encoder->new_crtc)
10461                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10462         }
10463
10464         /* Check for pipes that will be enabled/disabled ... */
10465         for_each_intel_crtc(dev, intel_crtc) {
10466                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10467                         continue;
10468
10469                 if (!intel_crtc->new_enabled)
10470                         *disable_pipes |= 1 << intel_crtc->pipe;
10471                 else
10472                         *prepare_pipes |= 1 << intel_crtc->pipe;
10473         }
10474
10475
10476         /* set_mode is also used to update properties on life display pipes. */
10477         intel_crtc = to_intel_crtc(crtc);
10478         if (intel_crtc->new_enabled)
10479                 *prepare_pipes |= 1 << intel_crtc->pipe;
10480
10481         /*
10482          * For simplicity do a full modeset on any pipe where the output routing
10483          * changed. We could be more clever, but that would require us to be
10484          * more careful with calling the relevant encoder->mode_set functions.
10485          */
10486         if (*prepare_pipes)
10487                 *modeset_pipes = *prepare_pipes;
10488
10489         /* ... and mask these out. */
10490         *modeset_pipes &= ~(*disable_pipes);
10491         *prepare_pipes &= ~(*disable_pipes);
10492
10493         /*
10494          * HACK: We don't (yet) fully support global modesets. intel_set_config
10495          * obies this rule, but the modeset restore mode of
10496          * intel_modeset_setup_hw_state does not.
10497          */
10498         *modeset_pipes &= 1 << intel_crtc->pipe;
10499         *prepare_pipes &= 1 << intel_crtc->pipe;
10500
10501         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10502                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10503 }
10504
10505 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10506 {
10507         struct drm_encoder *encoder;
10508         struct drm_device *dev = crtc->dev;
10509
10510         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10511                 if (encoder->crtc == crtc)
10512                         return true;
10513
10514         return false;
10515 }
10516
10517 static void
10518 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10519 {
10520         struct intel_encoder *intel_encoder;
10521         struct intel_crtc *intel_crtc;
10522         struct drm_connector *connector;
10523
10524         for_each_intel_encoder(dev, intel_encoder) {
10525                 if (!intel_encoder->base.crtc)
10526                         continue;
10527
10528                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10529
10530                 if (prepare_pipes & (1 << intel_crtc->pipe))
10531                         intel_encoder->connectors_active = false;
10532         }
10533
10534         intel_modeset_commit_output_state(dev);
10535
10536         /* Double check state. */
10537         for_each_intel_crtc(dev, intel_crtc) {
10538                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10539                 WARN_ON(intel_crtc->new_config &&
10540                         intel_crtc->new_config != &intel_crtc->config);
10541                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10542         }
10543
10544         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10545                 if (!connector->encoder || !connector->encoder->crtc)
10546                         continue;
10547
10548                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10549
10550                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10551                         struct drm_property *dpms_property =
10552                                 dev->mode_config.dpms_property;
10553
10554                         connector->dpms = DRM_MODE_DPMS_ON;
10555                         drm_object_property_set_value(&connector->base,
10556                                                          dpms_property,
10557                                                          DRM_MODE_DPMS_ON);
10558
10559                         intel_encoder = to_intel_encoder(connector->encoder);
10560                         intel_encoder->connectors_active = true;
10561                 }
10562         }
10563
10564 }
10565
10566 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10567 {
10568         int diff;
10569
10570         if (clock1 == clock2)
10571                 return true;
10572
10573         if (!clock1 || !clock2)
10574                 return false;
10575
10576         diff = abs(clock1 - clock2);
10577
10578         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10579                 return true;
10580
10581         return false;
10582 }
10583
10584 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10585         list_for_each_entry((intel_crtc), \
10586                             &(dev)->mode_config.crtc_list, \
10587                             base.head) \
10588                 if (mask & (1 <<(intel_crtc)->pipe))
10589
10590 static bool
10591 intel_pipe_config_compare(struct drm_device *dev,
10592                           struct intel_crtc_config *current_config,
10593                           struct intel_crtc_config *pipe_config)
10594 {
10595 #define PIPE_CONF_CHECK_X(name) \
10596         if (current_config->name != pipe_config->name) { \
10597                 DRM_ERROR("mismatch in " #name " " \
10598                           "(expected 0x%08x, found 0x%08x)\n", \
10599                           current_config->name, \
10600                           pipe_config->name); \
10601                 return false; \
10602         }
10603
10604 #define PIPE_CONF_CHECK_I(name) \
10605         if (current_config->name != pipe_config->name) { \
10606                 DRM_ERROR("mismatch in " #name " " \
10607                           "(expected %i, found %i)\n", \
10608                           current_config->name, \
10609                           pipe_config->name); \
10610                 return false; \
10611         }
10612
10613 /* This is required for BDW+ where there is only one set of registers for
10614  * switching between high and low RR.
10615  * This macro can be used whenever a comparison has to be made between one
10616  * hw state and multiple sw state variables.
10617  */
10618 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10619         if ((current_config->name != pipe_config->name) && \
10620                 (current_config->alt_name != pipe_config->name)) { \
10621                         DRM_ERROR("mismatch in " #name " " \
10622                                   "(expected %i or %i, found %i)\n", \
10623                                   current_config->name, \
10624                                   current_config->alt_name, \
10625                                   pipe_config->name); \
10626                         return false; \
10627         }
10628
10629 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10630         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10631                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10632                           "(expected %i, found %i)\n", \
10633                           current_config->name & (mask), \
10634                           pipe_config->name & (mask)); \
10635                 return false; \
10636         }
10637
10638 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10639         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10640                 DRM_ERROR("mismatch in " #name " " \
10641                           "(expected %i, found %i)\n", \
10642                           current_config->name, \
10643                           pipe_config->name); \
10644                 return false; \
10645         }
10646
10647 #define PIPE_CONF_QUIRK(quirk)  \
10648         ((current_config->quirks | pipe_config->quirks) & (quirk))
10649
10650         PIPE_CONF_CHECK_I(cpu_transcoder);
10651
10652         PIPE_CONF_CHECK_I(has_pch_encoder);
10653         PIPE_CONF_CHECK_I(fdi_lanes);
10654         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10655         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10656         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10657         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10658         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10659
10660         PIPE_CONF_CHECK_I(has_dp_encoder);
10661
10662         if (INTEL_INFO(dev)->gen < 8) {
10663                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10664                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10665                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10666                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10667                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10668
10669                 if (current_config->has_drrs) {
10670                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10671                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10672                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10673                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10674                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10675                 }
10676         } else {
10677                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10678                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10679                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10680                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10681                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10682         }
10683
10684         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10685         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10686         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10687         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10688         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10689         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10690
10691         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10692         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10693         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10694         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10695         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10696         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10697
10698         PIPE_CONF_CHECK_I(pixel_multiplier);
10699         PIPE_CONF_CHECK_I(has_hdmi_sink);
10700         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10701             IS_VALLEYVIEW(dev))
10702                 PIPE_CONF_CHECK_I(limited_color_range);
10703
10704         PIPE_CONF_CHECK_I(has_audio);
10705
10706         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10707                               DRM_MODE_FLAG_INTERLACE);
10708
10709         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10710                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10711                                       DRM_MODE_FLAG_PHSYNC);
10712                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10713                                       DRM_MODE_FLAG_NHSYNC);
10714                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10715                                       DRM_MODE_FLAG_PVSYNC);
10716                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10717                                       DRM_MODE_FLAG_NVSYNC);
10718         }
10719
10720         PIPE_CONF_CHECK_I(pipe_src_w);
10721         PIPE_CONF_CHECK_I(pipe_src_h);
10722
10723         /*
10724          * FIXME: BIOS likes to set up a cloned config with lvds+external
10725          * screen. Since we don't yet re-compute the pipe config when moving
10726          * just the lvds port away to another pipe the sw tracking won't match.
10727          *
10728          * Proper atomic modesets with recomputed global state will fix this.
10729          * Until then just don't check gmch state for inherited modes.
10730          */
10731         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10732                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10733                 /* pfit ratios are autocomputed by the hw on gen4+ */
10734                 if (INTEL_INFO(dev)->gen < 4)
10735                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10736                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10737         }
10738
10739         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10740         if (current_config->pch_pfit.enabled) {
10741                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10742                 PIPE_CONF_CHECK_I(pch_pfit.size);
10743         }
10744
10745         /* BDW+ don't expose a synchronous way to read the state */
10746         if (IS_HASWELL(dev))
10747                 PIPE_CONF_CHECK_I(ips_enabled);
10748
10749         PIPE_CONF_CHECK_I(double_wide);
10750
10751         PIPE_CONF_CHECK_X(ddi_pll_sel);
10752
10753         PIPE_CONF_CHECK_I(shared_dpll);
10754         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10755         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10756         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10757         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10758         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10759
10760         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10761                 PIPE_CONF_CHECK_I(pipe_bpp);
10762
10763         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10764         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10765
10766 #undef PIPE_CONF_CHECK_X
10767 #undef PIPE_CONF_CHECK_I
10768 #undef PIPE_CONF_CHECK_I_ALT
10769 #undef PIPE_CONF_CHECK_FLAGS
10770 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10771 #undef PIPE_CONF_QUIRK
10772
10773         return true;
10774 }
10775
10776 static void
10777 check_connector_state(struct drm_device *dev)
10778 {
10779         struct intel_connector *connector;
10780
10781         list_for_each_entry(connector, &dev->mode_config.connector_list,
10782                             base.head) {
10783                 /* This also checks the encoder/connector hw state with the
10784                  * ->get_hw_state callbacks. */
10785                 intel_connector_check_state(connector);
10786
10787                 WARN(&connector->new_encoder->base != connector->base.encoder,
10788                      "connector's staged encoder doesn't match current encoder\n");
10789         }
10790 }
10791
10792 static void
10793 check_encoder_state(struct drm_device *dev)
10794 {
10795         struct intel_encoder *encoder;
10796         struct intel_connector *connector;
10797
10798         for_each_intel_encoder(dev, encoder) {
10799                 bool enabled = false;
10800                 bool active = false;
10801                 enum pipe pipe, tracked_pipe;
10802
10803                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10804                               encoder->base.base.id,
10805                               encoder->base.name);
10806
10807                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10808                      "encoder's stage crtc doesn't match current crtc\n");
10809                 WARN(encoder->connectors_active && !encoder->base.crtc,
10810                      "encoder's active_connectors set, but no crtc\n");
10811
10812                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10813                                     base.head) {
10814                         if (connector->base.encoder != &encoder->base)
10815                                 continue;
10816                         enabled = true;
10817                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10818                                 active = true;
10819                 }
10820                 /*
10821                  * for MST connectors if we unplug the connector is gone
10822                  * away but the encoder is still connected to a crtc
10823                  * until a modeset happens in response to the hotplug.
10824                  */
10825                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10826                         continue;
10827
10828                 WARN(!!encoder->base.crtc != enabled,
10829                      "encoder's enabled state mismatch "
10830                      "(expected %i, found %i)\n",
10831                      !!encoder->base.crtc, enabled);
10832                 WARN(active && !encoder->base.crtc,
10833                      "active encoder with no crtc\n");
10834
10835                 WARN(encoder->connectors_active != active,
10836                      "encoder's computed active state doesn't match tracked active state "
10837                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10838
10839                 active = encoder->get_hw_state(encoder, &pipe);
10840                 WARN(active != encoder->connectors_active,
10841                      "encoder's hw state doesn't match sw tracking "
10842                      "(expected %i, found %i)\n",
10843                      encoder->connectors_active, active);
10844
10845                 if (!encoder->base.crtc)
10846                         continue;
10847
10848                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10849                 WARN(active && pipe != tracked_pipe,
10850                      "active encoder's pipe doesn't match"
10851                      "(expected %i, found %i)\n",
10852                      tracked_pipe, pipe);
10853
10854         }
10855 }
10856
10857 static void
10858 check_crtc_state(struct drm_device *dev)
10859 {
10860         struct drm_i915_private *dev_priv = dev->dev_private;
10861         struct intel_crtc *crtc;
10862         struct intel_encoder *encoder;
10863         struct intel_crtc_config pipe_config;
10864
10865         for_each_intel_crtc(dev, crtc) {
10866                 bool enabled = false;
10867                 bool active = false;
10868
10869                 memset(&pipe_config, 0, sizeof(pipe_config));
10870
10871                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10872                               crtc->base.base.id);
10873
10874                 WARN(crtc->active && !crtc->base.enabled,
10875                      "active crtc, but not enabled in sw tracking\n");
10876
10877                 for_each_intel_encoder(dev, encoder) {
10878                         if (encoder->base.crtc != &crtc->base)
10879                                 continue;
10880                         enabled = true;
10881                         if (encoder->connectors_active)
10882                                 active = true;
10883                 }
10884
10885                 WARN(active != crtc->active,
10886                      "crtc's computed active state doesn't match tracked active state "
10887                      "(expected %i, found %i)\n", active, crtc->active);
10888                 WARN(enabled != crtc->base.enabled,
10889                      "crtc's computed enabled state doesn't match tracked enabled state "
10890                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10891
10892                 active = dev_priv->display.get_pipe_config(crtc,
10893                                                            &pipe_config);
10894
10895                 /* hw state is inconsistent with the pipe quirk */
10896                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10897                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10898                         active = crtc->active;
10899
10900                 for_each_intel_encoder(dev, encoder) {
10901                         enum pipe pipe;
10902                         if (encoder->base.crtc != &crtc->base)
10903                                 continue;
10904                         if (encoder->get_hw_state(encoder, &pipe))
10905                                 encoder->get_config(encoder, &pipe_config);
10906                 }
10907
10908                 WARN(crtc->active != active,
10909                      "crtc active state doesn't match with hw state "
10910                      "(expected %i, found %i)\n", crtc->active, active);
10911
10912                 if (active &&
10913                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10914                         WARN(1, "pipe state doesn't match!\n");
10915                         intel_dump_pipe_config(crtc, &pipe_config,
10916                                                "[hw state]");
10917                         intel_dump_pipe_config(crtc, &crtc->config,
10918                                                "[sw state]");
10919                 }
10920         }
10921 }
10922
10923 static void
10924 check_shared_dpll_state(struct drm_device *dev)
10925 {
10926         struct drm_i915_private *dev_priv = dev->dev_private;
10927         struct intel_crtc *crtc;
10928         struct intel_dpll_hw_state dpll_hw_state;
10929         int i;
10930
10931         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10932                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10933                 int enabled_crtcs = 0, active_crtcs = 0;
10934                 bool active;
10935
10936                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10937
10938                 DRM_DEBUG_KMS("%s\n", pll->name);
10939
10940                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10941
10942                 WARN(pll->active > pll->refcount,
10943                      "more active pll users than references: %i vs %i\n",
10944                      pll->active, pll->refcount);
10945                 WARN(pll->active && !pll->on,
10946                      "pll in active use but not on in sw tracking\n");
10947                 WARN(pll->on && !pll->active,
10948                      "pll in on but not on in use in sw tracking\n");
10949                 WARN(pll->on != active,
10950                      "pll on state mismatch (expected %i, found %i)\n",
10951                      pll->on, active);
10952
10953                 for_each_intel_crtc(dev, crtc) {
10954                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10955                                 enabled_crtcs++;
10956                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10957                                 active_crtcs++;
10958                 }
10959                 WARN(pll->active != active_crtcs,
10960                      "pll active crtcs mismatch (expected %i, found %i)\n",
10961                      pll->active, active_crtcs);
10962                 WARN(pll->refcount != enabled_crtcs,
10963                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10964                      pll->refcount, enabled_crtcs);
10965
10966                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10967                                        sizeof(dpll_hw_state)),
10968                      "pll hw state mismatch\n");
10969         }
10970 }
10971
10972 void
10973 intel_modeset_check_state(struct drm_device *dev)
10974 {
10975         check_connector_state(dev);
10976         check_encoder_state(dev);
10977         check_crtc_state(dev);
10978         check_shared_dpll_state(dev);
10979 }
10980
10981 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10982                                      int dotclock)
10983 {
10984         /*
10985          * FDI already provided one idea for the dotclock.
10986          * Yell if the encoder disagrees.
10987          */
10988         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10989              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10990              pipe_config->adjusted_mode.crtc_clock, dotclock);
10991 }
10992
10993 static void update_scanline_offset(struct intel_crtc *crtc)
10994 {
10995         struct drm_device *dev = crtc->base.dev;
10996
10997         /*
10998          * The scanline counter increments at the leading edge of hsync.
10999          *
11000          * On most platforms it starts counting from vtotal-1 on the
11001          * first active line. That means the scanline counter value is
11002          * always one less than what we would expect. Ie. just after
11003          * start of vblank, which also occurs at start of hsync (on the
11004          * last active line), the scanline counter will read vblank_start-1.
11005          *
11006          * On gen2 the scanline counter starts counting from 1 instead
11007          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11008          * to keep the value positive), instead of adding one.
11009          *
11010          * On HSW+ the behaviour of the scanline counter depends on the output
11011          * type. For DP ports it behaves like most other platforms, but on HDMI
11012          * there's an extra 1 line difference. So we need to add two instead of
11013          * one to the value.
11014          */
11015         if (IS_GEN2(dev)) {
11016                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11017                 int vtotal;
11018
11019                 vtotal = mode->crtc_vtotal;
11020                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11021                         vtotal /= 2;
11022
11023                 crtc->scanline_offset = vtotal - 1;
11024         } else if (HAS_DDI(dev) &&
11025                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11026                 crtc->scanline_offset = 2;
11027         } else
11028                 crtc->scanline_offset = 1;
11029 }
11030
11031 static int __intel_set_mode(struct drm_crtc *crtc,
11032                             struct drm_display_mode *mode,
11033                             int x, int y, struct drm_framebuffer *fb)
11034 {
11035         struct drm_device *dev = crtc->dev;
11036         struct drm_i915_private *dev_priv = dev->dev_private;
11037         struct drm_display_mode *saved_mode;
11038         struct intel_crtc_config *pipe_config = NULL;
11039         struct intel_crtc *intel_crtc;
11040         unsigned disable_pipes, prepare_pipes, modeset_pipes;
11041         int ret = 0;
11042
11043         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11044         if (!saved_mode)
11045                 return -ENOMEM;
11046
11047         intel_modeset_affected_pipes(crtc, &modeset_pipes,
11048                                      &prepare_pipes, &disable_pipes);
11049
11050         *saved_mode = crtc->mode;
11051
11052         /* Hack: Because we don't (yet) support global modeset on multiple
11053          * crtcs, we don't keep track of the new mode for more than one crtc.
11054          * Hence simply check whether any bit is set in modeset_pipes in all the
11055          * pieces of code that are not yet converted to deal with mutliple crtcs
11056          * changing their mode at the same time. */
11057         if (modeset_pipes) {
11058                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11059                 if (IS_ERR(pipe_config)) {
11060                         ret = PTR_ERR(pipe_config);
11061                         pipe_config = NULL;
11062
11063                         goto out;
11064                 }
11065                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11066                                        "[modeset]");
11067                 to_intel_crtc(crtc)->new_config = pipe_config;
11068         }
11069
11070         /*
11071          * See if the config requires any additional preparation, e.g.
11072          * to adjust global state with pipes off.  We need to do this
11073          * here so we can get the modeset_pipe updated config for the new
11074          * mode set on this crtc.  For other crtcs we need to use the
11075          * adjusted_mode bits in the crtc directly.
11076          */
11077         if (IS_VALLEYVIEW(dev)) {
11078                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11079
11080                 /* may have added more to prepare_pipes than we should */
11081                 prepare_pipes &= ~disable_pipes;
11082         }
11083
11084         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11085                 intel_crtc_disable(&intel_crtc->base);
11086
11087         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11088                 if (intel_crtc->base.enabled)
11089                         dev_priv->display.crtc_disable(&intel_crtc->base);
11090         }
11091
11092         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11093          * to set it here already despite that we pass it down the callchain.
11094          */
11095         if (modeset_pipes) {
11096                 crtc->mode = *mode;
11097                 /* mode_set/enable/disable functions rely on a correct pipe
11098                  * config. */
11099                 to_intel_crtc(crtc)->config = *pipe_config;
11100                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11101
11102                 /*
11103                  * Calculate and store various constants which
11104                  * are later needed by vblank and swap-completion
11105                  * timestamping. They are derived from true hwmode.
11106                  */
11107                 drm_calc_timestamping_constants(crtc,
11108                                                 &pipe_config->adjusted_mode);
11109         }
11110
11111         /* Only after disabling all output pipelines that will be changed can we
11112          * update the the output configuration. */
11113         intel_modeset_update_state(dev, prepare_pipes);
11114
11115         if (dev_priv->display.modeset_global_resources)
11116                 dev_priv->display.modeset_global_resources(dev);
11117
11118         /* Set up the DPLL and any encoders state that needs to adjust or depend
11119          * on the DPLL.
11120          */
11121         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11122                 struct drm_framebuffer *old_fb = crtc->primary->fb;
11123                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11124                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11125
11126                 mutex_lock(&dev->struct_mutex);
11127                 ret = intel_pin_and_fence_fb_obj(dev,
11128                                                  obj,
11129                                                  NULL);
11130                 if (ret != 0) {
11131                         DRM_ERROR("pin & fence failed\n");
11132                         mutex_unlock(&dev->struct_mutex);
11133                         goto done;
11134                 }
11135                 if (old_fb)
11136                         intel_unpin_fb_obj(old_obj);
11137                 i915_gem_track_fb(old_obj, obj,
11138                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11139                 mutex_unlock(&dev->struct_mutex);
11140
11141                 crtc->primary->fb = fb;
11142                 crtc->x = x;
11143                 crtc->y = y;
11144
11145                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11146                                                       x, y, fb);
11147                 if (ret)
11148                         goto done;
11149         }
11150
11151         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11152         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11153                 update_scanline_offset(intel_crtc);
11154
11155                 dev_priv->display.crtc_enable(&intel_crtc->base);
11156         }
11157
11158         /* FIXME: add subpixel order */
11159 done:
11160         if (ret && crtc->enabled)
11161                 crtc->mode = *saved_mode;
11162
11163 out:
11164         kfree(pipe_config);
11165         kfree(saved_mode);
11166         return ret;
11167 }
11168
11169 static int intel_set_mode(struct drm_crtc *crtc,
11170                           struct drm_display_mode *mode,
11171                           int x, int y, struct drm_framebuffer *fb)
11172 {
11173         int ret;
11174
11175         ret = __intel_set_mode(crtc, mode, x, y, fb);
11176
11177         if (ret == 0)
11178                 intel_modeset_check_state(crtc->dev);
11179
11180         return ret;
11181 }
11182
11183 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11184 {
11185         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11186 }
11187
11188 #undef for_each_intel_crtc_masked
11189
11190 static void intel_set_config_free(struct intel_set_config *config)
11191 {
11192         if (!config)
11193                 return;
11194
11195         kfree(config->save_connector_encoders);
11196         kfree(config->save_encoder_crtcs);
11197         kfree(config->save_crtc_enabled);
11198         kfree(config);
11199 }
11200
11201 static int intel_set_config_save_state(struct drm_device *dev,
11202                                        struct intel_set_config *config)
11203 {
11204         struct drm_crtc *crtc;
11205         struct drm_encoder *encoder;
11206         struct drm_connector *connector;
11207         int count;
11208
11209         config->save_crtc_enabled =
11210                 kcalloc(dev->mode_config.num_crtc,
11211                         sizeof(bool), GFP_KERNEL);
11212         if (!config->save_crtc_enabled)
11213                 return -ENOMEM;
11214
11215         config->save_encoder_crtcs =
11216                 kcalloc(dev->mode_config.num_encoder,
11217                         sizeof(struct drm_crtc *), GFP_KERNEL);
11218         if (!config->save_encoder_crtcs)
11219                 return -ENOMEM;
11220
11221         config->save_connector_encoders =
11222                 kcalloc(dev->mode_config.num_connector,
11223                         sizeof(struct drm_encoder *), GFP_KERNEL);
11224         if (!config->save_connector_encoders)
11225                 return -ENOMEM;
11226
11227         /* Copy data. Note that driver private data is not affected.
11228          * Should anything bad happen only the expected state is
11229          * restored, not the drivers personal bookkeeping.
11230          */
11231         count = 0;
11232         for_each_crtc(dev, crtc) {
11233                 config->save_crtc_enabled[count++] = crtc->enabled;
11234         }
11235
11236         count = 0;
11237         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11238                 config->save_encoder_crtcs[count++] = encoder->crtc;
11239         }
11240
11241         count = 0;
11242         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11243                 config->save_connector_encoders[count++] = connector->encoder;
11244         }
11245
11246         return 0;
11247 }
11248
11249 static void intel_set_config_restore_state(struct drm_device *dev,
11250                                            struct intel_set_config *config)
11251 {
11252         struct intel_crtc *crtc;
11253         struct intel_encoder *encoder;
11254         struct intel_connector *connector;
11255         int count;
11256
11257         count = 0;
11258         for_each_intel_crtc(dev, crtc) {
11259                 crtc->new_enabled = config->save_crtc_enabled[count++];
11260
11261                 if (crtc->new_enabled)
11262                         crtc->new_config = &crtc->config;
11263                 else
11264                         crtc->new_config = NULL;
11265         }
11266
11267         count = 0;
11268         for_each_intel_encoder(dev, encoder) {
11269                 encoder->new_crtc =
11270                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11271         }
11272
11273         count = 0;
11274         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11275                 connector->new_encoder =
11276                         to_intel_encoder(config->save_connector_encoders[count++]);
11277         }
11278 }
11279
11280 static bool
11281 is_crtc_connector_off(struct drm_mode_set *set)
11282 {
11283         int i;
11284
11285         if (set->num_connectors == 0)
11286                 return false;
11287
11288         if (WARN_ON(set->connectors == NULL))
11289                 return false;
11290
11291         for (i = 0; i < set->num_connectors; i++)
11292                 if (set->connectors[i]->encoder &&
11293                     set->connectors[i]->encoder->crtc == set->crtc &&
11294                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11295                         return true;
11296
11297         return false;
11298 }
11299
11300 static void
11301 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11302                                       struct intel_set_config *config)
11303 {
11304
11305         /* We should be able to check here if the fb has the same properties
11306          * and then just flip_or_move it */
11307         if (is_crtc_connector_off(set)) {
11308                 config->mode_changed = true;
11309         } else if (set->crtc->primary->fb != set->fb) {
11310                 /*
11311                  * If we have no fb, we can only flip as long as the crtc is
11312                  * active, otherwise we need a full mode set.  The crtc may
11313                  * be active if we've only disabled the primary plane, or
11314                  * in fastboot situations.
11315                  */
11316                 if (set->crtc->primary->fb == NULL) {
11317                         struct intel_crtc *intel_crtc =
11318                                 to_intel_crtc(set->crtc);
11319
11320                         if (intel_crtc->active) {
11321                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11322                                 config->fb_changed = true;
11323                         } else {
11324                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11325                                 config->mode_changed = true;
11326                         }
11327                 } else if (set->fb == NULL) {
11328                         config->mode_changed = true;
11329                 } else if (set->fb->pixel_format !=
11330                            set->crtc->primary->fb->pixel_format) {
11331                         config->mode_changed = true;
11332                 } else {
11333                         config->fb_changed = true;
11334                 }
11335         }
11336
11337         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11338                 config->fb_changed = true;
11339
11340         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11341                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11342                 drm_mode_debug_printmodeline(&set->crtc->mode);
11343                 drm_mode_debug_printmodeline(set->mode);
11344                 config->mode_changed = true;
11345         }
11346
11347         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11348                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11349 }
11350
11351 static int
11352 intel_modeset_stage_output_state(struct drm_device *dev,
11353                                  struct drm_mode_set *set,
11354                                  struct intel_set_config *config)
11355 {
11356         struct intel_connector *connector;
11357         struct intel_encoder *encoder;
11358         struct intel_crtc *crtc;
11359         int ro;
11360
11361         /* The upper layers ensure that we either disable a crtc or have a list
11362          * of connectors. For paranoia, double-check this. */
11363         WARN_ON(!set->fb && (set->num_connectors != 0));
11364         WARN_ON(set->fb && (set->num_connectors == 0));
11365
11366         list_for_each_entry(connector, &dev->mode_config.connector_list,
11367                             base.head) {
11368                 /* Otherwise traverse passed in connector list and get encoders
11369                  * for them. */
11370                 for (ro = 0; ro < set->num_connectors; ro++) {
11371                         if (set->connectors[ro] == &connector->base) {
11372                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11373                                 break;
11374                         }
11375                 }
11376
11377                 /* If we disable the crtc, disable all its connectors. Also, if
11378                  * the connector is on the changing crtc but not on the new
11379                  * connector list, disable it. */
11380                 if ((!set->fb || ro == set->num_connectors) &&
11381                     connector->base.encoder &&
11382                     connector->base.encoder->crtc == set->crtc) {
11383                         connector->new_encoder = NULL;
11384
11385                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11386                                 connector->base.base.id,
11387                                 connector->base.name);
11388                 }
11389
11390
11391                 if (&connector->new_encoder->base != connector->base.encoder) {
11392                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11393                         config->mode_changed = true;
11394                 }
11395         }
11396         /* connector->new_encoder is now updated for all connectors. */
11397
11398         /* Update crtc of enabled connectors. */
11399         list_for_each_entry(connector, &dev->mode_config.connector_list,
11400                             base.head) {
11401                 struct drm_crtc *new_crtc;
11402
11403                 if (!connector->new_encoder)
11404                         continue;
11405
11406                 new_crtc = connector->new_encoder->base.crtc;
11407
11408                 for (ro = 0; ro < set->num_connectors; ro++) {
11409                         if (set->connectors[ro] == &connector->base)
11410                                 new_crtc = set->crtc;
11411                 }
11412
11413                 /* Make sure the new CRTC will work with the encoder */
11414                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11415                                          new_crtc)) {
11416                         return -EINVAL;
11417                 }
11418                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11419
11420                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11421                         connector->base.base.id,
11422                         connector->base.name,
11423                         new_crtc->base.id);
11424         }
11425
11426         /* Check for any encoders that needs to be disabled. */
11427         for_each_intel_encoder(dev, encoder) {
11428                 int num_connectors = 0;
11429                 list_for_each_entry(connector,
11430                                     &dev->mode_config.connector_list,
11431                                     base.head) {
11432                         if (connector->new_encoder == encoder) {
11433                                 WARN_ON(!connector->new_encoder->new_crtc);
11434                                 num_connectors++;
11435                         }
11436                 }
11437
11438                 if (num_connectors == 0)
11439                         encoder->new_crtc = NULL;
11440                 else if (num_connectors > 1)
11441                         return -EINVAL;
11442
11443                 /* Only now check for crtc changes so we don't miss encoders
11444                  * that will be disabled. */
11445                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11446                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11447                         config->mode_changed = true;
11448                 }
11449         }
11450         /* Now we've also updated encoder->new_crtc for all encoders. */
11451         list_for_each_entry(connector, &dev->mode_config.connector_list,
11452                             base.head) {
11453                 if (connector->new_encoder)
11454                         if (connector->new_encoder != connector->encoder)
11455                                 connector->encoder = connector->new_encoder;
11456         }
11457         for_each_intel_crtc(dev, crtc) {
11458                 crtc->new_enabled = false;
11459
11460                 for_each_intel_encoder(dev, encoder) {
11461                         if (encoder->new_crtc == crtc) {
11462                                 crtc->new_enabled = true;
11463                                 break;
11464                         }
11465                 }
11466
11467                 if (crtc->new_enabled != crtc->base.enabled) {
11468                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11469                                       crtc->new_enabled ? "en" : "dis");
11470                         config->mode_changed = true;
11471                 }
11472
11473                 if (crtc->new_enabled)
11474                         crtc->new_config = &crtc->config;
11475                 else
11476                         crtc->new_config = NULL;
11477         }
11478
11479         return 0;
11480 }
11481
11482 static void disable_crtc_nofb(struct intel_crtc *crtc)
11483 {
11484         struct drm_device *dev = crtc->base.dev;
11485         struct intel_encoder *encoder;
11486         struct intel_connector *connector;
11487
11488         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11489                       pipe_name(crtc->pipe));
11490
11491         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11492                 if (connector->new_encoder &&
11493                     connector->new_encoder->new_crtc == crtc)
11494                         connector->new_encoder = NULL;
11495         }
11496
11497         for_each_intel_encoder(dev, encoder) {
11498                 if (encoder->new_crtc == crtc)
11499                         encoder->new_crtc = NULL;
11500         }
11501
11502         crtc->new_enabled = false;
11503         crtc->new_config = NULL;
11504 }
11505
11506 static int intel_crtc_set_config(struct drm_mode_set *set)
11507 {
11508         struct drm_device *dev;
11509         struct drm_mode_set save_set;
11510         struct intel_set_config *config;
11511         int ret;
11512
11513         BUG_ON(!set);
11514         BUG_ON(!set->crtc);
11515         BUG_ON(!set->crtc->helper_private);
11516
11517         /* Enforce sane interface api - has been abused by the fb helper. */
11518         BUG_ON(!set->mode && set->fb);
11519         BUG_ON(set->fb && set->num_connectors == 0);
11520
11521         if (set->fb) {
11522                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11523                                 set->crtc->base.id, set->fb->base.id,
11524                                 (int)set->num_connectors, set->x, set->y);
11525         } else {
11526                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11527         }
11528
11529         dev = set->crtc->dev;
11530
11531         ret = -ENOMEM;
11532         config = kzalloc(sizeof(*config), GFP_KERNEL);
11533         if (!config)
11534                 goto out_config;
11535
11536         ret = intel_set_config_save_state(dev, config);
11537         if (ret)
11538                 goto out_config;
11539
11540         save_set.crtc = set->crtc;
11541         save_set.mode = &set->crtc->mode;
11542         save_set.x = set->crtc->x;
11543         save_set.y = set->crtc->y;
11544         save_set.fb = set->crtc->primary->fb;
11545
11546         /* Compute whether we need a full modeset, only an fb base update or no
11547          * change at all. In the future we might also check whether only the
11548          * mode changed, e.g. for LVDS where we only change the panel fitter in
11549          * such cases. */
11550         intel_set_config_compute_mode_changes(set, config);
11551
11552         ret = intel_modeset_stage_output_state(dev, set, config);
11553         if (ret)
11554                 goto fail;
11555
11556         if (config->mode_changed) {
11557                 ret = intel_set_mode(set->crtc, set->mode,
11558                                      set->x, set->y, set->fb);
11559         } else if (config->fb_changed) {
11560                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11561
11562                 intel_crtc_wait_for_pending_flips(set->crtc);
11563
11564                 ret = intel_pipe_set_base(set->crtc,
11565                                           set->x, set->y, set->fb);
11566
11567                 /*
11568                  * We need to make sure the primary plane is re-enabled if it
11569                  * has previously been turned off.
11570                  */
11571                 if (!intel_crtc->primary_enabled && ret == 0) {
11572                         WARN_ON(!intel_crtc->active);
11573                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11574                 }
11575
11576                 /*
11577                  * In the fastboot case this may be our only check of the
11578                  * state after boot.  It would be better to only do it on
11579                  * the first update, but we don't have a nice way of doing that
11580                  * (and really, set_config isn't used much for high freq page
11581                  * flipping, so increasing its cost here shouldn't be a big
11582                  * deal).
11583                  */
11584                 if (i915.fastboot && ret == 0)
11585                         intel_modeset_check_state(set->crtc->dev);
11586         }
11587
11588         if (ret) {
11589                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11590                               set->crtc->base.id, ret);
11591 fail:
11592                 intel_set_config_restore_state(dev, config);
11593
11594                 /*
11595                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11596                  * force the pipe off to avoid oopsing in the modeset code
11597                  * due to fb==NULL. This should only happen during boot since
11598                  * we don't yet reconstruct the FB from the hardware state.
11599                  */
11600                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11601                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11602
11603                 /* Try to restore the config */
11604                 if (config->mode_changed &&
11605                     intel_set_mode(save_set.crtc, save_set.mode,
11606                                    save_set.x, save_set.y, save_set.fb))
11607                         DRM_ERROR("failed to restore config after modeset failure\n");
11608         }
11609
11610 out_config:
11611         intel_set_config_free(config);
11612         return ret;
11613 }
11614
11615 static const struct drm_crtc_funcs intel_crtc_funcs = {
11616         .gamma_set = intel_crtc_gamma_set,
11617         .set_config = intel_crtc_set_config,
11618         .destroy = intel_crtc_destroy,
11619         .page_flip = intel_crtc_page_flip,
11620 };
11621
11622 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11623                                       struct intel_shared_dpll *pll,
11624                                       struct intel_dpll_hw_state *hw_state)
11625 {
11626         uint32_t val;
11627
11628         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11629                 return false;
11630
11631         val = I915_READ(PCH_DPLL(pll->id));
11632         hw_state->dpll = val;
11633         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11634         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11635
11636         return val & DPLL_VCO_ENABLE;
11637 }
11638
11639 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11640                                   struct intel_shared_dpll *pll)
11641 {
11642         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11643         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11644 }
11645
11646 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11647                                 struct intel_shared_dpll *pll)
11648 {
11649         /* PCH refclock must be enabled first */
11650         ibx_assert_pch_refclk_enabled(dev_priv);
11651
11652         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11653
11654         /* Wait for the clocks to stabilize. */
11655         POSTING_READ(PCH_DPLL(pll->id));
11656         udelay(150);
11657
11658         /* The pixel multiplier can only be updated once the
11659          * DPLL is enabled and the clocks are stable.
11660          *
11661          * So write it again.
11662          */
11663         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11664         POSTING_READ(PCH_DPLL(pll->id));
11665         udelay(200);
11666 }
11667
11668 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11669                                  struct intel_shared_dpll *pll)
11670 {
11671         struct drm_device *dev = dev_priv->dev;
11672         struct intel_crtc *crtc;
11673
11674         /* Make sure no transcoder isn't still depending on us. */
11675         for_each_intel_crtc(dev, crtc) {
11676                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11677                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11678         }
11679
11680         I915_WRITE(PCH_DPLL(pll->id), 0);
11681         POSTING_READ(PCH_DPLL(pll->id));
11682         udelay(200);
11683 }
11684
11685 static char *ibx_pch_dpll_names[] = {
11686         "PCH DPLL A",
11687         "PCH DPLL B",
11688 };
11689
11690 static void ibx_pch_dpll_init(struct drm_device *dev)
11691 {
11692         struct drm_i915_private *dev_priv = dev->dev_private;
11693         int i;
11694
11695         dev_priv->num_shared_dpll = 2;
11696
11697         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11698                 dev_priv->shared_dplls[i].id = i;
11699                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11700                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11701                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11702                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11703                 dev_priv->shared_dplls[i].get_hw_state =
11704                         ibx_pch_dpll_get_hw_state;
11705         }
11706 }
11707
11708 static void intel_shared_dpll_init(struct drm_device *dev)
11709 {
11710         struct drm_i915_private *dev_priv = dev->dev_private;
11711
11712         if (HAS_DDI(dev))
11713                 intel_ddi_pll_init(dev);
11714         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11715                 ibx_pch_dpll_init(dev);
11716         else
11717                 dev_priv->num_shared_dpll = 0;
11718
11719         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11720 }
11721
11722 static int
11723 intel_primary_plane_disable(struct drm_plane *plane)
11724 {
11725         struct drm_device *dev = plane->dev;
11726         struct intel_crtc *intel_crtc;
11727
11728         if (!plane->fb)
11729                 return 0;
11730
11731         BUG_ON(!plane->crtc);
11732
11733         intel_crtc = to_intel_crtc(plane->crtc);
11734
11735         /*
11736          * Even though we checked plane->fb above, it's still possible that
11737          * the primary plane has been implicitly disabled because the crtc
11738          * coordinates given weren't visible, or because we detected
11739          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11740          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11741          * In either case, we need to unpin the FB and let the fb pointer get
11742          * updated, but otherwise we don't need to touch the hardware.
11743          */
11744         if (!intel_crtc->primary_enabled)
11745                 goto disable_unpin;
11746
11747         intel_crtc_wait_for_pending_flips(plane->crtc);
11748         intel_disable_primary_hw_plane(plane, plane->crtc);
11749
11750 disable_unpin:
11751         mutex_lock(&dev->struct_mutex);
11752         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11753                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11754         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11755         mutex_unlock(&dev->struct_mutex);
11756         plane->fb = NULL;
11757
11758         return 0;
11759 }
11760
11761 static int
11762 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11763                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11764                              unsigned int crtc_w, unsigned int crtc_h,
11765                              uint32_t src_x, uint32_t src_y,
11766                              uint32_t src_w, uint32_t src_h)
11767 {
11768         struct drm_device *dev = crtc->dev;
11769         struct drm_i915_private *dev_priv = dev->dev_private;
11770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11771         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11772         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11773         struct drm_rect dest = {
11774                 /* integer pixels */
11775                 .x1 = crtc_x,
11776                 .y1 = crtc_y,
11777                 .x2 = crtc_x + crtc_w,
11778                 .y2 = crtc_y + crtc_h,
11779         };
11780         struct drm_rect src = {
11781                 /* 16.16 fixed point */
11782                 .x1 = src_x,
11783                 .y1 = src_y,
11784                 .x2 = src_x + src_w,
11785                 .y2 = src_y + src_h,
11786         };
11787         const struct drm_rect clip = {
11788                 /* integer pixels */
11789                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11790                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11791         };
11792         const struct {
11793                 int crtc_x, crtc_y;
11794                 unsigned int crtc_w, crtc_h;
11795                 uint32_t src_x, src_y, src_w, src_h;
11796         } orig = {
11797                 .crtc_x = crtc_x,
11798                 .crtc_y = crtc_y,
11799                 .crtc_w = crtc_w,
11800                 .crtc_h = crtc_h,
11801                 .src_x = src_x,
11802                 .src_y = src_y,
11803                 .src_w = src_w,
11804                 .src_h = src_h,
11805         };
11806         struct intel_plane *intel_plane = to_intel_plane(plane);
11807         bool visible;
11808         int ret;
11809
11810         ret = drm_plane_helper_check_update(plane, crtc, fb,
11811                                             &src, &dest, &clip,
11812                                             DRM_PLANE_HELPER_NO_SCALING,
11813                                             DRM_PLANE_HELPER_NO_SCALING,
11814                                             false, true, &visible);
11815
11816         if (ret)
11817                 return ret;
11818
11819         /*
11820          * If the CRTC isn't enabled, we're just pinning the framebuffer,
11821          * updating the fb pointer, and returning without touching the
11822          * hardware.  This allows us to later do a drmModeSetCrtc with fb=-1 to
11823          * turn on the display with all planes setup as desired.
11824          */
11825         if (!crtc->enabled) {
11826                 mutex_lock(&dev->struct_mutex);
11827
11828                 /*
11829                  * If we already called setplane while the crtc was disabled,
11830                  * we may have an fb pinned; unpin it.
11831                  */
11832                 if (plane->fb)
11833                         intel_unpin_fb_obj(old_obj);
11834
11835                 i915_gem_track_fb(old_obj, obj,
11836                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11837
11838                 /* Pin and return without programming hardware */
11839                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11840                 mutex_unlock(&dev->struct_mutex);
11841
11842                 return ret;
11843         }
11844
11845         intel_crtc_wait_for_pending_flips(crtc);
11846
11847         /*
11848          * If clipping results in a non-visible primary plane, we'll disable
11849          * the primary plane.  Note that this is a bit different than what
11850          * happens if userspace explicitly disables the plane by passing fb=0
11851          * because plane->fb still gets set and pinned.
11852          */
11853         if (!visible) {
11854                 mutex_lock(&dev->struct_mutex);
11855
11856                 /*
11857                  * Try to pin the new fb first so that we can bail out if we
11858                  * fail.
11859                  */
11860                 if (plane->fb != fb) {
11861                         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11862                         if (ret) {
11863                                 mutex_unlock(&dev->struct_mutex);
11864                                 return ret;
11865                         }
11866                 }
11867
11868                 i915_gem_track_fb(old_obj, obj,
11869                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11870
11871                 if (intel_crtc->primary_enabled)
11872                         intel_disable_primary_hw_plane(plane, crtc);
11873
11874
11875                 if (plane->fb != fb)
11876                         if (plane->fb)
11877                                 intel_unpin_fb_obj(old_obj);
11878
11879                 mutex_unlock(&dev->struct_mutex);
11880
11881         } else {
11882                 if (intel_crtc && intel_crtc->active &&
11883                     intel_crtc->primary_enabled) {
11884                         /*
11885                          * FBC does not work on some platforms for rotated
11886                          * planes, so disable it when rotation is not 0 and
11887                          * update it when rotation is set back to 0.
11888                          *
11889                          * FIXME: This is redundant with the fbc update done in
11890                          * the primary plane enable function except that that
11891                          * one is done too late. We eventually need to unify
11892                          * this.
11893                          */
11894                         if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11895                             dev_priv->fbc.plane == intel_crtc->plane &&
11896                             intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11897                                 intel_disable_fbc(dev);
11898                         }
11899                 }
11900                 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11901                 if (ret)
11902                         return ret;
11903
11904                 if (!intel_crtc->primary_enabled)
11905                         intel_enable_primary_hw_plane(plane, crtc);
11906         }
11907
11908         intel_plane->crtc_x = orig.crtc_x;
11909         intel_plane->crtc_y = orig.crtc_y;
11910         intel_plane->crtc_w = orig.crtc_w;
11911         intel_plane->crtc_h = orig.crtc_h;
11912         intel_plane->src_x = orig.src_x;
11913         intel_plane->src_y = orig.src_y;
11914         intel_plane->src_w = orig.src_w;
11915         intel_plane->src_h = orig.src_h;
11916         intel_plane->obj = obj;
11917
11918         return 0;
11919 }
11920
11921 /* Common destruction function for both primary and cursor planes */
11922 static void intel_plane_destroy(struct drm_plane *plane)
11923 {
11924         struct intel_plane *intel_plane = to_intel_plane(plane);
11925         drm_plane_cleanup(plane);
11926         kfree(intel_plane);
11927 }
11928
11929 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11930         .update_plane = intel_primary_plane_setplane,
11931         .disable_plane = intel_primary_plane_disable,
11932         .destroy = intel_plane_destroy,
11933         .set_property = intel_plane_set_property
11934 };
11935
11936 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11937                                                     int pipe)
11938 {
11939         struct intel_plane *primary;
11940         const uint32_t *intel_primary_formats;
11941         int num_formats;
11942
11943         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11944         if (primary == NULL)
11945                 return NULL;
11946
11947         primary->can_scale = false;
11948         primary->max_downscale = 1;
11949         primary->pipe = pipe;
11950         primary->plane = pipe;
11951         primary->rotation = BIT(DRM_ROTATE_0);
11952         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11953                 primary->plane = !pipe;
11954
11955         if (INTEL_INFO(dev)->gen <= 3) {
11956                 intel_primary_formats = intel_primary_formats_gen2;
11957                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11958         } else {
11959                 intel_primary_formats = intel_primary_formats_gen4;
11960                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11961         }
11962
11963         drm_universal_plane_init(dev, &primary->base, 0,
11964                                  &intel_primary_plane_funcs,
11965                                  intel_primary_formats, num_formats,
11966                                  DRM_PLANE_TYPE_PRIMARY);
11967
11968         if (INTEL_INFO(dev)->gen >= 4) {
11969                 if (!dev->mode_config.rotation_property)
11970                         dev->mode_config.rotation_property =
11971                                 drm_mode_create_rotation_property(dev,
11972                                                         BIT(DRM_ROTATE_0) |
11973                                                         BIT(DRM_ROTATE_180));
11974                 if (dev->mode_config.rotation_property)
11975                         drm_object_attach_property(&primary->base.base,
11976                                 dev->mode_config.rotation_property,
11977                                 primary->rotation);
11978         }
11979
11980         return &primary->base;
11981 }
11982
11983 static int
11984 intel_cursor_plane_disable(struct drm_plane *plane)
11985 {
11986         if (!plane->fb)
11987                 return 0;
11988
11989         BUG_ON(!plane->crtc);
11990
11991         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11992 }
11993
11994 static int
11995 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11996                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11997                           unsigned int crtc_w, unsigned int crtc_h,
11998                           uint32_t src_x, uint32_t src_y,
11999                           uint32_t src_w, uint32_t src_h)
12000 {
12001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12002         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12003         struct drm_i915_gem_object *obj = intel_fb->obj;
12004         struct drm_rect dest = {
12005                 /* integer pixels */
12006                 .x1 = crtc_x,
12007                 .y1 = crtc_y,
12008                 .x2 = crtc_x + crtc_w,
12009                 .y2 = crtc_y + crtc_h,
12010         };
12011         struct drm_rect src = {
12012                 /* 16.16 fixed point */
12013                 .x1 = src_x,
12014                 .y1 = src_y,
12015                 .x2 = src_x + src_w,
12016                 .y2 = src_y + src_h,
12017         };
12018         const struct drm_rect clip = {
12019                 /* integer pixels */
12020                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12021                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12022         };
12023         bool visible;
12024         int ret;
12025
12026         ret = drm_plane_helper_check_update(plane, crtc, fb,
12027                                             &src, &dest, &clip,
12028                                             DRM_PLANE_HELPER_NO_SCALING,
12029                                             DRM_PLANE_HELPER_NO_SCALING,
12030                                             true, true, &visible);
12031         if (ret)
12032                 return ret;
12033
12034         crtc->cursor_x = crtc_x;
12035         crtc->cursor_y = crtc_y;
12036         if (fb != crtc->cursor->fb) {
12037                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12038         } else {
12039                 intel_crtc_update_cursor(crtc, visible);
12040
12041                 intel_frontbuffer_flip(crtc->dev,
12042                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12043
12044                 return 0;
12045         }
12046 }
12047 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12048         .update_plane = intel_cursor_plane_update,
12049         .disable_plane = intel_cursor_plane_disable,
12050         .destroy = intel_plane_destroy,
12051 };
12052
12053 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12054                                                    int pipe)
12055 {
12056         struct intel_plane *cursor;
12057
12058         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12059         if (cursor == NULL)
12060                 return NULL;
12061
12062         cursor->can_scale = false;
12063         cursor->max_downscale = 1;
12064         cursor->pipe = pipe;
12065         cursor->plane = pipe;
12066
12067         drm_universal_plane_init(dev, &cursor->base, 0,
12068                                  &intel_cursor_plane_funcs,
12069                                  intel_cursor_formats,
12070                                  ARRAY_SIZE(intel_cursor_formats),
12071                                  DRM_PLANE_TYPE_CURSOR);
12072         return &cursor->base;
12073 }
12074
12075 static void intel_crtc_init(struct drm_device *dev, int pipe)
12076 {
12077         struct drm_i915_private *dev_priv = dev->dev_private;
12078         struct intel_crtc *intel_crtc;
12079         struct drm_plane *primary = NULL;
12080         struct drm_plane *cursor = NULL;
12081         int i, ret;
12082
12083         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12084         if (intel_crtc == NULL)
12085                 return;
12086
12087         primary = intel_primary_plane_create(dev, pipe);
12088         if (!primary)
12089                 goto fail;
12090
12091         cursor = intel_cursor_plane_create(dev, pipe);
12092         if (!cursor)
12093                 goto fail;
12094
12095         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12096                                         cursor, &intel_crtc_funcs);
12097         if (ret)
12098                 goto fail;
12099
12100         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12101         for (i = 0; i < 256; i++) {
12102                 intel_crtc->lut_r[i] = i;
12103                 intel_crtc->lut_g[i] = i;
12104                 intel_crtc->lut_b[i] = i;
12105         }
12106
12107         /*
12108          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12109          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12110          */
12111         intel_crtc->pipe = pipe;
12112         intel_crtc->plane = pipe;
12113         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12114                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12115                 intel_crtc->plane = !pipe;
12116         }
12117
12118         intel_crtc->cursor_base = ~0;
12119         intel_crtc->cursor_cntl = ~0;
12120         intel_crtc->cursor_size = ~0;
12121
12122         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12123                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12124         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12125         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12126
12127         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12128
12129         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12130         return;
12131
12132 fail:
12133         if (primary)
12134                 drm_plane_cleanup(primary);
12135         if (cursor)
12136                 drm_plane_cleanup(cursor);
12137         kfree(intel_crtc);
12138 }
12139
12140 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12141 {
12142         struct drm_encoder *encoder = connector->base.encoder;
12143         struct drm_device *dev = connector->base.dev;
12144
12145         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12146
12147         if (!encoder)
12148                 return INVALID_PIPE;
12149
12150         return to_intel_crtc(encoder->crtc)->pipe;
12151 }
12152
12153 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12154                                 struct drm_file *file)
12155 {
12156         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12157         struct drm_crtc *drmmode_crtc;
12158         struct intel_crtc *crtc;
12159
12160         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12161                 return -ENODEV;
12162
12163         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12164
12165         if (!drmmode_crtc) {
12166                 DRM_ERROR("no such CRTC id\n");
12167                 return -ENOENT;
12168         }
12169
12170         crtc = to_intel_crtc(drmmode_crtc);
12171         pipe_from_crtc_id->pipe = crtc->pipe;
12172
12173         return 0;
12174 }
12175
12176 static int intel_encoder_clones(struct intel_encoder *encoder)
12177 {
12178         struct drm_device *dev = encoder->base.dev;
12179         struct intel_encoder *source_encoder;
12180         int index_mask = 0;
12181         int entry = 0;
12182
12183         for_each_intel_encoder(dev, source_encoder) {
12184                 if (encoders_cloneable(encoder, source_encoder))
12185                         index_mask |= (1 << entry);
12186
12187                 entry++;
12188         }
12189
12190         return index_mask;
12191 }
12192
12193 static bool has_edp_a(struct drm_device *dev)
12194 {
12195         struct drm_i915_private *dev_priv = dev->dev_private;
12196
12197         if (!IS_MOBILE(dev))
12198                 return false;
12199
12200         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12201                 return false;
12202
12203         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12204                 return false;
12205
12206         return true;
12207 }
12208
12209 const char *intel_output_name(int output)
12210 {
12211         static const char *names[] = {
12212                 [INTEL_OUTPUT_UNUSED] = "Unused",
12213                 [INTEL_OUTPUT_ANALOG] = "Analog",
12214                 [INTEL_OUTPUT_DVO] = "DVO",
12215                 [INTEL_OUTPUT_SDVO] = "SDVO",
12216                 [INTEL_OUTPUT_LVDS] = "LVDS",
12217                 [INTEL_OUTPUT_TVOUT] = "TV",
12218                 [INTEL_OUTPUT_HDMI] = "HDMI",
12219                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12220                 [INTEL_OUTPUT_EDP] = "eDP",
12221                 [INTEL_OUTPUT_DSI] = "DSI",
12222                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12223         };
12224
12225         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12226                 return "Invalid";
12227
12228         return names[output];
12229 }
12230
12231 static bool intel_crt_present(struct drm_device *dev)
12232 {
12233         struct drm_i915_private *dev_priv = dev->dev_private;
12234
12235         if (IS_ULT(dev))
12236                 return false;
12237
12238         if (IS_CHERRYVIEW(dev))
12239                 return false;
12240
12241         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12242                 return false;
12243
12244         return true;
12245 }
12246
12247 static void intel_setup_outputs(struct drm_device *dev)
12248 {
12249         struct drm_i915_private *dev_priv = dev->dev_private;
12250         struct intel_encoder *encoder;
12251         bool dpd_is_edp = false;
12252
12253         intel_lvds_init(dev);
12254
12255         if (intel_crt_present(dev))
12256                 intel_crt_init(dev);
12257
12258         if (HAS_DDI(dev)) {
12259                 int found;
12260
12261                 /* Haswell uses DDI functions to detect digital outputs */
12262                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12263                 /* DDI A only supports eDP */
12264                 if (found)
12265                         intel_ddi_init(dev, PORT_A);
12266
12267                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12268                  * register */
12269                 found = I915_READ(SFUSE_STRAP);
12270
12271                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12272                         intel_ddi_init(dev, PORT_B);
12273                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12274                         intel_ddi_init(dev, PORT_C);
12275                 if (found & SFUSE_STRAP_DDID_DETECTED)
12276                         intel_ddi_init(dev, PORT_D);
12277         } else if (HAS_PCH_SPLIT(dev)) {
12278                 int found;
12279                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12280
12281                 if (has_edp_a(dev))
12282                         intel_dp_init(dev, DP_A, PORT_A);
12283
12284                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12285                         /* PCH SDVOB multiplex with HDMIB */
12286                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12287                         if (!found)
12288                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12289                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12290                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12291                 }
12292
12293                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12294                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12295
12296                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12297                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12298
12299                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12300                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12301
12302                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12303                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12304         } else if (IS_VALLEYVIEW(dev)) {
12305                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12306                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12307                                         PORT_B);
12308                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12309                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12310                 }
12311
12312                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12313                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12314                                         PORT_C);
12315                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12316                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12317                 }
12318
12319                 if (IS_CHERRYVIEW(dev)) {
12320                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12321                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12322                                                 PORT_D);
12323                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12324                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12325                         }
12326                 }
12327
12328                 intel_dsi_init(dev);
12329         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12330                 bool found = false;
12331
12332                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12333                         DRM_DEBUG_KMS("probing SDVOB\n");
12334                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12335                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12336                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12337                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12338                         }
12339
12340                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12341                                 intel_dp_init(dev, DP_B, PORT_B);
12342                 }
12343
12344                 /* Before G4X SDVOC doesn't have its own detect register */
12345
12346                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12347                         DRM_DEBUG_KMS("probing SDVOC\n");
12348                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12349                 }
12350
12351                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12352
12353                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12354                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12355                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12356                         }
12357                         if (SUPPORTS_INTEGRATED_DP(dev))
12358                                 intel_dp_init(dev, DP_C, PORT_C);
12359                 }
12360
12361                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12362                     (I915_READ(DP_D) & DP_DETECTED))
12363                         intel_dp_init(dev, DP_D, PORT_D);
12364         } else if (IS_GEN2(dev))
12365                 intel_dvo_init(dev);
12366
12367         if (SUPPORTS_TV(dev))
12368                 intel_tv_init(dev);
12369
12370         intel_edp_psr_init(dev);
12371
12372         for_each_intel_encoder(dev, encoder) {
12373                 encoder->base.possible_crtcs = encoder->crtc_mask;
12374                 encoder->base.possible_clones =
12375                         intel_encoder_clones(encoder);
12376         }
12377
12378         intel_init_pch_refclk(dev);
12379
12380         drm_helper_move_panel_connectors_to_head(dev);
12381 }
12382
12383 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12384 {
12385         struct drm_device *dev = fb->dev;
12386         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12387
12388         drm_framebuffer_cleanup(fb);
12389         mutex_lock(&dev->struct_mutex);
12390         WARN_ON(!intel_fb->obj->framebuffer_references--);
12391         drm_gem_object_unreference(&intel_fb->obj->base);
12392         mutex_unlock(&dev->struct_mutex);
12393         kfree(intel_fb);
12394 }
12395
12396 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12397                                                 struct drm_file *file,
12398                                                 unsigned int *handle)
12399 {
12400         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12401         struct drm_i915_gem_object *obj = intel_fb->obj;
12402
12403         return drm_gem_handle_create(file, &obj->base, handle);
12404 }
12405
12406 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12407         .destroy = intel_user_framebuffer_destroy,
12408         .create_handle = intel_user_framebuffer_create_handle,
12409 };
12410
12411 static int intel_framebuffer_init(struct drm_device *dev,
12412                                   struct intel_framebuffer *intel_fb,
12413                                   struct drm_mode_fb_cmd2 *mode_cmd,
12414                                   struct drm_i915_gem_object *obj)
12415 {
12416         int aligned_height;
12417         int pitch_limit;
12418         int ret;
12419
12420         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12421
12422         if (obj->tiling_mode == I915_TILING_Y) {
12423                 DRM_DEBUG("hardware does not support tiling Y\n");
12424                 return -EINVAL;
12425         }
12426
12427         if (mode_cmd->pitches[0] & 63) {
12428                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12429                           mode_cmd->pitches[0]);
12430                 return -EINVAL;
12431         }
12432
12433         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12434                 pitch_limit = 32*1024;
12435         } else if (INTEL_INFO(dev)->gen >= 4) {
12436                 if (obj->tiling_mode)
12437                         pitch_limit = 16*1024;
12438                 else
12439                         pitch_limit = 32*1024;
12440         } else if (INTEL_INFO(dev)->gen >= 3) {
12441                 if (obj->tiling_mode)
12442                         pitch_limit = 8*1024;
12443                 else
12444                         pitch_limit = 16*1024;
12445         } else
12446                 /* XXX DSPC is limited to 4k tiled */
12447                 pitch_limit = 8*1024;
12448
12449         if (mode_cmd->pitches[0] > pitch_limit) {
12450                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12451                           obj->tiling_mode ? "tiled" : "linear",
12452                           mode_cmd->pitches[0], pitch_limit);
12453                 return -EINVAL;
12454         }
12455
12456         if (obj->tiling_mode != I915_TILING_NONE &&
12457             mode_cmd->pitches[0] != obj->stride) {
12458                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12459                           mode_cmd->pitches[0], obj->stride);
12460                 return -EINVAL;
12461         }
12462
12463         /* Reject formats not supported by any plane early. */
12464         switch (mode_cmd->pixel_format) {
12465         case DRM_FORMAT_C8:
12466         case DRM_FORMAT_RGB565:
12467         case DRM_FORMAT_XRGB8888:
12468         case DRM_FORMAT_ARGB8888:
12469                 break;
12470         case DRM_FORMAT_XRGB1555:
12471         case DRM_FORMAT_ARGB1555:
12472                 if (INTEL_INFO(dev)->gen > 3) {
12473                         DRM_DEBUG("unsupported pixel format: %s\n",
12474                                   drm_get_format_name(mode_cmd->pixel_format));
12475                         return -EINVAL;
12476                 }
12477                 break;
12478         case DRM_FORMAT_XBGR8888:
12479         case DRM_FORMAT_ABGR8888:
12480         case DRM_FORMAT_XRGB2101010:
12481         case DRM_FORMAT_ARGB2101010:
12482         case DRM_FORMAT_XBGR2101010:
12483         case DRM_FORMAT_ABGR2101010:
12484                 if (INTEL_INFO(dev)->gen < 4) {
12485                         DRM_DEBUG("unsupported pixel format: %s\n",
12486                                   drm_get_format_name(mode_cmd->pixel_format));
12487                         return -EINVAL;
12488                 }
12489                 break;
12490         case DRM_FORMAT_YUYV:
12491         case DRM_FORMAT_UYVY:
12492         case DRM_FORMAT_YVYU:
12493         case DRM_FORMAT_VYUY:
12494                 if (INTEL_INFO(dev)->gen < 5) {
12495                         DRM_DEBUG("unsupported pixel format: %s\n",
12496                                   drm_get_format_name(mode_cmd->pixel_format));
12497                         return -EINVAL;
12498                 }
12499                 break;
12500         default:
12501                 DRM_DEBUG("unsupported pixel format: %s\n",
12502                           drm_get_format_name(mode_cmd->pixel_format));
12503                 return -EINVAL;
12504         }
12505
12506         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12507         if (mode_cmd->offsets[0] != 0)
12508                 return -EINVAL;
12509
12510         aligned_height = intel_align_height(dev, mode_cmd->height,
12511                                             obj->tiling_mode);
12512         /* FIXME drm helper for size checks (especially planar formats)? */
12513         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12514                 return -EINVAL;
12515
12516         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12517         intel_fb->obj = obj;
12518         intel_fb->obj->framebuffer_references++;
12519
12520         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12521         if (ret) {
12522                 DRM_ERROR("framebuffer init failed %d\n", ret);
12523                 return ret;
12524         }
12525
12526         return 0;
12527 }
12528
12529 static struct drm_framebuffer *
12530 intel_user_framebuffer_create(struct drm_device *dev,
12531                               struct drm_file *filp,
12532                               struct drm_mode_fb_cmd2 *mode_cmd)
12533 {
12534         struct drm_i915_gem_object *obj;
12535
12536         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12537                                                 mode_cmd->handles[0]));
12538         if (&obj->base == NULL)
12539                 return ERR_PTR(-ENOENT);
12540
12541         return intel_framebuffer_create(dev, mode_cmd, obj);
12542 }
12543
12544 #ifndef CONFIG_DRM_I915_FBDEV
12545 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12546 {
12547 }
12548 #endif
12549
12550 static const struct drm_mode_config_funcs intel_mode_funcs = {
12551         .fb_create = intel_user_framebuffer_create,
12552         .output_poll_changed = intel_fbdev_output_poll_changed,
12553 };
12554
12555 /* Set up chip specific display functions */
12556 static void intel_init_display(struct drm_device *dev)
12557 {
12558         struct drm_i915_private *dev_priv = dev->dev_private;
12559
12560         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12561                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12562         else if (IS_CHERRYVIEW(dev))
12563                 dev_priv->display.find_dpll = chv_find_best_dpll;
12564         else if (IS_VALLEYVIEW(dev))
12565                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12566         else if (IS_PINEVIEW(dev))
12567                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12568         else
12569                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12570
12571         if (HAS_DDI(dev)) {
12572                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12573                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12574                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12575                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12576                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12577                 dev_priv->display.off = ironlake_crtc_off;
12578                 dev_priv->display.update_primary_plane =
12579                         ironlake_update_primary_plane;
12580         } else if (HAS_PCH_SPLIT(dev)) {
12581                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12582                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12583                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12584                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12585                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12586                 dev_priv->display.off = ironlake_crtc_off;
12587                 dev_priv->display.update_primary_plane =
12588                         ironlake_update_primary_plane;
12589         } else if (IS_VALLEYVIEW(dev)) {
12590                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12591                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12592                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12593                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12594                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12595                 dev_priv->display.off = i9xx_crtc_off;
12596                 dev_priv->display.update_primary_plane =
12597                         i9xx_update_primary_plane;
12598         } else {
12599                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12600                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12601                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12602                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12603                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12604                 dev_priv->display.off = i9xx_crtc_off;
12605                 dev_priv->display.update_primary_plane =
12606                         i9xx_update_primary_plane;
12607         }
12608
12609         /* Returns the core display clock speed */
12610         if (IS_VALLEYVIEW(dev))
12611                 dev_priv->display.get_display_clock_speed =
12612                         valleyview_get_display_clock_speed;
12613         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12614                 dev_priv->display.get_display_clock_speed =
12615                         i945_get_display_clock_speed;
12616         else if (IS_I915G(dev))
12617                 dev_priv->display.get_display_clock_speed =
12618                         i915_get_display_clock_speed;
12619         else if (IS_I945GM(dev) || IS_845G(dev))
12620                 dev_priv->display.get_display_clock_speed =
12621                         i9xx_misc_get_display_clock_speed;
12622         else if (IS_PINEVIEW(dev))
12623                 dev_priv->display.get_display_clock_speed =
12624                         pnv_get_display_clock_speed;
12625         else if (IS_I915GM(dev))
12626                 dev_priv->display.get_display_clock_speed =
12627                         i915gm_get_display_clock_speed;
12628         else if (IS_I865G(dev))
12629                 dev_priv->display.get_display_clock_speed =
12630                         i865_get_display_clock_speed;
12631         else if (IS_I85X(dev))
12632                 dev_priv->display.get_display_clock_speed =
12633                         i855_get_display_clock_speed;
12634         else /* 852, 830 */
12635                 dev_priv->display.get_display_clock_speed =
12636                         i830_get_display_clock_speed;
12637
12638         if (IS_G4X(dev)) {
12639                 dev_priv->display.write_eld = g4x_write_eld;
12640         } else if (IS_GEN5(dev)) {
12641                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12642                 dev_priv->display.write_eld = ironlake_write_eld;
12643         } else if (IS_GEN6(dev)) {
12644                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12645                 dev_priv->display.write_eld = ironlake_write_eld;
12646                 dev_priv->display.modeset_global_resources =
12647                         snb_modeset_global_resources;
12648         } else if (IS_IVYBRIDGE(dev)) {
12649                 /* FIXME: detect B0+ stepping and use auto training */
12650                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12651                 dev_priv->display.write_eld = ironlake_write_eld;
12652                 dev_priv->display.modeset_global_resources =
12653                         ivb_modeset_global_resources;
12654         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12655                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12656                 dev_priv->display.write_eld = haswell_write_eld;
12657                 dev_priv->display.modeset_global_resources =
12658                         haswell_modeset_global_resources;
12659         } else if (IS_VALLEYVIEW(dev)) {
12660                 dev_priv->display.modeset_global_resources =
12661                         valleyview_modeset_global_resources;
12662                 dev_priv->display.write_eld = ironlake_write_eld;
12663         }
12664
12665         /* Default just returns -ENODEV to indicate unsupported */
12666         dev_priv->display.queue_flip = intel_default_queue_flip;
12667
12668         switch (INTEL_INFO(dev)->gen) {
12669         case 2:
12670                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12671                 break;
12672
12673         case 3:
12674                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12675                 break;
12676
12677         case 4:
12678         case 5:
12679                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12680                 break;
12681
12682         case 6:
12683                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12684                 break;
12685         case 7:
12686         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12687                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12688                 break;
12689         }
12690
12691         intel_panel_init_backlight_funcs(dev);
12692
12693         mutex_init(&dev_priv->pps_mutex);
12694 }
12695
12696 /*
12697  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12698  * resume, or other times.  This quirk makes sure that's the case for
12699  * affected systems.
12700  */
12701 static void quirk_pipea_force(struct drm_device *dev)
12702 {
12703         struct drm_i915_private *dev_priv = dev->dev_private;
12704
12705         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12706         DRM_INFO("applying pipe a force quirk\n");
12707 }
12708
12709 static void quirk_pipeb_force(struct drm_device *dev)
12710 {
12711         struct drm_i915_private *dev_priv = dev->dev_private;
12712
12713         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12714         DRM_INFO("applying pipe b force quirk\n");
12715 }
12716
12717 /*
12718  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12719  */
12720 static void quirk_ssc_force_disable(struct drm_device *dev)
12721 {
12722         struct drm_i915_private *dev_priv = dev->dev_private;
12723         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12724         DRM_INFO("applying lvds SSC disable quirk\n");
12725 }
12726
12727 /*
12728  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12729  * brightness value
12730  */
12731 static void quirk_invert_brightness(struct drm_device *dev)
12732 {
12733         struct drm_i915_private *dev_priv = dev->dev_private;
12734         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12735         DRM_INFO("applying inverted panel brightness quirk\n");
12736 }
12737
12738 /* Some VBT's incorrectly indicate no backlight is present */
12739 static void quirk_backlight_present(struct drm_device *dev)
12740 {
12741         struct drm_i915_private *dev_priv = dev->dev_private;
12742         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12743         DRM_INFO("applying backlight present quirk\n");
12744 }
12745
12746 struct intel_quirk {
12747         int device;
12748         int subsystem_vendor;
12749         int subsystem_device;
12750         void (*hook)(struct drm_device *dev);
12751 };
12752
12753 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12754 struct intel_dmi_quirk {
12755         void (*hook)(struct drm_device *dev);
12756         const struct dmi_system_id (*dmi_id_list)[];
12757 };
12758
12759 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12760 {
12761         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12762         return 1;
12763 }
12764
12765 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12766         {
12767                 .dmi_id_list = &(const struct dmi_system_id[]) {
12768                         {
12769                                 .callback = intel_dmi_reverse_brightness,
12770                                 .ident = "NCR Corporation",
12771                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12772                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12773                                 },
12774                         },
12775                         { }  /* terminating entry */
12776                 },
12777                 .hook = quirk_invert_brightness,
12778         },
12779 };
12780
12781 static struct intel_quirk intel_quirks[] = {
12782         /* HP Mini needs pipe A force quirk (LP: #322104) */
12783         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12784
12785         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12786         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12787
12788         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12789         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12790
12791         /* 830 needs to leave pipe A & dpll A up */
12792         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12793
12794         /* 830 needs to leave pipe B & dpll B up */
12795         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12796
12797         /* Lenovo U160 cannot use SSC on LVDS */
12798         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12799
12800         /* Sony Vaio Y cannot use SSC on LVDS */
12801         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12802
12803         /* Acer Aspire 5734Z must invert backlight brightness */
12804         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12805
12806         /* Acer/eMachines G725 */
12807         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12808
12809         /* Acer/eMachines e725 */
12810         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12811
12812         /* Acer/Packard Bell NCL20 */
12813         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12814
12815         /* Acer Aspire 4736Z */
12816         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12817
12818         /* Acer Aspire 5336 */
12819         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12820
12821         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12822         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12823
12824         /* Acer C720 Chromebook (Core i3 4005U) */
12825         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12826
12827         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12828         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12829
12830         /* HP Chromebook 14 (Celeron 2955U) */
12831         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12832 };
12833
12834 static void intel_init_quirks(struct drm_device *dev)
12835 {
12836         struct pci_dev *d = dev->pdev;
12837         int i;
12838
12839         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12840                 struct intel_quirk *q = &intel_quirks[i];
12841
12842                 if (d->device == q->device &&
12843                     (d->subsystem_vendor == q->subsystem_vendor ||
12844                      q->subsystem_vendor == PCI_ANY_ID) &&
12845                     (d->subsystem_device == q->subsystem_device ||
12846                      q->subsystem_device == PCI_ANY_ID))
12847                         q->hook(dev);
12848         }
12849         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12850                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12851                         intel_dmi_quirks[i].hook(dev);
12852         }
12853 }
12854
12855 /* Disable the VGA plane that we never use */
12856 static void i915_disable_vga(struct drm_device *dev)
12857 {
12858         struct drm_i915_private *dev_priv = dev->dev_private;
12859         u8 sr1;
12860         u32 vga_reg = i915_vgacntrl_reg(dev);
12861
12862         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12863         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12864         outb(SR01, VGA_SR_INDEX);
12865         sr1 = inb(VGA_SR_DATA);
12866         outb(sr1 | 1<<5, VGA_SR_DATA);
12867         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12868         udelay(300);
12869
12870         /*
12871          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12872          * from S3 without preserving (some of?) the other bits.
12873          */
12874         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12875         POSTING_READ(vga_reg);
12876 }
12877
12878 void intel_modeset_init_hw(struct drm_device *dev)
12879 {
12880         intel_prepare_ddi(dev);
12881
12882         if (IS_VALLEYVIEW(dev))
12883                 vlv_update_cdclk(dev);
12884
12885         intel_init_clock_gating(dev);
12886
12887         intel_enable_gt_powersave(dev);
12888 }
12889
12890 void intel_modeset_suspend_hw(struct drm_device *dev)
12891 {
12892         intel_suspend_hw(dev);
12893 }
12894
12895 void intel_modeset_init(struct drm_device *dev)
12896 {
12897         struct drm_i915_private *dev_priv = dev->dev_private;
12898         int sprite, ret;
12899         enum pipe pipe;
12900         struct intel_crtc *crtc;
12901
12902         drm_mode_config_init(dev);
12903
12904         dev->mode_config.min_width = 0;
12905         dev->mode_config.min_height = 0;
12906
12907         dev->mode_config.preferred_depth = 24;
12908         dev->mode_config.prefer_shadow = 1;
12909
12910         dev->mode_config.funcs = &intel_mode_funcs;
12911
12912         intel_init_quirks(dev);
12913
12914         intel_init_pm(dev);
12915
12916         if (INTEL_INFO(dev)->num_pipes == 0)
12917                 return;
12918
12919         intel_init_display(dev);
12920
12921         if (IS_GEN2(dev)) {
12922                 dev->mode_config.max_width = 2048;
12923                 dev->mode_config.max_height = 2048;
12924         } else if (IS_GEN3(dev)) {
12925                 dev->mode_config.max_width = 4096;
12926                 dev->mode_config.max_height = 4096;
12927         } else {
12928                 dev->mode_config.max_width = 8192;
12929                 dev->mode_config.max_height = 8192;
12930         }
12931
12932         if (IS_845G(dev) || IS_I865G(dev)) {
12933                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12934                 dev->mode_config.cursor_height = 1023;
12935         } else if (IS_GEN2(dev)) {
12936                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12937                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12938         } else {
12939                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12940                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12941         }
12942
12943         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12944
12945         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12946                       INTEL_INFO(dev)->num_pipes,
12947                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12948
12949         for_each_pipe(dev_priv, pipe) {
12950                 intel_crtc_init(dev, pipe);
12951                 for_each_sprite(pipe, sprite) {
12952                         ret = intel_plane_init(dev, pipe, sprite);
12953                         if (ret)
12954                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12955                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12956                 }
12957         }
12958
12959         intel_init_dpio(dev);
12960
12961         intel_shared_dpll_init(dev);
12962
12963         /* save the BIOS value before clobbering it */
12964         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12965         /* Just disable it once at startup */
12966         i915_disable_vga(dev);
12967         intel_setup_outputs(dev);
12968
12969         /* Just in case the BIOS is doing something questionable. */
12970         intel_disable_fbc(dev);
12971
12972         drm_modeset_lock_all(dev);
12973         intel_modeset_setup_hw_state(dev, false);
12974         drm_modeset_unlock_all(dev);
12975
12976         for_each_intel_crtc(dev, crtc) {
12977                 if (!crtc->active)
12978                         continue;
12979
12980                 /*
12981                  * Note that reserving the BIOS fb up front prevents us
12982                  * from stuffing other stolen allocations like the ring
12983                  * on top.  This prevents some ugliness at boot time, and
12984                  * can even allow for smooth boot transitions if the BIOS
12985                  * fb is large enough for the active pipe configuration.
12986                  */
12987                 if (dev_priv->display.get_plane_config) {
12988                         dev_priv->display.get_plane_config(crtc,
12989                                                            &crtc->plane_config);
12990                         /*
12991                          * If the fb is shared between multiple heads, we'll
12992                          * just get the first one.
12993                          */
12994                         intel_find_plane_obj(crtc, &crtc->plane_config);
12995                 }
12996         }
12997 }
12998
12999 static void intel_enable_pipe_a(struct drm_device *dev)
13000 {
13001         struct intel_connector *connector;
13002         struct drm_connector *crt = NULL;
13003         struct intel_load_detect_pipe load_detect_temp;
13004         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13005
13006         /* We can't just switch on the pipe A, we need to set things up with a
13007          * proper mode and output configuration. As a gross hack, enable pipe A
13008          * by enabling the load detect pipe once. */
13009         list_for_each_entry(connector,
13010                             &dev->mode_config.connector_list,
13011                             base.head) {
13012                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13013                         crt = &connector->base;
13014                         break;
13015                 }
13016         }
13017
13018         if (!crt)
13019                 return;
13020
13021         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13022                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13023 }
13024
13025 static bool
13026 intel_check_plane_mapping(struct intel_crtc *crtc)
13027 {
13028         struct drm_device *dev = crtc->base.dev;
13029         struct drm_i915_private *dev_priv = dev->dev_private;
13030         u32 reg, val;
13031
13032         if (INTEL_INFO(dev)->num_pipes == 1)
13033                 return true;
13034
13035         reg = DSPCNTR(!crtc->plane);
13036         val = I915_READ(reg);
13037
13038         if ((val & DISPLAY_PLANE_ENABLE) &&
13039             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13040                 return false;
13041
13042         return true;
13043 }
13044
13045 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13046 {
13047         struct drm_device *dev = crtc->base.dev;
13048         struct drm_i915_private *dev_priv = dev->dev_private;
13049         u32 reg;
13050
13051         /* Clear any frame start delays used for debugging left by the BIOS */
13052         reg = PIPECONF(crtc->config.cpu_transcoder);
13053         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13054
13055         /* restore vblank interrupts to correct state */
13056         if (crtc->active) {
13057                 update_scanline_offset(crtc);
13058                 drm_vblank_on(dev, crtc->pipe);
13059         } else
13060                 drm_vblank_off(dev, crtc->pipe);
13061
13062         /* We need to sanitize the plane -> pipe mapping first because this will
13063          * disable the crtc (and hence change the state) if it is wrong. Note
13064          * that gen4+ has a fixed plane -> pipe mapping.  */
13065         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13066                 struct intel_connector *connector;
13067                 bool plane;
13068
13069                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13070                               crtc->base.base.id);
13071
13072                 /* Pipe has the wrong plane attached and the plane is active.
13073                  * Temporarily change the plane mapping and disable everything
13074                  * ...  */
13075                 plane = crtc->plane;
13076                 crtc->plane = !plane;
13077                 crtc->primary_enabled = true;
13078                 dev_priv->display.crtc_disable(&crtc->base);
13079                 crtc->plane = plane;
13080
13081                 /* ... and break all links. */
13082                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13083                                     base.head) {
13084                         if (connector->encoder->base.crtc != &crtc->base)
13085                                 continue;
13086
13087                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13088                         connector->base.encoder = NULL;
13089                 }
13090                 /* multiple connectors may have the same encoder:
13091                  *  handle them and break crtc link separately */
13092                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13093                                     base.head)
13094                         if (connector->encoder->base.crtc == &crtc->base) {
13095                                 connector->encoder->base.crtc = NULL;
13096                                 connector->encoder->connectors_active = false;
13097                         }
13098
13099                 WARN_ON(crtc->active);
13100                 crtc->base.enabled = false;
13101         }
13102
13103         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13104             crtc->pipe == PIPE_A && !crtc->active) {
13105                 /* BIOS forgot to enable pipe A, this mostly happens after
13106                  * resume. Force-enable the pipe to fix this, the update_dpms
13107                  * call below we restore the pipe to the right state, but leave
13108                  * the required bits on. */
13109                 intel_enable_pipe_a(dev);
13110         }
13111
13112         /* Adjust the state of the output pipe according to whether we
13113          * have active connectors/encoders. */
13114         intel_crtc_update_dpms(&crtc->base);
13115
13116         if (crtc->active != crtc->base.enabled) {
13117                 struct intel_encoder *encoder;
13118
13119                 /* This can happen either due to bugs in the get_hw_state
13120                  * functions or because the pipe is force-enabled due to the
13121                  * pipe A quirk. */
13122                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13123                               crtc->base.base.id,
13124                               crtc->base.enabled ? "enabled" : "disabled",
13125                               crtc->active ? "enabled" : "disabled");
13126
13127                 crtc->base.enabled = crtc->active;
13128
13129                 /* Because we only establish the connector -> encoder ->
13130                  * crtc links if something is active, this means the
13131                  * crtc is now deactivated. Break the links. connector
13132                  * -> encoder links are only establish when things are
13133                  *  actually up, hence no need to break them. */
13134                 WARN_ON(crtc->active);
13135
13136                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13137                         WARN_ON(encoder->connectors_active);
13138                         encoder->base.crtc = NULL;
13139                 }
13140         }
13141
13142         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13143                 /*
13144                  * We start out with underrun reporting disabled to avoid races.
13145                  * For correct bookkeeping mark this on active crtcs.
13146                  *
13147                  * Also on gmch platforms we dont have any hardware bits to
13148                  * disable the underrun reporting. Which means we need to start
13149                  * out with underrun reporting disabled also on inactive pipes,
13150                  * since otherwise we'll complain about the garbage we read when
13151                  * e.g. coming up after runtime pm.
13152                  *
13153                  * No protection against concurrent access is required - at
13154                  * worst a fifo underrun happens which also sets this to false.
13155                  */
13156                 crtc->cpu_fifo_underrun_disabled = true;
13157                 crtc->pch_fifo_underrun_disabled = true;
13158         }
13159 }
13160
13161 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13162 {
13163         struct intel_connector *connector;
13164         struct drm_device *dev = encoder->base.dev;
13165
13166         /* We need to check both for a crtc link (meaning that the
13167          * encoder is active and trying to read from a pipe) and the
13168          * pipe itself being active. */
13169         bool has_active_crtc = encoder->base.crtc &&
13170                 to_intel_crtc(encoder->base.crtc)->active;
13171
13172         if (encoder->connectors_active && !has_active_crtc) {
13173                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13174                               encoder->base.base.id,
13175                               encoder->base.name);
13176
13177                 /* Connector is active, but has no active pipe. This is
13178                  * fallout from our resume register restoring. Disable
13179                  * the encoder manually again. */
13180                 if (encoder->base.crtc) {
13181                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13182                                       encoder->base.base.id,
13183                                       encoder->base.name);
13184                         encoder->disable(encoder);
13185                         if (encoder->post_disable)
13186                                 encoder->post_disable(encoder);
13187                 }
13188                 encoder->base.crtc = NULL;
13189                 encoder->connectors_active = false;
13190
13191                 /* Inconsistent output/port/pipe state happens presumably due to
13192                  * a bug in one of the get_hw_state functions. Or someplace else
13193                  * in our code, like the register restore mess on resume. Clamp
13194                  * things to off as a safer default. */
13195                 list_for_each_entry(connector,
13196                                     &dev->mode_config.connector_list,
13197                                     base.head) {
13198                         if (connector->encoder != encoder)
13199                                 continue;
13200                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13201                         connector->base.encoder = NULL;
13202                 }
13203         }
13204         /* Enabled encoders without active connectors will be fixed in
13205          * the crtc fixup. */
13206 }
13207
13208 void i915_redisable_vga_power_on(struct drm_device *dev)
13209 {
13210         struct drm_i915_private *dev_priv = dev->dev_private;
13211         u32 vga_reg = i915_vgacntrl_reg(dev);
13212
13213         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13214                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13215                 i915_disable_vga(dev);
13216         }
13217 }
13218
13219 void i915_redisable_vga(struct drm_device *dev)
13220 {
13221         struct drm_i915_private *dev_priv = dev->dev_private;
13222
13223         /* This function can be called both from intel_modeset_setup_hw_state or
13224          * at a very early point in our resume sequence, where the power well
13225          * structures are not yet restored. Since this function is at a very
13226          * paranoid "someone might have enabled VGA while we were not looking"
13227          * level, just check if the power well is enabled instead of trying to
13228          * follow the "don't touch the power well if we don't need it" policy
13229          * the rest of the driver uses. */
13230         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13231                 return;
13232
13233         i915_redisable_vga_power_on(dev);
13234 }
13235
13236 static bool primary_get_hw_state(struct intel_crtc *crtc)
13237 {
13238         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13239
13240         if (!crtc->active)
13241                 return false;
13242
13243         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13244 }
13245
13246 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13247 {
13248         struct drm_i915_private *dev_priv = dev->dev_private;
13249         enum pipe pipe;
13250         struct intel_crtc *crtc;
13251         struct intel_encoder *encoder;
13252         struct intel_connector *connector;
13253         int i;
13254
13255         for_each_intel_crtc(dev, crtc) {
13256                 memset(&crtc->config, 0, sizeof(crtc->config));
13257
13258                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13259
13260                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13261                                                                  &crtc->config);
13262
13263                 crtc->base.enabled = crtc->active;
13264                 crtc->primary_enabled = primary_get_hw_state(crtc);
13265
13266                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13267                               crtc->base.base.id,
13268                               crtc->active ? "enabled" : "disabled");
13269         }
13270
13271         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13272                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13273
13274                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13275                 pll->active = 0;
13276                 for_each_intel_crtc(dev, crtc) {
13277                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13278                                 pll->active++;
13279                 }
13280                 pll->refcount = pll->active;
13281
13282                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13283                               pll->name, pll->refcount, pll->on);
13284
13285                 if (pll->refcount)
13286                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13287         }
13288
13289         for_each_intel_encoder(dev, encoder) {
13290                 pipe = 0;
13291
13292                 if (encoder->get_hw_state(encoder, &pipe)) {
13293                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13294                         encoder->base.crtc = &crtc->base;
13295                         encoder->get_config(encoder, &crtc->config);
13296                 } else {
13297                         encoder->base.crtc = NULL;
13298                 }
13299
13300                 encoder->connectors_active = false;
13301                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13302                               encoder->base.base.id,
13303                               encoder->base.name,
13304                               encoder->base.crtc ? "enabled" : "disabled",
13305                               pipe_name(pipe));
13306         }
13307
13308         list_for_each_entry(connector, &dev->mode_config.connector_list,
13309                             base.head) {
13310                 if (connector->get_hw_state(connector)) {
13311                         connector->base.dpms = DRM_MODE_DPMS_ON;
13312                         connector->encoder->connectors_active = true;
13313                         connector->base.encoder = &connector->encoder->base;
13314                 } else {
13315                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13316                         connector->base.encoder = NULL;
13317                 }
13318                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13319                               connector->base.base.id,
13320                               connector->base.name,
13321                               connector->base.encoder ? "enabled" : "disabled");
13322         }
13323 }
13324
13325 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13326  * and i915 state tracking structures. */
13327 void intel_modeset_setup_hw_state(struct drm_device *dev,
13328                                   bool force_restore)
13329 {
13330         struct drm_i915_private *dev_priv = dev->dev_private;
13331         enum pipe pipe;
13332         struct intel_crtc *crtc;
13333         struct intel_encoder *encoder;
13334         int i;
13335
13336         intel_modeset_readout_hw_state(dev);
13337
13338         /*
13339          * Now that we have the config, copy it to each CRTC struct
13340          * Note that this could go away if we move to using crtc_config
13341          * checking everywhere.
13342          */
13343         for_each_intel_crtc(dev, crtc) {
13344                 if (crtc->active && i915.fastboot) {
13345                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13346                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13347                                       crtc->base.base.id);
13348                         drm_mode_debug_printmodeline(&crtc->base.mode);
13349                 }
13350         }
13351
13352         /* HW state is read out, now we need to sanitize this mess. */
13353         for_each_intel_encoder(dev, encoder) {
13354                 intel_sanitize_encoder(encoder);
13355         }
13356
13357         for_each_pipe(dev_priv, pipe) {
13358                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13359                 intel_sanitize_crtc(crtc);
13360                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13361         }
13362
13363         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13364                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13365
13366                 if (!pll->on || pll->active)
13367                         continue;
13368
13369                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13370
13371                 pll->disable(dev_priv, pll);
13372                 pll->on = false;
13373         }
13374
13375         if (HAS_PCH_SPLIT(dev))
13376                 ilk_wm_get_hw_state(dev);
13377
13378         if (force_restore) {
13379                 i915_redisable_vga(dev);
13380
13381                 /*
13382                  * We need to use raw interfaces for restoring state to avoid
13383                  * checking (bogus) intermediate states.
13384                  */
13385                 for_each_pipe(dev_priv, pipe) {
13386                         struct drm_crtc *crtc =
13387                                 dev_priv->pipe_to_crtc_mapping[pipe];
13388
13389                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13390                                          crtc->primary->fb);
13391                 }
13392         } else {
13393                 intel_modeset_update_staged_output_state(dev);
13394         }
13395
13396         intel_modeset_check_state(dev);
13397 }
13398
13399 void intel_modeset_gem_init(struct drm_device *dev)
13400 {
13401         struct drm_crtc *c;
13402         struct drm_i915_gem_object *obj;
13403
13404         mutex_lock(&dev->struct_mutex);
13405         intel_init_gt_powersave(dev);
13406         mutex_unlock(&dev->struct_mutex);
13407
13408         intel_modeset_init_hw(dev);
13409
13410         intel_setup_overlay(dev);
13411
13412         /*
13413          * Make sure any fbs we allocated at startup are properly
13414          * pinned & fenced.  When we do the allocation it's too early
13415          * for this.
13416          */
13417         mutex_lock(&dev->struct_mutex);
13418         for_each_crtc(dev, c) {
13419                 obj = intel_fb_obj(c->primary->fb);
13420                 if (obj == NULL)
13421                         continue;
13422
13423                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13424                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13425                                   to_intel_crtc(c)->pipe);
13426                         drm_framebuffer_unreference(c->primary->fb);
13427                         c->primary->fb = NULL;
13428                 }
13429         }
13430         mutex_unlock(&dev->struct_mutex);
13431 }
13432
13433 void intel_connector_unregister(struct intel_connector *intel_connector)
13434 {
13435         struct drm_connector *connector = &intel_connector->base;
13436
13437         intel_panel_destroy_backlight(connector);
13438         drm_connector_unregister(connector);
13439 }
13440
13441 void intel_modeset_cleanup(struct drm_device *dev)
13442 {
13443         struct drm_i915_private *dev_priv = dev->dev_private;
13444         struct drm_connector *connector;
13445
13446         /*
13447          * Interrupts and polling as the first thing to avoid creating havoc.
13448          * Too much stuff here (turning of rps, connectors, ...) would
13449          * experience fancy races otherwise.
13450          */
13451         drm_irq_uninstall(dev);
13452         intel_hpd_cancel_work(dev_priv);
13453         dev_priv->pm._irqs_disabled = true;
13454
13455         /*
13456          * Due to the hpd irq storm handling the hotplug work can re-arm the
13457          * poll handlers. Hence disable polling after hpd handling is shut down.
13458          */
13459         drm_kms_helper_poll_fini(dev);
13460
13461         mutex_lock(&dev->struct_mutex);
13462
13463         intel_unregister_dsm_handler();
13464
13465         intel_disable_fbc(dev);
13466
13467         intel_disable_gt_powersave(dev);
13468
13469         ironlake_teardown_rc6(dev);
13470
13471         mutex_unlock(&dev->struct_mutex);
13472
13473         /* flush any delayed tasks or pending work */
13474         flush_scheduled_work();
13475
13476         /* destroy the backlight and sysfs files before encoders/connectors */
13477         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13478                 struct intel_connector *intel_connector;
13479
13480                 intel_connector = to_intel_connector(connector);
13481                 intel_connector->unregister(intel_connector);
13482         }
13483
13484         drm_mode_config_cleanup(dev);
13485
13486         intel_cleanup_overlay(dev);
13487
13488         mutex_lock(&dev->struct_mutex);
13489         intel_cleanup_gt_powersave(dev);
13490         mutex_unlock(&dev->struct_mutex);
13491 }
13492
13493 /*
13494  * Return which encoder is currently attached for connector.
13495  */
13496 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13497 {
13498         return &intel_attached_encoder(connector)->base;
13499 }
13500
13501 void intel_connector_attach_encoder(struct intel_connector *connector,
13502                                     struct intel_encoder *encoder)
13503 {
13504         connector->encoder = encoder;
13505         drm_mode_connector_attach_encoder(&connector->base,
13506                                           &encoder->base);
13507 }
13508
13509 /*
13510  * set vga decode state - true == enable VGA decode
13511  */
13512 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13513 {
13514         struct drm_i915_private *dev_priv = dev->dev_private;
13515         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13516         u16 gmch_ctrl;
13517
13518         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13519                 DRM_ERROR("failed to read control word\n");
13520                 return -EIO;
13521         }
13522
13523         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13524                 return 0;
13525
13526         if (state)
13527                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13528         else
13529                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13530
13531         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13532                 DRM_ERROR("failed to write control word\n");
13533                 return -EIO;
13534         }
13535
13536         return 0;
13537 }
13538
13539 struct intel_display_error_state {
13540
13541         u32 power_well_driver;
13542
13543         int num_transcoders;
13544
13545         struct intel_cursor_error_state {
13546                 u32 control;
13547                 u32 position;
13548                 u32 base;
13549                 u32 size;
13550         } cursor[I915_MAX_PIPES];
13551
13552         struct intel_pipe_error_state {
13553                 bool power_domain_on;
13554                 u32 source;
13555                 u32 stat;
13556         } pipe[I915_MAX_PIPES];
13557
13558         struct intel_plane_error_state {
13559                 u32 control;
13560                 u32 stride;
13561                 u32 size;
13562                 u32 pos;
13563                 u32 addr;
13564                 u32 surface;
13565                 u32 tile_offset;
13566         } plane[I915_MAX_PIPES];
13567
13568         struct intel_transcoder_error_state {
13569                 bool power_domain_on;
13570                 enum transcoder cpu_transcoder;
13571
13572                 u32 conf;
13573
13574                 u32 htotal;
13575                 u32 hblank;
13576                 u32 hsync;
13577                 u32 vtotal;
13578                 u32 vblank;
13579                 u32 vsync;
13580         } transcoder[4];
13581 };
13582
13583 struct intel_display_error_state *
13584 intel_display_capture_error_state(struct drm_device *dev)
13585 {
13586         struct drm_i915_private *dev_priv = dev->dev_private;
13587         struct intel_display_error_state *error;
13588         int transcoders[] = {
13589                 TRANSCODER_A,
13590                 TRANSCODER_B,
13591                 TRANSCODER_C,
13592                 TRANSCODER_EDP,
13593         };
13594         int i;
13595
13596         if (INTEL_INFO(dev)->num_pipes == 0)
13597                 return NULL;
13598
13599         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13600         if (error == NULL)
13601                 return NULL;
13602
13603         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13604                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13605
13606         for_each_pipe(dev_priv, i) {
13607                 error->pipe[i].power_domain_on =
13608                         intel_display_power_enabled_unlocked(dev_priv,
13609                                                            POWER_DOMAIN_PIPE(i));
13610                 if (!error->pipe[i].power_domain_on)
13611                         continue;
13612
13613                 error->cursor[i].control = I915_READ(CURCNTR(i));
13614                 error->cursor[i].position = I915_READ(CURPOS(i));
13615                 error->cursor[i].base = I915_READ(CURBASE(i));
13616
13617                 error->plane[i].control = I915_READ(DSPCNTR(i));
13618                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13619                 if (INTEL_INFO(dev)->gen <= 3) {
13620                         error->plane[i].size = I915_READ(DSPSIZE(i));
13621                         error->plane[i].pos = I915_READ(DSPPOS(i));
13622                 }
13623                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13624                         error->plane[i].addr = I915_READ(DSPADDR(i));
13625                 if (INTEL_INFO(dev)->gen >= 4) {
13626                         error->plane[i].surface = I915_READ(DSPSURF(i));
13627                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13628                 }
13629
13630                 error->pipe[i].source = I915_READ(PIPESRC(i));
13631
13632                 if (HAS_GMCH_DISPLAY(dev))
13633                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13634         }
13635
13636         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13637         if (HAS_DDI(dev_priv->dev))
13638                 error->num_transcoders++; /* Account for eDP. */
13639
13640         for (i = 0; i < error->num_transcoders; i++) {
13641                 enum transcoder cpu_transcoder = transcoders[i];
13642
13643                 error->transcoder[i].power_domain_on =
13644                         intel_display_power_enabled_unlocked(dev_priv,
13645                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13646                 if (!error->transcoder[i].power_domain_on)
13647                         continue;
13648
13649                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13650
13651                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13652                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13653                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13654                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13655                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13656                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13657                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13658         }
13659
13660         return error;
13661 }
13662
13663 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13664
13665 void
13666 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13667                                 struct drm_device *dev,
13668                                 struct intel_display_error_state *error)
13669 {
13670         struct drm_i915_private *dev_priv = dev->dev_private;
13671         int i;
13672
13673         if (!error)
13674                 return;
13675
13676         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13677         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13678                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13679                            error->power_well_driver);
13680         for_each_pipe(dev_priv, i) {
13681                 err_printf(m, "Pipe [%d]:\n", i);
13682                 err_printf(m, "  Power: %s\n",
13683                            error->pipe[i].power_domain_on ? "on" : "off");
13684                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13685                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13686
13687                 err_printf(m, "Plane [%d]:\n", i);
13688                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13689                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13690                 if (INTEL_INFO(dev)->gen <= 3) {
13691                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13692                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13693                 }
13694                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13695                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13696                 if (INTEL_INFO(dev)->gen >= 4) {
13697                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13698                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13699                 }
13700
13701                 err_printf(m, "Cursor [%d]:\n", i);
13702                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13703                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13704                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13705         }
13706
13707         for (i = 0; i < error->num_transcoders; i++) {
13708                 err_printf(m, "CPU transcoder: %c\n",
13709                            transcoder_name(error->transcoder[i].cpu_transcoder));
13710                 err_printf(m, "  Power: %s\n",
13711                            error->transcoder[i].power_domain_on ? "on" : "off");
13712                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13713                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13714                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13715                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13716                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13717                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13718                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13719         }
13720 }
13721
13722 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13723 {
13724         struct intel_crtc *crtc;
13725
13726         for_each_intel_crtc(dev, crtc) {
13727                 struct intel_unpin_work *work;
13728                 unsigned long irqflags;
13729
13730                 spin_lock_irqsave(&dev->event_lock, irqflags);
13731
13732                 work = crtc->unpin_work;
13733
13734                 if (work && work->event &&
13735                     work->event->base.file_priv == file) {
13736                         kfree(work->event);
13737                         work->event = NULL;
13738                 }
13739
13740                 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13741         }
13742 }