drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atomfirmware.h"
  27 #include "gmc_v10_0.h"
  28
  29 #include "hdp/hdp_5_0_0_offset.h"
  30 #include "hdp/hdp_5_0_0_sh_mask.h"
  31 #include "gc/gc_10_1_0_sh_mask.h"
  32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  33 #include "dcn/dcn_2_0_0_offset.h"
  34 #include "dcn/dcn_2_0_0_sh_mask.h"
  35 #include "oss/osssys_5_0_0_offset.h"
  36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  37 #include "navi10_enum.h"
  38
  39 #include "soc15.h"
  40 #include "soc15_common.h"
  41
  42 #include "nbio_v2_3.h"
  43
  44 #include "gfxhub_v2_0.h"
  45 #include "mmhub_v2_0.h"
  46 #include "athub_v2_0.h"
  47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
  48 #define AMDGPU_NUM_OF_VMIDS                     8
  49
  50 #if 0
  51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
  52 {
  53         /* TODO add golden setting for hdp */
  54 };
  55 #endif
  56
  57 static int
  58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  59                                    struct amdgpu_irq_src *src, unsigned type,
  60                                    enum amdgpu_interrupt_state state)
  61 {
  62         struct amdgpu_vmhub *hub;
  63         u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
  64
  65         bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  66                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  67                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  68                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  69                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  70                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  71                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
  72
  73         bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  74                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  75                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  76                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  77                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  78                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  79                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
  80
  81         switch (state) {
  82         case AMDGPU_IRQ_STATE_DISABLE:
  83                 /* MM HUB */
  84                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
  85                 for (i = 0; i < 16; i++) {
  86                         reg = hub->vm_context0_cntl + i;
  87                         tmp = RREG32(reg);
  88                         tmp &= ~bits[AMDGPU_MMHUB_0];
  89                         WREG32(reg, tmp);
  90                 }
  91
  92                 /* GFX HUB */
  93                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
  94                 for (i = 0; i < 16; i++) {
  95                         reg = hub->vm_context0_cntl + i;
  96                         tmp = RREG32(reg);
  97                         tmp &= ~bits[AMDGPU_GFXHUB_0];
  98                         WREG32(reg, tmp);
  99                 }
 100                 break;
 101         case AMDGPU_IRQ_STATE_ENABLE:
 102                 /* MM HUB */
 103                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 104                 for (i = 0; i < 16; i++) {
 105                         reg = hub->vm_context0_cntl + i;
 106                         tmp = RREG32(reg);
 107                         tmp |= bits[AMDGPU_MMHUB_0];
 108                         WREG32(reg, tmp);
 109                 }
 110
 111                 /* GFX HUB */
 112                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 113                 for (i = 0; i < 16; i++) {
 114                         reg = hub->vm_context0_cntl + i;
 115                         tmp = RREG32(reg);
 116                         tmp |= bits[AMDGPU_GFXHUB_0];
 117                         WREG32(reg, tmp);
 118                 }
 119                 break;
 120         default:
 121                 break;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
 128                                        struct amdgpu_irq_src *source,
 129                                        struct amdgpu_iv_entry *entry)
 130 {
 131         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 132         uint32_t status = 0;
 133         u64 addr;
 134
 135         addr = (u64)entry->src_data[0] << 12;
 136         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 137
 138         if (!amdgpu_sriov_vf(adev)) {
 139                 /*
 140                  * Issue a dummy read to wait for the status register to
 141                  * be updated to avoid reading an incorrect value due to
 142                  * the new fast GRBM interface.
 143                  */
 144                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 145                         RREG32(hub->vm_l2_pro_fault_status);
 146
 147                 status = RREG32(hub->vm_l2_pro_fault_status);
 148                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 149         }
 150
 151         if (printk_ratelimit()) {
 152                 struct amdgpu_task_info task_info;
 153
 154                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 155                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 156
 157                 dev_err(adev->dev,
 158                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 159                         "for process %s pid %d thread %s pid %d)\n",
 160                         entry->vmid_src ? "mmhub" : "gfxhub",
 161                         entry->src_id, entry->ring_id, entry->vmid,
 162                         entry->pasid, task_info.process_name, task_info.tgid,
 163                         task_info.task_name, task_info.pid);
 164                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 165                         addr, entry->client_id);
 166                 if (!amdgpu_sriov_vf(adev)) {
 167                         dev_err(adev->dev,
 168                                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 169                                 status);
 170                         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 171                                 REG_GET_FIELD(status,
 172                                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 173                         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 174                                 REG_GET_FIELD(status,
 175                                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 176                         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 177                                 REG_GET_FIELD(status,
 178                                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 179                         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 180                                 REG_GET_FIELD(status,
 181                                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 182                         dev_err(adev->dev, "\t RW: 0x%lx\n",
 183                                 REG_GET_FIELD(status,
 184                                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
 185                 }
 186         }
 187
 188         return 0;
 189 }
 190
 191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
 192         .set = gmc_v10_0_vm_fault_interrupt_state,
 193         .process = gmc_v10_0_process_interrupt,
 194 };
 195
 196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 197 {
 198         adev->gmc.vm_fault.num_types = 1;
 199         adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
 200 }
 201
 202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
 203                                              uint32_t flush_type)
 204 {
 205         u32 req = 0;
 206
 207         /* invalidate using legacy mode on vmid*/
 208         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
 209                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 210         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 211         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 212         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 213         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 214         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 215         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 216         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
 217                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 218
 219         return req;
 220 }
 221
 222 /*
 223  * GART
 224  * VMID 0 is the physical GPU addresses as used by the kernel.
 225  * VMIDs 1-15 are used for userspace clients and are handled
 226  * by the amdgpu vm/hsa code.
 227  */
 228
 229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 230                                    unsigned int vmhub, uint32_t flush_type)
 231 {
 232         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 233         u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);
 234         /* Use register 17 for GART */
 235         const unsigned eng = 17;
 236         unsigned int i;
 237
 238         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 239
 240         /*
 241          * Issue a dummy read to wait for the ACK register to be cleared
 242          * to avoid a false ACK due to the new fast GRBM interface.
 243          */
 244         if (vmhub == AMDGPU_GFXHUB_0)
 245                 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
 246
 247         /* Wait for ACK with a delay.*/
 248         for (i = 0; i < adev->usec_timeout; i++) {
 249                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 250                 tmp &= 1 << vmid;
 251                 if (tmp)
 252                         break;
 253
 254                 udelay(1);
 255         }
 256
 257         if (i < adev->usec_timeout)
 258                 return;
 259
 260         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 261 }
 262
 263 /**
 264  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
 265  *
 266  * @adev: amdgpu_device pointer
 267  * @vmid: vm instance to flush
 268  *
 269  * Flush the TLB for the requested page table.
 270  */
 271 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 272                                         uint32_t vmhub, uint32_t flush_type)
 273 {
 274         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 275         struct dma_fence *fence;
 276         struct amdgpu_job *job;
 277
 278         int r;
 279
 280         /* flush hdp cache */
 281         adev->nbio_funcs->hdp_flush(adev, NULL);
 282
 283         mutex_lock(&adev->mman.gtt_window_lock);
 284
 285         if (vmhub == AMDGPU_MMHUB_0) {
 286                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
 287                 mutex_unlock(&adev->mman.gtt_window_lock);
 288                 return;
 289         }
 290
 291         BUG_ON(vmhub != AMDGPU_GFXHUB_0);
 292
 293         if (!adev->mman.buffer_funcs_enabled ||
 294             !adev->ib_pool_ready ||
 295             adev->in_gpu_reset) {
 296                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
 297                 mutex_unlock(&adev->mman.gtt_window_lock);
 298                 return;
 299         }
 300
 301         /* The SDMA on Navi has a bug which can theoretically result in memory
 302          * corruption if an invalidation happens at the same time as an VA
 303          * translation. Avoid this by doing the invalidation from the SDMA
 304          * itself.
 305          */
 306         r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job);
 307         if (r)
 308                 goto error_alloc;
 309
 310         job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 311         job->vm_needs_flush = true;
 312         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 313         r = amdgpu_job_submit(job, &adev->mman.entity,
 314                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 315         if (r)
 316                 goto error_submit;
 317
 318         mutex_unlock(&adev->mman.gtt_window_lock);
 319
 320         dma_fence_wait(fence, false);
 321         dma_fence_put(fence);
 322
 323         return;
 324
 325 error_submit:
 326         amdgpu_job_free(job);
 327
 328 error_alloc:
 329         mutex_unlock(&adev->mman.gtt_window_lock);
 330         DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 331 }
 332
 333 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 334                                              unsigned vmid, uint64_t pd_addr)
 335 {
 336         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 337         uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
 338         unsigned eng = ring->vm_inv_eng;
 339
 340         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 341                               lower_32_bits(pd_addr));
 342
 343         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 344                               upper_32_bits(pd_addr));
 345
 346         amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
 347
 348         /* wait for the invalidate to complete */
 349         amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
 350                                   1 << vmid, 1 << vmid);
 351
 352         return pd_addr;
 353 }
 354
 355 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 356                                          unsigned pasid)
 357 {
 358         struct amdgpu_device *adev = ring->adev;
 359         uint32_t reg;
 360
 361         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 362                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 363         else
 364                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 365
 366         amdgpu_ring_emit_wreg(ring, reg, pasid);
 367 }
 368
 369 /*
 370  * PTE format on NAVI 10:
 371  * 63:59 reserved
 372  * 58:57 reserved
 373  * 56 F
 374  * 55 L
 375  * 54 reserved
 376  * 53:52 SW
 377  * 51 T
 378  * 50:48 mtype
 379  * 47:12 4k physical page base address
 380  * 11:7 fragment
 381  * 6 write
 382  * 5 read
 383  * 4 exe
 384  * 3 Z
 385  * 2 snooped
 386  * 1 system
 387  * 0 valid
 388  *
 389  * PDE format on NAVI 10:
 390  * 63:59 block fragment size
 391  * 58:55 reserved
 392  * 54 P
 393  * 53:48 reserved
 394  * 47:6 physical base address of PD or PTE
 395  * 5:3 reserved
 396  * 2 C
 397  * 1 system
 398  * 0 valid
 399  */
 400 static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev,
 401                                            uint32_t flags)
 402 {
 403         uint64_t pte_flag = 0;
 404
 405         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 406                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 407         if (flags & AMDGPU_VM_PAGE_READABLE)
 408                 pte_flag |= AMDGPU_PTE_READABLE;
 409         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 410                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 411
 412         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 413         case AMDGPU_VM_MTYPE_DEFAULT:
 414                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 415                 break;
 416         case AMDGPU_VM_MTYPE_NC:
 417                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 418                 break;
 419         case AMDGPU_VM_MTYPE_WC:
 420                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 421                 break;
 422         case AMDGPU_VM_MTYPE_CC:
 423                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 424                 break;
 425         case AMDGPU_VM_MTYPE_UC:
 426                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 427                 break;
 428         default:
 429                 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 430                 break;
 431         }
 432
 433         if (flags & AMDGPU_VM_PAGE_PRT)
 434                 pte_flag |= AMDGPU_PTE_PRT;
 435
 436         return pte_flag;
 437 }
 438
 439 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
 440                                  uint64_t *addr, uint64_t *flags)
 441 {
 442         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 443                 *addr = adev->vm_manager.vram_base_offset + *addr -
 444                         adev->gmc.vram_start;
 445         BUG_ON(*addr & 0xFFFF00000000003FULL);
 446
 447         if (!adev->gmc.translate_further)
 448                 return;
 449
 450         if (level == AMDGPU_VM_PDB1) {
 451                 /* Set the block fragment size */
 452                 if (!(*flags & AMDGPU_PDE_PTE))
 453                         *flags |= AMDGPU_PDE_BFS(0x9);
 454
 455         } else if (level == AMDGPU_VM_PDB0) {
 456                 if (*flags & AMDGPU_PDE_PTE)
 457                         *flags &= ~AMDGPU_PDE_PTE;
 458                 else
 459                         *flags |= AMDGPU_PTE_TF;
 460         }
 461 }
 462
 463 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
 464         .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
 465         .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
 466         .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
 467         .get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags,
 468         .get_vm_pde = gmc_v10_0_get_vm_pde
 469 };
 470
 471 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
 472 {
 473         if (adev->gmc.gmc_funcs == NULL)
 474                 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 475 }
 476
 477 static int gmc_v10_0_early_init(void *handle)
 478 {
 479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 480
 481         gmc_v10_0_set_gmc_funcs(adev);
 482         gmc_v10_0_set_irq_funcs(adev);
 483
 484         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 485         adev->gmc.shared_aperture_end =
 486                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 487         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 488         adev->gmc.private_aperture_end =
 489                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 490
 491         return 0;
 492 }
 493
 494 static int gmc_v10_0_late_init(void *handle)
 495 {
 496         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 497         unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
 498         unsigned i;
 499
 500         for(i = 0; i < adev->num_rings; ++i) {
 501                 struct amdgpu_ring *ring = adev->rings[i];
 502                 unsigned vmhub = ring->funcs->vmhub;
 503
 504                 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
 505                 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
 506                          ring->idx, ring->name, ring->vm_inv_eng,
 507                          ring->funcs->vmhub);
 508         }
 509
 510         /* Engine 17 is used for GART flushes */
 511         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
 512                 BUG_ON(vm_inv_eng[i] > 17);
 513
 514         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 515 }
 516
 517 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 518                                         struct amdgpu_gmc *mc)
 519 {
 520         u64 base = 0;
 521
 522         if (!amdgpu_sriov_vf(adev))
 523                 base = gfxhub_v2_0_get_fb_location(adev);
 524
 525         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 526         amdgpu_gmc_gart_location(adev, mc);
 527
 528         /* base offset of vram pages */
 529         adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
 530 }
 531
 532 /**
 533  * gmc_v10_0_mc_init - initialize the memory controller driver params
 534  *
 535  * @adev: amdgpu_device pointer
 536  *
 537  * Look up the amount of vram, vram width, and decide how to place
 538  * vram and gart within the GPU's physical address space.
 539  * Returns 0 for success.
 540  */
 541 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 542 {
 543         int chansize, numchan;
 544
 545         if (!amdgpu_emu_mode)
 546                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 547         else {
 548                 /* hard code vram_width for emulation */
 549                 chansize = 128;
 550                 numchan = 1;
 551                 adev->gmc.vram_width = numchan * chansize;
 552         }
 553
 554         /* Could aper size report 0 ? */
 555         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 556         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 557
 558         /* size in MB on si */
 559         adev->gmc.mc_vram_size =
 560                 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 561         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 562         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 563
 564         /* In case the PCI BAR is larger than the actual amount of vram */
 565         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 566                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 567
 568         /* set the gart size */
 569         if (amdgpu_gart_size == -1) {
 570                 switch (adev->asic_type) {
 571                 case CHIP_NAVI10:
 572                 case CHIP_NAVI14:
 573                 case CHIP_NAVI12:
 574                 default:
 575                         adev->gmc.gart_size = 512ULL << 20;
 576                         break;
 577                 }
 578         } else
 579                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 580
 581         gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
 582
 583         return 0;
 584 }
 585
 586 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
 587 {
 588         int r;
 589
 590         if (adev->gart.bo) {
 591                 WARN(1, "NAVI10 PCIE GART already initialized\n");
 592                 return 0;
 593         }
 594
 595         /* Initialize common gart structure */
 596         r = amdgpu_gart_init(adev);
 597         if (r)
 598                 return r;
 599
 600         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 601         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 602                                  AMDGPU_PTE_EXECUTABLE;
 603
 604         return amdgpu_gart_table_vram_alloc(adev);
 605 }
 606
 607 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 608 {
 609         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 610         unsigned size;
 611
 612         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 613                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 614         } else {
 615                 u32 viewport;
 616                 u32 pitch;
 617
 618                 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 619                 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
 620                 size = (REG_GET_FIELD(viewport,
 621                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 622                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 623                                 4);
 624         }
 625         /* return 0 if the pre-OS buffer uses up most of vram */
 626         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
 627                 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
 628                                 be aware of gart table overwrite\n");
 629                 return 0;
 630         }
 631
 632         return size;
 633 }
 634
 635
 636
 637 static int gmc_v10_0_sw_init(void *handle)
 638 {
 639         int r;
 640         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 641
 642         gfxhub_v2_0_init(adev);
 643         mmhub_v2_0_init(adev);
 644
 645         spin_lock_init(&adev->gmc.invalidate_lock);
 646
 647         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
 648         switch (adev->asic_type) {
 649         case CHIP_NAVI10:
 650         case CHIP_NAVI14:
 651         case CHIP_NAVI12:
 652                 adev->num_vmhubs = 2;
 653                 /*
 654                  * To fulfill 4-level page support,
 655                  * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
 656                  * block size 512 (9bit)
 657                  */
 658                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 659                 break;
 660         default:
 661                 break;
 662         }
 663
 664         /* This interrupt is VMC page fault.*/
 665         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
 666                               VMC_1_0__SRCID__VM_FAULT,
 667                               &adev->gmc.vm_fault);
 668         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
 669                               UTCL2_1_0__SRCID__FAULT,
 670                               &adev->gmc.vm_fault);
 671         if (r)
 672                 return r;
 673
 674         /*
 675          * Set the internal MC address mask This is the max address of the GPU's
 676          * internal address space.
 677          */
 678         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 679
 680         /*
 681          * Reserve 8M stolen memory for navi10 like vega10
 682          * TODO: will check if it's really needed on asic.
 683          */
 684         if (amdgpu_emu_mode == 1)
 685                 adev->gmc.stolen_size = 0;
 686         else
 687                 adev->gmc.stolen_size = 9 * 1024 *1024;
 688
 689         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 690         if (r) {
 691                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 692                 return r;
 693         }
 694
 695         r = gmc_v10_0_mc_init(adev);
 696         if (r)
 697                 return r;
 698
 699         adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
 700
 701         /* Memory manager */
 702         r = amdgpu_bo_init(adev);
 703         if (r)
 704                 return r;
 705
 706         r = gmc_v10_0_gart_init(adev);
 707         if (r)
 708                 return r;
 709
 710         /*
 711          * number of VMs
 712          * VMID 0 is reserved for System
 713          * amdgpu graphics/compute will use VMIDs 1-7
 714          * amdkfd will use VMIDs 8-15
 715          */
 716         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 717         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 718
 719         amdgpu_vm_manager_init(adev);
 720
 721         return 0;
 722 }
 723
 724 /**
 725  * gmc_v8_0_gart_fini - vm fini callback
 726  *
 727  * @adev: amdgpu_device pointer
 728  *
 729  * Tears down the driver GART/VM setup (CIK).
 730  */
 731 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
 732 {
 733         amdgpu_gart_table_vram_free(adev);
 734         amdgpu_gart_fini(adev);
 735 }
 736
 737 static int gmc_v10_0_sw_fini(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740
 741         amdgpu_vm_manager_fini(adev);
 742         gmc_v10_0_gart_fini(adev);
 743         amdgpu_gem_force_release(adev);
 744         amdgpu_bo_fini(adev);
 745
 746         return 0;
 747 }
 748
 749 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 750 {
 751         switch (adev->asic_type) {
 752         case CHIP_NAVI10:
 753         case CHIP_NAVI14:
 754         case CHIP_NAVI12:
 755                 break;
 756         default:
 757                 break;
 758         }
 759 }
 760
 761 /**
 762  * gmc_v10_0_gart_enable - gart enable
 763  *
 764  * @adev: amdgpu_device pointer
 765  */
 766 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
 767 {
 768         int r;
 769         bool value;
 770         u32 tmp;
 771
 772         if (adev->gart.bo == NULL) {
 773                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 774                 return -EINVAL;
 775         }
 776
 777         r = amdgpu_gart_table_vram_pin(adev);
 778         if (r)
 779                 return r;
 780
 781         r = gfxhub_v2_0_gart_enable(adev);
 782         if (r)
 783                 return r;
 784
 785         r = mmhub_v2_0_gart_enable(adev);
 786         if (r)
 787                 return r;
 788
 789         tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
 790         tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
 791         WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
 792
 793         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
 794         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 795
 796         /* Flush HDP after it is initialized */
 797         adev->nbio_funcs->hdp_flush(adev, NULL);
 798
 799         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 800                 false : true;
 801
 802         gfxhub_v2_0_set_fault_enable_default(adev, value);
 803         mmhub_v2_0_set_fault_enable_default(adev, value);
 804         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
 805         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
 806
 807         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 808                  (unsigned)(adev->gmc.gart_size >> 20),
 809                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 810
 811         adev->gart.ready = true;
 812
 813         return 0;
 814 }
 815
 816 static int gmc_v10_0_hw_init(void *handle)
 817 {
 818         int r;
 819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 820
 821         /* The sequence of these two function calls matters.*/
 822         gmc_v10_0_init_golden_registers(adev);
 823
 824         r = gmc_v10_0_gart_enable(adev);
 825         if (r)
 826                 return r;
 827
 828         return 0;
 829 }
 830
 831 /**
 832  * gmc_v10_0_gart_disable - gart disable
 833  *
 834  * @adev: amdgpu_device pointer
 835  *
 836  * This disables all VM page table.
 837  */
 838 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
 839 {
 840         gfxhub_v2_0_gart_disable(adev);
 841         mmhub_v2_0_gart_disable(adev);
 842         amdgpu_gart_table_vram_unpin(adev);
 843 }
 844
 845 static int gmc_v10_0_hw_fini(void *handle)
 846 {
 847         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 848
 849         if (amdgpu_sriov_vf(adev)) {
 850                 /* full access mode, so don't touch any GMC register */
 851                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 852                 return 0;
 853         }
 854
 855         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 856         gmc_v10_0_gart_disable(adev);
 857
 858         return 0;
 859 }
 860
 861 static int gmc_v10_0_suspend(void *handle)
 862 {
 863         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 864
 865         gmc_v10_0_hw_fini(adev);
 866
 867         return 0;
 868 }
 869
 870 static int gmc_v10_0_resume(void *handle)
 871 {
 872         int r;
 873         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 874
 875         r = gmc_v10_0_hw_init(adev);
 876         if (r)
 877                 return r;
 878
 879         amdgpu_vmid_reset_all(adev);
 880
 881         return 0;
 882 }
 883
 884 static bool gmc_v10_0_is_idle(void *handle)
 885 {
 886         /* MC is always ready in GMC v10.*/
 887         return true;
 888 }
 889
 890 static int gmc_v10_0_wait_for_idle(void *handle)
 891 {
 892         /* There is no need to wait for MC idle in GMC v10.*/
 893         return 0;
 894 }
 895
 896 static int gmc_v10_0_soft_reset(void *handle)
 897 {
 898         return 0;
 899 }
 900
 901 static int gmc_v10_0_set_clockgating_state(void *handle,
 902                                            enum amd_clockgating_state state)
 903 {
 904         int r;
 905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 906
 907         r = mmhub_v2_0_set_clockgating(adev, state);
 908         if (r)
 909                 return r;
 910
 911         return athub_v2_0_set_clockgating(adev, state);
 912 }
 913
 914 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
 915 {
 916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 917
 918         mmhub_v2_0_get_clockgating(adev, flags);
 919
 920         athub_v2_0_get_clockgating(adev, flags);
 921 }
 922
 923 static int gmc_v10_0_set_powergating_state(void *handle,
 924                                            enum amd_powergating_state state)
 925 {
 926         return 0;
 927 }
 928
 929 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
 930         .name = "gmc_v10_0",
 931         .early_init = gmc_v10_0_early_init,
 932         .late_init = gmc_v10_0_late_init,
 933         .sw_init = gmc_v10_0_sw_init,
 934         .sw_fini = gmc_v10_0_sw_fini,
 935         .hw_init = gmc_v10_0_hw_init,
 936         .hw_fini = gmc_v10_0_hw_fini,
 937         .suspend = gmc_v10_0_suspend,
 938         .resume = gmc_v10_0_resume,
 939         .is_idle = gmc_v10_0_is_idle,
 940         .wait_for_idle = gmc_v10_0_wait_for_idle,
 941         .soft_reset = gmc_v10_0_soft_reset,
 942         .set_clockgating_state = gmc_v10_0_set_clockgating_state,
 943         .set_powergating_state = gmc_v10_0_set_powergating_state,
 944         .get_clockgating_state = gmc_v10_0_get_clockgating_state,
 945 };
 946
 947 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
 948 {
 949         .type = AMD_IP_BLOCK_TYPE_GMC,
 950         .major = 10,
 951         .minor = 0,
 952         .rev = 0,
 953         .funcs = &gmc_v10_0_ip_funcs,
 954 };