drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 6):
 150                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 151                 break;
 152         case IP_VERSION(13, 0, 10):
 153                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 154                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 155                 break;
 156         default:
 157                 return -EINVAL;
 158         }
 159         return ret;
 160 }
 161
 162 static int psp_early_init(void *handle)
 163 {
 164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 165         struct psp_context *psp = &adev->psp;
 166
 167         switch (adev->ip_versions[MP0_HWIP][0]) {
 168         case IP_VERSION(9, 0, 0):
 169                 psp_v3_1_set_psp_funcs(psp);
 170                 psp->autoload_supported = false;
 171                 break;
 172         case IP_VERSION(10, 0, 0):
 173         case IP_VERSION(10, 0, 1):
 174                 psp_v10_0_set_psp_funcs(psp);
 175                 psp->autoload_supported = false;
 176                 break;
 177         case IP_VERSION(11, 0, 2):
 178         case IP_VERSION(11, 0, 4):
 179                 psp_v11_0_set_psp_funcs(psp);
 180                 psp->autoload_supported = false;
 181                 break;
 182         case IP_VERSION(11, 0, 0):
 183         case IP_VERSION(11, 0, 5):
 184         case IP_VERSION(11, 0, 9):
 185         case IP_VERSION(11, 0, 7):
 186         case IP_VERSION(11, 0, 11):
 187         case IP_VERSION(11, 5, 0):
 188         case IP_VERSION(11, 0, 12):
 189         case IP_VERSION(11, 0, 13):
 190                 psp_v11_0_set_psp_funcs(psp);
 191                 psp->autoload_supported = true;
 192                 break;
 193         case IP_VERSION(11, 0, 3):
 194         case IP_VERSION(12, 0, 1):
 195                 psp_v12_0_set_psp_funcs(psp);
 196                 break;
 197         case IP_VERSION(13, 0, 2):
 198         case IP_VERSION(13, 0, 6):
 199                 psp_v13_0_set_psp_funcs(psp);
 200                 break;
 201         case IP_VERSION(13, 0, 1):
 202         case IP_VERSION(13, 0, 3):
 203         case IP_VERSION(13, 0, 5):
 204         case IP_VERSION(13, 0, 8):
 205         case IP_VERSION(13, 0, 10):
 206         case IP_VERSION(13, 0, 11):
 207                 psp_v13_0_set_psp_funcs(psp);
 208                 psp->autoload_supported = true;
 209                 break;
 210         case IP_VERSION(11, 0, 8):
 211                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 212                         psp_v11_0_8_set_psp_funcs(psp);
 213                         psp->autoload_supported = false;
 214                 }
 215                 break;
 216         case IP_VERSION(13, 0, 0):
 217         case IP_VERSION(13, 0, 7):
 218                 psp_v13_0_set_psp_funcs(psp);
 219                 psp->autoload_supported = true;
 220                 break;
 221         case IP_VERSION(13, 0, 4):
 222                 psp_v13_0_4_set_psp_funcs(psp);
 223                 psp->autoload_supported = true;
 224                 break;
 225         default:
 226                 return -EINVAL;
 227         }
 228
 229         psp->adev = adev;
 230
 231         psp_check_pmfw_centralized_cstate_management(psp);
 232
 233         if (amdgpu_sriov_vf(adev))
 234                 return psp_init_sriov_microcode(psp);
 235         else
 236                 return psp_init_microcode(psp);
 237 }
 238
 239 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 240 {
 241         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 242                               &mem_ctx->shared_buf);
 243         mem_ctx->shared_bo = NULL;
 244 }
 245
 246 static void psp_free_shared_bufs(struct psp_context *psp)
 247 {
 248         void *tmr_buf;
 249         void **pptr;
 250
 251         /* free TMR memory buffer */
 252         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 253         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 254         psp->tmr_bo = NULL;
 255
 256         /* free xgmi shared memory */
 257         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 258
 259         /* free ras shared memory */
 260         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 261
 262         /* free hdcp shared memory */
 263         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 264
 265         /* free dtm shared memory */
 266         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 267
 268         /* free rap shared memory */
 269         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 270
 271         /* free securedisplay shared memory */
 272         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 273
 274
 275 }
 276
 277 static void psp_memory_training_fini(struct psp_context *psp)
 278 {
 279         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 280
 281         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 282         kfree(ctx->sys_cache);
 283         ctx->sys_cache = NULL;
 284 }
 285
 286 static int psp_memory_training_init(struct psp_context *psp)
 287 {
 288         int ret;
 289         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 290
 291         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 292                 DRM_DEBUG("memory training is not supported!\n");
 293                 return 0;
 294         }
 295
 296         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 297         if (ctx->sys_cache == NULL) {
 298                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 299                 ret = -ENOMEM;
 300                 goto Err_out;
 301         }
 302
 303         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 304                   ctx->train_data_size,
 305                   ctx->p2c_train_data_offset,
 306                   ctx->c2p_train_data_offset);
 307         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 308         return 0;
 309
 310 Err_out:
 311         psp_memory_training_fini(psp);
 312         return ret;
 313 }
 314
 315 /*
 316  * Helper funciton to query psp runtime database entry
 317  *
 318  * @adev: amdgpu_device pointer
 319  * @entry_type: the type of psp runtime database entry
 320  * @db_entry: runtime database entry pointer
 321  *
 322  * Return false if runtime database doesn't exit or entry is invalid
 323  * or true if the specific database entry is found, and copy to @db_entry
 324  */
 325 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 326                                      enum psp_runtime_entry_type entry_type,
 327                                      void *db_entry)
 328 {
 329         uint64_t db_header_pos, db_dir_pos;
 330         struct psp_runtime_data_header db_header = {0};
 331         struct psp_runtime_data_directory db_dir = {0};
 332         bool ret = false;
 333         int i;
 334
 335         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6))
 336                 return false;
 337
 338         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 339         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 340
 341         /* read runtime db header from vram */
 342         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 343                         sizeof(struct psp_runtime_data_header), false);
 344
 345         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 346                 /* runtime db doesn't exist, exit */
 347                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 348                 return false;
 349         }
 350
 351         /* read runtime database entry from vram */
 352         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 353                         sizeof(struct psp_runtime_data_directory), false);
 354
 355         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 356                 /* invalid db entry count, exit */
 357                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 358                 return false;
 359         }
 360
 361         /* look up for requested entry type */
 362         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 363                 if (db_dir.entry_list[i].entry_type == entry_type) {
 364                         switch (entry_type) {
 365                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 366                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 367                                         /* invalid db entry size */
 368                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 369                                         return false;
 370                                 }
 371                                 /* read runtime database entry */
 372                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 373                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 374                                 ret = true;
 375                                 break;
 376                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 377                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 378                                         /* invalid db entry size */
 379                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 380                                         return false;
 381                                 }
 382                                 /* read runtime database entry */
 383                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 384                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 385                                 ret = true;
 386                                 break;
 387                         default:
 388                                 ret = false;
 389                                 break;
 390                         }
 391                 }
 392         }
 393
 394         return ret;
 395 }
 396
 397 static int psp_sw_init(void *handle)
 398 {
 399         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 400         struct psp_context *psp = &adev->psp;
 401         int ret;
 402         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 403         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 404         struct psp_runtime_scpm_entry scpm_entry;
 405
 406         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 407         if (!psp->cmd) {
 408                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 409                 ret = -ENOMEM;
 410         }
 411
 412         adev->psp.xgmi_context.supports_extended_data =
 413                 !adev->gmc.xgmi.connected_to_cpu &&
 414                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 415
 416         memset(&scpm_entry, 0, sizeof(scpm_entry));
 417         if ((psp_get_runtime_db_entry(adev,
 418                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 419                                 &scpm_entry)) &&
 420             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 421                 adev->scpm_enabled = true;
 422                 adev->scpm_status = scpm_entry.scpm_status;
 423         } else {
 424                 adev->scpm_enabled = false;
 425                 adev->scpm_status = SCPM_DISABLE;
 426         }
 427
 428         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 429
 430         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 431         if (psp_get_runtime_db_entry(adev,
 432                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 433                                 &boot_cfg_entry)) {
 434                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 435                 if ((psp->boot_cfg_bitmask) &
 436                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 437                         /* If psp runtime database exists, then
 438                          * only enable two stage memory training
 439                          * when TWO_STAGE_DRAM_TRAINING bit is set
 440                          * in runtime database */
 441                         mem_training_ctx->enable_mem_training = true;
 442                 }
 443
 444         } else {
 445                 /* If psp runtime database doesn't exist or
 446                  * is invalid, force enable two stage memory
 447                  * training */
 448                 mem_training_ctx->enable_mem_training = true;
 449         }
 450
 451         if (mem_training_ctx->enable_mem_training) {
 452                 ret = psp_memory_training_init(psp);
 453                 if (ret) {
 454                         DRM_ERROR("Failed to initialize memory training!\n");
 455                         return ret;
 456                 }
 457
 458                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 459                 if (ret) {
 460                         DRM_ERROR("Failed to process memory training!\n");
 461                         return ret;
 462                 }
 463         }
 464
 465         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 466             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 467                 ret = psp_sysfs_init(adev);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 473                                       amdgpu_sriov_vf(adev) ?
 474                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 475                                       &psp->fw_pri_bo,
 476                                       &psp->fw_pri_mc_addr,
 477                                       &psp->fw_pri_buf);
 478         if (ret)
 479                 return ret;
 480
 481         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 482                                       AMDGPU_GEM_DOMAIN_VRAM |
 483                                       AMDGPU_GEM_DOMAIN_GTT,
 484                                       &psp->fence_buf_bo,
 485                                       &psp->fence_buf_mc_addr,
 486                                       &psp->fence_buf);
 487         if (ret)
 488                 goto failed1;
 489
 490         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 491                                       AMDGPU_GEM_DOMAIN_VRAM |
 492                                       AMDGPU_GEM_DOMAIN_GTT,
 493                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 494                                       (void **)&psp->cmd_buf_mem);
 495         if (ret)
 496                 goto failed2;
 497
 498         return 0;
 499
 500 failed2:
 501         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 502                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 503 failed1:
 504         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 505                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 506         return ret;
 507 }
 508
 509 static int psp_sw_fini(void *handle)
 510 {
 511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 512         struct psp_context *psp = &adev->psp;
 513         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 514
 515         psp_memory_training_fini(psp);
 516
 517         amdgpu_ucode_release(&psp->sos_fw);
 518         amdgpu_ucode_release(&psp->asd_fw);
 519         amdgpu_ucode_release(&psp->ta_fw);
 520         amdgpu_ucode_release(&psp->cap_fw);
 521         amdgpu_ucode_release(&psp->toc_fw);
 522
 523         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 524             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 525                 psp_sysfs_fini(adev);
 526
 527         kfree(cmd);
 528         cmd = NULL;
 529
 530         psp_free_shared_bufs(psp);
 531
 532         if (psp->km_ring.ring_mem)
 533                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 534                                       &psp->km_ring.ring_mem_mc_addr,
 535                                       (void **)&psp->km_ring.ring_mem);
 536
 537         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 538                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 539         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 540                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 541         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 542                               (void **)&psp->cmd_buf_mem);
 543
 544         return 0;
 545 }
 546
 547 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 548                  uint32_t reg_val, uint32_t mask, bool check_changed)
 549 {
 550         uint32_t val;
 551         int i;
 552         struct amdgpu_device *adev = psp->adev;
 553
 554         if (psp->adev->no_hw_access)
 555                 return 0;
 556
 557         for (i = 0; i < adev->usec_timeout; i++) {
 558                 val = RREG32(reg_index);
 559                 if (check_changed) {
 560                         if (val != reg_val)
 561                                 return 0;
 562                 } else {
 563                         if ((val & mask) == reg_val)
 564                                 return 0;
 565                 }
 566                 udelay(1);
 567         }
 568
 569         return -ETIME;
 570 }
 571
 572 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
 573                                uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
 574 {
 575         uint32_t val;
 576         int i;
 577         struct amdgpu_device *adev = psp->adev;
 578
 579         if (psp->adev->no_hw_access)
 580                 return 0;
 581
 582         for (i = 0; i < msec_timeout; i++) {
 583                 val = RREG32(reg_index);
 584                 if ((val & mask) == reg_val)
 585                         return 0;
 586                 msleep(1);
 587         }
 588
 589         return -ETIME;
 590 }
 591
 592 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 593 {
 594         switch (cmd_id) {
 595         case GFX_CMD_ID_LOAD_TA:
 596                 return "LOAD_TA";
 597         case GFX_CMD_ID_UNLOAD_TA:
 598                 return "UNLOAD_TA";
 599         case GFX_CMD_ID_INVOKE_CMD:
 600                 return "INVOKE_CMD";
 601         case GFX_CMD_ID_LOAD_ASD:
 602                 return "LOAD_ASD";
 603         case GFX_CMD_ID_SETUP_TMR:
 604                 return "SETUP_TMR";
 605         case GFX_CMD_ID_LOAD_IP_FW:
 606                 return "LOAD_IP_FW";
 607         case GFX_CMD_ID_DESTROY_TMR:
 608                 return "DESTROY_TMR";
 609         case GFX_CMD_ID_SAVE_RESTORE:
 610                 return "SAVE_RESTORE_IP_FW";
 611         case GFX_CMD_ID_SETUP_VMR:
 612                 return "SETUP_VMR";
 613         case GFX_CMD_ID_DESTROY_VMR:
 614                 return "DESTROY_VMR";
 615         case GFX_CMD_ID_PROG_REG:
 616                 return "PROG_REG";
 617         case GFX_CMD_ID_GET_FW_ATTESTATION:
 618                 return "GET_FW_ATTESTATION";
 619         case GFX_CMD_ID_LOAD_TOC:
 620                 return "ID_LOAD_TOC";
 621         case GFX_CMD_ID_AUTOLOAD_RLC:
 622                 return "AUTOLOAD_RLC";
 623         case GFX_CMD_ID_BOOT_CFG:
 624                 return "BOOT_CFG";
 625         default:
 626                 return "UNKNOWN CMD";
 627         }
 628 }
 629
 630 static int
 631 psp_cmd_submit_buf(struct psp_context *psp,
 632                    struct amdgpu_firmware_info *ucode,
 633                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 634 {
 635         int ret;
 636         int index;
 637         int timeout = 20000;
 638         bool ras_intr = false;
 639         bool skip_unsupport = false;
 640
 641         if (psp->adev->no_hw_access)
 642                 return 0;
 643
 644         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 645
 646         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 647
 648         index = atomic_inc_return(&psp->fence_value);
 649         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 650         if (ret) {
 651                 atomic_dec(&psp->fence_value);
 652                 goto exit;
 653         }
 654
 655         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 656         while (*((unsigned int *)psp->fence_buf) != index) {
 657                 if (--timeout == 0)
 658                         break;
 659                 /*
 660                  * Shouldn't wait for timeout when err_event_athub occurs,
 661                  * because gpu reset thread triggered and lock resource should
 662                  * be released for psp resume sequence.
 663                  */
 664                 ras_intr = amdgpu_ras_intr_triggered();
 665                 if (ras_intr)
 666                         break;
 667                 usleep_range(10, 100);
 668                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 669         }
 670
 671         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 672         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 673                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 674
 675         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 676
 677         /* In some cases, psp response status is not 0 even there is no
 678          * problem while the command is submitted. Some version of PSP FW
 679          * doesn't write 0 to that field.
 680          * So here we would like to only print a warning instead of an error
 681          * during psp initialization to avoid breaking hw_init and it doesn't
 682          * return -EINVAL.
 683          */
 684         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 685                 if (ucode)
 686                         DRM_WARN("failed to load ucode %s(0x%X) ",
 687                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 688                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 689                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 690                          psp->cmd_buf_mem->resp.status);
 691                 /* If any firmware (including CAP) load fails under SRIOV, it should
 692                  * return failure to stop the VF from initializing.
 693                  * Also return failure in case of timeout
 694                  */
 695                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 696                         ret = -EINVAL;
 697                         goto exit;
 698                 }
 699         }
 700
 701         if (ucode) {
 702                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 703                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 704         }
 705
 706 exit:
 707         return ret;
 708 }
 709
 710 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 711 {
 712         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 713
 714         mutex_lock(&psp->mutex);
 715
 716         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 717
 718         return cmd;
 719 }
 720
 721 static void release_psp_cmd_buf(struct psp_context *psp)
 722 {
 723         mutex_unlock(&psp->mutex);
 724 }
 725
 726 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 727                                  struct psp_gfx_cmd_resp *cmd,
 728                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 729 {
 730         struct amdgpu_device *adev = psp->adev;
 731         uint32_t size = 0;
 732         uint64_t tmr_pa = 0;
 733
 734         if (tmr_bo) {
 735                 size = amdgpu_bo_size(tmr_bo);
 736                 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 737         }
 738
 739         if (amdgpu_sriov_vf(psp->adev))
 740                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 741         else
 742                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 743         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 744         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 745         cmd->cmd.cmd_setup_tmr.buf_size = size;
 746         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 747         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 748         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 749 }
 750
 751 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 752                                       uint64_t pri_buf_mc, uint32_t size)
 753 {
 754         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 755         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 756         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 757         cmd->cmd.cmd_load_toc.toc_size = size;
 758 }
 759
 760 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 761 static int psp_load_toc(struct psp_context *psp,
 762                         uint32_t *tmr_size)
 763 {
 764         int ret;
 765         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 766
 767         /* Copy toc to psp firmware private buffer */
 768         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 769
 770         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 771
 772         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 773                                  psp->fence_buf_mc_addr);
 774         if (!ret)
 775                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 776
 777         release_psp_cmd_buf(psp);
 778
 779         return ret;
 780 }
 781
 782 static bool psp_boottime_tmr(struct psp_context *psp)
 783 {
 784         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 785         case IP_VERSION(13, 0, 6):
 786                 return true;
 787         default:
 788                 return false;
 789         }
 790 }
 791
 792 /* Set up Trusted Memory Region */
 793 static int psp_tmr_init(struct psp_context *psp)
 794 {
 795         int ret = 0;
 796         int tmr_size;
 797         void *tmr_buf;
 798         void **pptr;
 799
 800         /*
 801          * According to HW engineer, they prefer the TMR address be "naturally
 802          * aligned" , e.g. the start address be an integer divide of TMR size.
 803          *
 804          * Note: this memory need be reserved till the driver
 805          * uninitializes.
 806          */
 807         tmr_size = PSP_TMR_SIZE(psp->adev);
 808
 809         /* For ASICs support RLC autoload, psp will parse the toc
 810          * and calculate the total size of TMR needed */
 811         if (!amdgpu_sriov_vf(psp->adev) &&
 812             psp->toc.start_addr &&
 813             psp->toc.size_bytes &&
 814             psp->fw_pri_buf) {
 815                 ret = psp_load_toc(psp, &tmr_size);
 816                 if (ret) {
 817                         DRM_ERROR("Failed to load toc\n");
 818                         return ret;
 819                 }
 820         }
 821
 822         if (!psp->tmr_bo) {
 823                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 824                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 825                                               PSP_TMR_ALIGNMENT,
 826                                               AMDGPU_HAS_VRAM(psp->adev) ?
 827                                               AMDGPU_GEM_DOMAIN_VRAM :
 828                                               AMDGPU_GEM_DOMAIN_GTT,
 829                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 830                                               pptr);
 831         }
 832
 833         return ret;
 834 }
 835
 836 static bool psp_skip_tmr(struct psp_context *psp)
 837 {
 838         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 839         case IP_VERSION(11, 0, 9):
 840         case IP_VERSION(11, 0, 7):
 841         case IP_VERSION(13, 0, 2):
 842         case IP_VERSION(13, 0, 10):
 843                 return true;
 844         default:
 845                 return false;
 846         }
 847 }
 848
 849 static int psp_tmr_load(struct psp_context *psp)
 850 {
 851         int ret;
 852         struct psp_gfx_cmd_resp *cmd;
 853
 854         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 855          * Already set up by host driver.
 856          */
 857         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 858                 return 0;
 859
 860         cmd = acquire_psp_cmd_buf(psp);
 861
 862         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 863         if (psp->tmr_bo)
 864                 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 865                          amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 866
 867         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 868                                  psp->fence_buf_mc_addr);
 869
 870         release_psp_cmd_buf(psp);
 871
 872         return ret;
 873 }
 874
 875 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 876                                         struct psp_gfx_cmd_resp *cmd)
 877 {
 878         if (amdgpu_sriov_vf(psp->adev))
 879                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 880         else
 881                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 882 }
 883
 884 static int psp_tmr_unload(struct psp_context *psp)
 885 {
 886         int ret;
 887         struct psp_gfx_cmd_resp *cmd;
 888
 889         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 890          * as TMR is not loaded at all
 891          */
 892         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 893                 return 0;
 894
 895         cmd = acquire_psp_cmd_buf(psp);
 896
 897         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 898         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 899
 900         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 901                                  psp->fence_buf_mc_addr);
 902
 903         release_psp_cmd_buf(psp);
 904
 905         return ret;
 906 }
 907
 908 static int psp_tmr_terminate(struct psp_context *psp)
 909 {
 910         return psp_tmr_unload(psp);
 911 }
 912
 913 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 914                                         uint64_t *output_ptr)
 915 {
 916         int ret;
 917         struct psp_gfx_cmd_resp *cmd;
 918
 919         if (!output_ptr)
 920                 return -EINVAL;
 921
 922         if (amdgpu_sriov_vf(psp->adev))
 923                 return 0;
 924
 925         cmd = acquire_psp_cmd_buf(psp);
 926
 927         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 928
 929         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 930                                  psp->fence_buf_mc_addr);
 931
 932         if (!ret) {
 933                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 934                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 935         }
 936
 937         release_psp_cmd_buf(psp);
 938
 939         return ret;
 940 }
 941
 942 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 943 {
 944         struct psp_context *psp = &adev->psp;
 945         struct psp_gfx_cmd_resp *cmd;
 946         int ret;
 947
 948         if (amdgpu_sriov_vf(adev))
 949                 return 0;
 950
 951         cmd = acquire_psp_cmd_buf(psp);
 952
 953         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 954         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 955
 956         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 957         if (!ret) {
 958                 *boot_cfg =
 959                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 960         }
 961
 962         release_psp_cmd_buf(psp);
 963
 964         return ret;
 965 }
 966
 967 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 968 {
 969         int ret;
 970         struct psp_context *psp = &adev->psp;
 971         struct psp_gfx_cmd_resp *cmd;
 972
 973         if (amdgpu_sriov_vf(adev))
 974                 return 0;
 975
 976         cmd = acquire_psp_cmd_buf(psp);
 977
 978         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 979         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 980         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 981         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 982
 983         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 984
 985         release_psp_cmd_buf(psp);
 986
 987         return ret;
 988 }
 989
 990 static int psp_rl_load(struct amdgpu_device *adev)
 991 {
 992         int ret;
 993         struct psp_context *psp = &adev->psp;
 994         struct psp_gfx_cmd_resp *cmd;
 995
 996         if (!is_psp_fw_valid(psp->rl))
 997                 return 0;
 998
 999         cmd = acquire_psp_cmd_buf(psp);
1000
1001         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1002         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
1003
1004         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1005         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1006         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
1007         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
1008         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1009
1010         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1011
1012         release_psp_cmd_buf(psp);
1013
1014         return ret;
1015 }
1016
1017 int psp_spatial_partition(struct psp_context *psp, int mode)
1018 {
1019         struct psp_gfx_cmd_resp *cmd;
1020         int ret;
1021
1022         if (amdgpu_sriov_vf(psp->adev))
1023                 return 0;
1024
1025         cmd = acquire_psp_cmd_buf(psp);
1026
1027         cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1028         cmd->cmd.cmd_spatial_part.mode = mode;
1029
1030         dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1031         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1032
1033         release_psp_cmd_buf(psp);
1034
1035         return ret;
1036 }
1037
1038 static int psp_asd_initialize(struct psp_context *psp)
1039 {
1040         int ret;
1041
1042         /* If PSP version doesn't match ASD version, asd loading will be failed.
1043          * add workaround to bypass it for sriov now.
1044          * TODO: add version check to make it common
1045          */
1046         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1047                 return 0;
1048
1049         psp->asd_context.mem_context.shared_mc_addr  = 0;
1050         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1051         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
1052
1053         ret = psp_ta_load(psp, &psp->asd_context);
1054         if (!ret)
1055                 psp->asd_context.initialized = true;
1056
1057         return ret;
1058 }
1059
1060 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1061                                        uint32_t session_id)
1062 {
1063         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1064         cmd->cmd.cmd_unload_ta.session_id = session_id;
1065 }
1066
1067 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1068 {
1069         int ret;
1070         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1071
1072         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1073
1074         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1075
1076         context->resp_status = cmd->resp.status;
1077
1078         release_psp_cmd_buf(psp);
1079
1080         return ret;
1081 }
1082
1083 static int psp_asd_terminate(struct psp_context *psp)
1084 {
1085         int ret;
1086
1087         if (amdgpu_sriov_vf(psp->adev))
1088                 return 0;
1089
1090         if (!psp->asd_context.initialized)
1091                 return 0;
1092
1093         ret = psp_ta_unload(psp, &psp->asd_context);
1094         if (!ret)
1095                 psp->asd_context.initialized = false;
1096
1097         return ret;
1098 }
1099
1100 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1101                 uint32_t id, uint32_t value)
1102 {
1103         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1104         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1105         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1106 }
1107
1108 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1109                 uint32_t value)
1110 {
1111         struct psp_gfx_cmd_resp *cmd;
1112         int ret = 0;
1113
1114         if (reg >= PSP_REG_LAST)
1115                 return -EINVAL;
1116
1117         cmd = acquire_psp_cmd_buf(psp);
1118
1119         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1120         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1121         if (ret)
1122                 DRM_ERROR("PSP failed to program reg id %d", reg);
1123
1124         release_psp_cmd_buf(psp);
1125
1126         return ret;
1127 }
1128
1129 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1130                                      uint64_t ta_bin_mc,
1131                                      struct ta_context *context)
1132 {
1133         cmd->cmd_id                             = context->ta_load_type;
1134         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1135         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1136         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1137
1138         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1139                 lower_32_bits(context->mem_context.shared_mc_addr);
1140         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1141                 upper_32_bits(context->mem_context.shared_mc_addr);
1142         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1143 }
1144
1145 int psp_ta_init_shared_buf(struct psp_context *psp,
1146                                   struct ta_mem_context *mem_ctx)
1147 {
1148         /*
1149         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1150         * physical) for ta to host memory
1151         */
1152         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1153                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1154                                       AMDGPU_GEM_DOMAIN_GTT,
1155                                       &mem_ctx->shared_bo,
1156                                       &mem_ctx->shared_mc_addr,
1157                                       &mem_ctx->shared_buf);
1158 }
1159
1160 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1161                                        uint32_t ta_cmd_id,
1162                                        uint32_t session_id)
1163 {
1164         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1165         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1166         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1167 }
1168
1169 int psp_ta_invoke(struct psp_context *psp,
1170                   uint32_t ta_cmd_id,
1171                   struct ta_context *context)
1172 {
1173         int ret;
1174         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1175
1176         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1177
1178         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1179                                  psp->fence_buf_mc_addr);
1180
1181         context->resp_status = cmd->resp.status;
1182
1183         release_psp_cmd_buf(psp);
1184
1185         return ret;
1186 }
1187
1188 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1189 {
1190         int ret;
1191         struct psp_gfx_cmd_resp *cmd;
1192
1193         cmd = acquire_psp_cmd_buf(psp);
1194
1195         psp_copy_fw(psp, context->bin_desc.start_addr,
1196                     context->bin_desc.size_bytes);
1197
1198         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1199
1200         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1201                                  psp->fence_buf_mc_addr);
1202
1203         context->resp_status = cmd->resp.status;
1204
1205         if (!ret)
1206                 context->session_id = cmd->resp.session_id;
1207
1208         release_psp_cmd_buf(psp);
1209
1210         return ret;
1211 }
1212
1213 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1214 {
1215         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1216 }
1217
1218 int psp_xgmi_terminate(struct psp_context *psp)
1219 {
1220         int ret;
1221         struct amdgpu_device *adev = psp->adev;
1222
1223         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1224         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1225             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1226              adev->gmc.xgmi.connected_to_cpu))
1227                 return 0;
1228
1229         if (!psp->xgmi_context.context.initialized)
1230                 return 0;
1231
1232         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1233
1234         psp->xgmi_context.context.initialized = false;
1235
1236         return ret;
1237 }
1238
1239 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1240 {
1241         struct ta_xgmi_shared_memory *xgmi_cmd;
1242         int ret;
1243
1244         if (!psp->ta_fw ||
1245             !psp->xgmi_context.context.bin_desc.size_bytes ||
1246             !psp->xgmi_context.context.bin_desc.start_addr)
1247                 return -ENOENT;
1248
1249         if (!load_ta)
1250                 goto invoke;
1251
1252         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1253         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1254
1255         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1256                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1257                 if (ret)
1258                         return ret;
1259         }
1260
1261         /* Load XGMI TA */
1262         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1263         if (!ret)
1264                 psp->xgmi_context.context.initialized = true;
1265         else
1266                 return ret;
1267
1268 invoke:
1269         /* Initialize XGMI session */
1270         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1271         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1272         xgmi_cmd->flag_extend_link_record = set_extended_data;
1273         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1274
1275         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1276
1277         return ret;
1278 }
1279
1280 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1281 {
1282         struct ta_xgmi_shared_memory *xgmi_cmd;
1283         int ret;
1284
1285         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1286         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1287
1288         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1289
1290         /* Invoke xgmi ta to get hive id */
1291         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1292         if (ret)
1293                 return ret;
1294
1295         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1296
1297         return 0;
1298 }
1299
1300 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1301 {
1302         struct ta_xgmi_shared_memory *xgmi_cmd;
1303         int ret;
1304
1305         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1306         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1307
1308         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1309
1310         /* Invoke xgmi ta to get the node id */
1311         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1312         if (ret)
1313                 return ret;
1314
1315         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1316
1317         return 0;
1318 }
1319
1320 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1321 {
1322         return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1323                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1324                 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1325 }
1326
1327 /*
1328  * Chips that support extended topology information require the driver to
1329  * reflect topology information in the opposite direction.  This is
1330  * because the TA has already exceeded its link record limit and if the
1331  * TA holds bi-directional information, the driver would have to do
1332  * multiple fetches instead of just two.
1333  */
1334 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1335                                         struct psp_xgmi_node_info node_info)
1336 {
1337         struct amdgpu_device *mirror_adev;
1338         struct amdgpu_hive_info *hive;
1339         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1340         uint64_t dst_node_id = node_info.node_id;
1341         uint8_t dst_num_hops = node_info.num_hops;
1342         uint8_t dst_num_links = node_info.num_links;
1343
1344         hive = amdgpu_get_xgmi_hive(psp->adev);
1345         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1346                 struct psp_xgmi_topology_info *mirror_top_info;
1347                 int j;
1348
1349                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1350                         continue;
1351
1352                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1353                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1354                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1355                                 continue;
1356
1357                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1358                         /*
1359                          * prevent 0 num_links value re-reflection since reflection
1360                          * criteria is based on num_hops (direct or indirect).
1361                          *
1362                          */
1363                         if (dst_num_links)
1364                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1365
1366                         break;
1367                 }
1368
1369                 break;
1370         }
1371
1372         amdgpu_put_xgmi_hive(hive);
1373 }
1374
1375 int psp_xgmi_get_topology_info(struct psp_context *psp,
1376                                int number_devices,
1377                                struct psp_xgmi_topology_info *topology,
1378                                bool get_extended_data)
1379 {
1380         struct ta_xgmi_shared_memory *xgmi_cmd;
1381         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1382         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1383         int i;
1384         int ret;
1385
1386         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1387                 return -EINVAL;
1388
1389         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1390         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1391         xgmi_cmd->flag_extend_link_record = get_extended_data;
1392
1393         /* Fill in the shared memory with topology information as input */
1394         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1395         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1396         topology_info_input->num_nodes = number_devices;
1397
1398         for (i = 0; i < topology_info_input->num_nodes; i++) {
1399                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1400                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1401                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1402                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1403         }
1404
1405         /* Invoke xgmi ta to get the topology information */
1406         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1407         if (ret)
1408                 return ret;
1409
1410         /* Read the output topology information from the shared memory */
1411         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1412         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1413         for (i = 0; i < topology->num_nodes; i++) {
1414                 /* extended data will either be 0 or equal to non-extended data */
1415                 if (topology_info_output->nodes[i].num_hops)
1416                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1417
1418                 /* non-extended data gets everything here so no need to update */
1419                 if (!get_extended_data) {
1420                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1421                         topology->nodes[i].is_sharing_enabled =
1422                                         topology_info_output->nodes[i].is_sharing_enabled;
1423                         topology->nodes[i].sdma_engine =
1424                                         topology_info_output->nodes[i].sdma_engine;
1425                 }
1426
1427         }
1428
1429         /* Invoke xgmi ta again to get the link information */
1430         if (psp_xgmi_peer_link_info_supported(psp)) {
1431                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1432                 bool requires_reflection =
1433                         (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1434                                 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1435
1436                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1437
1438                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1439
1440                 if (ret)
1441                         return ret;
1442
1443                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1444                 for (i = 0; i < topology->num_nodes; i++) {
1445                         /* accumulate num_links on extended data */
1446                         topology->nodes[i].num_links = get_extended_data ?
1447                                         topology->nodes[i].num_links +
1448                                                         link_info_output->nodes[i].num_links :
1449                                         ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1450                                          link_info_output->nodes[i].num_links);
1451
1452                         /* reflect the topology information for bi-directionality */
1453                         if (requires_reflection && topology->nodes[i].num_hops)
1454                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1455                 }
1456         }
1457
1458         return 0;
1459 }
1460
1461 int psp_xgmi_set_topology_info(struct psp_context *psp,
1462                                int number_devices,
1463                                struct psp_xgmi_topology_info *topology)
1464 {
1465         struct ta_xgmi_shared_memory *xgmi_cmd;
1466         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1467         int i;
1468
1469         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1470                 return -EINVAL;
1471
1472         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1473         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1474
1475         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1476         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1477         topology_info_input->num_nodes = number_devices;
1478
1479         for (i = 0; i < topology_info_input->num_nodes; i++) {
1480                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1481                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1482                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1483                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1484         }
1485
1486         /* Invoke xgmi ta to set topology information */
1487         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1488 }
1489
1490 // ras begin
1491 static void psp_ras_ta_check_status(struct psp_context *psp)
1492 {
1493         struct ta_ras_shared_memory *ras_cmd =
1494                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1495
1496         switch (ras_cmd->ras_status) {
1497         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1498                 dev_warn(psp->adev->dev,
1499                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1500                 break;
1501         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1502                 dev_warn(psp->adev->dev,
1503                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1504                 break;
1505         case TA_RAS_STATUS__SUCCESS:
1506                 break;
1507         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1508                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1509                         dev_warn(psp->adev->dev,
1510                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1511                 break;
1512         default:
1513                 dev_warn(psp->adev->dev,
1514                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1515                 break;
1516         }
1517 }
1518
1519 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1520 {
1521         struct ta_ras_shared_memory *ras_cmd;
1522         int ret;
1523
1524         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1525
1526         /*
1527          * TODO: bypass the loading in sriov for now
1528          */
1529         if (amdgpu_sriov_vf(psp->adev))
1530                 return 0;
1531
1532         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1533
1534         if (amdgpu_ras_intr_triggered())
1535                 return ret;
1536
1537         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1538                 DRM_WARN("RAS: Unsupported Interface");
1539                 return -EINVAL;
1540         }
1541
1542         if (!ret) {
1543                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1544                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1545
1546                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1547                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1548                         dev_warn(psp->adev->dev,
1549                                  "RAS internal register access blocked\n");
1550
1551                 psp_ras_ta_check_status(psp);
1552         }
1553
1554         return ret;
1555 }
1556
1557 int psp_ras_enable_features(struct psp_context *psp,
1558                 union ta_ras_cmd_input *info, bool enable)
1559 {
1560         struct ta_ras_shared_memory *ras_cmd;
1561         int ret;
1562
1563         if (!psp->ras_context.context.initialized)
1564                 return -EINVAL;
1565
1566         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1567         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1568
1569         if (enable)
1570                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1571         else
1572                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1573
1574         ras_cmd->ras_in_message = *info;
1575
1576         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1577         if (ret)
1578                 return -EINVAL;
1579
1580         return 0;
1581 }
1582
1583 int psp_ras_terminate(struct psp_context *psp)
1584 {
1585         int ret;
1586
1587         /*
1588          * TODO: bypass the terminate in sriov for now
1589          */
1590         if (amdgpu_sriov_vf(psp->adev))
1591                 return 0;
1592
1593         if (!psp->ras_context.context.initialized)
1594                 return 0;
1595
1596         ret = psp_ta_unload(psp, &psp->ras_context.context);
1597
1598         psp->ras_context.context.initialized = false;
1599
1600         return ret;
1601 }
1602
1603 int psp_ras_initialize(struct psp_context *psp)
1604 {
1605         int ret;
1606         uint32_t boot_cfg = 0xFF;
1607         struct amdgpu_device *adev = psp->adev;
1608         struct ta_ras_shared_memory *ras_cmd;
1609
1610         /*
1611          * TODO: bypass the initialize in sriov for now
1612          */
1613         if (amdgpu_sriov_vf(adev))
1614                 return 0;
1615
1616         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1617             !adev->psp.ras_context.context.bin_desc.start_addr) {
1618                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1619                 return 0;
1620         }
1621
1622         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1623                 /* query GECC enablement status from boot config
1624                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1625                  */
1626                 ret = psp_boot_config_get(adev, &boot_cfg);
1627                 if (ret)
1628                         dev_warn(adev->dev, "PSP get boot config failed\n");
1629
1630                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1631                         if (!boot_cfg) {
1632                                 dev_info(adev->dev, "GECC is disabled\n");
1633                         } else {
1634                                 /* disable GECC in next boot cycle if ras is
1635                                  * disabled by module parameter amdgpu_ras_enable
1636                                  * and/or amdgpu_ras_mask, or boot_config_get call
1637                                  * is failed
1638                                  */
1639                                 ret = psp_boot_config_set(adev, 0);
1640                                 if (ret)
1641                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1642                                 else
1643                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1644                         }
1645                 } else {
1646                         if (boot_cfg == 1) {
1647                                 dev_info(adev->dev, "GECC is enabled\n");
1648                         } else {
1649                                 /* enable GECC in next boot cycle if it is disabled
1650                                  * in boot config, or force enable GECC if failed to
1651                                  * get boot configuration
1652                                  */
1653                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1654                                 if (ret)
1655                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1656                                 else
1657                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1658                         }
1659                 }
1660         }
1661
1662         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1663         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1664
1665         if (!psp->ras_context.context.mem_context.shared_buf) {
1666                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1667                 if (ret)
1668                         return ret;
1669         }
1670
1671         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1672         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1673
1674         if (amdgpu_ras_is_poison_mode_supported(adev))
1675                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1676         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1677                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1678         ras_cmd->ras_in_message.init_flags.xcc_mask =
1679                 adev->gfx.xcc_mask;
1680         ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1681
1682         ret = psp_ta_load(psp, &psp->ras_context.context);
1683
1684         if (!ret && !ras_cmd->ras_status)
1685                 psp->ras_context.context.initialized = true;
1686         else {
1687                 if (ras_cmd->ras_status)
1688                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1689
1690                 /* fail to load RAS TA */
1691                 psp->ras_context.context.initialized = false;
1692         }
1693
1694         return ret;
1695 }
1696
1697 int psp_ras_trigger_error(struct psp_context *psp,
1698                           struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1699 {
1700         struct ta_ras_shared_memory *ras_cmd;
1701         struct amdgpu_device *adev = psp->adev;
1702         int ret;
1703         uint32_t dev_mask;
1704
1705         if (!psp->ras_context.context.initialized)
1706                 return -EINVAL;
1707
1708         switch (info->block_id) {
1709         case TA_RAS_BLOCK__GFX:
1710                 dev_mask = GET_MASK(GC, instance_mask);
1711                 break;
1712         case TA_RAS_BLOCK__SDMA:
1713                 dev_mask = GET_MASK(SDMA0, instance_mask);
1714                 break;
1715         case TA_RAS_BLOCK__VCN:
1716         case TA_RAS_BLOCK__JPEG:
1717                 dev_mask = GET_MASK(VCN, instance_mask);
1718                 break;
1719         default:
1720                 dev_mask = instance_mask;
1721                 break;
1722         }
1723
1724         /* reuse sub_block_index for backward compatibility */
1725         dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1726         dev_mask &= AMDGPU_RAS_INST_MASK;
1727         info->sub_block_index |= dev_mask;
1728
1729         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1730         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1731
1732         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1733         ras_cmd->ras_in_message.trigger_error = *info;
1734
1735         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1736         if (ret)
1737                 return -EINVAL;
1738
1739         /* If err_event_athub occurs error inject was successful, however
1740            return status from TA is no long reliable */
1741         if (amdgpu_ras_intr_triggered())
1742                 return 0;
1743
1744         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1745                 return -EACCES;
1746         else if (ras_cmd->ras_status)
1747                 return -EINVAL;
1748
1749         return 0;
1750 }
1751 // ras end
1752
1753 // HDCP start
1754 static int psp_hdcp_initialize(struct psp_context *psp)
1755 {
1756         int ret;
1757
1758         /*
1759          * TODO: bypass the initialize in sriov for now
1760          */
1761         if (amdgpu_sriov_vf(psp->adev))
1762                 return 0;
1763
1764         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1765             !psp->hdcp_context.context.bin_desc.start_addr) {
1766                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1767                 return 0;
1768         }
1769
1770         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1771         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1772
1773         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1774                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1775                 if (ret)
1776                         return ret;
1777         }
1778
1779         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1780         if (!ret) {
1781                 psp->hdcp_context.context.initialized = true;
1782                 mutex_init(&psp->hdcp_context.mutex);
1783         }
1784
1785         return ret;
1786 }
1787
1788 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1789 {
1790         /*
1791          * TODO: bypass the loading in sriov for now
1792          */
1793         if (amdgpu_sriov_vf(psp->adev))
1794                 return 0;
1795
1796         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1797 }
1798
1799 static int psp_hdcp_terminate(struct psp_context *psp)
1800 {
1801         int ret;
1802
1803         /*
1804          * TODO: bypass the terminate in sriov for now
1805          */
1806         if (amdgpu_sriov_vf(psp->adev))
1807                 return 0;
1808
1809         if (!psp->hdcp_context.context.initialized)
1810                 return 0;
1811
1812         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1813
1814         psp->hdcp_context.context.initialized = false;
1815
1816         return ret;
1817 }
1818 // HDCP end
1819
1820 // DTM start
1821 static int psp_dtm_initialize(struct psp_context *psp)
1822 {
1823         int ret;
1824
1825         /*
1826          * TODO: bypass the initialize in sriov for now
1827          */
1828         if (amdgpu_sriov_vf(psp->adev))
1829                 return 0;
1830
1831         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1832             !psp->dtm_context.context.bin_desc.start_addr) {
1833                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1834                 return 0;
1835         }
1836
1837         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1838         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1839
1840         if (!psp->dtm_context.context.mem_context.shared_buf) {
1841                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1842                 if (ret)
1843                         return ret;
1844         }
1845
1846         ret = psp_ta_load(psp, &psp->dtm_context.context);
1847         if (!ret) {
1848                 psp->dtm_context.context.initialized = true;
1849                 mutex_init(&psp->dtm_context.mutex);
1850         }
1851
1852         return ret;
1853 }
1854
1855 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1856 {
1857         /*
1858          * TODO: bypass the loading in sriov for now
1859          */
1860         if (amdgpu_sriov_vf(psp->adev))
1861                 return 0;
1862
1863         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1864 }
1865
1866 static int psp_dtm_terminate(struct psp_context *psp)
1867 {
1868         int ret;
1869
1870         /*
1871          * TODO: bypass the terminate in sriov for now
1872          */
1873         if (amdgpu_sriov_vf(psp->adev))
1874                 return 0;
1875
1876         if (!psp->dtm_context.context.initialized)
1877                 return 0;
1878
1879         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1880
1881         psp->dtm_context.context.initialized = false;
1882
1883         return ret;
1884 }
1885 // DTM end
1886
1887 // RAP start
1888 static int psp_rap_initialize(struct psp_context *psp)
1889 {
1890         int ret;
1891         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1892
1893         /*
1894          * TODO: bypass the initialize in sriov for now
1895          */
1896         if (amdgpu_sriov_vf(psp->adev))
1897                 return 0;
1898
1899         if (!psp->rap_context.context.bin_desc.size_bytes ||
1900             !psp->rap_context.context.bin_desc.start_addr) {
1901                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1902                 return 0;
1903         }
1904
1905         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1906         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1907
1908         if (!psp->rap_context.context.mem_context.shared_buf) {
1909                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1910                 if (ret)
1911                         return ret;
1912         }
1913
1914         ret = psp_ta_load(psp, &psp->rap_context.context);
1915         if (!ret) {
1916                 psp->rap_context.context.initialized = true;
1917                 mutex_init(&psp->rap_context.mutex);
1918         } else
1919                 return ret;
1920
1921         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1922         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1923                 psp_rap_terminate(psp);
1924                 /* free rap shared memory */
1925                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1926
1927                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1928                          ret, status);
1929
1930                 return ret;
1931         }
1932
1933         return 0;
1934 }
1935
1936 static int psp_rap_terminate(struct psp_context *psp)
1937 {
1938         int ret;
1939
1940         if (!psp->rap_context.context.initialized)
1941                 return 0;
1942
1943         ret = psp_ta_unload(psp, &psp->rap_context.context);
1944
1945         psp->rap_context.context.initialized = false;
1946
1947         return ret;
1948 }
1949
1950 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1951 {
1952         struct ta_rap_shared_memory *rap_cmd;
1953         int ret = 0;
1954
1955         if (!psp->rap_context.context.initialized)
1956                 return 0;
1957
1958         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1959             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1960                 return -EINVAL;
1961
1962         mutex_lock(&psp->rap_context.mutex);
1963
1964         rap_cmd = (struct ta_rap_shared_memory *)
1965                   psp->rap_context.context.mem_context.shared_buf;
1966         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1967
1968         rap_cmd->cmd_id = ta_cmd_id;
1969         rap_cmd->validation_method_id = METHOD_A;
1970
1971         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1972         if (ret)
1973                 goto out_unlock;
1974
1975         if (status)
1976                 *status = rap_cmd->rap_status;
1977
1978 out_unlock:
1979         mutex_unlock(&psp->rap_context.mutex);
1980
1981         return ret;
1982 }
1983 // RAP end
1984
1985 /* securedisplay start */
1986 static int psp_securedisplay_initialize(struct psp_context *psp)
1987 {
1988         int ret;
1989         struct ta_securedisplay_cmd *securedisplay_cmd;
1990
1991         /*
1992          * TODO: bypass the initialize in sriov for now
1993          */
1994         if (amdgpu_sriov_vf(psp->adev))
1995                 return 0;
1996
1997         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1998             !psp->securedisplay_context.context.bin_desc.start_addr) {
1999                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2000                 return 0;
2001         }
2002
2003         psp->securedisplay_context.context.mem_context.shared_mem_size =
2004                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
2005         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
2006
2007         if (!psp->securedisplay_context.context.initialized) {
2008                 ret = psp_ta_init_shared_buf(psp,
2009                                              &psp->securedisplay_context.context.mem_context);
2010                 if (ret)
2011                         return ret;
2012         }
2013
2014         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2015         if (!ret) {
2016                 psp->securedisplay_context.context.initialized = true;
2017                 mutex_init(&psp->securedisplay_context.mutex);
2018         } else
2019                 return ret;
2020
2021         mutex_lock(&psp->securedisplay_context.mutex);
2022
2023         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2024                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2025
2026         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2027
2028         mutex_unlock(&psp->securedisplay_context.mutex);
2029
2030         if (ret) {
2031                 psp_securedisplay_terminate(psp);
2032                 /* free securedisplay shared memory */
2033                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2034                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2035                 return -EINVAL;
2036         }
2037
2038         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2039                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2040                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2041                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int psp_securedisplay_terminate(struct psp_context *psp)
2048 {
2049         int ret;
2050
2051         /*
2052          * TODO:bypass the terminate in sriov for now
2053          */
2054         if (amdgpu_sriov_vf(psp->adev))
2055                 return 0;
2056
2057         if (!psp->securedisplay_context.context.initialized)
2058                 return 0;
2059
2060         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2061
2062         psp->securedisplay_context.context.initialized = false;
2063
2064         return ret;
2065 }
2066
2067 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2068 {
2069         int ret;
2070
2071         if (!psp->securedisplay_context.context.initialized)
2072                 return -EINVAL;
2073
2074         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2075             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2076                 return -EINVAL;
2077
2078         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2079
2080         return ret;
2081 }
2082 /* SECUREDISPLAY end */
2083
2084 static int psp_hw_start(struct psp_context *psp)
2085 {
2086         struct amdgpu_device *adev = psp->adev;
2087         int ret;
2088
2089         if (!amdgpu_sriov_vf(adev)) {
2090                 if ((is_psp_fw_valid(psp->kdb)) &&
2091                     (psp->funcs->bootloader_load_kdb != NULL)) {
2092                         ret = psp_bootloader_load_kdb(psp);
2093                         if (ret) {
2094                                 DRM_ERROR("PSP load kdb failed!\n");
2095                                 return ret;
2096                         }
2097                 }
2098
2099                 if ((is_psp_fw_valid(psp->spl)) &&
2100                     (psp->funcs->bootloader_load_spl != NULL)) {
2101                         ret = psp_bootloader_load_spl(psp);
2102                         if (ret) {
2103                                 DRM_ERROR("PSP load spl failed!\n");
2104                                 return ret;
2105                         }
2106                 }
2107
2108                 if ((is_psp_fw_valid(psp->sys)) &&
2109                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2110                         ret = psp_bootloader_load_sysdrv(psp);
2111                         if (ret) {
2112                                 DRM_ERROR("PSP load sys drv failed!\n");
2113                                 return ret;
2114                         }
2115                 }
2116
2117                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2118                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2119                         ret = psp_bootloader_load_soc_drv(psp);
2120                         if (ret) {
2121                                 DRM_ERROR("PSP load soc drv failed!\n");
2122                                 return ret;
2123                         }
2124                 }
2125
2126                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2127                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2128                         ret = psp_bootloader_load_intf_drv(psp);
2129                         if (ret) {
2130                                 DRM_ERROR("PSP load intf drv failed!\n");
2131                                 return ret;
2132                         }
2133                 }
2134
2135                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2136                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2137                         ret = psp_bootloader_load_dbg_drv(psp);
2138                         if (ret) {
2139                                 DRM_ERROR("PSP load dbg drv failed!\n");
2140                                 return ret;
2141                         }
2142                 }
2143
2144                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2145                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2146                         ret = psp_bootloader_load_ras_drv(psp);
2147                         if (ret) {
2148                                 DRM_ERROR("PSP load ras_drv failed!\n");
2149                                 return ret;
2150                         }
2151                 }
2152
2153                 if ((is_psp_fw_valid(psp->sos)) &&
2154                     (psp->funcs->bootloader_load_sos != NULL)) {
2155                         ret = psp_bootloader_load_sos(psp);
2156                         if (ret) {
2157                                 DRM_ERROR("PSP load sos failed!\n");
2158                                 return ret;
2159                         }
2160                 }
2161         }
2162
2163         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2164         if (ret) {
2165                 DRM_ERROR("PSP create ring failed!\n");
2166                 return ret;
2167         }
2168
2169         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2170                 goto skip_pin_bo;
2171
2172         if (!psp_boottime_tmr(psp)) {
2173                 ret = psp_tmr_init(psp);
2174                 if (ret) {
2175                         DRM_ERROR("PSP tmr init failed!\n");
2176                         return ret;
2177                 }
2178         }
2179
2180 skip_pin_bo:
2181         /*
2182          * For ASICs with DF Cstate management centralized
2183          * to PMFW, TMR setup should be performed after PMFW
2184          * loaded and before other non-psp firmware loaded.
2185          */
2186         if (psp->pmfw_centralized_cstate_management) {
2187                 ret = psp_load_smu_fw(psp);
2188                 if (ret)
2189                         return ret;
2190         }
2191
2192         ret = psp_tmr_load(psp);
2193         if (ret) {
2194                 DRM_ERROR("PSP load tmr failed!\n");
2195                 return ret;
2196         }
2197
2198         return 0;
2199 }
2200
2201 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2202                            enum psp_gfx_fw_type *type)
2203 {
2204         switch (ucode->ucode_id) {
2205         case AMDGPU_UCODE_ID_CAP:
2206                 *type = GFX_FW_TYPE_CAP;
2207                 break;
2208         case AMDGPU_UCODE_ID_SDMA0:
2209                 *type = GFX_FW_TYPE_SDMA0;
2210                 break;
2211         case AMDGPU_UCODE_ID_SDMA1:
2212                 *type = GFX_FW_TYPE_SDMA1;
2213                 break;
2214         case AMDGPU_UCODE_ID_SDMA2:
2215                 *type = GFX_FW_TYPE_SDMA2;
2216                 break;
2217         case AMDGPU_UCODE_ID_SDMA3:
2218                 *type = GFX_FW_TYPE_SDMA3;
2219                 break;
2220         case AMDGPU_UCODE_ID_SDMA4:
2221                 *type = GFX_FW_TYPE_SDMA4;
2222                 break;
2223         case AMDGPU_UCODE_ID_SDMA5:
2224                 *type = GFX_FW_TYPE_SDMA5;
2225                 break;
2226         case AMDGPU_UCODE_ID_SDMA6:
2227                 *type = GFX_FW_TYPE_SDMA6;
2228                 break;
2229         case AMDGPU_UCODE_ID_SDMA7:
2230                 *type = GFX_FW_TYPE_SDMA7;
2231                 break;
2232         case AMDGPU_UCODE_ID_CP_MES:
2233                 *type = GFX_FW_TYPE_CP_MES;
2234                 break;
2235         case AMDGPU_UCODE_ID_CP_MES_DATA:
2236                 *type = GFX_FW_TYPE_MES_STACK;
2237                 break;
2238         case AMDGPU_UCODE_ID_CP_MES1:
2239                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2240                 break;
2241         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2242                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2243                 break;
2244         case AMDGPU_UCODE_ID_CP_CE:
2245                 *type = GFX_FW_TYPE_CP_CE;
2246                 break;
2247         case AMDGPU_UCODE_ID_CP_PFP:
2248                 *type = GFX_FW_TYPE_CP_PFP;
2249                 break;
2250         case AMDGPU_UCODE_ID_CP_ME:
2251                 *type = GFX_FW_TYPE_CP_ME;
2252                 break;
2253         case AMDGPU_UCODE_ID_CP_MEC1:
2254                 *type = GFX_FW_TYPE_CP_MEC;
2255                 break;
2256         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2257                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2258                 break;
2259         case AMDGPU_UCODE_ID_CP_MEC2:
2260                 *type = GFX_FW_TYPE_CP_MEC;
2261                 break;
2262         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2263                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2264                 break;
2265         case AMDGPU_UCODE_ID_RLC_P:
2266                 *type = GFX_FW_TYPE_RLC_P;
2267                 break;
2268         case AMDGPU_UCODE_ID_RLC_V:
2269                 *type = GFX_FW_TYPE_RLC_V;
2270                 break;
2271         case AMDGPU_UCODE_ID_RLC_G:
2272                 *type = GFX_FW_TYPE_RLC_G;
2273                 break;
2274         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2275                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2276                 break;
2277         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2278                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2279                 break;
2280         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2281                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2282                 break;
2283         case AMDGPU_UCODE_ID_RLC_IRAM:
2284                 *type = GFX_FW_TYPE_RLC_IRAM;
2285                 break;
2286         case AMDGPU_UCODE_ID_RLC_DRAM:
2287                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2288                 break;
2289         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2290                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2291                 break;
2292         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2293                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2294                 break;
2295         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2296                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2297                 break;
2298         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2299                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2300                 break;
2301         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2302                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2303                 break;
2304         case AMDGPU_UCODE_ID_SMC:
2305                 *type = GFX_FW_TYPE_SMU;
2306                 break;
2307         case AMDGPU_UCODE_ID_PPTABLE:
2308                 *type = GFX_FW_TYPE_PPTABLE;
2309                 break;
2310         case AMDGPU_UCODE_ID_UVD:
2311                 *type = GFX_FW_TYPE_UVD;
2312                 break;
2313         case AMDGPU_UCODE_ID_UVD1:
2314                 *type = GFX_FW_TYPE_UVD1;
2315                 break;
2316         case AMDGPU_UCODE_ID_VCE:
2317                 *type = GFX_FW_TYPE_VCE;
2318                 break;
2319         case AMDGPU_UCODE_ID_VCN:
2320                 *type = GFX_FW_TYPE_VCN;
2321                 break;
2322         case AMDGPU_UCODE_ID_VCN1:
2323                 *type = GFX_FW_TYPE_VCN1;
2324                 break;
2325         case AMDGPU_UCODE_ID_DMCU_ERAM:
2326                 *type = GFX_FW_TYPE_DMCU_ERAM;
2327                 break;
2328         case AMDGPU_UCODE_ID_DMCU_INTV:
2329                 *type = GFX_FW_TYPE_DMCU_ISR;
2330                 break;
2331         case AMDGPU_UCODE_ID_VCN0_RAM:
2332                 *type = GFX_FW_TYPE_VCN0_RAM;
2333                 break;
2334         case AMDGPU_UCODE_ID_VCN1_RAM:
2335                 *type = GFX_FW_TYPE_VCN1_RAM;
2336                 break;
2337         case AMDGPU_UCODE_ID_DMCUB:
2338                 *type = GFX_FW_TYPE_DMUB;
2339                 break;
2340         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2341                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2342                 break;
2343         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2344                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2345                 break;
2346         case AMDGPU_UCODE_ID_IMU_I:
2347                 *type = GFX_FW_TYPE_IMU_I;
2348                 break;
2349         case AMDGPU_UCODE_ID_IMU_D:
2350                 *type = GFX_FW_TYPE_IMU_D;
2351                 break;
2352         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2353                 *type = GFX_FW_TYPE_RS64_PFP;
2354                 break;
2355         case AMDGPU_UCODE_ID_CP_RS64_ME:
2356                 *type = GFX_FW_TYPE_RS64_ME;
2357                 break;
2358         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2359                 *type = GFX_FW_TYPE_RS64_MEC;
2360                 break;
2361         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2362                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2363                 break;
2364         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2365                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2366                 break;
2367         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2368                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2369                 break;
2370         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2371                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2372                 break;
2373         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2374                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2375                 break;
2376         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2377                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2378                 break;
2379         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2380                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2381                 break;
2382         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2383                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2384                 break;
2385         case AMDGPU_UCODE_ID_MAXIMUM:
2386         default:
2387                 return -EINVAL;
2388         }
2389
2390         return 0;
2391 }
2392
2393 static void psp_print_fw_hdr(struct psp_context *psp,
2394                              struct amdgpu_firmware_info *ucode)
2395 {
2396         struct amdgpu_device *adev = psp->adev;
2397         struct common_firmware_header *hdr;
2398
2399         switch (ucode->ucode_id) {
2400         case AMDGPU_UCODE_ID_SDMA0:
2401         case AMDGPU_UCODE_ID_SDMA1:
2402         case AMDGPU_UCODE_ID_SDMA2:
2403         case AMDGPU_UCODE_ID_SDMA3:
2404         case AMDGPU_UCODE_ID_SDMA4:
2405         case AMDGPU_UCODE_ID_SDMA5:
2406         case AMDGPU_UCODE_ID_SDMA6:
2407         case AMDGPU_UCODE_ID_SDMA7:
2408                 hdr = (struct common_firmware_header *)
2409                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2410                 amdgpu_ucode_print_sdma_hdr(hdr);
2411                 break;
2412         case AMDGPU_UCODE_ID_CP_CE:
2413                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2414                 amdgpu_ucode_print_gfx_hdr(hdr);
2415                 break;
2416         case AMDGPU_UCODE_ID_CP_PFP:
2417                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2418                 amdgpu_ucode_print_gfx_hdr(hdr);
2419                 break;
2420         case AMDGPU_UCODE_ID_CP_ME:
2421                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2422                 amdgpu_ucode_print_gfx_hdr(hdr);
2423                 break;
2424         case AMDGPU_UCODE_ID_CP_MEC1:
2425                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2426                 amdgpu_ucode_print_gfx_hdr(hdr);
2427                 break;
2428         case AMDGPU_UCODE_ID_RLC_G:
2429                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2430                 amdgpu_ucode_print_rlc_hdr(hdr);
2431                 break;
2432         case AMDGPU_UCODE_ID_SMC:
2433                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2434                 amdgpu_ucode_print_smc_hdr(hdr);
2435                 break;
2436         default:
2437                 break;
2438         }
2439 }
2440
2441 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2442                                        struct psp_gfx_cmd_resp *cmd)
2443 {
2444         int ret;
2445         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2446
2447         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2448         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2449         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2450         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2451
2452         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2453         if (ret)
2454                 DRM_ERROR("Unknown firmware type\n");
2455
2456         return ret;
2457 }
2458
2459 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2460                                   struct amdgpu_firmware_info *ucode)
2461 {
2462         int ret = 0;
2463         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2464
2465         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2466         if (!ret) {
2467                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2468                                          psp->fence_buf_mc_addr);
2469         }
2470
2471         release_psp_cmd_buf(psp);
2472
2473         return ret;
2474 }
2475
2476 static int psp_load_smu_fw(struct psp_context *psp)
2477 {
2478         int ret;
2479         struct amdgpu_device *adev = psp->adev;
2480         struct amdgpu_firmware_info *ucode =
2481                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2482         struct amdgpu_ras *ras = psp->ras_context.ras;
2483
2484         /*
2485          * Skip SMU FW reloading in case of using BACO for runpm only,
2486          * as SMU is always alive.
2487          */
2488         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2489                 return 0;
2490
2491         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2492                 return 0;
2493
2494         if ((amdgpu_in_reset(adev) &&
2495              ras && adev->ras_enabled &&
2496              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2497               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2498                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2499                 if (ret)
2500                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2501         }
2502
2503         ret = psp_execute_non_psp_fw_load(psp, ucode);
2504
2505         if (ret)
2506                 DRM_ERROR("PSP load smu failed!\n");
2507
2508         return ret;
2509 }
2510
2511 static bool fw_load_skip_check(struct psp_context *psp,
2512                                struct amdgpu_firmware_info *ucode)
2513 {
2514         if (!ucode->fw || !ucode->ucode_size)
2515                 return true;
2516
2517         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2518             (psp_smu_reload_quirk(psp) ||
2519              psp->autoload_supported ||
2520              psp->pmfw_centralized_cstate_management))
2521                 return true;
2522
2523         if (amdgpu_sriov_vf(psp->adev) &&
2524             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2525                 return true;
2526
2527         if (psp->autoload_supported &&
2528             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2529              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2530                 /* skip mec JT when autoload is enabled */
2531                 return true;
2532
2533         return false;
2534 }
2535
2536 int psp_load_fw_list(struct psp_context *psp,
2537                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2538 {
2539         int ret = 0, i;
2540         struct amdgpu_firmware_info *ucode;
2541
2542         for (i = 0; i < ucode_count; ++i) {
2543                 ucode = ucode_list[i];
2544                 psp_print_fw_hdr(psp, ucode);
2545                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2546                 if (ret)
2547                         return ret;
2548         }
2549         return ret;
2550 }
2551
2552 static int psp_load_non_psp_fw(struct psp_context *psp)
2553 {
2554         int i, ret;
2555         struct amdgpu_firmware_info *ucode;
2556         struct amdgpu_device *adev = psp->adev;
2557
2558         if (psp->autoload_supported &&
2559             !psp->pmfw_centralized_cstate_management) {
2560                 ret = psp_load_smu_fw(psp);
2561                 if (ret)
2562                         return ret;
2563         }
2564
2565         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2566                 ucode = &adev->firmware.ucode[i];
2567
2568                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2569                     !fw_load_skip_check(psp, ucode)) {
2570                         ret = psp_load_smu_fw(psp);
2571                         if (ret)
2572                                 return ret;
2573                         continue;
2574                 }
2575
2576                 if (fw_load_skip_check(psp, ucode))
2577                         continue;
2578
2579                 if (psp->autoload_supported &&
2580                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2581                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2582                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2583                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2584                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2585                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2586                         /* PSP only receive one SDMA fw for sienna_cichlid,
2587                          * as all four sdma fw are same */
2588                         continue;
2589
2590                 psp_print_fw_hdr(psp, ucode);
2591
2592                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2593                 if (ret)
2594                         return ret;
2595
2596                 /* Start rlc autoload after psp recieved all the gfx firmware */
2597                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2598                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2599                         ret = psp_rlc_autoload_start(psp);
2600                         if (ret) {
2601                                 DRM_ERROR("Failed to start rlc autoload\n");
2602                                 return ret;
2603                         }
2604                 }
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int psp_load_fw(struct amdgpu_device *adev)
2611 {
2612         int ret;
2613         struct psp_context *psp = &adev->psp;
2614
2615         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2616                 /* should not destroy ring, only stop */
2617                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2618         } else {
2619                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2620
2621                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2622                 if (ret) {
2623                         DRM_ERROR("PSP ring init failed!\n");
2624                         goto failed;
2625                 }
2626         }
2627
2628         ret = psp_hw_start(psp);
2629         if (ret)
2630                 goto failed;
2631
2632         ret = psp_load_non_psp_fw(psp);
2633         if (ret)
2634                 goto failed1;
2635
2636         ret = psp_asd_initialize(psp);
2637         if (ret) {
2638                 DRM_ERROR("PSP load asd failed!\n");
2639                 goto failed1;
2640         }
2641
2642         ret = psp_rl_load(adev);
2643         if (ret) {
2644                 DRM_ERROR("PSP load RL failed!\n");
2645                 goto failed1;
2646         }
2647
2648         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2649                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2650                         ret = psp_xgmi_initialize(psp, false, true);
2651                         /* Warning the XGMI seesion initialize failure
2652                         * Instead of stop driver initialization
2653                         */
2654                         if (ret)
2655                                 dev_err(psp->adev->dev,
2656                                         "XGMI: Failed to initialize XGMI session\n");
2657                 }
2658         }
2659
2660         if (psp->ta_fw) {
2661                 ret = psp_ras_initialize(psp);
2662                 if (ret)
2663                         dev_err(psp->adev->dev,
2664                                         "RAS: Failed to initialize RAS\n");
2665
2666                 ret = psp_hdcp_initialize(psp);
2667                 if (ret)
2668                         dev_err(psp->adev->dev,
2669                                 "HDCP: Failed to initialize HDCP\n");
2670
2671                 ret = psp_dtm_initialize(psp);
2672                 if (ret)
2673                         dev_err(psp->adev->dev,
2674                                 "DTM: Failed to initialize DTM\n");
2675
2676                 ret = psp_rap_initialize(psp);
2677                 if (ret)
2678                         dev_err(psp->adev->dev,
2679                                 "RAP: Failed to initialize RAP\n");
2680
2681                 ret = psp_securedisplay_initialize(psp);
2682                 if (ret)
2683                         dev_err(psp->adev->dev,
2684                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2685         }
2686
2687         return 0;
2688
2689 failed1:
2690         psp_free_shared_bufs(psp);
2691 failed:
2692         /*
2693          * all cleanup jobs (xgmi terminate, ras terminate,
2694          * ring destroy, cmd/fence/fw buffers destory,
2695          * psp->cmd destory) are delayed to psp_hw_fini
2696          */
2697         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2698         return ret;
2699 }
2700
2701 static int psp_hw_init(void *handle)
2702 {
2703         int ret;
2704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2705
2706         mutex_lock(&adev->firmware.mutex);
2707         /*
2708          * This sequence is just used on hw_init only once, no need on
2709          * resume.
2710          */
2711         ret = amdgpu_ucode_init_bo(adev);
2712         if (ret)
2713                 goto failed;
2714
2715         ret = psp_load_fw(adev);
2716         if (ret) {
2717                 DRM_ERROR("PSP firmware loading failed\n");
2718                 goto failed;
2719         }
2720
2721         mutex_unlock(&adev->firmware.mutex);
2722         return 0;
2723
2724 failed:
2725         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2726         mutex_unlock(&adev->firmware.mutex);
2727         return -EINVAL;
2728 }
2729
2730 static int psp_hw_fini(void *handle)
2731 {
2732         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2733         struct psp_context *psp = &adev->psp;
2734
2735         if (psp->ta_fw) {
2736                 psp_ras_terminate(psp);
2737                 psp_securedisplay_terminate(psp);
2738                 psp_rap_terminate(psp);
2739                 psp_dtm_terminate(psp);
2740                 psp_hdcp_terminate(psp);
2741
2742                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2743                         psp_xgmi_terminate(psp);
2744         }
2745
2746         psp_asd_terminate(psp);
2747         psp_tmr_terminate(psp);
2748
2749         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2750
2751         return 0;
2752 }
2753
2754 static int psp_suspend(void *handle)
2755 {
2756         int ret = 0;
2757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2758         struct psp_context *psp = &adev->psp;
2759
2760         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2761             psp->xgmi_context.context.initialized) {
2762                 ret = psp_xgmi_terminate(psp);
2763                 if (ret) {
2764                         DRM_ERROR("Failed to terminate xgmi ta\n");
2765                         goto out;
2766                 }
2767         }
2768
2769         if (psp->ta_fw) {
2770                 ret = psp_ras_terminate(psp);
2771                 if (ret) {
2772                         DRM_ERROR("Failed to terminate ras ta\n");
2773                         goto out;
2774                 }
2775                 ret = psp_hdcp_terminate(psp);
2776                 if (ret) {
2777                         DRM_ERROR("Failed to terminate hdcp ta\n");
2778                         goto out;
2779                 }
2780                 ret = psp_dtm_terminate(psp);
2781                 if (ret) {
2782                         DRM_ERROR("Failed to terminate dtm ta\n");
2783                         goto out;
2784                 }
2785                 ret = psp_rap_terminate(psp);
2786                 if (ret) {
2787                         DRM_ERROR("Failed to terminate rap ta\n");
2788                         goto out;
2789                 }
2790                 ret = psp_securedisplay_terminate(psp);
2791                 if (ret) {
2792                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2793                         goto out;
2794                 }
2795         }
2796
2797         ret = psp_asd_terminate(psp);
2798         if (ret) {
2799                 DRM_ERROR("Failed to terminate asd\n");
2800                 goto out;
2801         }
2802
2803         ret = psp_tmr_terminate(psp);
2804         if (ret) {
2805                 DRM_ERROR("Failed to terminate tmr\n");
2806                 goto out;
2807         }
2808
2809         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2810         if (ret)
2811                 DRM_ERROR("PSP ring stop failed\n");
2812
2813 out:
2814         return ret;
2815 }
2816
2817 static int psp_resume(void *handle)
2818 {
2819         int ret;
2820         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2821         struct psp_context *psp = &adev->psp;
2822
2823         DRM_INFO("PSP is resuming...\n");
2824
2825         if (psp->mem_train_ctx.enable_mem_training) {
2826                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2827                 if (ret) {
2828                         DRM_ERROR("Failed to process memory training!\n");
2829                         return ret;
2830                 }
2831         }
2832
2833         mutex_lock(&adev->firmware.mutex);
2834
2835         ret = psp_hw_start(psp);
2836         if (ret)
2837                 goto failed;
2838
2839         ret = psp_load_non_psp_fw(psp);
2840         if (ret)
2841                 goto failed;
2842
2843         ret = psp_asd_initialize(psp);
2844         if (ret) {
2845                 DRM_ERROR("PSP load asd failed!\n");
2846                 goto failed;
2847         }
2848
2849         ret = psp_rl_load(adev);
2850         if (ret) {
2851                 dev_err(adev->dev, "PSP load RL failed!\n");
2852                 goto failed;
2853         }
2854
2855         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2856                 ret = psp_xgmi_initialize(psp, false, true);
2857                 /* Warning the XGMI seesion initialize failure
2858                  * Instead of stop driver initialization
2859                  */
2860                 if (ret)
2861                         dev_err(psp->adev->dev,
2862                                 "XGMI: Failed to initialize XGMI session\n");
2863         }
2864
2865         if (psp->ta_fw) {
2866                 ret = psp_ras_initialize(psp);
2867                 if (ret)
2868                         dev_err(psp->adev->dev,
2869                                         "RAS: Failed to initialize RAS\n");
2870
2871                 ret = psp_hdcp_initialize(psp);
2872                 if (ret)
2873                         dev_err(psp->adev->dev,
2874                                 "HDCP: Failed to initialize HDCP\n");
2875
2876                 ret = psp_dtm_initialize(psp);
2877                 if (ret)
2878                         dev_err(psp->adev->dev,
2879                                 "DTM: Failed to initialize DTM\n");
2880
2881                 ret = psp_rap_initialize(psp);
2882                 if (ret)
2883                         dev_err(psp->adev->dev,
2884                                 "RAP: Failed to initialize RAP\n");
2885
2886                 ret = psp_securedisplay_initialize(psp);
2887                 if (ret)
2888                         dev_err(psp->adev->dev,
2889                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2890         }
2891
2892         mutex_unlock(&adev->firmware.mutex);
2893
2894         return 0;
2895
2896 failed:
2897         DRM_ERROR("PSP resume failed\n");
2898         mutex_unlock(&adev->firmware.mutex);
2899         return ret;
2900 }
2901
2902 int psp_gpu_reset(struct amdgpu_device *adev)
2903 {
2904         int ret;
2905
2906         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2907                 return 0;
2908
2909         mutex_lock(&adev->psp.mutex);
2910         ret = psp_mode1_reset(&adev->psp);
2911         mutex_unlock(&adev->psp.mutex);
2912
2913         return ret;
2914 }
2915
2916 int psp_rlc_autoload_start(struct psp_context *psp)
2917 {
2918         int ret;
2919         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2920
2921         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2922
2923         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2924                                  psp->fence_buf_mc_addr);
2925
2926         release_psp_cmd_buf(psp);
2927
2928         return ret;
2929 }
2930
2931 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2932                         uint64_t cmd_gpu_addr, int cmd_size)
2933 {
2934         struct amdgpu_firmware_info ucode = {0};
2935
2936         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2937                 AMDGPU_UCODE_ID_VCN0_RAM;
2938         ucode.mc_addr = cmd_gpu_addr;
2939         ucode.ucode_size = cmd_size;
2940
2941         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2942 }
2943
2944 int psp_ring_cmd_submit(struct psp_context *psp,
2945                         uint64_t cmd_buf_mc_addr,
2946                         uint64_t fence_mc_addr,
2947                         int index)
2948 {
2949         unsigned int psp_write_ptr_reg = 0;
2950         struct psp_gfx_rb_frame *write_frame;
2951         struct psp_ring *ring = &psp->km_ring;
2952         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2953         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2954                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2955         struct amdgpu_device *adev = psp->adev;
2956         uint32_t ring_size_dw = ring->ring_size / 4;
2957         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2958
2959         /* KM (GPCOM) prepare write pointer */
2960         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2961
2962         /* Update KM RB frame pointer to new frame */
2963         /* write_frame ptr increments by size of rb_frame in bytes */
2964         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2965         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2966                 write_frame = ring_buffer_start;
2967         else
2968                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2969         /* Check invalid write_frame ptr address */
2970         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2971                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2972                           ring_buffer_start, ring_buffer_end, write_frame);
2973                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2974                 return -EINVAL;
2975         }
2976
2977         /* Initialize KM RB frame */
2978         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2979
2980         /* Update KM RB frame */
2981         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2982         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2983         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2984         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2985         write_frame->fence_value = index;
2986         amdgpu_device_flush_hdp(adev, NULL);
2987
2988         /* Update the write Pointer in DWORDs */
2989         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2990         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2991         return 0;
2992 }
2993
2994 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2995 {
2996         struct amdgpu_device *adev = psp->adev;
2997         char fw_name[PSP_FW_NAME_LEN];
2998         const struct psp_firmware_header_v1_0 *asd_hdr;
2999         int err = 0;
3000
3001         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
3002         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
3003         if (err)
3004                 goto out;
3005
3006         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3007         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3008         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3009         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3010         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3011                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3012         return 0;
3013 out:
3014         amdgpu_ucode_release(&adev->psp.asd_fw);
3015         return err;
3016 }
3017
3018 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3019 {
3020         struct amdgpu_device *adev = psp->adev;
3021         char fw_name[PSP_FW_NAME_LEN];
3022         const struct psp_firmware_header_v1_0 *toc_hdr;
3023         int err = 0;
3024
3025         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3026         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3027         if (err)
3028                 goto out;
3029
3030         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3031         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3032         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3033         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3034         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3035                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3036         return 0;
3037 out:
3038         amdgpu_ucode_release(&adev->psp.toc_fw);
3039         return err;
3040 }
3041
3042 static int parse_sos_bin_descriptor(struct psp_context *psp,
3043                                    const struct psp_fw_bin_desc *desc,
3044                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3045 {
3046         uint8_t *ucode_start_addr  = NULL;
3047
3048         if (!psp || !desc || !sos_hdr)
3049                 return -EINVAL;
3050
3051         ucode_start_addr  = (uint8_t *)sos_hdr +
3052                             le32_to_cpu(desc->offset_bytes) +
3053                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3054
3055         switch (desc->fw_type) {
3056         case PSP_FW_TYPE_PSP_SOS:
3057                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3058                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3059                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3060                 psp->sos.start_addr        = ucode_start_addr;
3061                 break;
3062         case PSP_FW_TYPE_PSP_SYS_DRV:
3063                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3064                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3065                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3066                 psp->sys.start_addr        = ucode_start_addr;
3067                 break;
3068         case PSP_FW_TYPE_PSP_KDB:
3069                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3070                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3071                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3072                 psp->kdb.start_addr        = ucode_start_addr;
3073                 break;
3074         case PSP_FW_TYPE_PSP_TOC:
3075                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3076                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3077                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3078                 psp->toc.start_addr        = ucode_start_addr;
3079                 break;
3080         case PSP_FW_TYPE_PSP_SPL:
3081                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3082                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3083                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3084                 psp->spl.start_addr        = ucode_start_addr;
3085                 break;
3086         case PSP_FW_TYPE_PSP_RL:
3087                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3088                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3089                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3090                 psp->rl.start_addr         = ucode_start_addr;
3091                 break;
3092         case PSP_FW_TYPE_PSP_SOC_DRV:
3093                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3094                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3095                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3096                 psp->soc_drv.start_addr         = ucode_start_addr;
3097                 break;
3098         case PSP_FW_TYPE_PSP_INTF_DRV:
3099                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3100                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3101                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3102                 psp->intf_drv.start_addr        = ucode_start_addr;
3103                 break;
3104         case PSP_FW_TYPE_PSP_DBG_DRV:
3105                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3106                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3107                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3108                 psp->dbg_drv.start_addr         = ucode_start_addr;
3109                 break;
3110         case PSP_FW_TYPE_PSP_RAS_DRV:
3111                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3112                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3113                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3114                 psp->ras_drv.start_addr         = ucode_start_addr;
3115                 break;
3116         default:
3117                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3118                 break;
3119         }
3120
3121         return 0;
3122 }
3123
3124 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3125 {
3126         const struct psp_firmware_header_v1_0 *sos_hdr;
3127         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3128         uint8_t *ucode_array_start_addr;
3129
3130         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3131         ucode_array_start_addr = (uint8_t *)sos_hdr +
3132                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3133
3134         if (adev->gmc.xgmi.connected_to_cpu ||
3135             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3136                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3137                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3138
3139                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3140                 adev->psp.sys.start_addr = ucode_array_start_addr;
3141
3142                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3143                 adev->psp.sos.start_addr = ucode_array_start_addr +
3144                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3145         } else {
3146                 /* Load alternate PSP SOS FW */
3147                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3148
3149                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3150                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3151
3152                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3153                 adev->psp.sys.start_addr = ucode_array_start_addr +
3154                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3155
3156                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3157                 adev->psp.sos.start_addr = ucode_array_start_addr +
3158                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3159         }
3160
3161         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3162                 dev_warn(adev->dev, "PSP SOS FW not available");
3163                 return -EINVAL;
3164         }
3165
3166         return 0;
3167 }
3168
3169 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3170 {
3171         struct amdgpu_device *adev = psp->adev;
3172         char fw_name[PSP_FW_NAME_LEN];
3173         const struct psp_firmware_header_v1_0 *sos_hdr;
3174         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3175         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3176         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3177         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3178         int err = 0;
3179         uint8_t *ucode_array_start_addr;
3180         int fw_index = 0;
3181
3182         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3183         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3184         if (err)
3185                 goto out;
3186
3187         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3188         ucode_array_start_addr = (uint8_t *)sos_hdr +
3189                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3190         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3191
3192         switch (sos_hdr->header.header_version_major) {
3193         case 1:
3194                 err = psp_init_sos_base_fw(adev);
3195                 if (err)
3196                         goto out;
3197
3198                 if (sos_hdr->header.header_version_minor == 1) {
3199                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3200                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3201                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3202                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3203                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3204                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3205                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3206                 }
3207                 if (sos_hdr->header.header_version_minor == 2) {
3208                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3209                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3210                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3211                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3212                 }
3213                 if (sos_hdr->header.header_version_minor == 3) {
3214                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3215                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3216                         adev->psp.toc.start_addr = ucode_array_start_addr +
3217                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3218                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3219                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3220                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3221                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3222                         adev->psp.spl.start_addr = ucode_array_start_addr +
3223                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3224                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3225                         adev->psp.rl.start_addr = ucode_array_start_addr +
3226                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3227                 }
3228                 break;
3229         case 2:
3230                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3231
3232                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3233                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3234                         err = -EINVAL;
3235                         goto out;
3236                 }
3237
3238                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3239                         err = parse_sos_bin_descriptor(psp,
3240                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3241                                                        sos_hdr_v2_0);
3242                         if (err)
3243                                 goto out;
3244                 }
3245                 break;
3246         default:
3247                 dev_err(adev->dev,
3248                         "unsupported psp sos firmware\n");
3249                 err = -EINVAL;
3250                 goto out;
3251         }
3252
3253         return 0;
3254 out:
3255         amdgpu_ucode_release(&adev->psp.sos_fw);
3256
3257         return err;
3258 }
3259
3260 static int parse_ta_bin_descriptor(struct psp_context *psp,
3261                                    const struct psp_fw_bin_desc *desc,
3262                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3263 {
3264         uint8_t *ucode_start_addr  = NULL;
3265
3266         if (!psp || !desc || !ta_hdr)
3267                 return -EINVAL;
3268
3269         ucode_start_addr  = (uint8_t *)ta_hdr +
3270                             le32_to_cpu(desc->offset_bytes) +
3271                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3272
3273         switch (desc->fw_type) {
3274         case TA_FW_TYPE_PSP_ASD:
3275                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3276                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3277                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3278                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3279                 break;
3280         case TA_FW_TYPE_PSP_XGMI:
3281                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3282                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3283                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3284                 break;
3285         case TA_FW_TYPE_PSP_RAS:
3286                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3287                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3288                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3289                 break;
3290         case TA_FW_TYPE_PSP_HDCP:
3291                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3292                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3293                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3294                 break;
3295         case TA_FW_TYPE_PSP_DTM:
3296                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3297                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3298                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3299                 break;
3300         case TA_FW_TYPE_PSP_RAP:
3301                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3302                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3303                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3304                 break;
3305         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3306                 psp->securedisplay_context.context.bin_desc.fw_version =
3307                         le32_to_cpu(desc->fw_version);
3308                 psp->securedisplay_context.context.bin_desc.size_bytes =
3309                         le32_to_cpu(desc->size_bytes);
3310                 psp->securedisplay_context.context.bin_desc.start_addr =
3311                         ucode_start_addr;
3312                 break;
3313         default:
3314                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3315                 break;
3316         }
3317
3318         return 0;
3319 }
3320
3321 static int parse_ta_v1_microcode(struct psp_context *psp)
3322 {
3323         const struct ta_firmware_header_v1_0 *ta_hdr;
3324         struct amdgpu_device *adev = psp->adev;
3325
3326         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3327
3328         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3329                 return -EINVAL;
3330
3331         adev->psp.xgmi_context.context.bin_desc.fw_version =
3332                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3333         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3334                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3335         adev->psp.xgmi_context.context.bin_desc.start_addr =
3336                 (uint8_t *)ta_hdr +
3337                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3338
3339         adev->psp.ras_context.context.bin_desc.fw_version =
3340                 le32_to_cpu(ta_hdr->ras.fw_version);
3341         adev->psp.ras_context.context.bin_desc.size_bytes =
3342                 le32_to_cpu(ta_hdr->ras.size_bytes);
3343         adev->psp.ras_context.context.bin_desc.start_addr =
3344                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3345                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3346
3347         adev->psp.hdcp_context.context.bin_desc.fw_version =
3348                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3349         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3350                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3351         adev->psp.hdcp_context.context.bin_desc.start_addr =
3352                 (uint8_t *)ta_hdr +
3353                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3354
3355         adev->psp.dtm_context.context.bin_desc.fw_version =
3356                 le32_to_cpu(ta_hdr->dtm.fw_version);
3357         adev->psp.dtm_context.context.bin_desc.size_bytes =
3358                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3359         adev->psp.dtm_context.context.bin_desc.start_addr =
3360                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3361                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3362
3363         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3364                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3365         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3366                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3367         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3368                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3369                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3370
3371         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3372
3373         return 0;
3374 }
3375
3376 static int parse_ta_v2_microcode(struct psp_context *psp)
3377 {
3378         const struct ta_firmware_header_v2_0 *ta_hdr;
3379         struct amdgpu_device *adev = psp->adev;
3380         int err = 0;
3381         int ta_index = 0;
3382
3383         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3384
3385         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3386                 return -EINVAL;
3387
3388         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3389                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3390                 return -EINVAL;
3391         }
3392
3393         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3394                 err = parse_ta_bin_descriptor(psp,
3395                                               &ta_hdr->ta_fw_bin[ta_index],
3396                                               ta_hdr);
3397                 if (err)
3398                         return err;
3399         }
3400
3401         return 0;
3402 }
3403
3404 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3405 {
3406         const struct common_firmware_header *hdr;
3407         struct amdgpu_device *adev = psp->adev;
3408         char fw_name[PSP_FW_NAME_LEN];
3409         int err;
3410
3411         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3412         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3413         if (err)
3414                 return err;
3415
3416         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3417         switch (le16_to_cpu(hdr->header_version_major)) {
3418         case 1:
3419                 err = parse_ta_v1_microcode(psp);
3420                 break;
3421         case 2:
3422                 err = parse_ta_v2_microcode(psp);
3423                 break;
3424         default:
3425                 dev_err(adev->dev, "unsupported TA header version\n");
3426                 err = -EINVAL;
3427         }
3428
3429         if (err)
3430                 amdgpu_ucode_release(&adev->psp.ta_fw);
3431
3432         return err;
3433 }
3434
3435 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3436 {
3437         struct amdgpu_device *adev = psp->adev;
3438         char fw_name[PSP_FW_NAME_LEN];
3439         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3440         struct amdgpu_firmware_info *info = NULL;
3441         int err = 0;
3442
3443         if (!amdgpu_sriov_vf(adev)) {
3444                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3445                 return -EINVAL;
3446         }
3447
3448         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3449         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3450         if (err) {
3451                 if (err == -ENODEV) {
3452                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3453                         err = 0;
3454                         goto out;
3455                 }
3456                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3457         }
3458
3459         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3460         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3461         info->fw = adev->psp.cap_fw;
3462         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3463                 adev->psp.cap_fw->data;
3464         adev->firmware.fw_size += ALIGN(
3465                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3466         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3467         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3468         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3469
3470         return 0;
3471
3472 out:
3473         amdgpu_ucode_release(&adev->psp.cap_fw);
3474         return err;
3475 }
3476
3477 static int psp_set_clockgating_state(void *handle,
3478                                      enum amd_clockgating_state state)
3479 {
3480         return 0;
3481 }
3482
3483 static int psp_set_powergating_state(void *handle,
3484                                      enum amd_powergating_state state)
3485 {
3486         return 0;
3487 }
3488
3489 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3490                                          struct device_attribute *attr,
3491                                          char *buf)
3492 {
3493         struct drm_device *ddev = dev_get_drvdata(dev);
3494         struct amdgpu_device *adev = drm_to_adev(ddev);
3495         uint32_t fw_ver;
3496         int ret;
3497
3498         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3499                 DRM_INFO("PSP block is not ready yet.");
3500                 return -EBUSY;
3501         }
3502
3503         mutex_lock(&adev->psp.mutex);
3504         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3505         mutex_unlock(&adev->psp.mutex);
3506
3507         if (ret) {
3508                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3509                 return ret;
3510         }
3511
3512         return sysfs_emit(buf, "%x\n", fw_ver);
3513 }
3514
3515 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3516                                                        struct device_attribute *attr,
3517                                                        const char *buf,
3518                                                        size_t count)
3519 {
3520         struct drm_device *ddev = dev_get_drvdata(dev);
3521         struct amdgpu_device *adev = drm_to_adev(ddev);
3522         int ret, idx;
3523         char fw_name[100];
3524         const struct firmware *usbc_pd_fw;
3525         struct amdgpu_bo *fw_buf_bo = NULL;
3526         uint64_t fw_pri_mc_addr;
3527         void *fw_pri_cpu_addr;
3528
3529         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3530                 DRM_INFO("PSP block is not ready yet.");
3531                 return -EBUSY;
3532         }
3533
3534         if (!drm_dev_enter(ddev, &idx))
3535                 return -ENODEV;
3536
3537         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3538         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3539         if (ret)
3540                 goto fail;
3541
3542         /* LFB address which is aligned to 1MB boundary per PSP request */
3543         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3544                                       AMDGPU_GEM_DOMAIN_VRAM |
3545                                       AMDGPU_GEM_DOMAIN_GTT,
3546                                       &fw_buf_bo, &fw_pri_mc_addr,
3547                                       &fw_pri_cpu_addr);
3548         if (ret)
3549                 goto rel_buf;
3550
3551         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3552
3553         mutex_lock(&adev->psp.mutex);
3554         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3555         mutex_unlock(&adev->psp.mutex);
3556
3557         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3558
3559 rel_buf:
3560         release_firmware(usbc_pd_fw);
3561 fail:
3562         if (ret) {
3563                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3564                 count = ret;
3565         }
3566
3567         drm_dev_exit(idx);
3568         return count;
3569 }
3570
3571 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3572 {
3573         int idx;
3574
3575         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3576                 return;
3577
3578         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3579         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3580
3581         drm_dev_exit(idx);
3582 }
3583
3584 static DEVICE_ATTR(usbc_pd_fw, 0644,
3585                    psp_usbc_pd_fw_sysfs_read,
3586                    psp_usbc_pd_fw_sysfs_write);
3587
3588 int is_psp_fw_valid(struct psp_bin_desc bin)
3589 {
3590         return bin.size_bytes;
3591 }
3592
3593 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3594                                         struct bin_attribute *bin_attr,
3595                                         char *buffer, loff_t pos, size_t count)
3596 {
3597         struct device *dev = kobj_to_dev(kobj);
3598         struct drm_device *ddev = dev_get_drvdata(dev);
3599         struct amdgpu_device *adev = drm_to_adev(ddev);
3600
3601         adev->psp.vbflash_done = false;
3602
3603         /* Safeguard against memory drain */
3604         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3605                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3606                 kvfree(adev->psp.vbflash_tmp_buf);
3607                 adev->psp.vbflash_tmp_buf = NULL;
3608                 adev->psp.vbflash_image_size = 0;
3609                 return -ENOMEM;
3610         }
3611
3612         /* TODO Just allocate max for now and optimize to realloc later if needed */
3613         if (!adev->psp.vbflash_tmp_buf) {
3614                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3615                 if (!adev->psp.vbflash_tmp_buf)
3616                         return -ENOMEM;
3617         }
3618
3619         mutex_lock(&adev->psp.mutex);
3620         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3621         adev->psp.vbflash_image_size += count;
3622         mutex_unlock(&adev->psp.mutex);
3623
3624         dev_info(adev->dev, "VBIOS flash write PSP done");
3625
3626         return count;
3627 }
3628
3629 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3630                                        struct bin_attribute *bin_attr, char *buffer,
3631                                        loff_t pos, size_t count)
3632 {
3633         struct device *dev = kobj_to_dev(kobj);
3634         struct drm_device *ddev = dev_get_drvdata(dev);
3635         struct amdgpu_device *adev = drm_to_adev(ddev);
3636         struct amdgpu_bo *fw_buf_bo = NULL;
3637         uint64_t fw_pri_mc_addr;
3638         void *fw_pri_cpu_addr;
3639         int ret;
3640
3641         if (adev->psp.vbflash_image_size == 0)
3642                 return -EINVAL;
3643
3644         dev_info(adev->dev, "VBIOS flash to PSP started");
3645
3646         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3647                                         AMDGPU_GPU_PAGE_SIZE,
3648                                         AMDGPU_GEM_DOMAIN_VRAM,
3649                                         &fw_buf_bo,
3650                                         &fw_pri_mc_addr,
3651                                         &fw_pri_cpu_addr);
3652         if (ret)
3653                 goto rel_buf;
3654
3655         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3656
3657         mutex_lock(&adev->psp.mutex);
3658         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3659         mutex_unlock(&adev->psp.mutex);
3660
3661         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3662
3663 rel_buf:
3664         kvfree(adev->psp.vbflash_tmp_buf);
3665         adev->psp.vbflash_tmp_buf = NULL;
3666         adev->psp.vbflash_image_size = 0;
3667
3668         if (ret) {
3669                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3670                 return ret;
3671         }
3672
3673         dev_info(adev->dev, "VBIOS flash to PSP done");
3674         return 0;
3675 }
3676
3677 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3678                                          struct device_attribute *attr,
3679                                          char *buf)
3680 {
3681         struct drm_device *ddev = dev_get_drvdata(dev);
3682         struct amdgpu_device *adev = drm_to_adev(ddev);
3683         uint32_t vbflash_status;
3684
3685         vbflash_status = psp_vbflash_status(&adev->psp);
3686         if (!adev->psp.vbflash_done)
3687                 vbflash_status = 0;
3688         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3689                 vbflash_status = 1;
3690
3691         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3692 }
3693
3694 static const struct bin_attribute psp_vbflash_bin_attr = {
3695         .attr = {.name = "psp_vbflash", .mode = 0660},
3696         .size = 0,
3697         .write = amdgpu_psp_vbflash_write,
3698         .read = amdgpu_psp_vbflash_read,
3699 };
3700
3701 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3702
3703 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3704 {
3705         int ret = 0;
3706         struct psp_context *psp = &adev->psp;
3707
3708         if (amdgpu_sriov_vf(adev))
3709                 return -EINVAL;
3710
3711         switch (adev->ip_versions[MP0_HWIP][0]) {
3712         case IP_VERSION(13, 0, 0):
3713         case IP_VERSION(13, 0, 7):
3714         case IP_VERSION(13, 0, 10):
3715                 if (!psp->adev) {
3716                         psp->adev = adev;
3717                         psp_v13_0_set_psp_funcs(psp);
3718                 }
3719                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3720                 if (ret)
3721                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3722                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3723                 if (ret)
3724                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3725                 return ret;
3726         default:
3727                 return 0;
3728         }
3729 }
3730
3731 const struct amd_ip_funcs psp_ip_funcs = {
3732         .name = "psp",
3733         .early_init = psp_early_init,
3734         .late_init = NULL,
3735         .sw_init = psp_sw_init,
3736         .sw_fini = psp_sw_fini,
3737         .hw_init = psp_hw_init,
3738         .hw_fini = psp_hw_fini,
3739         .suspend = psp_suspend,
3740         .resume = psp_resume,
3741         .is_idle = NULL,
3742         .check_soft_reset = NULL,
3743         .wait_for_idle = NULL,
3744         .soft_reset = NULL,
3745         .set_clockgating_state = psp_set_clockgating_state,
3746         .set_powergating_state = psp_set_powergating_state,
3747 };
3748
3749 static int psp_sysfs_init(struct amdgpu_device *adev)
3750 {
3751         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3752
3753         if (ret)
3754                 DRM_ERROR("Failed to create USBC PD FW control file!");
3755
3756         return ret;
3757 }
3758
3759 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3760 {
3761         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3762         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3763 }
3764
3765 static void psp_sysfs_fini(struct amdgpu_device *adev)
3766 {
3767         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3768 }
3769
3770 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3771         .type = AMD_IP_BLOCK_TYPE_PSP,
3772         .major = 3,
3773         .minor = 1,
3774         .rev = 0,
3775         .funcs = &psp_ip_funcs,
3776 };
3777
3778 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3779         .type = AMD_IP_BLOCK_TYPE_PSP,
3780         .major = 10,
3781         .minor = 0,
3782         .rev = 0,
3783         .funcs = &psp_ip_funcs,
3784 };
3785
3786 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3787         .type = AMD_IP_BLOCK_TYPE_PSP,
3788         .major = 11,
3789         .minor = 0,
3790         .rev = 0,
3791         .funcs = &psp_ip_funcs,
3792 };
3793
3794 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3795         .type = AMD_IP_BLOCK_TYPE_PSP,
3796         .major = 11,
3797         .minor = 0,
3798         .rev = 8,
3799         .funcs = &psp_ip_funcs,
3800 };
3801
3802 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3803         .type = AMD_IP_BLOCK_TYPE_PSP,
3804         .major = 12,
3805         .minor = 0,
3806         .rev = 0,
3807         .funcs = &psp_ip_funcs,
3808 };
3809
3810 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3811         .type = AMD_IP_BLOCK_TYPE_PSP,
3812         .major = 13,
3813         .minor = 0,
3814         .rev = 0,
3815         .funcs = &psp_ip_funcs,
3816 };
3817
3818 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3819         .type = AMD_IP_BLOCK_TYPE_PSP,
3820         .major = 13,
3821         .minor = 0,
3822         .rev = 4,
3823         .funcs = &psp_ip_funcs,
3824 };