drivers/watchdog/aspeed_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2016 IBM Corporation
   4  *
   5  * Joel Stanley <[email protected]>
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/watchdog.h>
  18
  19 static bool nowayout = WATCHDOG_NOWAYOUT;
  20 module_param(nowayout, bool, 0);
  21 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  22                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  23
  24 struct aspeed_wdt_config {
  25         u32 ext_pulse_width_mask;
  26         u32 irq_shift;
  27         u32 irq_mask;
  28 };
  29
  30 struct aspeed_wdt {
  31         struct watchdog_device  wdd;
  32         void __iomem            *base;
  33         u32                     ctrl;
  34         const struct aspeed_wdt_config *cfg;
  35 };
  36
  37 static const struct aspeed_wdt_config ast2400_config = {
  38         .ext_pulse_width_mask = 0xff,
  39         .irq_shift = 0,
  40         .irq_mask = 0,
  41 };
  42
  43 static const struct aspeed_wdt_config ast2500_config = {
  44         .ext_pulse_width_mask = 0xfffff,
  45         .irq_shift = 12,
  46         .irq_mask = GENMASK(31, 12),
  47 };
  48
  49 static const struct aspeed_wdt_config ast2600_config = {
  50         .ext_pulse_width_mask = 0xfffff,
  51         .irq_shift = 0,
  52         .irq_mask = GENMASK(31, 10),
  53 };
  54
  55 static const struct of_device_id aspeed_wdt_of_table[] = {
  56         { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
  57         { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
  58         { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
  59         { },
  60 };
  61 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
  62
  63 #define WDT_STATUS              0x00
  64 #define WDT_RELOAD_VALUE        0x04
  65 #define WDT_RESTART             0x08
  66 #define WDT_CTRL                0x0C
  67 #define   WDT_CTRL_BOOT_SECONDARY       BIT(7)
  68 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
  69 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
  70 #define   WDT_CTRL_RESET_MODE_ARM_CPU   (0x10 << 5)
  71 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
  72 #define   WDT_CTRL_WDT_EXT              BIT(3)
  73 #define   WDT_CTRL_WDT_INTR             BIT(2)
  74 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
  75 #define   WDT_CTRL_ENABLE               BIT(0)
  76 #define WDT_TIMEOUT_STATUS      0x10
  77 #define   WDT_TIMEOUT_STATUS_IRQ                BIT(2)
  78 #define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY     BIT(1)
  79 #define WDT_CLEAR_TIMEOUT_STATUS        0x14
  80 #define   WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION     BIT(0)
  81
  82 /*
  83  * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
  84  * enabled), specifically:
  85  *
  86  * * Pulse duration
  87  * * Drive mode: push-pull vs open-drain
  88  * * Polarity: Active high or active low
  89  *
  90  * Pulse duration configuration is available on both the AST2400 and AST2500,
  91  * though the field changes between SoCs:
  92  *
  93  * AST2400: Bits 7:0
  94  * AST2500: Bits 19:0
  95  *
  96  * This difference is captured in struct aspeed_wdt_config.
  97  *
  98  * The AST2500 exposes the drive mode and polarity options, but not in a
  99  * regular fashion. For read purposes, bit 31 represents active high or low,
 100  * and bit 30 represents push-pull or open-drain. With respect to write, magic
 101  * values need to be written to the top byte to change the state of the drive
 102  * mode and polarity bits. Any other value written to the top byte has no
 103  * effect on the state of the drive mode or polarity bits. However, the pulse
 104  * width value must be preserved (as desired) if written.
 105  */
 106 #define WDT_RESET_WIDTH         0x18
 107 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
 108 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
 109 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
 110 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
 111 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
 112 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
 113
 114 #define WDT_RESTART_MAGIC       0x4755
 115
 116 /* 32 bits at 1MHz, in milliseconds */
 117 #define WDT_MAX_TIMEOUT_MS      4294967
 118 #define WDT_DEFAULT_TIMEOUT     30
 119 #define WDT_RATE_1MHZ           1000000
 120
 121 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
 122 {
 123         return container_of(wdd, struct aspeed_wdt, wdd);
 124 }
 125
 126 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
 127 {
 128         wdt->ctrl |= WDT_CTRL_ENABLE;
 129
 130         writel(0, wdt->base + WDT_CTRL);
 131         writel(count, wdt->base + WDT_RELOAD_VALUE);
 132         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 133         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 134 }
 135
 136 static int aspeed_wdt_start(struct watchdog_device *wdd)
 137 {
 138         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 139
 140         aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
 141
 142         return 0;
 143 }
 144
 145 static int aspeed_wdt_stop(struct watchdog_device *wdd)
 146 {
 147         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 148
 149         wdt->ctrl &= ~WDT_CTRL_ENABLE;
 150         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 151
 152         return 0;
 153 }
 154
 155 static int aspeed_wdt_ping(struct watchdog_device *wdd)
 156 {
 157         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 158
 159         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 160
 161         return 0;
 162 }
 163
 164 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
 165                                   unsigned int timeout)
 166 {
 167         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 168         u32 actual;
 169
 170         wdd->timeout = timeout;
 171
 172         actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
 173
 174         writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
 175         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 176
 177         return 0;
 178 }
 179
 180 static int aspeed_wdt_set_pretimeout(struct watchdog_device *wdd,
 181                                      unsigned int pretimeout)
 182 {
 183         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 184         u32 actual = pretimeout * WDT_RATE_1MHZ;
 185         u32 s = wdt->cfg->irq_shift;
 186         u32 m = wdt->cfg->irq_mask;
 187
 188         wdd->pretimeout = pretimeout;
 189         wdt->ctrl &= ~m;
 190         if (pretimeout)
 191                 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR;
 192         else
 193                 wdt->ctrl &= ~WDT_CTRL_WDT_INTR;
 194
 195         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 196
 197         return 0;
 198 }
 199
 200 static int aspeed_wdt_restart(struct watchdog_device *wdd,
 201                               unsigned long action, void *data)
 202 {
 203         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 204
 205         wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
 206         aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
 207
 208         mdelay(1000);
 209
 210         return 0;
 211 }
 212
 213 /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
 214 static ssize_t access_cs0_show(struct device *dev,
 215                                struct device_attribute *attr, char *buf)
 216 {
 217         struct aspeed_wdt *wdt = dev_get_drvdata(dev);
 218         u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 219
 220         return sysfs_emit(buf, "%u\n",
 221                           !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
 222 }
 223
 224 static ssize_t access_cs0_store(struct device *dev,
 225                                 struct device_attribute *attr, const char *buf,
 226                                 size_t size)
 227 {
 228         struct aspeed_wdt *wdt = dev_get_drvdata(dev);
 229         unsigned long val;
 230
 231         if (kstrtoul(buf, 10, &val))
 232                 return -EINVAL;
 233
 234         if (val)
 235                 writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
 236                        wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
 237
 238         return size;
 239 }
 240
 241 /*
 242  * This attribute exists only if the system has booted from the alternate
 243  * flash with 'alt-boot' option.
 244  *
 245  * At alternate flash the 'access_cs0' sysfs node provides:
 246  *   ast2400: a way to get access to the primary SPI flash chip at CS0
 247  *            after booting from the alternate chip at CS1.
 248  *   ast2500: a way to restore the normal address mapping from
 249  *            (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
 250  *
 251  * Clearing the boot code selection and timeout counter also resets to the
 252  * initial state the chip select line mapping. When the SoC is in normal
 253  * mapping state (i.e. booted from CS0), clearing those bits does nothing for
 254  * both versions of the SoC. For alternate boot mode (booted from CS1 due to
 255  * wdt2 expiration) the behavior differs as described above.
 256  *
 257  * This option can be used with wdt2 (watchdog1) only.
 258  */
 259 static DEVICE_ATTR_RW(access_cs0);
 260
 261 static struct attribute *bswitch_attrs[] = {
 262         &dev_attr_access_cs0.attr,
 263         NULL
 264 };
 265 ATTRIBUTE_GROUPS(bswitch);
 266
 267 static const struct watchdog_ops aspeed_wdt_ops = {
 268         .start          = aspeed_wdt_start,
 269         .stop           = aspeed_wdt_stop,
 270         .ping           = aspeed_wdt_ping,
 271         .set_timeout    = aspeed_wdt_set_timeout,
 272         .set_pretimeout = aspeed_wdt_set_pretimeout,
 273         .restart        = aspeed_wdt_restart,
 274         .owner          = THIS_MODULE,
 275 };
 276
 277 static const struct watchdog_info aspeed_wdt_info = {
 278         .options        = WDIOF_KEEPALIVEPING
 279                         | WDIOF_MAGICCLOSE
 280                         | WDIOF_SETTIMEOUT,
 281         .identity       = KBUILD_MODNAME,
 282 };
 283
 284 static const struct watchdog_info aspeed_wdt_pretimeout_info = {
 285         .options        = WDIOF_KEEPALIVEPING
 286                         | WDIOF_PRETIMEOUT
 287                         | WDIOF_MAGICCLOSE
 288                         | WDIOF_SETTIMEOUT,
 289         .identity       = KBUILD_MODNAME,
 290 };
 291
 292 static irqreturn_t aspeed_wdt_irq(int irq, void *arg)
 293 {
 294         struct watchdog_device *wdd = arg;
 295         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 296         u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 297
 298         if (status & WDT_TIMEOUT_STATUS_IRQ)
 299                 watchdog_notify_pretimeout(wdd);
 300
 301         return IRQ_HANDLED;
 302 }
 303
 304 static int aspeed_wdt_probe(struct platform_device *pdev)
 305 {
 306         struct device *dev = &pdev->dev;
 307         const struct of_device_id *ofdid;
 308         struct aspeed_wdt *wdt;
 309         struct device_node *np;
 310         const char *reset_type;
 311         u32 duration;
 312         u32 status;
 313         int ret;
 314
 315         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 316         if (!wdt)
 317                 return -ENOMEM;
 318
 319         np = dev->of_node;
 320
 321         ofdid = of_match_node(aspeed_wdt_of_table, np);
 322         if (!ofdid)
 323                 return -EINVAL;
 324         wdt->cfg = ofdid->data;
 325
 326         wdt->base = devm_platform_ioremap_resource(pdev, 0);
 327         if (IS_ERR(wdt->base))
 328                 return PTR_ERR(wdt->base);
 329
 330         wdt->wdd.info = &aspeed_wdt_info;
 331
 332         if (wdt->cfg->irq_mask) {
 333                 int irq = platform_get_irq_optional(pdev, 0);
 334
 335                 if (irq > 0) {
 336                         ret = devm_request_irq(dev, irq, aspeed_wdt_irq,
 337                                                IRQF_SHARED, dev_name(dev),
 338                                                wdt);
 339                         if (ret)
 340                                 return ret;
 341
 342                         wdt->wdd.info = &aspeed_wdt_pretimeout_info;
 343                 }
 344         }
 345
 346         wdt->wdd.ops = &aspeed_wdt_ops;
 347         wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
 348         wdt->wdd.parent = dev;
 349
 350         wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
 351         watchdog_init_timeout(&wdt->wdd, 0, dev);
 352
 353         watchdog_set_nowayout(&wdt->wdd, nowayout);
 354
 355         /*
 356          * On clock rates:
 357          *  - ast2400 wdt can run at PCLK, or 1MHz
 358          *  - ast2500 only runs at 1MHz, hard coding bit 4 to 1
 359          *  - ast2600 always runs at 1MHz
 360          *
 361          * Set the ast2400 to run at 1MHz as it simplifies the driver.
 362          */
 363         if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
 364                 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
 365
 366         /*
 367          * Control reset on a per-device basis to ensure the
 368          * host is not affected by a BMC reboot
 369          */
 370         ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
 371         if (ret) {
 372                 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
 373         } else {
 374                 if (!strcmp(reset_type, "cpu"))
 375                         wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
 376                                      WDT_CTRL_RESET_SYSTEM;
 377                 else if (!strcmp(reset_type, "soc"))
 378                         wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
 379                                      WDT_CTRL_RESET_SYSTEM;
 380                 else if (!strcmp(reset_type, "system"))
 381                         wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
 382                                      WDT_CTRL_RESET_SYSTEM;
 383                 else if (strcmp(reset_type, "none"))
 384                         return -EINVAL;
 385         }
 386         if (of_property_read_bool(np, "aspeed,external-signal"))
 387                 wdt->ctrl |= WDT_CTRL_WDT_EXT;
 388         if (of_property_read_bool(np, "aspeed,alt-boot"))
 389                 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
 390
 391         if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
 392                 /*
 393                  * The watchdog is running, but invoke aspeed_wdt_start() to
 394                  * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
 395                  * configuration conforms to the driver's expectations.
 396                  * Primarily, ensure we're using the 1MHz clock source.
 397                  */
 398                 aspeed_wdt_start(&wdt->wdd);
 399                 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
 400         }
 401
 402         if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
 403                 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
 404                 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
 405
 406                 reg &= wdt->cfg->ext_pulse_width_mask;
 407                 if (of_property_read_bool(np, "aspeed,ext-active-high"))
 408                         reg |= WDT_ACTIVE_HIGH_MAGIC;
 409                 else
 410                         reg |= WDT_ACTIVE_LOW_MAGIC;
 411
 412                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 413
 414                 reg &= wdt->cfg->ext_pulse_width_mask;
 415                 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
 416                         reg |= WDT_PUSH_PULL_MAGIC;
 417                 else
 418                         reg |= WDT_OPEN_DRAIN_MAGIC;
 419
 420                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 421         }
 422
 423         if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
 424                 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1;
 425
 426                 if (duration == 0 || duration > max_duration) {
 427                         dev_err(dev, "Invalid pulse duration: %uus\n",
 428                                 duration);
 429                         duration = max(1U, min(max_duration, duration));
 430                         dev_info(dev, "Pulse duration set to %uus\n",
 431                                  duration);
 432                 }
 433
 434                 /*
 435                  * The watchdog is always configured with a 1MHz source, so
 436                  * there is no need to scale the microsecond value. However we
 437                  * need to offset it - from the datasheet:
 438                  *
 439                  * "This register decides the asserting duration of wdt_ext and
 440                  * wdt_rstarm signal. The default value is 0xFF. It means the
 441                  * default asserting duration of wdt_ext and wdt_rstarm is
 442                  * 256us."
 443                  *
 444                  * This implies a value of 0 gives a 1us pulse.
 445                  */
 446                 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
 447         }
 448
 449         status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 450         if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
 451                 wdt->wdd.bootstatus = WDIOF_CARDRESET;
 452
 453                 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
 454                     of_device_is_compatible(np, "aspeed,ast2500-wdt"))
 455                         wdt->wdd.groups = bswitch_groups;
 456         }
 457
 458         dev_set_drvdata(dev, wdt);
 459
 460         return devm_watchdog_register_device(dev, &wdt->wdd);
 461 }
 462
 463 static struct platform_driver aspeed_watchdog_driver = {
 464         .probe = aspeed_wdt_probe,
 465         .driver = {
 466                 .name = KBUILD_MODNAME,
 467                 .of_match_table = of_match_ptr(aspeed_wdt_of_table),
 468         },
 469 };
 470
 471 static int __init aspeed_wdt_init(void)
 472 {
 473         return platform_driver_register(&aspeed_watchdog_driver);
 474 }
 475 arch_initcall(aspeed_wdt_init);
 476
 477 static void __exit aspeed_wdt_exit(void)
 478 {
 479         platform_driver_unregister(&aspeed_watchdog_driver);
 480 }
 481 module_exit(aspeed_wdt_exit);
 482
 483 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
 484 MODULE_LICENSE("GPL");