drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "nbio_v6_1.h"
  62 #include "nbio_v7_0.h"
  63 #include "nbio_v7_4.h"
  64 #include "vega10_ih.h"
  65 #include "sdma_v4_0.h"
  66 #include "uvd_v7_0.h"
  67 #include "vce_v4_0.h"
  68 #include "vcn_v1_0.h"
  69 #include "vcn_v2_0.h"
  70 #include "jpeg_v2_0.h"
  71 #include "vcn_v2_5.h"
  72 #include "jpeg_v2_5.h"
  73 #include "dce_virtual.h"
  74 #include "mxgpu_ai.h"
  75 #include "amdgpu_smu.h"
  76 #include "amdgpu_ras.h"
  77 #include "amdgpu_xgmi.h"
  78 #include <uapi/linux/kfd_ioctl.h>
  79
  80 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  84
  85 /* for Vega20 register name change */
  86 #define mmHDP_MEM_POWER_CTRL    0x00d4
  87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  92
  93 /* for Vega20/arcturus regiter offset change */
  94 #define mmROM_INDEX_VG20                                0x00e4
  95 #define mmROM_INDEX_VG20_BASE_IDX                       0
  96 #define mmROM_DATA_VG20                                 0x00e5
  97 #define mmROM_DATA_VG20_BASE_IDX                        0
  98
  99 /*
 100  * Indirect registers accessor
 101  */
 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 103 {
 104         unsigned long flags, address, data;
 105         u32 r;
 106         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 107         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 108
 109         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 110         WREG32(address, reg);
 111         (void)RREG32(address);
 112         r = RREG32(data);
 113         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 114         return r;
 115 }
 116
 117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 118 {
 119         unsigned long flags, address, data;
 120
 121         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 122         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 123
 124         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 125         WREG32(address, reg);
 126         (void)RREG32(address);
 127         WREG32(data, v);
 128         (void)RREG32(data);
 129         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 130 }
 131
 132 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 133 {
 134         unsigned long flags, address, data;
 135         u64 r;
 136         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 137         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 138
 139         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 140         /* read low 32 bit */
 141         WREG32(address, reg);
 142         (void)RREG32(address);
 143         r = RREG32(data);
 144
 145         /* read high 32 bit*/
 146         WREG32(address, reg + 4);
 147         (void)RREG32(address);
 148         r |= ((u64)RREG32(data) << 32);
 149         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 150         return r;
 151 }
 152
 153 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 154 {
 155         unsigned long flags, address, data;
 156
 157         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 158         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 159
 160         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 161         /* write low 32 bit */
 162         WREG32(address, reg);
 163         (void)RREG32(address);
 164         WREG32(data, (u32)(v & 0xffffffffULL));
 165         (void)RREG32(data);
 166
 167         /* write high 32 bit */
 168         WREG32(address, reg + 4);
 169         (void)RREG32(address);
 170         WREG32(data, (u32)(v >> 32));
 171         (void)RREG32(data);
 172         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 173 }
 174
 175 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 176 {
 177         unsigned long flags, address, data;
 178         u32 r;
 179
 180         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 181         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 182
 183         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 184         WREG32(address, ((reg) & 0x1ff));
 185         r = RREG32(data);
 186         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 187         return r;
 188 }
 189
 190 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 191 {
 192         unsigned long flags, address, data;
 193
 194         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 195         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 196
 197         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 198         WREG32(address, ((reg) & 0x1ff));
 199         WREG32(data, (v));
 200         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 201 }
 202
 203 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 204 {
 205         unsigned long flags, address, data;
 206         u32 r;
 207
 208         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 209         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 210
 211         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 212         WREG32(address, (reg));
 213         r = RREG32(data);
 214         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 215         return r;
 216 }
 217
 218 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 219 {
 220         unsigned long flags, address, data;
 221
 222         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 223         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 224
 225         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 226         WREG32(address, (reg));
 227         WREG32(data, (v));
 228         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 229 }
 230
 231 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 232 {
 233         unsigned long flags;
 234         u32 r;
 235
 236         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 237         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 238         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 239         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 240         return r;
 241 }
 242
 243 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 244 {
 245         unsigned long flags;
 246
 247         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 248         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 249         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 250         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 251 }
 252
 253 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 254 {
 255         unsigned long flags;
 256         u32 r;
 257
 258         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 259         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 260         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 261         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 262         return r;
 263 }
 264
 265 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 266 {
 267         unsigned long flags;
 268
 269         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 270         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 271         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 272         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 273 }
 274
 275 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 276 {
 277         return adev->nbio.funcs->get_memsize(adev);
 278 }
 279
 280 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 281 {
 282         u32 reference_clock = adev->clock.spll.reference_freq;
 283
 284         if (adev->asic_type == CHIP_RAVEN)
 285                 return reference_clock / 4;
 286
 287         return reference_clock;
 288 }
 289
 290
 291 void soc15_grbm_select(struct amdgpu_device *adev,
 292                      u32 me, u32 pipe, u32 queue, u32 vmid)
 293 {
 294         u32 grbm_gfx_cntl = 0;
 295         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 296         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 297         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 298         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 299
 300         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 301 }
 302
 303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 304 {
 305         /* todo */
 306 }
 307
 308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 309 {
 310         /* todo */
 311         return false;
 312 }
 313
 314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 315                                      u8 *bios, u32 length_bytes)
 316 {
 317         u32 *dw_ptr;
 318         u32 i, length_dw;
 319         uint32_t rom_index_offset;
 320         uint32_t rom_data_offset;
 321
 322         if (bios == NULL)
 323                 return false;
 324         if (length_bytes == 0)
 325                 return false;
 326         /* APU vbios image is part of sbios image */
 327         if (adev->flags & AMD_IS_APU)
 328                 return false;
 329
 330         dw_ptr = (u32 *)bios;
 331         length_dw = ALIGN(length_bytes, 4) / 4;
 332
 333         switch (adev->asic_type) {
 334         case CHIP_VEGA20:
 335         case CHIP_ARCTURUS:
 336                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
 337                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
 338                 break;
 339         default:
 340                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
 341                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
 342                 break;
 343         }
 344
 345         /* set rom index to 0 */
 346         WREG32(rom_index_offset, 0);
 347         /* read out the rom data */
 348         for (i = 0; i < length_dw; i++)
 349                 dw_ptr[i] = RREG32(rom_data_offset);
 350
 351         return true;
 352 }
 353
 354 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 355         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 356         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 357         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 358         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 359         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 360         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 361         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 362         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 363         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 364         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 365         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 366         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 367         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 368         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 369         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 370         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 371         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 372         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 373         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 374         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 375 };
 376
 377 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 378                                          u32 sh_num, u32 reg_offset)
 379 {
 380         uint32_t val;
 381
 382         mutex_lock(&adev->grbm_idx_mutex);
 383         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 384                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 385
 386         val = RREG32(reg_offset);
 387
 388         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 389                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 390         mutex_unlock(&adev->grbm_idx_mutex);
 391         return val;
 392 }
 393
 394 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 395                                          bool indexed, u32 se_num,
 396                                          u32 sh_num, u32 reg_offset)
 397 {
 398         if (indexed) {
 399                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 400         } else {
 401                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 402                         return adev->gfx.config.gb_addr_config;
 403                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 404                         return adev->gfx.config.db_debug2;
 405                 return RREG32(reg_offset);
 406         }
 407 }
 408
 409 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 410                             u32 sh_num, u32 reg_offset, u32 *value)
 411 {
 412         uint32_t i;
 413         struct soc15_allowed_register_entry  *en;
 414
 415         *value = 0;
 416         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 417                 en = &soc15_allowed_read_registers[i];
 418                 if (adev->reg_offset[en->hwip][en->inst] &&
 419                         reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 420                                         + en->reg_offset))
 421                         continue;
 422
 423                 *value = soc15_get_register_value(adev,
 424                                                   soc15_allowed_read_registers[i].grbm_indexed,
 425                                                   se_num, sh_num, reg_offset);
 426                 return 0;
 427         }
 428         return -EINVAL;
 429 }
 430
 431
 432 /**
 433  * soc15_program_register_sequence - program an array of registers.
 434  *
 435  * @adev: amdgpu_device pointer
 436  * @regs: pointer to the register array
 437  * @array_size: size of the register array
 438  *
 439  * Programs an array or registers with and and or masks.
 440  * This is a helper for setting golden registers.
 441  */
 442
 443 void soc15_program_register_sequence(struct amdgpu_device *adev,
 444                                              const struct soc15_reg_golden *regs,
 445                                              const u32 array_size)
 446 {
 447         const struct soc15_reg_golden *entry;
 448         u32 tmp, reg;
 449         int i;
 450
 451         for (i = 0; i < array_size; ++i) {
 452                 entry = &regs[i];
 453                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 454
 455                 if (entry->and_mask == 0xffffffff) {
 456                         tmp = entry->or_mask;
 457                 } else {
 458                         tmp = RREG32(reg);
 459                         tmp &= ~(entry->and_mask);
 460                         tmp |= (entry->or_mask & entry->and_mask);
 461                 }
 462
 463                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 464                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 465                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 466                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 467                         WREG32_RLC(reg, tmp);
 468                 else
 469                         WREG32(reg, tmp);
 470
 471         }
 472
 473 }
 474
 475 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 476 {
 477         u32 i;
 478         int ret = 0;
 479
 480         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 481
 482         dev_info(adev->dev, "GPU mode1 reset\n");
 483
 484         /* disable BM */
 485         pci_clear_master(adev->pdev);
 486
 487         pci_save_state(adev->pdev);
 488
 489         ret = psp_gpu_reset(adev);
 490         if (ret)
 491                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 492
 493         pci_restore_state(adev->pdev);
 494
 495         /* wait for asic to come out of reset */
 496         for (i = 0; i < adev->usec_timeout; i++) {
 497                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 498
 499                 if (memsize != 0xffffffff)
 500                         break;
 501                 udelay(1);
 502         }
 503
 504         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 505
 506         return ret;
 507 }
 508
 509 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 510 {
 511         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 512         int ret = 0;
 513
 514         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 515         if (ras && ras->supported)
 516                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 517
 518         ret = amdgpu_dpm_baco_reset(adev);
 519         if (ret)
 520                 return ret;
 521
 522         /* re-enable doorbell interrupt after BACO exit */
 523         if (ras && ras->supported)
 524                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 525
 526         return 0;
 527 }
 528
 529 static enum amd_reset_method
 530 soc15_asic_reset_method(struct amdgpu_device *adev)
 531 {
 532         bool baco_reset = false;
 533         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 534
 535         switch (adev->asic_type) {
 536         case CHIP_RAVEN:
 537         case CHIP_RENOIR:
 538                 return AMD_RESET_METHOD_MODE2;
 539         case CHIP_VEGA10:
 540         case CHIP_VEGA12:
 541         case CHIP_ARCTURUS:
 542                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 543                 break;
 544         case CHIP_VEGA20:
 545                 if (adev->psp.sos_fw_version >= 0x80067)
 546                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 547
 548                 /*
 549                  * 1. PMFW version > 0x284300: all cases use baco
 550                  * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 551                  */
 552                 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
 553                         baco_reset = false;
 554                 break;
 555         default:
 556                 break;
 557         }
 558
 559         if (baco_reset)
 560                 return AMD_RESET_METHOD_BACO;
 561         else
 562                 return AMD_RESET_METHOD_MODE1;
 563 }
 564
 565 static int soc15_asic_reset(struct amdgpu_device *adev)
 566 {
 567         /* original raven doesn't have full asic reset */
 568         if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
 569             !(adev->apu_flags & AMD_APU_IS_RAVEN2))
 570                 return 0;
 571
 572         switch (soc15_asic_reset_method(adev)) {
 573                 case AMD_RESET_METHOD_BACO:
 574                         return soc15_asic_baco_reset(adev);
 575                 case AMD_RESET_METHOD_MODE2:
 576                         return amdgpu_dpm_mode2_reset(adev);
 577                 default:
 578                         return soc15_asic_mode1_reset(adev);
 579         }
 580 }
 581
 582 static bool soc15_supports_baco(struct amdgpu_device *adev)
 583 {
 584         switch (adev->asic_type) {
 585         case CHIP_VEGA10:
 586         case CHIP_VEGA12:
 587         case CHIP_ARCTURUS:
 588                 return amdgpu_dpm_is_baco_supported(adev);
 589         case CHIP_VEGA20:
 590                 if (adev->psp.sos_fw_version >= 0x80067)
 591                         return amdgpu_dpm_is_baco_supported(adev);
 592                 return false;
 593         default:
 594                 return false;
 595         }
 596 }
 597
 598 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 599                         u32 cntl_reg, u32 status_reg)
 600 {
 601         return 0;
 602 }*/
 603
 604 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 605 {
 606         /*int r;
 607
 608         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 609         if (r)
 610                 return r;
 611
 612         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 613         */
 614         return 0;
 615 }
 616
 617 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 618 {
 619         /* todo */
 620
 621         return 0;
 622 }
 623
 624 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 625 {
 626         if (pci_is_root_bus(adev->pdev->bus))
 627                 return;
 628
 629         if (amdgpu_pcie_gen2 == 0)
 630                 return;
 631
 632         if (adev->flags & AMD_IS_APU)
 633                 return;
 634
 635         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 636                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 637                 return;
 638
 639         /* todo */
 640 }
 641
 642 static void soc15_program_aspm(struct amdgpu_device *adev)
 643 {
 644
 645         if (amdgpu_aspm == 0)
 646                 return;
 647
 648         /* todo */
 649 }
 650
 651 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 652                                            bool enable)
 653 {
 654         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 655         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 656 }
 657
 658 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 659 {
 660         .type = AMD_IP_BLOCK_TYPE_COMMON,
 661         .major = 2,
 662         .minor = 0,
 663         .rev = 0,
 664         .funcs = &soc15_common_ip_funcs,
 665 };
 666
 667 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 668 {
 669         return adev->nbio.funcs->get_rev_id(adev);
 670 }
 671
 672 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 673 {
 674         int r;
 675
 676         /* Set IP register base before any HW register access */
 677         switch (adev->asic_type) {
 678         case CHIP_VEGA10:
 679         case CHIP_VEGA12:
 680         case CHIP_RAVEN:
 681                 vega10_reg_base_init(adev);
 682                 break;
 683         case CHIP_RENOIR:
 684                 if (amdgpu_discovery) {
 685                         r = amdgpu_discovery_reg_base_init(adev);
 686                         if (r) {
 687                                 DRM_WARN("failed to init reg base from ip discovery table, "
 688                                          "fallback to legacy init method\n");
 689                                 vega10_reg_base_init(adev);
 690                         }
 691                 }
 692                 break;
 693         case CHIP_VEGA20:
 694                 vega20_reg_base_init(adev);
 695                 break;
 696         case CHIP_ARCTURUS:
 697                 arct_reg_base_init(adev);
 698                 break;
 699         default:
 700                 return -EINVAL;
 701         }
 702
 703         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 704                 adev->gmc.xgmi.supported = true;
 705
 706         if (adev->flags & AMD_IS_APU) {
 707                 adev->nbio.funcs = &nbio_v7_0_funcs;
 708                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
 709         } else if (adev->asic_type == CHIP_VEGA20 ||
 710                    adev->asic_type == CHIP_ARCTURUS) {
 711                 adev->nbio.funcs = &nbio_v7_4_funcs;
 712                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
 713         } else {
 714                 adev->nbio.funcs = &nbio_v6_1_funcs;
 715                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
 716         }
 717
 718         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 719                 adev->df.funcs = &df_v3_6_funcs;
 720         else
 721                 adev->df.funcs = &df_v1_7_funcs;
 722
 723         adev->rev_id = soc15_get_rev_id(adev);
 724
 725         if (amdgpu_sriov_vf(adev))
 726                 adev->virt.ops = &xgpu_ai_virt_ops;
 727
 728         switch (adev->asic_type) {
 729         case CHIP_VEGA10:
 730         case CHIP_VEGA12:
 731         case CHIP_VEGA20:
 732                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 733                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 734
 735                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 736                 if (amdgpu_sriov_vf(adev)) {
 737                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 738                                 if (adev->asic_type == CHIP_VEGA20)
 739                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 740                                 else
 741                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 742                         }
 743                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 744                 } else {
 745                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 746                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 747                                 if (adev->asic_type == CHIP_VEGA20)
 748                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 749                                 else
 750                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 751                         }
 752                 }
 753                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 754                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 755                 if (is_support_sw_smu(adev)) {
 756                         if (!amdgpu_sriov_vf(adev))
 757                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 758                 } else {
 759                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 760                 }
 761                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 762                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 763 #if defined(CONFIG_DRM_AMD_DC)
 764                 else if (amdgpu_device_has_dc_support(adev))
 765                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 766 #endif
 767                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 768                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 769                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 770                 }
 771                 break;
 772         case CHIP_RAVEN:
 773                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 774                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 775                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 776                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 777                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 778                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 779                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 780                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 781                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 782                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 783 #if defined(CONFIG_DRM_AMD_DC)
 784                 else if (amdgpu_device_has_dc_support(adev))
 785                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 786 #endif
 787                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 788                 break;
 789         case CHIP_ARCTURUS:
 790                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 791                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 792
 793                 if (amdgpu_sriov_vf(adev)) {
 794                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 795                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 796                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 797                 } else {
 798                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 799                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 800                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 801                 }
 802
 803                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 804                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 805                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 806                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 807                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 808
 809                 if (amdgpu_sriov_vf(adev)) {
 810                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 811                                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 812                 } else {
 813                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 814                 }
 815                 if (!amdgpu_sriov_vf(adev))
 816                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 817                 break;
 818         case CHIP_RENOIR:
 819                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 820                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 821                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 822                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 823                         amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 824                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 825                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 826                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 827                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 828                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 829 #if defined(CONFIG_DRM_AMD_DC)
 830                 else if (amdgpu_device_has_dc_support(adev))
 831                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 832 #endif
 833                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 834                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 835                 break;
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 844 {
 845         adev->nbio.funcs->hdp_flush(adev, ring);
 846 }
 847
 848 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 849                                  struct amdgpu_ring *ring)
 850 {
 851         if (!ring || !ring->funcs->emit_wreg)
 852                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 853         else
 854                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 855                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 856 }
 857
 858 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 859 {
 860         /* change this when we implement soft reset */
 861         return true;
 862 }
 863
 864 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
 865 {
 866         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
 867                 return;
 868         /*read back hdp ras counter to reset it to 0 */
 869         RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
 870 }
 871
 872 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 873                                  uint64_t *count1)
 874 {
 875         uint32_t perfctr = 0;
 876         uint64_t cnt0_of, cnt1_of;
 877         int tmp;
 878
 879         /* This reports 0 on APUs, so return to avoid writing/reading registers
 880          * that may or may not be different from their GPU counterparts
 881          */
 882         if (adev->flags & AMD_IS_APU)
 883                 return;
 884
 885         /* Set the 2 events that we wish to watch, defined above */
 886         /* Reg 40 is # received msgs */
 887         /* Reg 104 is # of posted requests sent */
 888         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 889         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 890
 891         /* Write to enable desired perf counters */
 892         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 893         /* Zero out and enable the perf counters
 894          * Write 0x5:
 895          * Bit 0 = Start all counters(1)
 896          * Bit 2 = Global counter reset enable(1)
 897          */
 898         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 899
 900         msleep(1000);
 901
 902         /* Load the shadow and disable the perf counters
 903          * Write 0x2:
 904          * Bit 0 = Stop counters(0)
 905          * Bit 1 = Load the shadow counters(1)
 906          */
 907         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 908
 909         /* Read register values to get any >32bit overflow */
 910         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 911         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 912         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 913
 914         /* Get the values and add the overflow */
 915         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 916         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 917 }
 918
 919 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 920                                  uint64_t *count1)
 921 {
 922         uint32_t perfctr = 0;
 923         uint64_t cnt0_of, cnt1_of;
 924         int tmp;
 925
 926         /* This reports 0 on APUs, so return to avoid writing/reading registers
 927          * that may or may not be different from their GPU counterparts
 928          */
 929         if (adev->flags & AMD_IS_APU)
 930                 return;
 931
 932         /* Set the 2 events that we wish to watch, defined above */
 933         /* Reg 40 is # received msgs */
 934         /* Reg 108 is # of posted requests sent on VG20 */
 935         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 936                                 EVENT0_SEL, 40);
 937         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 938                                 EVENT1_SEL, 108);
 939
 940         /* Write to enable desired perf counters */
 941         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 942         /* Zero out and enable the perf counters
 943          * Write 0x5:
 944          * Bit 0 = Start all counters(1)
 945          * Bit 2 = Global counter reset enable(1)
 946          */
 947         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 948
 949         msleep(1000);
 950
 951         /* Load the shadow and disable the perf counters
 952          * Write 0x2:
 953          * Bit 0 = Stop counters(0)
 954          * Bit 1 = Load the shadow counters(1)
 955          */
 956         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 957
 958         /* Read register values to get any >32bit overflow */
 959         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 960         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 961         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 962
 963         /* Get the values and add the overflow */
 964         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 965         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 966 }
 967
 968 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 969 {
 970         u32 sol_reg;
 971
 972         /* Just return false for soc15 GPUs.  Reset does not seem to
 973          * be necessary.
 974          */
 975         if (!amdgpu_passthrough(adev))
 976                 return false;
 977
 978         if (adev->flags & AMD_IS_APU)
 979                 return false;
 980
 981         /* Check sOS sign of life register to confirm sys driver and sOS
 982          * are already been loaded.
 983          */
 984         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 985         if (sol_reg)
 986                 return true;
 987
 988         return false;
 989 }
 990
 991 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 992 {
 993         uint64_t nak_r, nak_g;
 994
 995         /* Get the number of NAKs received and generated */
 996         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 997         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 998
 999         /* Add the total number of NAKs, i.e the number of replays */
1000         return (nak_r + nak_g);
1001 }
1002
1003 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1004 {
1005         .read_disabled_bios = &soc15_read_disabled_bios,
1006         .read_bios_from_rom = &soc15_read_bios_from_rom,
1007         .read_register = &soc15_read_register,
1008         .reset = &soc15_asic_reset,
1009         .reset_method = &soc15_asic_reset_method,
1010         .set_vga_state = &soc15_vga_set_state,
1011         .get_xclk = &soc15_get_xclk,
1012         .set_uvd_clocks = &soc15_set_uvd_clocks,
1013         .set_vce_clocks = &soc15_set_vce_clocks,
1014         .get_config_memsize = &soc15_get_config_memsize,
1015         .flush_hdp = &soc15_flush_hdp,
1016         .invalidate_hdp = &soc15_invalidate_hdp,
1017         .need_full_reset = &soc15_need_full_reset,
1018         .init_doorbell_index = &vega10_doorbell_index_init,
1019         .get_pcie_usage = &soc15_get_pcie_usage,
1020         .need_reset_on_init = &soc15_need_reset_on_init,
1021         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1022         .supports_baco = &soc15_supports_baco,
1023 };
1024
1025 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1026 {
1027         .read_disabled_bios = &soc15_read_disabled_bios,
1028         .read_bios_from_rom = &soc15_read_bios_from_rom,
1029         .read_register = &soc15_read_register,
1030         .reset = &soc15_asic_reset,
1031         .reset_method = &soc15_asic_reset_method,
1032         .set_vga_state = &soc15_vga_set_state,
1033         .get_xclk = &soc15_get_xclk,
1034         .set_uvd_clocks = &soc15_set_uvd_clocks,
1035         .set_vce_clocks = &soc15_set_vce_clocks,
1036         .get_config_memsize = &soc15_get_config_memsize,
1037         .flush_hdp = &soc15_flush_hdp,
1038         .invalidate_hdp = &soc15_invalidate_hdp,
1039         .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1040         .need_full_reset = &soc15_need_full_reset,
1041         .init_doorbell_index = &vega20_doorbell_index_init,
1042         .get_pcie_usage = &vega20_get_pcie_usage,
1043         .need_reset_on_init = &soc15_need_reset_on_init,
1044         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1045         .supports_baco = &soc15_supports_baco,
1046 };
1047
1048 static int soc15_common_early_init(void *handle)
1049 {
1050 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1054         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1055         adev->smc_rreg = NULL;
1056         adev->smc_wreg = NULL;
1057         adev->pcie_rreg = &soc15_pcie_rreg;
1058         adev->pcie_wreg = &soc15_pcie_wreg;
1059         adev->pcie_rreg64 = &soc15_pcie_rreg64;
1060         adev->pcie_wreg64 = &soc15_pcie_wreg64;
1061         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1062         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1063         adev->didt_rreg = &soc15_didt_rreg;
1064         adev->didt_wreg = &soc15_didt_wreg;
1065         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1066         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1067         adev->se_cac_rreg = &soc15_se_cac_rreg;
1068         adev->se_cac_wreg = &soc15_se_cac_wreg;
1069
1070
1071         adev->external_rev_id = 0xFF;
1072         switch (adev->asic_type) {
1073         case CHIP_VEGA10:
1074                 adev->asic_funcs = &soc15_asic_funcs;
1075                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1076                         AMD_CG_SUPPORT_GFX_MGLS |
1077                         AMD_CG_SUPPORT_GFX_RLC_LS |
1078                         AMD_CG_SUPPORT_GFX_CP_LS |
1079                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1080                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1081                         AMD_CG_SUPPORT_GFX_CGCG |
1082                         AMD_CG_SUPPORT_GFX_CGLS |
1083                         AMD_CG_SUPPORT_BIF_MGCG |
1084                         AMD_CG_SUPPORT_BIF_LS |
1085                         AMD_CG_SUPPORT_HDP_LS |
1086                         AMD_CG_SUPPORT_DRM_MGCG |
1087                         AMD_CG_SUPPORT_DRM_LS |
1088                         AMD_CG_SUPPORT_ROM_MGCG |
1089                         AMD_CG_SUPPORT_DF_MGCG |
1090                         AMD_CG_SUPPORT_SDMA_MGCG |
1091                         AMD_CG_SUPPORT_SDMA_LS |
1092                         AMD_CG_SUPPORT_MC_MGCG |
1093                         AMD_CG_SUPPORT_MC_LS;
1094                 adev->pg_flags = 0;
1095                 adev->external_rev_id = 0x1;
1096                 break;
1097         case CHIP_VEGA12:
1098                 adev->asic_funcs = &soc15_asic_funcs;
1099                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1100                         AMD_CG_SUPPORT_GFX_MGLS |
1101                         AMD_CG_SUPPORT_GFX_CGCG |
1102                         AMD_CG_SUPPORT_GFX_CGLS |
1103                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1104                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1105                         AMD_CG_SUPPORT_GFX_CP_LS |
1106                         AMD_CG_SUPPORT_MC_LS |
1107                         AMD_CG_SUPPORT_MC_MGCG |
1108                         AMD_CG_SUPPORT_SDMA_MGCG |
1109                         AMD_CG_SUPPORT_SDMA_LS |
1110                         AMD_CG_SUPPORT_BIF_MGCG |
1111                         AMD_CG_SUPPORT_BIF_LS |
1112                         AMD_CG_SUPPORT_HDP_MGCG |
1113                         AMD_CG_SUPPORT_HDP_LS |
1114                         AMD_CG_SUPPORT_ROM_MGCG |
1115                         AMD_CG_SUPPORT_VCE_MGCG |
1116                         AMD_CG_SUPPORT_UVD_MGCG;
1117                 adev->pg_flags = 0;
1118                 adev->external_rev_id = adev->rev_id + 0x14;
1119                 break;
1120         case CHIP_VEGA20:
1121                 adev->asic_funcs = &vega20_asic_funcs;
1122                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1123                         AMD_CG_SUPPORT_GFX_MGLS |
1124                         AMD_CG_SUPPORT_GFX_CGCG |
1125                         AMD_CG_SUPPORT_GFX_CGLS |
1126                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1127                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1128                         AMD_CG_SUPPORT_GFX_CP_LS |
1129                         AMD_CG_SUPPORT_MC_LS |
1130                         AMD_CG_SUPPORT_MC_MGCG |
1131                         AMD_CG_SUPPORT_SDMA_MGCG |
1132                         AMD_CG_SUPPORT_SDMA_LS |
1133                         AMD_CG_SUPPORT_BIF_MGCG |
1134                         AMD_CG_SUPPORT_BIF_LS |
1135                         AMD_CG_SUPPORT_HDP_MGCG |
1136                         AMD_CG_SUPPORT_HDP_LS |
1137                         AMD_CG_SUPPORT_ROM_MGCG |
1138                         AMD_CG_SUPPORT_VCE_MGCG |
1139                         AMD_CG_SUPPORT_UVD_MGCG;
1140                 adev->pg_flags = 0;
1141                 adev->external_rev_id = adev->rev_id + 0x28;
1142                 break;
1143         case CHIP_RAVEN:
1144                 adev->asic_funcs = &soc15_asic_funcs;
1145                 if (adev->pdev->device == 0x15dd)
1146                         adev->apu_flags |= AMD_APU_IS_RAVEN;
1147                 if (adev->pdev->device == 0x15d8)
1148                         adev->apu_flags |= AMD_APU_IS_PICASSO;
1149                 if (adev->rev_id >= 0x8)
1150                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
1151
1152                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1153                         adev->external_rev_id = adev->rev_id + 0x79;
1154                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1155                         adev->external_rev_id = adev->rev_id + 0x41;
1156                 else if (adev->rev_id == 1)
1157                         adev->external_rev_id = adev->rev_id + 0x20;
1158                 else
1159                         adev->external_rev_id = adev->rev_id + 0x01;
1160
1161                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1162                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1163                                 AMD_CG_SUPPORT_GFX_MGLS |
1164                                 AMD_CG_SUPPORT_GFX_CP_LS |
1165                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1166                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1167                                 AMD_CG_SUPPORT_GFX_CGCG |
1168                                 AMD_CG_SUPPORT_GFX_CGLS |
1169                                 AMD_CG_SUPPORT_BIF_LS |
1170                                 AMD_CG_SUPPORT_HDP_LS |
1171                                 AMD_CG_SUPPORT_ROM_MGCG |
1172                                 AMD_CG_SUPPORT_MC_MGCG |
1173                                 AMD_CG_SUPPORT_MC_LS |
1174                                 AMD_CG_SUPPORT_SDMA_MGCG |
1175                                 AMD_CG_SUPPORT_SDMA_LS |
1176                                 AMD_CG_SUPPORT_VCN_MGCG;
1177
1178                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1179                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1180                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181                                 AMD_CG_SUPPORT_GFX_MGLS |
1182                                 AMD_CG_SUPPORT_GFX_CP_LS |
1183                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1184                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1185                                 AMD_CG_SUPPORT_GFX_CGCG |
1186                                 AMD_CG_SUPPORT_GFX_CGLS |
1187                                 AMD_CG_SUPPORT_BIF_LS |
1188                                 AMD_CG_SUPPORT_HDP_LS |
1189                                 AMD_CG_SUPPORT_ROM_MGCG |
1190                                 AMD_CG_SUPPORT_MC_MGCG |
1191                                 AMD_CG_SUPPORT_MC_LS |
1192                                 AMD_CG_SUPPORT_SDMA_MGCG |
1193                                 AMD_CG_SUPPORT_SDMA_LS;
1194
1195                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1196                                 AMD_PG_SUPPORT_MMHUB |
1197                                 AMD_PG_SUPPORT_VCN |
1198                                 AMD_PG_SUPPORT_VCN_DPG;
1199                 } else {
1200                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1201                                 AMD_CG_SUPPORT_GFX_MGLS |
1202                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1203                                 AMD_CG_SUPPORT_GFX_CP_LS |
1204                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1205                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1206                                 AMD_CG_SUPPORT_GFX_CGCG |
1207                                 AMD_CG_SUPPORT_GFX_CGLS |
1208                                 AMD_CG_SUPPORT_BIF_MGCG |
1209                                 AMD_CG_SUPPORT_BIF_LS |
1210                                 AMD_CG_SUPPORT_HDP_MGCG |
1211                                 AMD_CG_SUPPORT_HDP_LS |
1212                                 AMD_CG_SUPPORT_DRM_MGCG |
1213                                 AMD_CG_SUPPORT_DRM_LS |
1214                                 AMD_CG_SUPPORT_ROM_MGCG |
1215                                 AMD_CG_SUPPORT_MC_MGCG |
1216                                 AMD_CG_SUPPORT_MC_LS |
1217                                 AMD_CG_SUPPORT_SDMA_MGCG |
1218                                 AMD_CG_SUPPORT_SDMA_LS |
1219                                 AMD_CG_SUPPORT_VCN_MGCG;
1220
1221                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1222                 }
1223                 break;
1224         case CHIP_ARCTURUS:
1225                 adev->asic_funcs = &vega20_asic_funcs;
1226                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1227                         AMD_CG_SUPPORT_GFX_MGLS |
1228                         AMD_CG_SUPPORT_GFX_CGCG |
1229                         AMD_CG_SUPPORT_GFX_CGLS |
1230                         AMD_CG_SUPPORT_GFX_CP_LS |
1231                         AMD_CG_SUPPORT_HDP_MGCG |
1232                         AMD_CG_SUPPORT_HDP_LS |
1233                         AMD_CG_SUPPORT_SDMA_MGCG |
1234                         AMD_CG_SUPPORT_SDMA_LS |
1235                         AMD_CG_SUPPORT_MC_MGCG |
1236                         AMD_CG_SUPPORT_MC_LS |
1237                         AMD_CG_SUPPORT_IH_CG |
1238                         AMD_CG_SUPPORT_VCN_MGCG |
1239                         AMD_CG_SUPPORT_JPEG_MGCG;
1240                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1241                 adev->external_rev_id = adev->rev_id + 0x32;
1242                 break;
1243         case CHIP_RENOIR:
1244                 adev->asic_funcs = &soc15_asic_funcs;
1245                 adev->apu_flags |= AMD_APU_IS_RENOIR;
1246                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1247                                  AMD_CG_SUPPORT_GFX_MGLS |
1248                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1249                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1250                                  AMD_CG_SUPPORT_GFX_CGCG |
1251                                  AMD_CG_SUPPORT_GFX_CGLS |
1252                                  AMD_CG_SUPPORT_GFX_CP_LS |
1253                                  AMD_CG_SUPPORT_MC_MGCG |
1254                                  AMD_CG_SUPPORT_MC_LS |
1255                                  AMD_CG_SUPPORT_SDMA_MGCG |
1256                                  AMD_CG_SUPPORT_SDMA_LS |
1257                                  AMD_CG_SUPPORT_BIF_LS |
1258                                  AMD_CG_SUPPORT_HDP_LS |
1259                                  AMD_CG_SUPPORT_ROM_MGCG |
1260                                  AMD_CG_SUPPORT_VCN_MGCG |
1261                                  AMD_CG_SUPPORT_JPEG_MGCG |
1262                                  AMD_CG_SUPPORT_IH_CG |
1263                                  AMD_CG_SUPPORT_ATHUB_LS |
1264                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1265                                  AMD_CG_SUPPORT_DF_MGCG;
1266                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1267                                  AMD_PG_SUPPORT_VCN |
1268                                  AMD_PG_SUPPORT_JPEG |
1269                                  AMD_PG_SUPPORT_VCN_DPG;
1270                 adev->external_rev_id = adev->rev_id + 0x91;
1271                 break;
1272         default:
1273                 /* FIXME: not supported yet */
1274                 return -EINVAL;
1275         }
1276
1277         if (amdgpu_sriov_vf(adev)) {
1278                 amdgpu_virt_init_setting(adev);
1279                 xgpu_ai_mailbox_set_irq_funcs(adev);
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int soc15_common_late_init(void *handle)
1286 {
1287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288         int r = 0;
1289
1290         if (amdgpu_sriov_vf(adev))
1291                 xgpu_ai_mailbox_get_irq(adev);
1292
1293         if (adev->asic_funcs &&
1294             adev->asic_funcs->reset_hdp_ras_error_count)
1295                 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1296
1297         if (adev->nbio.funcs->ras_late_init)
1298                 r = adev->nbio.funcs->ras_late_init(adev);
1299
1300         return r;
1301 }
1302
1303 static int soc15_common_sw_init(void *handle)
1304 {
1305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306
1307         if (amdgpu_sriov_vf(adev))
1308                 xgpu_ai_mailbox_add_irq_id(adev);
1309
1310         adev->df.funcs->sw_init(adev);
1311
1312         return 0;
1313 }
1314
1315 static int soc15_common_sw_fini(void *handle)
1316 {
1317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319         amdgpu_nbio_ras_fini(adev);
1320         adev->df.funcs->sw_fini(adev);
1321         return 0;
1322 }
1323
1324 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1325 {
1326         int i;
1327         struct amdgpu_ring *ring;
1328
1329         /* sdma/ih doorbell range are programed by hypervisor */
1330         if (!amdgpu_sriov_vf(adev)) {
1331                 for (i = 0; i < adev->sdma.num_instances; i++) {
1332                         ring = &adev->sdma.instance[i].ring;
1333                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1334                                 ring->use_doorbell, ring->doorbell_index,
1335                                 adev->doorbell_index.sdma_doorbell_range);
1336                 }
1337
1338                 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1339                                                 adev->irq.ih.doorbell_index);
1340         }
1341 }
1342
1343 static int soc15_common_hw_init(void *handle)
1344 {
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         /* enable pcie gen2/3 link */
1348         soc15_pcie_gen3_enable(adev);
1349         /* enable aspm */
1350         soc15_program_aspm(adev);
1351         /* setup nbio registers */
1352         adev->nbio.funcs->init_registers(adev);
1353         /* remap HDP registers to a hole in mmio space,
1354          * for the purpose of expose those registers
1355          * to process space
1356          */
1357         if (adev->nbio.funcs->remap_hdp_registers)
1358                 adev->nbio.funcs->remap_hdp_registers(adev);
1359
1360         /* enable the doorbell aperture */
1361         soc15_enable_doorbell_aperture(adev, true);
1362         /* HW doorbell routing policy: doorbell writing not
1363          * in SDMA/IH/MM/ACV range will be routed to CP. So
1364          * we need to init SDMA/IH/MM/ACV doorbell range prior
1365          * to CP ip block init and ring test.
1366          */
1367         soc15_doorbell_range_init(adev);
1368
1369         return 0;
1370 }
1371
1372 static int soc15_common_hw_fini(void *handle)
1373 {
1374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376         /* disable the doorbell aperture */
1377         soc15_enable_doorbell_aperture(adev, false);
1378         if (amdgpu_sriov_vf(adev))
1379                 xgpu_ai_mailbox_put_irq(adev);
1380
1381         if (adev->nbio.ras_if &&
1382             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1383                 if (adev->nbio.funcs->init_ras_controller_interrupt)
1384                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1385                 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1386                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1387         }
1388
1389         return 0;
1390 }
1391
1392 static int soc15_common_suspend(void *handle)
1393 {
1394         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1395
1396         return soc15_common_hw_fini(adev);
1397 }
1398
1399 static int soc15_common_resume(void *handle)
1400 {
1401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1402
1403         return soc15_common_hw_init(adev);
1404 }
1405
1406 static bool soc15_common_is_idle(void *handle)
1407 {
1408         return true;
1409 }
1410
1411 static int soc15_common_wait_for_idle(void *handle)
1412 {
1413         return 0;
1414 }
1415
1416 static int soc15_common_soft_reset(void *handle)
1417 {
1418         return 0;
1419 }
1420
1421 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1422 {
1423         uint32_t def, data;
1424
1425         if (adev->asic_type == CHIP_VEGA20 ||
1426                 adev->asic_type == CHIP_ARCTURUS) {
1427                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1428
1429                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1430                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1431                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1432                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1433                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1434                 else
1435                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1436                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1437                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1438                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1439
1440                 if (def != data)
1441                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1442         } else {
1443                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1444
1445                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1446                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1447                 else
1448                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1449
1450                 if (def != data)
1451                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1452         }
1453 }
1454
1455 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1456 {
1457         uint32_t def, data;
1458
1459         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1460
1461         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1462                 data &= ~(0x01000000 |
1463                           0x02000000 |
1464                           0x04000000 |
1465                           0x08000000 |
1466                           0x10000000 |
1467                           0x20000000 |
1468                           0x40000000 |
1469                           0x80000000);
1470         else
1471                 data |= (0x01000000 |
1472                          0x02000000 |
1473                          0x04000000 |
1474                          0x08000000 |
1475                          0x10000000 |
1476                          0x20000000 |
1477                          0x40000000 |
1478                          0x80000000);
1479
1480         if (def != data)
1481                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1482 }
1483
1484 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1485 {
1486         uint32_t def, data;
1487
1488         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1489
1490         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1491                 data |= 1;
1492         else
1493                 data &= ~1;
1494
1495         if (def != data)
1496                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1497 }
1498
1499 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1500                                                        bool enable)
1501 {
1502         uint32_t def, data;
1503
1504         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1505
1506         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1507                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1508                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1509         else
1510                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1511                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1512
1513         if (def != data)
1514                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1515 }
1516
1517 static int soc15_common_set_clockgating_state(void *handle,
1518                                             enum amd_clockgating_state state)
1519 {
1520         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1521
1522         if (amdgpu_sriov_vf(adev))
1523                 return 0;
1524
1525         switch (adev->asic_type) {
1526         case CHIP_VEGA10:
1527         case CHIP_VEGA12:
1528         case CHIP_VEGA20:
1529                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1530                                 state == AMD_CG_STATE_GATE);
1531                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1532                                 state == AMD_CG_STATE_GATE);
1533                 soc15_update_hdp_light_sleep(adev,
1534                                 state == AMD_CG_STATE_GATE);
1535                 soc15_update_drm_clock_gating(adev,
1536                                 state == AMD_CG_STATE_GATE);
1537                 soc15_update_drm_light_sleep(adev,
1538                                 state == AMD_CG_STATE_GATE);
1539                 soc15_update_rom_medium_grain_clock_gating(adev,
1540                                 state == AMD_CG_STATE_GATE);
1541                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1542                                 state == AMD_CG_STATE_GATE);
1543                 break;
1544         case CHIP_RAVEN:
1545         case CHIP_RENOIR:
1546                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1547                                 state == AMD_CG_STATE_GATE);
1548                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1549                                 state == AMD_CG_STATE_GATE);
1550                 soc15_update_hdp_light_sleep(adev,
1551                                 state == AMD_CG_STATE_GATE);
1552                 soc15_update_drm_clock_gating(adev,
1553                                 state == AMD_CG_STATE_GATE);
1554                 soc15_update_drm_light_sleep(adev,
1555                                 state == AMD_CG_STATE_GATE);
1556                 soc15_update_rom_medium_grain_clock_gating(adev,
1557                                 state == AMD_CG_STATE_GATE);
1558                 break;
1559         case CHIP_ARCTURUS:
1560                 soc15_update_hdp_light_sleep(adev,
1561                                 state == AMD_CG_STATE_GATE);
1562                 break;
1563         default:
1564                 break;
1565         }
1566         return 0;
1567 }
1568
1569 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1570 {
1571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1572         int data;
1573
1574         if (amdgpu_sriov_vf(adev))
1575                 *flags = 0;
1576
1577         adev->nbio.funcs->get_clockgating_state(adev, flags);
1578
1579         /* AMD_CG_SUPPORT_HDP_LS */
1580         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1581         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1582                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1583
1584         /* AMD_CG_SUPPORT_DRM_MGCG */
1585         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1586         if (!(data & 0x01000000))
1587                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1588
1589         /* AMD_CG_SUPPORT_DRM_LS */
1590         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1591         if (data & 0x1)
1592                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1593
1594         /* AMD_CG_SUPPORT_ROM_MGCG */
1595         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1596         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1597                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1598
1599         adev->df.funcs->get_clockgating_state(adev, flags);
1600 }
1601
1602 static int soc15_common_set_powergating_state(void *handle,
1603                                             enum amd_powergating_state state)
1604 {
1605         /* todo */
1606         return 0;
1607 }
1608
1609 const struct amd_ip_funcs soc15_common_ip_funcs = {
1610         .name = "soc15_common",
1611         .early_init = soc15_common_early_init,
1612         .late_init = soc15_common_late_init,
1613         .sw_init = soc15_common_sw_init,
1614         .sw_fini = soc15_common_sw_fini,
1615         .hw_init = soc15_common_hw_init,
1616         .hw_fini = soc15_common_hw_fini,
1617         .suspend = soc15_common_suspend,
1618         .resume = soc15_common_resume,
1619         .is_idle = soc15_common_is_idle,
1620         .wait_for_idle = soc15_common_wait_for_idle,
1621         .soft_reset = soc15_common_soft_reset,
1622         .set_clockgating_state = soc15_common_set_clockgating_state,
1623         .set_powergating_state = soc15_common_set_powergating_state,
1624         .get_clockgating_state= soc15_common_get_clockgating_state,
1625 };