drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v5_0.h"
  45
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  48
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  54
  55 #define SDMA1_REG_OFFSET 0x600
  56 #define SDMA0_HYP_DEC_REG_START 0x5880
  57 #define SDMA0_HYP_DEC_REG_END 0x5893
  58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  59
  60 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  64
  65 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  90 };
  91
  92 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113 };
 114
 115 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 118 };
 119
 120 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 123 };
 124
 125 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 128 };
 129
 130 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 131 {
 132         u32 base;
 133
 134         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 135             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 136                 base = adev->reg_offset[GC_HWIP][0][1];
 137                 if (instance == 1)
 138                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 139         } else {
 140                 base = adev->reg_offset[GC_HWIP][0][0];
 141                 if (instance == 1)
 142                         internal_offset += SDMA1_REG_OFFSET;
 143         }
 144
 145         return base + internal_offset;
 146 }
 147
 148 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 149 {
 150         switch (adev->asic_type) {
 151         case CHIP_NAVI10:
 152                 soc15_program_register_sequence(adev,
 153                                                 golden_settings_sdma_5,
 154                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 155                 soc15_program_register_sequence(adev,
 156                                                 golden_settings_sdma_nv10,
 157                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 158                 break;
 159         case CHIP_NAVI14:
 160                 soc15_program_register_sequence(adev,
 161                                                 golden_settings_sdma_5,
 162                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 163                 soc15_program_register_sequence(adev,
 164                                                 golden_settings_sdma_nv14,
 165                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 166                 break;
 167         case CHIP_NAVI12:
 168                 if (amdgpu_sriov_vf(adev))
 169                         soc15_program_register_sequence(adev,
 170                                                         golden_settings_sdma_5_sriov,
 171                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 172                 else
 173                         soc15_program_register_sequence(adev,
 174                                                         golden_settings_sdma_5,
 175                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 176                 soc15_program_register_sequence(adev,
 177                                                 golden_settings_sdma_nv12,
 178                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 179                 break;
 180         default:
 181                 break;
 182         }
 183 }
 184
 185 /**
 186  * sdma_v5_0_init_microcode - load ucode images from disk
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Use the firmware interface to load the ucode images into
 191  * the driver (not loaded into hw).
 192  * Returns 0 on success, error on failure.
 193  */
 194
 195 // emulation only, won't work on real chip
 196 // navi10 real chip need to use PSP to load firmware
 197 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 198 {
 199         const char *chip_name;
 200         char fw_name[30];
 201         int err = 0, i;
 202         struct amdgpu_firmware_info *info = NULL;
 203         const struct common_firmware_header *header = NULL;
 204         const struct sdma_firmware_header_v1_0 *hdr;
 205
 206         DRM_DEBUG("\n");
 207
 208         switch (adev->asic_type) {
 209         case CHIP_NAVI10:
 210                 chip_name = "navi10";
 211                 break;
 212         case CHIP_NAVI14:
 213                 chip_name = "navi14";
 214                 break;
 215         case CHIP_NAVI12:
 216                 chip_name = "navi12";
 217                 break;
 218         default:
 219                 BUG();
 220         }
 221
 222         for (i = 0; i < adev->sdma.num_instances; i++) {
 223                 if (i == 0)
 224                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 225                 else
 226                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 227                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 228                 if (err)
 229                         goto out;
 230                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 231                 if (err)
 232                         goto out;
 233                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 234                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 235                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 236                 if (adev->sdma.instance[i].feature_version >= 20)
 237                         adev->sdma.instance[i].burst_nop = true;
 238                 DRM_DEBUG("psp_load == '%s'\n",
 239                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 240
 241                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 242                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 243                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 244                         info->fw = adev->sdma.instance[i].fw;
 245                         header = (const struct common_firmware_header *)info->fw->data;
 246                         adev->firmware.fw_size +=
 247                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 248                 }
 249         }
 250 out:
 251         if (err) {
 252                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 253                 for (i = 0; i < adev->sdma.num_instances; i++) {
 254                         release_firmware(adev->sdma.instance[i].fw);
 255                         adev->sdma.instance[i].fw = NULL;
 256                 }
 257         }
 258         return err;
 259 }
 260
 261 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 262 {
 263         unsigned ret;
 264
 265         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 266         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 267         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 268         amdgpu_ring_write(ring, 1);
 269         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 270         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 271
 272         return ret;
 273 }
 274
 275 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 276                                            unsigned offset)
 277 {
 278         unsigned cur;
 279
 280         BUG_ON(offset > ring->buf_mask);
 281         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 282
 283         cur = (ring->wptr - 1) & ring->buf_mask;
 284         if (cur > offset)
 285                 ring->ring[offset] = cur - offset;
 286         else
 287                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 288 }
 289
 290 /**
 291  * sdma_v5_0_ring_get_rptr - get the current read pointer
 292  *
 293  * @ring: amdgpu ring pointer
 294  *
 295  * Get the current rptr from the hardware (NAVI10+).
 296  */
 297 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 298 {
 299         u64 *rptr;
 300
 301         /* XXX check if swapping is necessary on BE */
 302         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 303
 304         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 305         return ((*rptr) >> 2);
 306 }
 307
 308 /**
 309  * sdma_v5_0_ring_get_wptr - get the current write pointer
 310  *
 311  * @ring: amdgpu ring pointer
 312  *
 313  * Get the current wptr from the hardware (NAVI10+).
 314  */
 315 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 316 {
 317         struct amdgpu_device *adev = ring->adev;
 318         u64 *wptr = NULL;
 319         uint64_t local_wptr = 0;
 320
 321         if (ring->use_doorbell) {
 322                 /* XXX check if swapping is necessary on BE */
 323                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 324                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 325                 *wptr = (*wptr) >> 2;
 326                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 327         } else {
 328                 u32 lowbit, highbit;
 329
 330                 wptr = &local_wptr;
 331                 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 332                 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 333
 334                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 335                                 ring->me, highbit, lowbit);
 336                 *wptr = highbit;
 337                 *wptr = (*wptr) << 32;
 338                 *wptr |= lowbit;
 339         }
 340
 341         return *wptr;
 342 }
 343
 344 /**
 345  * sdma_v5_0_ring_set_wptr - commit the write pointer
 346  *
 347  * @ring: amdgpu ring pointer
 348  *
 349  * Write the wptr back to the hardware (NAVI10+).
 350  */
 351 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 352 {
 353         struct amdgpu_device *adev = ring->adev;
 354
 355         DRM_DEBUG("Setting write pointer\n");
 356         if (ring->use_doorbell) {
 357                 DRM_DEBUG("Using doorbell -- "
 358                                 "wptr_offs == 0x%08x "
 359                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 360                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 361                                 ring->wptr_offs,
 362                                 lower_32_bits(ring->wptr << 2),
 363                                 upper_32_bits(ring->wptr << 2));
 364                 /* XXX check if swapping is necessary on BE */
 365                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 366                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 367                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 368                                 ring->doorbell_index, ring->wptr << 2);
 369                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 370         } else {
 371                 DRM_DEBUG("Not using doorbell -- "
 372                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 373                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 374                                 ring->me,
 375                                 lower_32_bits(ring->wptr << 2),
 376                                 ring->me,
 377                                 upper_32_bits(ring->wptr << 2));
 378                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 379                         lower_32_bits(ring->wptr << 2));
 380                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 381                         upper_32_bits(ring->wptr << 2));
 382         }
 383 }
 384
 385 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 386 {
 387         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 388         int i;
 389
 390         for (i = 0; i < count; i++)
 391                 if (sdma && sdma->burst_nop && (i == 0))
 392                         amdgpu_ring_write(ring, ring->funcs->nop |
 393                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 394                 else
 395                         amdgpu_ring_write(ring, ring->funcs->nop);
 396 }
 397
 398 /**
 399  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 400  *
 401  * @ring: amdgpu ring pointer
 402  * @ib: IB object to schedule
 403  *
 404  * Schedule an IB in the DMA ring (NAVI10).
 405  */
 406 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 407                                    struct amdgpu_job *job,
 408                                    struct amdgpu_ib *ib,
 409                                    uint32_t flags)
 410 {
 411         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 412         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 413
 414         /* Invalidate L2, because if we don't do it, we might get stale cache
 415          * lines from previous IBs.
 416          */
 417         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 418         amdgpu_ring_write(ring, 0);
 419         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 420                                  SDMA_GCR_GL2_WB |
 421                                  SDMA_GCR_GLM_INV |
 422                                  SDMA_GCR_GLM_WB) << 16);
 423         amdgpu_ring_write(ring, 0xffffff80);
 424         amdgpu_ring_write(ring, 0xffff);
 425
 426         /* An IB packet must end on a 8 DW boundary--the next dword
 427          * must be on a 8-dword boundary. Our IB packet below is 6
 428          * dwords long, thus add x number of NOPs, such that, in
 429          * modular arithmetic,
 430          * wptr + 6 + x = 8k, k >= 0, which in C is,
 431          * (wptr + 6 + x) % 8 = 0.
 432          * The expression below, is a solution of x.
 433          */
 434         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 435
 436         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 437                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 438         /* base must be 32 byte aligned */
 439         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 440         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 441         amdgpu_ring_write(ring, ib->length_dw);
 442         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 443         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 444 }
 445
 446 /**
 447  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 448  *
 449  * @ring: amdgpu ring pointer
 450  *
 451  * Emit an hdp flush packet on the requested DMA ring.
 452  */
 453 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 454 {
 455         struct amdgpu_device *adev = ring->adev;
 456         u32 ref_and_mask = 0;
 457         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 458
 459         if (ring->me == 0)
 460                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 461         else
 462                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 463
 464         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 465                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 466                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 467         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 468         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 469         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 470         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 471         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 472                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 473 }
 474
 475 /**
 476  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 477  *
 478  * @ring: amdgpu ring pointer
 479  * @fence: amdgpu fence object
 480  *
 481  * Add a DMA fence packet to the ring to write
 482  * the fence seq number and DMA trap packet to generate
 483  * an interrupt if needed (NAVI10).
 484  */
 485 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 486                                       unsigned flags)
 487 {
 488         struct amdgpu_device *adev = ring->adev;
 489         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 490         /* write the fence */
 491         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 492                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 493         /* zero in first two bits */
 494         BUG_ON(addr & 0x3);
 495         amdgpu_ring_write(ring, lower_32_bits(addr));
 496         amdgpu_ring_write(ring, upper_32_bits(addr));
 497         amdgpu_ring_write(ring, lower_32_bits(seq));
 498
 499         /* optionally write high bits as well */
 500         if (write64bit) {
 501                 addr += 4;
 502                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 503                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 504                 /* zero in first two bits */
 505                 BUG_ON(addr & 0x3);
 506                 amdgpu_ring_write(ring, lower_32_bits(addr));
 507                 amdgpu_ring_write(ring, upper_32_bits(addr));
 508                 amdgpu_ring_write(ring, upper_32_bits(seq));
 509         }
 510
 511         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 512         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 513                 /* generate an interrupt */
 514                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 515                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 516         }
 517 }
 518
 519
 520 /**
 521  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 522  *
 523  * @adev: amdgpu_device pointer
 524  *
 525  * Stop the gfx async dma ring buffers (NAVI10).
 526  */
 527 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 528 {
 529         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 530         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 531         u32 rb_cntl, ib_cntl;
 532         int i;
 533
 534         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 535             (adev->mman.buffer_funcs_ring == sdma1))
 536                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 537
 538         for (i = 0; i < adev->sdma.num_instances; i++) {
 539                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 540                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 541                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 542                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 543                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 544                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 545         }
 546 }
 547
 548 /**
 549  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 550  *
 551  * @adev: amdgpu_device pointer
 552  *
 553  * Stop the compute async dma queues (NAVI10).
 554  */
 555 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 556 {
 557         /* XXX todo */
 558 }
 559
 560 /**
 561  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 562  *
 563  * @adev: amdgpu_device pointer
 564  * @enable: enable/disable the DMA MEs context switch.
 565  *
 566  * Halt or unhalt the async dma engines context switch (NAVI10).
 567  */
 568 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 569 {
 570         u32 f32_cntl = 0, phase_quantum = 0;
 571         int i;
 572
 573         if (amdgpu_sdma_phase_quantum) {
 574                 unsigned value = amdgpu_sdma_phase_quantum;
 575                 unsigned unit = 0;
 576
 577                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 578                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 579                         value = (value + 1) >> 1;
 580                         unit++;
 581                 }
 582                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 583                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 584                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 585                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 586                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 587                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 588                         WARN_ONCE(1,
 589                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 590                                   value << unit);
 591                 }
 592                 phase_quantum =
 593                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 594                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 595         }
 596
 597         for (i = 0; i < adev->sdma.num_instances; i++) {
 598                 if (!amdgpu_sriov_vf(adev)) {
 599                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 600                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 601                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 602                 }
 603
 604                 if (enable && amdgpu_sdma_phase_quantum) {
 605                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 606                                phase_quantum);
 607                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 608                                phase_quantum);
 609                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 610                                phase_quantum);
 611                 }
 612                 if (!amdgpu_sriov_vf(adev))
 613                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 614         }
 615
 616 }
 617
 618 /**
 619  * sdma_v5_0_enable - stop the async dma engines
 620  *
 621  * @adev: amdgpu_device pointer
 622  * @enable: enable/disable the DMA MEs.
 623  *
 624  * Halt or unhalt the async dma engines (NAVI10).
 625  */
 626 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 627 {
 628         u32 f32_cntl;
 629         int i;
 630
 631         if (enable == false) {
 632                 sdma_v5_0_gfx_stop(adev);
 633                 sdma_v5_0_rlc_stop(adev);
 634         }
 635
 636         if (amdgpu_sriov_vf(adev))
 637                 return;
 638
 639         for (i = 0; i < adev->sdma.num_instances; i++) {
 640                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 641                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 642                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 643         }
 644 }
 645
 646 /**
 647  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 648  *
 649  * @adev: amdgpu_device pointer
 650  *
 651  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 652  * Returns 0 for success, error for failure.
 653  */
 654 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 655 {
 656         struct amdgpu_ring *ring;
 657         u32 rb_cntl, ib_cntl;
 658         u32 rb_bufsz;
 659         u32 wb_offset;
 660         u32 doorbell;
 661         u32 doorbell_offset;
 662         u32 temp;
 663         u32 wptr_poll_cntl;
 664         u64 wptr_gpu_addr;
 665         int i, r;
 666
 667         for (i = 0; i < adev->sdma.num_instances; i++) {
 668                 ring = &adev->sdma.instance[i].ring;
 669                 wb_offset = (ring->rptr_offs * 4);
 670
 671                 if (!amdgpu_sriov_vf(adev))
 672                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 673
 674                 /* Set ring buffer size in dwords */
 675                 rb_bufsz = order_base_2(ring->ring_size / 4);
 676                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 677                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 678 #ifdef __BIG_ENDIAN
 679                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 680                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 681                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 682 #endif
 683                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 684
 685                 /* Initialize the ring buffer's read and write pointers */
 686                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 687                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 688                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 689                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 690
 691                 /* setup the wptr shadow polling */
 692                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 693                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 694                        lower_32_bits(wptr_gpu_addr));
 695                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 696                        upper_32_bits(wptr_gpu_addr));
 697                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 698                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 699                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 700                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 701                                                F32_POLL_ENABLE, 1);
 702                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 703                        wptr_poll_cntl);
 704
 705                 /* set the wb address whether it's enabled or not */
 706                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 707                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 708                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 709                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 710
 711                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 712
 713                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 714                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 715
 716                 ring->wptr = 0;
 717
 718                 /* before programing wptr to a less value, need set minor_ptr_update first */
 719                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 720
 721                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 722                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 723                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 724                 }
 725
 726                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 727                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 728
 729                 if (ring->use_doorbell) {
 730                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 731                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 732                                         OFFSET, ring->doorbell_index);
 733                 } else {
 734                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 735                 }
 736                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 737                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 738
 739                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 740                                                       ring->doorbell_index, 20);
 741
 742                 if (amdgpu_sriov_vf(adev))
 743                         sdma_v5_0_ring_set_wptr(ring);
 744
 745                 /* set minor_ptr_update to 0 after wptr programed */
 746                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 747
 748                 if (!amdgpu_sriov_vf(adev)) {
 749                         /* set utc l1 enable flag always to 1 */
 750                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 751                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 752
 753                         /* enable MCBP */
 754                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 755                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 756
 757                         /* Set up RESP_MODE to non-copy addresses */
 758                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 759                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 760                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 761                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 762
 763                         /* program default cache read and write policy */
 764                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 765                         /* clean read policy and write policy bits */
 766                         temp &= 0xFF0FFF;
 767                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 768                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 769                 }
 770
 771                 if (!amdgpu_sriov_vf(adev)) {
 772                         /* unhalt engine */
 773                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 774                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 775                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 776                 }
 777
 778                 /* enable DMA RB */
 779                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 780                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 781
 782                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 783                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 784 #ifdef __BIG_ENDIAN
 785                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 786 #endif
 787                 /* enable DMA IBs */
 788                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 789
 790                 ring->sched.ready = true;
 791
 792                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 793                         sdma_v5_0_ctx_switch_enable(adev, true);
 794                         sdma_v5_0_enable(adev, true);
 795                 }
 796
 797                 r = amdgpu_ring_test_helper(ring);
 798                 if (r)
 799                         return r;
 800
 801                 if (adev->mman.buffer_funcs_ring == ring)
 802                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 803         }
 804
 805         return 0;
 806 }
 807
 808 /**
 809  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 810  *
 811  * @adev: amdgpu_device pointer
 812  *
 813  * Set up the compute DMA queues and enable them (NAVI10).
 814  * Returns 0 for success, error for failure.
 815  */
 816 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 817 {
 818         return 0;
 819 }
 820
 821 /**
 822  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 823  *
 824  * @adev: amdgpu_device pointer
 825  *
 826  * Loads the sDMA0/1 ucode.
 827  * Returns 0 for success, -EINVAL if the ucode is not available.
 828  */
 829 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 830 {
 831         const struct sdma_firmware_header_v1_0 *hdr;
 832         const __le32 *fw_data;
 833         u32 fw_size;
 834         int i, j;
 835
 836         /* halt the MEs */
 837         sdma_v5_0_enable(adev, false);
 838
 839         for (i = 0; i < adev->sdma.num_instances; i++) {
 840                 if (!adev->sdma.instance[i].fw)
 841                         return -EINVAL;
 842
 843                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 844                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 845                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 846
 847                 fw_data = (const __le32 *)
 848                         (adev->sdma.instance[i].fw->data +
 849                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 850
 851                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 852
 853                 for (j = 0; j < fw_size; j++) {
 854                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 855                                 msleep(1);
 856                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 857                 }
 858
 859                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 860         }
 861
 862         return 0;
 863 }
 864
 865 /**
 866  * sdma_v5_0_start - setup and start the async dma engines
 867  *
 868  * @adev: amdgpu_device pointer
 869  *
 870  * Set up the DMA engines and enable them (NAVI10).
 871  * Returns 0 for success, error for failure.
 872  */
 873 static int sdma_v5_0_start(struct amdgpu_device *adev)
 874 {
 875         int r = 0;
 876
 877         if (amdgpu_sriov_vf(adev)) {
 878                 sdma_v5_0_ctx_switch_enable(adev, false);
 879                 sdma_v5_0_enable(adev, false);
 880
 881                 /* set RB registers */
 882                 r = sdma_v5_0_gfx_resume(adev);
 883                 return r;
 884         }
 885
 886         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 887                 r = sdma_v5_0_load_microcode(adev);
 888                 if (r)
 889                         return r;
 890
 891                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 892                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 893                         msleep(1000);
 894         }
 895
 896         /* unhalt the MEs */
 897         sdma_v5_0_enable(adev, true);
 898         /* enable sdma ring preemption */
 899         sdma_v5_0_ctx_switch_enable(adev, true);
 900
 901         /* start the gfx rings and rlc compute queues */
 902         r = sdma_v5_0_gfx_resume(adev);
 903         if (r)
 904                 return r;
 905         r = sdma_v5_0_rlc_resume(adev);
 906
 907         return r;
 908 }
 909
 910 /**
 911  * sdma_v5_0_ring_test_ring - simple async dma engine test
 912  *
 913  * @ring: amdgpu_ring structure holding ring information
 914  *
 915  * Test the DMA engine by writing using it to write an
 916  * value to memory. (NAVI10).
 917  * Returns 0 for success, error for failure.
 918  */
 919 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 920 {
 921         struct amdgpu_device *adev = ring->adev;
 922         unsigned i;
 923         unsigned index;
 924         int r;
 925         u32 tmp;
 926         u64 gpu_addr;
 927
 928         r = amdgpu_device_wb_get(adev, &index);
 929         if (r) {
 930                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 931                 return r;
 932         }
 933
 934         gpu_addr = adev->wb.gpu_addr + (index * 4);
 935         tmp = 0xCAFEDEAD;
 936         adev->wb.wb[index] = cpu_to_le32(tmp);
 937
 938         r = amdgpu_ring_alloc(ring, 5);
 939         if (r) {
 940                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 941                 amdgpu_device_wb_free(adev, index);
 942                 return r;
 943         }
 944
 945         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 946                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 947         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 948         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 949         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 950         amdgpu_ring_write(ring, 0xDEADBEEF);
 951         amdgpu_ring_commit(ring);
 952
 953         for (i = 0; i < adev->usec_timeout; i++) {
 954                 tmp = le32_to_cpu(adev->wb.wb[index]);
 955                 if (tmp == 0xDEADBEEF)
 956                         break;
 957                 if (amdgpu_emu_mode == 1)
 958                         msleep(1);
 959                 else
 960                         udelay(1);
 961         }
 962
 963         if (i >= adev->usec_timeout)
 964                 r = -ETIMEDOUT;
 965
 966         amdgpu_device_wb_free(adev, index);
 967
 968         return r;
 969 }
 970
 971 /**
 972  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 973  *
 974  * @ring: amdgpu_ring structure holding ring information
 975  *
 976  * Test a simple IB in the DMA ring (NAVI10).
 977  * Returns 0 on success, error on failure.
 978  */
 979 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 980 {
 981         struct amdgpu_device *adev = ring->adev;
 982         struct amdgpu_ib ib;
 983         struct dma_fence *f = NULL;
 984         unsigned index;
 985         long r;
 986         u32 tmp = 0;
 987         u64 gpu_addr;
 988
 989         r = amdgpu_device_wb_get(adev, &index);
 990         if (r) {
 991                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 992                 return r;
 993         }
 994
 995         gpu_addr = adev->wb.gpu_addr + (index * 4);
 996         tmp = 0xCAFEDEAD;
 997         adev->wb.wb[index] = cpu_to_le32(tmp);
 998         memset(&ib, 0, sizeof(ib));
 999         r = amdgpu_ib_get(adev, NULL, 256,
1000                                         AMDGPU_IB_POOL_DIRECT, &ib);
1001         if (r) {
1002                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1003                 goto err0;
1004         }
1005
1006         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1007                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1008         ib.ptr[1] = lower_32_bits(gpu_addr);
1009         ib.ptr[2] = upper_32_bits(gpu_addr);
1010         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1011         ib.ptr[4] = 0xDEADBEEF;
1012         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1013         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1014         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1015         ib.length_dw = 8;
1016
1017         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1018         if (r)
1019                 goto err1;
1020
1021         r = dma_fence_wait_timeout(f, false, timeout);
1022         if (r == 0) {
1023                 DRM_ERROR("amdgpu: IB test timed out\n");
1024                 r = -ETIMEDOUT;
1025                 goto err1;
1026         } else if (r < 0) {
1027                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1028                 goto err1;
1029         }
1030         tmp = le32_to_cpu(adev->wb.wb[index]);
1031         if (tmp == 0xDEADBEEF)
1032                 r = 0;
1033         else
1034                 r = -EINVAL;
1035
1036 err1:
1037         amdgpu_ib_free(adev, &ib, NULL);
1038         dma_fence_put(f);
1039 err0:
1040         amdgpu_device_wb_free(adev, index);
1041         return r;
1042 }
1043
1044
1045 /**
1046  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1047  *
1048  * @ib: indirect buffer to fill with commands
1049  * @pe: addr of the page entry
1050  * @src: src addr to copy from
1051  * @count: number of page entries to update
1052  *
1053  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1054  */
1055 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1056                                   uint64_t pe, uint64_t src,
1057                                   unsigned count)
1058 {
1059         unsigned bytes = count * 8;
1060
1061         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1062                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1063         ib->ptr[ib->length_dw++] = bytes - 1;
1064         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1065         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1066         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1067         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1068         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1069
1070 }
1071
1072 /**
1073  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1074  *
1075  * @ib: indirect buffer to fill with commands
1076  * @pe: addr of the page entry
1077  * @addr: dst addr to write into pe
1078  * @count: number of page entries to update
1079  * @incr: increase next addr by incr bytes
1080  * @flags: access flags
1081  *
1082  * Update PTEs by writing them manually using sDMA (NAVI10).
1083  */
1084 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1085                                    uint64_t value, unsigned count,
1086                                    uint32_t incr)
1087 {
1088         unsigned ndw = count * 2;
1089
1090         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1091                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1092         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1093         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1094         ib->ptr[ib->length_dw++] = ndw - 1;
1095         for (; ndw > 0; ndw -= 2) {
1096                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1097                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1098                 value += incr;
1099         }
1100 }
1101
1102 /**
1103  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1104  *
1105  * @ib: indirect buffer to fill with commands
1106  * @pe: addr of the page entry
1107  * @addr: dst addr to write into pe
1108  * @count: number of page entries to update
1109  * @incr: increase next addr by incr bytes
1110  * @flags: access flags
1111  *
1112  * Update the page tables using sDMA (NAVI10).
1113  */
1114 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1115                                      uint64_t pe,
1116                                      uint64_t addr, unsigned count,
1117                                      uint32_t incr, uint64_t flags)
1118 {
1119         /* for physically contiguous pages (vram) */
1120         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1121         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1122         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1123         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1124         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1125         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1126         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1127         ib->ptr[ib->length_dw++] = incr; /* increment size */
1128         ib->ptr[ib->length_dw++] = 0;
1129         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1130 }
1131
1132 /**
1133  * sdma_v5_0_ring_pad_ib - pad the IB
1134  * @ib: indirect buffer to fill with padding
1135  *
1136  * Pad the IB with NOPs to a boundary multiple of 8.
1137  */
1138 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1139 {
1140         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1141         u32 pad_count;
1142         int i;
1143
1144         pad_count = (-ib->length_dw) & 0x7;
1145         for (i = 0; i < pad_count; i++)
1146                 if (sdma && sdma->burst_nop && (i == 0))
1147                         ib->ptr[ib->length_dw++] =
1148                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1149                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1150                 else
1151                         ib->ptr[ib->length_dw++] =
1152                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1153 }
1154
1155
1156 /**
1157  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1158  *
1159  * @ring: amdgpu_ring pointer
1160  *
1161  * Make sure all previous operations are completed (CIK).
1162  */
1163 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1164 {
1165         uint32_t seq = ring->fence_drv.sync_seq;
1166         uint64_t addr = ring->fence_drv.gpu_addr;
1167
1168         /* wait for idle */
1169         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1170                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1171                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1172                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1173         amdgpu_ring_write(ring, addr & 0xfffffffc);
1174         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1175         amdgpu_ring_write(ring, seq); /* reference */
1176         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1177         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1178                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1179 }
1180
1181
1182 /**
1183  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1184  *
1185  * @ring: amdgpu_ring pointer
1186  * @vm: amdgpu_vm pointer
1187  *
1188  * Update the page table base and flush the VM TLB
1189  * using sDMA (NAVI10).
1190  */
1191 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1192                                          unsigned vmid, uint64_t pd_addr)
1193 {
1194         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1195 }
1196
1197 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1198                                      uint32_t reg, uint32_t val)
1199 {
1200         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1201                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1202         amdgpu_ring_write(ring, reg);
1203         amdgpu_ring_write(ring, val);
1204 }
1205
1206 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1207                                          uint32_t val, uint32_t mask)
1208 {
1209         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1210                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1211                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1212         amdgpu_ring_write(ring, reg << 2);
1213         amdgpu_ring_write(ring, 0);
1214         amdgpu_ring_write(ring, val); /* reference */
1215         amdgpu_ring_write(ring, mask); /* mask */
1216         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1217                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1218 }
1219
1220 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1221                                                    uint32_t reg0, uint32_t reg1,
1222                                                    uint32_t ref, uint32_t mask)
1223 {
1224         amdgpu_ring_emit_wreg(ring, reg0, ref);
1225         /* wait for a cycle to reset vm_inv_eng*_ack */
1226         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1227         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1228 }
1229
1230 static int sdma_v5_0_early_init(void *handle)
1231 {
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233
1234         adev->sdma.num_instances = 2;
1235
1236         sdma_v5_0_set_ring_funcs(adev);
1237         sdma_v5_0_set_buffer_funcs(adev);
1238         sdma_v5_0_set_vm_pte_funcs(adev);
1239         sdma_v5_0_set_irq_funcs(adev);
1240
1241         return 0;
1242 }
1243
1244
1245 static int sdma_v5_0_sw_init(void *handle)
1246 {
1247         struct amdgpu_ring *ring;
1248         int r, i;
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251         /* SDMA trap event */
1252         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1253                               SDMA0_5_0__SRCID__SDMA_TRAP,
1254                               &adev->sdma.trap_irq);
1255         if (r)
1256                 return r;
1257
1258         /* SDMA trap event */
1259         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1260                               SDMA1_5_0__SRCID__SDMA_TRAP,
1261                               &adev->sdma.trap_irq);
1262         if (r)
1263                 return r;
1264
1265         r = sdma_v5_0_init_microcode(adev);
1266         if (r) {
1267                 DRM_ERROR("Failed to load sdma firmware!\n");
1268                 return r;
1269         }
1270
1271         for (i = 0; i < adev->sdma.num_instances; i++) {
1272                 ring = &adev->sdma.instance[i].ring;
1273                 ring->ring_obj = NULL;
1274                 ring->use_doorbell = true;
1275
1276                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1277                                 ring->use_doorbell?"true":"false");
1278
1279                 ring->doorbell_index = (i == 0) ?
1280                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1281                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1282
1283                 sprintf(ring->name, "sdma%d", i);
1284                 r = amdgpu_ring_init(adev, ring, 1024,
1285                                      &adev->sdma.trap_irq,
1286                                      (i == 0) ?
1287                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1288                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1289                                      AMDGPU_RING_PRIO_DEFAULT);
1290                 if (r)
1291                         return r;
1292         }
1293
1294         return r;
1295 }
1296
1297 static int sdma_v5_0_sw_fini(void *handle)
1298 {
1299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300         int i;
1301
1302         for (i = 0; i < adev->sdma.num_instances; i++) {
1303                 release_firmware(adev->sdma.instance[i].fw);
1304                 adev->sdma.instance[i].fw = NULL;
1305
1306                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int sdma_v5_0_hw_init(void *handle)
1313 {
1314         int r;
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         sdma_v5_0_init_golden_registers(adev);
1318
1319         r = sdma_v5_0_start(adev);
1320
1321         return r;
1322 }
1323
1324 static int sdma_v5_0_hw_fini(void *handle)
1325 {
1326         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327
1328         if (amdgpu_sriov_vf(adev))
1329                 return 0;
1330
1331         sdma_v5_0_ctx_switch_enable(adev, false);
1332         sdma_v5_0_enable(adev, false);
1333
1334         return 0;
1335 }
1336
1337 static int sdma_v5_0_suspend(void *handle)
1338 {
1339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340
1341         return sdma_v5_0_hw_fini(adev);
1342 }
1343
1344 static int sdma_v5_0_resume(void *handle)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347
1348         return sdma_v5_0_hw_init(adev);
1349 }
1350
1351 static bool sdma_v5_0_is_idle(void *handle)
1352 {
1353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354         u32 i;
1355
1356         for (i = 0; i < adev->sdma.num_instances; i++) {
1357                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1358
1359                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1360                         return false;
1361         }
1362
1363         return true;
1364 }
1365
1366 static int sdma_v5_0_wait_for_idle(void *handle)
1367 {
1368         unsigned i;
1369         u32 sdma0, sdma1;
1370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371
1372         for (i = 0; i < adev->usec_timeout; i++) {
1373                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1374                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1375
1376                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1377                         return 0;
1378                 udelay(1);
1379         }
1380         return -ETIMEDOUT;
1381 }
1382
1383 static int sdma_v5_0_soft_reset(void *handle)
1384 {
1385         /* todo */
1386
1387         return 0;
1388 }
1389
1390 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1391 {
1392         int i, r = 0;
1393         struct amdgpu_device *adev = ring->adev;
1394         u32 index = 0;
1395         u64 sdma_gfx_preempt;
1396
1397         amdgpu_sdma_get_index_from_ring(ring, &index);
1398         if (index == 0)
1399                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1400         else
1401                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1402
1403         /* assert preemption condition */
1404         amdgpu_ring_set_preempt_cond_exec(ring, false);
1405
1406         /* emit the trailing fence */
1407         ring->trail_seq += 1;
1408         amdgpu_ring_alloc(ring, 10);
1409         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1410                                   ring->trail_seq, 0);
1411         amdgpu_ring_commit(ring);
1412
1413         /* assert IB preemption */
1414         WREG32(sdma_gfx_preempt, 1);
1415
1416         /* poll the trailing fence */
1417         for (i = 0; i < adev->usec_timeout; i++) {
1418                 if (ring->trail_seq ==
1419                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1420                         break;
1421                 udelay(1);
1422         }
1423
1424         if (i >= adev->usec_timeout) {
1425                 r = -EINVAL;
1426                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1427         }
1428
1429         /* deassert IB preemption */
1430         WREG32(sdma_gfx_preempt, 0);
1431
1432         /* deassert the preemption condition */
1433         amdgpu_ring_set_preempt_cond_exec(ring, true);
1434         return r;
1435 }
1436
1437 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1438                                         struct amdgpu_irq_src *source,
1439                                         unsigned type,
1440                                         enum amdgpu_interrupt_state state)
1441 {
1442         u32 sdma_cntl;
1443
1444         if (!amdgpu_sriov_vf(adev)) {
1445                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1446                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1447                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1448
1449                 sdma_cntl = RREG32(reg_offset);
1450                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1451                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1452                 WREG32(reg_offset, sdma_cntl);
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1459                                       struct amdgpu_irq_src *source,
1460                                       struct amdgpu_iv_entry *entry)
1461 {
1462         DRM_DEBUG("IH: SDMA trap\n");
1463         switch (entry->client_id) {
1464         case SOC15_IH_CLIENTID_SDMA0:
1465                 switch (entry->ring_id) {
1466                 case 0:
1467                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1468                         break;
1469                 case 1:
1470                         /* XXX compute */
1471                         break;
1472                 case 2:
1473                         /* XXX compute */
1474                         break;
1475                 case 3:
1476                         /* XXX page queue*/
1477                         break;
1478                 }
1479                 break;
1480         case SOC15_IH_CLIENTID_SDMA1:
1481                 switch (entry->ring_id) {
1482                 case 0:
1483                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1484                         break;
1485                 case 1:
1486                         /* XXX compute */
1487                         break;
1488                 case 2:
1489                         /* XXX compute */
1490                         break;
1491                 case 3:
1492                         /* XXX page queue*/
1493                         break;
1494                 }
1495                 break;
1496         }
1497         return 0;
1498 }
1499
1500 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1501                                               struct amdgpu_irq_src *source,
1502                                               struct amdgpu_iv_entry *entry)
1503 {
1504         return 0;
1505 }
1506
1507 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1508                                                        bool enable)
1509 {
1510         uint32_t data, def;
1511         int i;
1512
1513         for (i = 0; i < adev->sdma.num_instances; i++) {
1514                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1515                         /* Enable sdma clock gating */
1516                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1517                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1518                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1519                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1520                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1521                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1522                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1523                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1524                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1525                         if (def != data)
1526                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1527                 } else {
1528                         /* Disable sdma clock gating */
1529                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1530                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1531                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1532                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1533                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1534                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1535                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1536                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1537                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1538                         if (def != data)
1539                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1540                 }
1541         }
1542 }
1543
1544 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1545                                                       bool enable)
1546 {
1547         uint32_t data, def;
1548         int i;
1549
1550         for (i = 0; i < adev->sdma.num_instances; i++) {
1551                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1552                         /* Enable sdma mem light sleep */
1553                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1554                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1555                         if (def != data)
1556                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1557
1558                 } else {
1559                         /* Disable sdma mem light sleep */
1560                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1561                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1562                         if (def != data)
1563                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1564
1565                 }
1566         }
1567 }
1568
1569 static int sdma_v5_0_set_clockgating_state(void *handle,
1570                                            enum amd_clockgating_state state)
1571 {
1572         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1573
1574         if (amdgpu_sriov_vf(adev))
1575                 return 0;
1576
1577         switch (adev->asic_type) {
1578         case CHIP_NAVI10:
1579         case CHIP_NAVI14:
1580         case CHIP_NAVI12:
1581                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1582                                 state == AMD_CG_STATE_GATE);
1583                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1584                                 state == AMD_CG_STATE_GATE);
1585                 break;
1586         default:
1587                 break;
1588         }
1589
1590         return 0;
1591 }
1592
1593 static int sdma_v5_0_set_powergating_state(void *handle,
1594                                           enum amd_powergating_state state)
1595 {
1596         return 0;
1597 }
1598
1599 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1600 {
1601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1602         int data;
1603
1604         if (amdgpu_sriov_vf(adev))
1605                 *flags = 0;
1606
1607         /* AMD_CG_SUPPORT_SDMA_MGCG */
1608         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1609         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1610                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1611
1612         /* AMD_CG_SUPPORT_SDMA_LS */
1613         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1614         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1615                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1616 }
1617
1618 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1619         .name = "sdma_v5_0",
1620         .early_init = sdma_v5_0_early_init,
1621         .late_init = NULL,
1622         .sw_init = sdma_v5_0_sw_init,
1623         .sw_fini = sdma_v5_0_sw_fini,
1624         .hw_init = sdma_v5_0_hw_init,
1625         .hw_fini = sdma_v5_0_hw_fini,
1626         .suspend = sdma_v5_0_suspend,
1627         .resume = sdma_v5_0_resume,
1628         .is_idle = sdma_v5_0_is_idle,
1629         .wait_for_idle = sdma_v5_0_wait_for_idle,
1630         .soft_reset = sdma_v5_0_soft_reset,
1631         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1632         .set_powergating_state = sdma_v5_0_set_powergating_state,
1633         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1634 };
1635
1636 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1637         .type = AMDGPU_RING_TYPE_SDMA,
1638         .align_mask = 0xf,
1639         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1640         .support_64bit_ptrs = true,
1641         .vmhub = AMDGPU_GFXHUB_0,
1642         .get_rptr = sdma_v5_0_ring_get_rptr,
1643         .get_wptr = sdma_v5_0_ring_get_wptr,
1644         .set_wptr = sdma_v5_0_ring_set_wptr,
1645         .emit_frame_size =
1646                 5 + /* sdma_v5_0_ring_init_cond_exec */
1647                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1648                 3 + /* hdp_invalidate */
1649                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1650                 /* sdma_v5_0_ring_emit_vm_flush */
1651                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1652                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1653                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1654         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1655         .emit_ib = sdma_v5_0_ring_emit_ib,
1656         .emit_fence = sdma_v5_0_ring_emit_fence,
1657         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1658         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1659         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1660         .test_ring = sdma_v5_0_ring_test_ring,
1661         .test_ib = sdma_v5_0_ring_test_ib,
1662         .insert_nop = sdma_v5_0_ring_insert_nop,
1663         .pad_ib = sdma_v5_0_ring_pad_ib,
1664         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1665         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1666         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1667         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1668         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1669         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1670 };
1671
1672 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1673 {
1674         int i;
1675
1676         for (i = 0; i < adev->sdma.num_instances; i++) {
1677                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1678                 adev->sdma.instance[i].ring.me = i;
1679         }
1680 }
1681
1682 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1683         .set = sdma_v5_0_set_trap_irq_state,
1684         .process = sdma_v5_0_process_trap_irq,
1685 };
1686
1687 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1688         .process = sdma_v5_0_process_illegal_inst_irq,
1689 };
1690
1691 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1692 {
1693         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1694                                         adev->sdma.num_instances;
1695         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1696         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1697 }
1698
1699 /**
1700  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1701  *
1702  * @ring: amdgpu_ring structure holding ring information
1703  * @src_offset: src GPU address
1704  * @dst_offset: dst GPU address
1705  * @byte_count: number of bytes to xfer
1706  *
1707  * Copy GPU buffers using the DMA engine (NAVI10).
1708  * Used by the amdgpu ttm implementation to move pages if
1709  * registered as the asic copy callback.
1710  */
1711 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1712                                        uint64_t src_offset,
1713                                        uint64_t dst_offset,
1714                                        uint32_t byte_count,
1715                                        bool tmz)
1716 {
1717         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1718                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1719                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1720         ib->ptr[ib->length_dw++] = byte_count - 1;
1721         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1722         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1723         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1724         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1725         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1726 }
1727
1728 /**
1729  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1730  *
1731  * @ring: amdgpu_ring structure holding ring information
1732  * @src_data: value to write to buffer
1733  * @dst_offset: dst GPU address
1734  * @byte_count: number of bytes to xfer
1735  *
1736  * Fill GPU buffers using the DMA engine (NAVI10).
1737  */
1738 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1739                                        uint32_t src_data,
1740                                        uint64_t dst_offset,
1741                                        uint32_t byte_count)
1742 {
1743         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1744         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1745         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1746         ib->ptr[ib->length_dw++] = src_data;
1747         ib->ptr[ib->length_dw++] = byte_count - 1;
1748 }
1749
1750 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1751         .copy_max_bytes = 0x400000,
1752         .copy_num_dw = 7,
1753         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1754
1755         .fill_max_bytes = 0x400000,
1756         .fill_num_dw = 5,
1757         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1758 };
1759
1760 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1761 {
1762         if (adev->mman.buffer_funcs == NULL) {
1763                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1764                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1765         }
1766 }
1767
1768 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1769         .copy_pte_num_dw = 7,
1770         .copy_pte = sdma_v5_0_vm_copy_pte,
1771         .write_pte = sdma_v5_0_vm_write_pte,
1772         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1773 };
1774
1775 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1776 {
1777         unsigned i;
1778
1779         if (adev->vm_manager.vm_pte_funcs == NULL) {
1780                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1781                 for (i = 0; i < adev->sdma.num_instances; i++) {
1782                         adev->vm_manager.vm_pte_scheds[i] =
1783                                 &adev->sdma.instance[i].ring.sched;
1784                 }
1785                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1786         }
1787 }
1788
1789 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1790         .type = AMD_IP_BLOCK_TYPE_SDMA,
1791         .major = 5,
1792         .minor = 0,
1793         .rev = 0,
1794         .funcs = &sdma_v5_0_ip_funcs,
1795 };