drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64
  65 static const struct amd_ip_funcs nv_common_ip_funcs;
  66
  67 /*
  68  * Indirect registers accessor
  69  */
  70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  71 {
  72         unsigned long flags, address, data;
  73         u32 r;
  74         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  75         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  76
  77         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  78         WREG32(address, reg);
  79         (void)RREG32(address);
  80         r = RREG32(data);
  81         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  82         return r;
  83 }
  84
  85 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  86 {
  87         unsigned long flags, address, data;
  88
  89         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  90         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  91
  92         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  93         WREG32(address, reg);
  94         (void)RREG32(address);
  95         WREG32(data, v);
  96         (void)RREG32(data);
  97         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  98 }
  99
 100 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 101 {
 102         unsigned long flags, address, data;
 103         u32 r;
 104
 105         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 106         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 107
 108         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 109         WREG32(address, (reg));
 110         r = RREG32(data);
 111         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 112         return r;
 113 }
 114
 115 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 116 {
 117         unsigned long flags, address, data;
 118
 119         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 120         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 121
 122         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 123         WREG32(address, (reg));
 124         WREG32(data, (v));
 125         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 126 }
 127
 128 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 129 {
 130         return adev->nbio.funcs->get_memsize(adev);
 131 }
 132
 133 static u32 nv_get_xclk(struct amdgpu_device *adev)
 134 {
 135         return adev->clock.spll.reference_freq;
 136 }
 137
 138
 139 void nv_grbm_select(struct amdgpu_device *adev,
 140                      u32 me, u32 pipe, u32 queue, u32 vmid)
 141 {
 142         u32 grbm_gfx_cntl = 0;
 143         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 144         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 145         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 146         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 147
 148         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 149 }
 150
 151 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 152 {
 153         /* todo */
 154 }
 155
 156 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 157 {
 158         /* todo */
 159         return false;
 160 }
 161
 162 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 163                                   u8 *bios, u32 length_bytes)
 164 {
 165         u32 *dw_ptr;
 166         u32 i, length_dw;
 167
 168         if (bios == NULL)
 169                 return false;
 170         if (length_bytes == 0)
 171                 return false;
 172         /* APU vbios image is part of sbios image */
 173         if (adev->flags & AMD_IS_APU)
 174                 return false;
 175
 176         dw_ptr = (u32 *)bios;
 177         length_dw = ALIGN(length_bytes, 4) / 4;
 178
 179         /* set rom index to 0 */
 180         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 181         /* read out the rom data */
 182         for (i = 0; i < length_dw; i++)
 183                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 184
 185         return true;
 186 }
 187
 188 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 189         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 190         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 191         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 192         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 193         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 194         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 195         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 196         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 197         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 198         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 199         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 200         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 201         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 202         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 203         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 204         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 205         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 206         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 207         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 208 };
 209
 210 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 211                                          u32 sh_num, u32 reg_offset)
 212 {
 213         uint32_t val;
 214
 215         mutex_lock(&adev->grbm_idx_mutex);
 216         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 217                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 218
 219         val = RREG32(reg_offset);
 220
 221         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 222                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 223         mutex_unlock(&adev->grbm_idx_mutex);
 224         return val;
 225 }
 226
 227 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 228                                       bool indexed, u32 se_num,
 229                                       u32 sh_num, u32 reg_offset)
 230 {
 231         if (indexed) {
 232                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 233         } else {
 234                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 235                         return adev->gfx.config.gb_addr_config;
 236                 return RREG32(reg_offset);
 237         }
 238 }
 239
 240 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 241                             u32 sh_num, u32 reg_offset, u32 *value)
 242 {
 243         uint32_t i;
 244         struct soc15_allowed_register_entry  *en;
 245
 246         *value = 0;
 247         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 248                 en = &nv_allowed_read_registers[i];
 249                 if (reg_offset !=
 250                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 251                         continue;
 252
 253                 *value = nv_get_register_value(adev,
 254                                                nv_allowed_read_registers[i].grbm_indexed,
 255                                                se_num, sh_num, reg_offset);
 256                 return 0;
 257         }
 258         return -EINVAL;
 259 }
 260
 261 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 262 {
 263         u32 i;
 264         int ret = 0;
 265
 266         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 267
 268         dev_info(adev->dev, "GPU mode1 reset\n");
 269
 270         /* disable BM */
 271         pci_clear_master(adev->pdev);
 272
 273         pci_save_state(adev->pdev);
 274
 275         ret = psp_gpu_reset(adev);
 276         if (ret)
 277                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 278
 279         pci_restore_state(adev->pdev);
 280
 281         /* wait for asic to come out of reset */
 282         for (i = 0; i < adev->usec_timeout; i++) {
 283                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 284
 285                 if (memsize != 0xffffffff)
 286                         break;
 287                 udelay(1);
 288         }
 289
 290         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 291
 292         return ret;
 293 }
 294
 295 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 296 {
 297         struct smu_context *smu = &adev->smu;
 298
 299         if (smu_baco_is_support(smu))
 300                 return true;
 301         else
 302                 return false;
 303 }
 304
 305 static enum amd_reset_method
 306 nv_asic_reset_method(struct amdgpu_device *adev)
 307 {
 308         struct smu_context *smu = &adev->smu;
 309
 310         if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
 311                 return AMD_RESET_METHOD_BACO;
 312         else
 313                 return AMD_RESET_METHOD_MODE1;
 314 }
 315
 316 static int nv_asic_reset(struct amdgpu_device *adev)
 317 {
 318         int ret = 0;
 319         struct smu_context *smu = &adev->smu;
 320
 321         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 322                 ret = smu_baco_enter(smu);
 323                 if (ret)
 324                         return ret;
 325                 ret = smu_baco_exit(smu);
 326                 if (ret)
 327                         return ret;
 328         } else {
 329                 ret = nv_asic_mode1_reset(adev);
 330         }
 331
 332         return ret;
 333 }
 334
 335 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 336 {
 337         /* todo */
 338         return 0;
 339 }
 340
 341 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 342 {
 343         /* todo */
 344         return 0;
 345 }
 346
 347 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 348 {
 349         if (pci_is_root_bus(adev->pdev->bus))
 350                 return;
 351
 352         if (amdgpu_pcie_gen2 == 0)
 353                 return;
 354
 355         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 356                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 357                 return;
 358
 359         /* todo */
 360 }
 361
 362 static void nv_program_aspm(struct amdgpu_device *adev)
 363 {
 364
 365         if (amdgpu_aspm == 0)
 366                 return;
 367
 368         /* todo */
 369 }
 370
 371 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 372                                         bool enable)
 373 {
 374         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 375         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 376 }
 377
 378 static const struct amdgpu_ip_block_version nv_common_ip_block =
 379 {
 380         .type = AMD_IP_BLOCK_TYPE_COMMON,
 381         .major = 1,
 382         .minor = 0,
 383         .rev = 0,
 384         .funcs = &nv_common_ip_funcs,
 385 };
 386
 387 static int nv_reg_base_init(struct amdgpu_device *adev)
 388 {
 389         int r;
 390
 391         if (amdgpu_discovery) {
 392                 r = amdgpu_discovery_reg_base_init(adev);
 393                 if (r) {
 394                         DRM_WARN("failed to init reg base from ip discovery table, "
 395                                         "fallback to legacy init method\n");
 396                         goto legacy_init;
 397                 }
 398
 399                 return 0;
 400         }
 401
 402 legacy_init:
 403         switch (adev->asic_type) {
 404         case CHIP_NAVI10:
 405                 navi10_reg_base_init(adev);
 406                 break;
 407         case CHIP_NAVI14:
 408                 navi14_reg_base_init(adev);
 409                 break;
 410         case CHIP_NAVI12:
 411                 navi12_reg_base_init(adev);
 412                 break;
 413         case CHIP_SIENNA_CICHLID:
 414                 sienna_cichlid_reg_base_init(adev);
 415                 break;
 416         default:
 417                 return -EINVAL;
 418         }
 419
 420         return 0;
 421 }
 422
 423 int nv_set_ip_blocks(struct amdgpu_device *adev)
 424 {
 425         int r;
 426
 427         adev->nbio.funcs = &nbio_v2_3_funcs;
 428         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 429
 430         if (amdgpu_sriov_vf(adev)) {
 431                 adev->virt.ops = &xgpu_nv_virt_ops;
 432                 /* try send GPU_INIT_DATA request to host */
 433                 amdgpu_virt_request_init_data(adev);
 434         }
 435
 436         /* Set IP register base before any HW register access */
 437         r = nv_reg_base_init(adev);
 438         if (r)
 439                 return r;
 440
 441         switch (adev->asic_type) {
 442         case CHIP_NAVI10:
 443         case CHIP_NAVI14:
 444                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 445                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 446                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 447                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 448                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 449                     !amdgpu_sriov_vf(adev))
 450                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 451                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 452                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 453 #if defined(CONFIG_DRM_AMD_DC)
 454                 else if (amdgpu_device_has_dc_support(adev))
 455                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 456 #endif
 457                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 458                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 459                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 460                     !amdgpu_sriov_vf(adev))
 461                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 462                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 463                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 464                 if (adev->enable_mes)
 465                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 466                 break;
 467         case CHIP_NAVI12:
 468                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 469                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 470                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 471                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 472                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 473                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 474                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 475                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 476 #if defined(CONFIG_DRM_AMD_DC)
 477                 else if (amdgpu_device_has_dc_support(adev))
 478                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 479 #endif
 480                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 481                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 482                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 483                     !amdgpu_sriov_vf(adev))
 484                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 485                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 486                 if (!amdgpu_sriov_vf(adev))
 487                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 488                 break;
 489         case CHIP_SIENNA_CICHLID:
 490                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 491                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 492                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 493                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 494                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 495                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 496                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 497                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 498                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 499                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 500 #if defined(CONFIG_DRM_AMD_DC)
 501                 else if (amdgpu_device_has_dc_support(adev))
 502                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 503 #endif
 504                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 505                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 506                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 507                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 508                 if (adev->enable_mes)
 509                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 510                 break;
 511         default:
 512                 return -EINVAL;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 519 {
 520         return adev->nbio.funcs->get_rev_id(adev);
 521 }
 522
 523 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 524 {
 525         adev->nbio.funcs->hdp_flush(adev, ring);
 526 }
 527
 528 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 529                                 struct amdgpu_ring *ring)
 530 {
 531         if (!ring || !ring->funcs->emit_wreg) {
 532                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 533         } else {
 534                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 535                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 536         }
 537 }
 538
 539 static bool nv_need_full_reset(struct amdgpu_device *adev)
 540 {
 541         return true;
 542 }
 543
 544 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 545 {
 546         u32 sol_reg;
 547
 548         if (adev->flags & AMD_IS_APU)
 549                 return false;
 550
 551         /* Check sOS sign of life register to confirm sys driver and sOS
 552          * are already been loaded.
 553          */
 554         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 555         if (sol_reg)
 556                 return true;
 557
 558         return false;
 559 }
 560
 561 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 562 {
 563
 564         /* TODO
 565          * dummy implement for pcie_replay_count sysfs interface
 566          * */
 567
 568         return 0;
 569 }
 570
 571 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 572 {
 573         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 574         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 575         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 576         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 577         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 578         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 579         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 580         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 581         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 582         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 583         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 584         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 585         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 586         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 587         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 588         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 589         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 590         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 591         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 592         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 593         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 594         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 595         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 596         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 597         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 598
 599         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 600         adev->doorbell_index.sdma_doorbell_range = 20;
 601 }
 602
 603 static const struct amdgpu_asic_funcs nv_asic_funcs =
 604 {
 605         .read_disabled_bios = &nv_read_disabled_bios,
 606         .read_bios_from_rom = &nv_read_bios_from_rom,
 607         .read_register = &nv_read_register,
 608         .reset = &nv_asic_reset,
 609         .reset_method = &nv_asic_reset_method,
 610         .set_vga_state = &nv_vga_set_state,
 611         .get_xclk = &nv_get_xclk,
 612         .set_uvd_clocks = &nv_set_uvd_clocks,
 613         .set_vce_clocks = &nv_set_vce_clocks,
 614         .get_config_memsize = &nv_get_config_memsize,
 615         .flush_hdp = &nv_flush_hdp,
 616         .invalidate_hdp = &nv_invalidate_hdp,
 617         .init_doorbell_index = &nv_init_doorbell_index,
 618         .need_full_reset = &nv_need_full_reset,
 619         .need_reset_on_init = &nv_need_reset_on_init,
 620         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 621         .supports_baco = &nv_asic_supports_baco,
 622 };
 623
 624 static int nv_common_early_init(void *handle)
 625 {
 626 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 627         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 628
 629         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 630         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 631         adev->smc_rreg = NULL;
 632         adev->smc_wreg = NULL;
 633         adev->pcie_rreg = &nv_pcie_rreg;
 634         adev->pcie_wreg = &nv_pcie_wreg;
 635
 636         /* TODO: will add them during VCN v2 implementation */
 637         adev->uvd_ctx_rreg = NULL;
 638         adev->uvd_ctx_wreg = NULL;
 639
 640         adev->didt_rreg = &nv_didt_rreg;
 641         adev->didt_wreg = &nv_didt_wreg;
 642
 643         adev->asic_funcs = &nv_asic_funcs;
 644
 645         adev->rev_id = nv_get_rev_id(adev);
 646         adev->external_rev_id = 0xff;
 647         switch (adev->asic_type) {
 648         case CHIP_NAVI10:
 649                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 650                         AMD_CG_SUPPORT_GFX_CGCG |
 651                         AMD_CG_SUPPORT_IH_CG |
 652                         AMD_CG_SUPPORT_HDP_MGCG |
 653                         AMD_CG_SUPPORT_HDP_LS |
 654                         AMD_CG_SUPPORT_SDMA_MGCG |
 655                         AMD_CG_SUPPORT_SDMA_LS |
 656                         AMD_CG_SUPPORT_MC_MGCG |
 657                         AMD_CG_SUPPORT_MC_LS |
 658                         AMD_CG_SUPPORT_ATHUB_MGCG |
 659                         AMD_CG_SUPPORT_ATHUB_LS |
 660                         AMD_CG_SUPPORT_VCN_MGCG |
 661                         AMD_CG_SUPPORT_JPEG_MGCG |
 662                         AMD_CG_SUPPORT_BIF_MGCG |
 663                         AMD_CG_SUPPORT_BIF_LS;
 664                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 665                         AMD_PG_SUPPORT_VCN_DPG |
 666                         AMD_PG_SUPPORT_JPEG |
 667                         AMD_PG_SUPPORT_ATHUB;
 668                 adev->external_rev_id = adev->rev_id + 0x1;
 669                 break;
 670         case CHIP_NAVI14:
 671                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 672                         AMD_CG_SUPPORT_GFX_CGCG |
 673                         AMD_CG_SUPPORT_IH_CG |
 674                         AMD_CG_SUPPORT_HDP_MGCG |
 675                         AMD_CG_SUPPORT_HDP_LS |
 676                         AMD_CG_SUPPORT_SDMA_MGCG |
 677                         AMD_CG_SUPPORT_SDMA_LS |
 678                         AMD_CG_SUPPORT_MC_MGCG |
 679                         AMD_CG_SUPPORT_MC_LS |
 680                         AMD_CG_SUPPORT_ATHUB_MGCG |
 681                         AMD_CG_SUPPORT_ATHUB_LS |
 682                         AMD_CG_SUPPORT_VCN_MGCG |
 683                         AMD_CG_SUPPORT_JPEG_MGCG |
 684                         AMD_CG_SUPPORT_BIF_MGCG |
 685                         AMD_CG_SUPPORT_BIF_LS;
 686                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 687                         AMD_PG_SUPPORT_JPEG |
 688                         AMD_PG_SUPPORT_VCN_DPG;
 689                 adev->external_rev_id = adev->rev_id + 20;
 690                 break;
 691         case CHIP_NAVI12:
 692                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 693                         AMD_CG_SUPPORT_GFX_MGLS |
 694                         AMD_CG_SUPPORT_GFX_CGCG |
 695                         AMD_CG_SUPPORT_GFX_CP_LS |
 696                         AMD_CG_SUPPORT_GFX_RLC_LS |
 697                         AMD_CG_SUPPORT_IH_CG |
 698                         AMD_CG_SUPPORT_HDP_MGCG |
 699                         AMD_CG_SUPPORT_HDP_LS |
 700                         AMD_CG_SUPPORT_SDMA_MGCG |
 701                         AMD_CG_SUPPORT_SDMA_LS |
 702                         AMD_CG_SUPPORT_MC_MGCG |
 703                         AMD_CG_SUPPORT_MC_LS |
 704                         AMD_CG_SUPPORT_ATHUB_MGCG |
 705                         AMD_CG_SUPPORT_ATHUB_LS |
 706                         AMD_CG_SUPPORT_VCN_MGCG |
 707                         AMD_CG_SUPPORT_JPEG_MGCG;
 708                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 709                         AMD_PG_SUPPORT_VCN_DPG |
 710                         AMD_PG_SUPPORT_JPEG |
 711                         AMD_PG_SUPPORT_ATHUB |
 712                         AMD_PG_SUPPORT_MMHUB;
 713                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 714                  * as a consequence, the rev_id and external_rev_id are wrong.
 715                  * workaround it by hardcoding rev_id to 0 (default value).
 716                  */
 717                 if (amdgpu_sriov_vf(adev))
 718                         adev->rev_id = 0;
 719                 adev->external_rev_id = adev->rev_id + 0xa;
 720                 break;
 721         case CHIP_SIENNA_CICHLID:
 722                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 723                         AMD_CG_SUPPORT_GFX_CGCG |
 724                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 725                         AMD_CG_SUPPORT_MC_MGCG |
 726                         AMD_CG_SUPPORT_VCN_MGCG |
 727                         AMD_CG_SUPPORT_JPEG_MGCG |
 728                         AMD_CG_SUPPORT_HDP_MGCG |
 729                         AMD_CG_SUPPORT_HDP_LS |
 730                         AMD_CG_SUPPORT_IH_CG |
 731                         AMD_CG_SUPPORT_MC_LS;
 732                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 733                         AMD_PG_SUPPORT_VCN_DPG |
 734                         AMD_PG_SUPPORT_JPEG |
 735                         AMD_PG_SUPPORT_ATHUB;
 736                 adev->external_rev_id = adev->rev_id + 0x28;
 737                 break;
 738         default:
 739                 /* FIXME: not supported yet */
 740                 return -EINVAL;
 741         }
 742
 743         if (amdgpu_sriov_vf(adev)) {
 744                 amdgpu_virt_init_setting(adev);
 745                 xgpu_nv_mailbox_set_irq_funcs(adev);
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int nv_common_late_init(void *handle)
 752 {
 753         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 754
 755         if (amdgpu_sriov_vf(adev))
 756                 xgpu_nv_mailbox_get_irq(adev);
 757
 758         return 0;
 759 }
 760
 761 static int nv_common_sw_init(void *handle)
 762 {
 763         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 764
 765         if (amdgpu_sriov_vf(adev))
 766                 xgpu_nv_mailbox_add_irq_id(adev);
 767
 768         return 0;
 769 }
 770
 771 static int nv_common_sw_fini(void *handle)
 772 {
 773         return 0;
 774 }
 775
 776 static int nv_common_hw_init(void *handle)
 777 {
 778         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 779
 780         /* enable pcie gen2/3 link */
 781         nv_pcie_gen3_enable(adev);
 782         /* enable aspm */
 783         nv_program_aspm(adev);
 784         /* setup nbio registers */
 785         adev->nbio.funcs->init_registers(adev);
 786         /* remap HDP registers to a hole in mmio space,
 787          * for the purpose of expose those registers
 788          * to process space
 789          */
 790         if (adev->nbio.funcs->remap_hdp_registers)
 791                 adev->nbio.funcs->remap_hdp_registers(adev);
 792         /* enable the doorbell aperture */
 793         nv_enable_doorbell_aperture(adev, true);
 794
 795         return 0;
 796 }
 797
 798 static int nv_common_hw_fini(void *handle)
 799 {
 800         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 801
 802         /* disable the doorbell aperture */
 803         nv_enable_doorbell_aperture(adev, false);
 804
 805         return 0;
 806 }
 807
 808 static int nv_common_suspend(void *handle)
 809 {
 810         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 811
 812         return nv_common_hw_fini(adev);
 813 }
 814
 815 static int nv_common_resume(void *handle)
 816 {
 817         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 818
 819         return nv_common_hw_init(adev);
 820 }
 821
 822 static bool nv_common_is_idle(void *handle)
 823 {
 824         return true;
 825 }
 826
 827 static int nv_common_wait_for_idle(void *handle)
 828 {
 829         return 0;
 830 }
 831
 832 static int nv_common_soft_reset(void *handle)
 833 {
 834         return 0;
 835 }
 836
 837 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 838                                            bool enable)
 839 {
 840         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 841         uint32_t hdp_mem_pwr_cntl;
 842
 843         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 844                                 AMD_CG_SUPPORT_HDP_DS |
 845                                 AMD_CG_SUPPORT_HDP_SD)))
 846                 return;
 847
 848         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 849         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 850
 851         /* Before doing clock/power mode switch,
 852          * forced on IPH & RC clock */
 853         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 854                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 855         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 856                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 857         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 858
 859         /* HDP 5.0 doesn't support dynamic power mode switch,
 860          * disable clock and power gating before any changing */
 861         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 862                                          IPH_MEM_POWER_CTRL_EN, 0);
 863         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 864                                          IPH_MEM_POWER_LS_EN, 0);
 865         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 866                                          IPH_MEM_POWER_DS_EN, 0);
 867         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 868                                          IPH_MEM_POWER_SD_EN, 0);
 869         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 870                                          RC_MEM_POWER_CTRL_EN, 0);
 871         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 872                                          RC_MEM_POWER_LS_EN, 0);
 873         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 874                                          RC_MEM_POWER_DS_EN, 0);
 875         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 876                                          RC_MEM_POWER_SD_EN, 0);
 877         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 878
 879         /* only one clock gating mode (LS/DS/SD) can be enabled */
 880         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 881                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 882                                                  HDP_MEM_POWER_CTRL,
 883                                                  IPH_MEM_POWER_LS_EN, enable);
 884                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 885                                                  HDP_MEM_POWER_CTRL,
 886                                                  RC_MEM_POWER_LS_EN, enable);
 887         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 888                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 889                                                  HDP_MEM_POWER_CTRL,
 890                                                  IPH_MEM_POWER_DS_EN, enable);
 891                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 892                                                  HDP_MEM_POWER_CTRL,
 893                                                  RC_MEM_POWER_DS_EN, enable);
 894         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 895                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 896                                                  HDP_MEM_POWER_CTRL,
 897                                                  IPH_MEM_POWER_SD_EN, enable);
 898                 /* RC should not use shut down mode, fallback to ds */
 899                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 900                                                  HDP_MEM_POWER_CTRL,
 901                                                  RC_MEM_POWER_DS_EN, enable);
 902         }
 903
 904         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
 905          * be set for SRAM LS/DS/SD */
 906         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
 907                                                         AMD_CG_SUPPORT_HDP_SD)) {
 908                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 909                                                 IPH_MEM_POWER_CTRL_EN, 1);
 910                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 911                                                 RC_MEM_POWER_CTRL_EN, 1);
 912         }
 913
 914         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 915
 916         /* restore IPH & RC clock override after clock/power mode changing */
 917         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
 918 }
 919
 920 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
 921                                        bool enable)
 922 {
 923         uint32_t hdp_clk_cntl;
 924
 925         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 926                 return;
 927
 928         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 929
 930         if (enable) {
 931                 hdp_clk_cntl &=
 932                         ~(uint32_t)
 933                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 934                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 935                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 936                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 937                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 938                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
 939         } else {
 940                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 941                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 942                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 943                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 944                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 945                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
 946         }
 947
 948         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 949 }
 950
 951 static int nv_common_set_clockgating_state(void *handle,
 952                                            enum amd_clockgating_state state)
 953 {
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955
 956         if (amdgpu_sriov_vf(adev))
 957                 return 0;
 958
 959         switch (adev->asic_type) {
 960         case CHIP_NAVI10:
 961         case CHIP_NAVI14:
 962         case CHIP_NAVI12:
 963         case CHIP_SIENNA_CICHLID:
 964                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 965                                 state == AMD_CG_STATE_GATE);
 966                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
 967                                 state == AMD_CG_STATE_GATE);
 968                 nv_update_hdp_mem_power_gating(adev,
 969                                    state == AMD_CG_STATE_GATE);
 970                 nv_update_hdp_clock_gating(adev,
 971                                 state == AMD_CG_STATE_GATE);
 972                 break;
 973         default:
 974                 break;
 975         }
 976         return 0;
 977 }
 978
 979 static int nv_common_set_powergating_state(void *handle,
 980                                            enum amd_powergating_state state)
 981 {
 982         /* TODO */
 983         return 0;
 984 }
 985
 986 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
 987 {
 988         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 989         uint32_t tmp;
 990
 991         if (amdgpu_sriov_vf(adev))
 992                 *flags = 0;
 993
 994         adev->nbio.funcs->get_clockgating_state(adev, flags);
 995
 996         /* AMD_CG_SUPPORT_HDP_MGCG */
 997         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 998         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 999                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1000                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1001                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1002                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1003                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
1004                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1005
1006         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
1007         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1008         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
1009                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1010         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
1011                 *flags |= AMD_CG_SUPPORT_HDP_DS;
1012         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
1013                 *flags |= AMD_CG_SUPPORT_HDP_SD;
1014
1015         return;
1016 }
1017
1018 static const struct amd_ip_funcs nv_common_ip_funcs = {
1019         .name = "nv_common",
1020         .early_init = nv_common_early_init,
1021         .late_init = nv_common_late_init,
1022         .sw_init = nv_common_sw_init,
1023         .sw_fini = nv_common_sw_fini,
1024         .hw_init = nv_common_hw_init,
1025         .hw_fini = nv_common_hw_fini,
1026         .suspend = nv_common_suspend,
1027         .resume = nv_common_resume,
1028         .is_idle = nv_common_is_idle,
1029         .wait_for_idle = nv_common_wait_for_idle,
1030         .soft_reset = nv_common_soft_reset,
1031         .set_clockgating_state = nv_common_set_clockgating_state,
1032         .set_powergating_state = nv_common_set_powergating_state,
1033         .get_clockgating_state = nv_common_get_clockgating_state,
1034 };