drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <[email protected]>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  44
  45 /* Firmware versions for VI */
  46 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
  47 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
  48 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
  49 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
  50
  51 /* Polaris10/11 firmware version */
  52 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
  53
  54 /* Firmware Names */
  55 #ifdef CONFIG_DRM_AMDGPU_CIK
  56 #define FIRMWARE_BONAIRE        "amdgpu/bonaire_uvd.bin"
  57 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
  58 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
  59 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
  60 #define FIRMWARE_MULLINS        "amdgpu/mullins_uvd.bin"
  61 #endif
  62 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  63 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  64 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  65 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
  66 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
  67 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
  68 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_uvd.bin"
  69 #define FIRMWARE_VEGAM          "amdgpu/vegam_uvd.bin"
  70
  71 #define FIRMWARE_VEGA10         "amdgpu/vega10_uvd.bin"
  72 #define FIRMWARE_VEGA12         "amdgpu/vega12_uvd.bin"
  73 #define FIRMWARE_VEGA20         "amdgpu/vega20_uvd.bin"
  74
  75 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
  76 #define UVD_GPCOM_VCPU_CMD              0x03c3
  77 #define UVD_GPCOM_VCPU_DATA0    0x03c4
  78 #define UVD_GPCOM_VCPU_DATA1    0x03c5
  79 #define UVD_NO_OP                               0x03ff
  80 #define UVD_BASE_SI                             0x3800
  81
  82 /**
  83  * amdgpu_uvd_cs_ctx - Command submission parser context
  84  *
  85  * Used for emulating virtual memory support on UVD 4.2.
  86  */
  87 struct amdgpu_uvd_cs_ctx {
  88         struct amdgpu_cs_parser *parser;
  89         unsigned reg, count;
  90         unsigned data0, data1;
  91         unsigned idx;
  92         unsigned ib_idx;
  93
  94         /* does the IB has a msg command */
  95         bool has_msg_cmd;
  96
  97         /* minimum buffer sizes */
  98         unsigned *buf_sizes;
  99 };
 100
 101 #ifdef CONFIG_DRM_AMDGPU_CIK
 102 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 103 MODULE_FIRMWARE(FIRMWARE_KABINI);
 104 MODULE_FIRMWARE(FIRMWARE_KAVERI);
 105 MODULE_FIRMWARE(FIRMWARE_HAWAII);
 106 MODULE_FIRMWARE(FIRMWARE_MULLINS);
 107 #endif
 108 MODULE_FIRMWARE(FIRMWARE_TONGA);
 109 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 110 MODULE_FIRMWARE(FIRMWARE_FIJI);
 111 MODULE_FIRMWARE(FIRMWARE_STONEY);
 112 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 113 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 114 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
 115 MODULE_FIRMWARE(FIRMWARE_VEGAM);
 116
 117 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 118 MODULE_FIRMWARE(FIRMWARE_VEGA12);
 119 MODULE_FIRMWARE(FIRMWARE_VEGA20);
 120
 121 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 122
 123 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 124 {
 125         struct amdgpu_ring *ring;
 126         struct drm_sched_rq *rq;
 127         unsigned long bo_size;
 128         const char *fw_name;
 129         const struct common_firmware_header *hdr;
 130         unsigned family_id;
 131         int i, j, r;
 132
 133         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 134
 135         switch (adev->asic_type) {
 136 #ifdef CONFIG_DRM_AMDGPU_CIK
 137         case CHIP_BONAIRE:
 138                 fw_name = FIRMWARE_BONAIRE;
 139                 break;
 140         case CHIP_KABINI:
 141                 fw_name = FIRMWARE_KABINI;
 142                 break;
 143         case CHIP_KAVERI:
 144                 fw_name = FIRMWARE_KAVERI;
 145                 break;
 146         case CHIP_HAWAII:
 147                 fw_name = FIRMWARE_HAWAII;
 148                 break;
 149         case CHIP_MULLINS:
 150                 fw_name = FIRMWARE_MULLINS;
 151                 break;
 152 #endif
 153         case CHIP_TONGA:
 154                 fw_name = FIRMWARE_TONGA;
 155                 break;
 156         case CHIP_FIJI:
 157                 fw_name = FIRMWARE_FIJI;
 158                 break;
 159         case CHIP_CARRIZO:
 160                 fw_name = FIRMWARE_CARRIZO;
 161                 break;
 162         case CHIP_STONEY:
 163                 fw_name = FIRMWARE_STONEY;
 164                 break;
 165         case CHIP_POLARIS10:
 166                 fw_name = FIRMWARE_POLARIS10;
 167                 break;
 168         case CHIP_POLARIS11:
 169                 fw_name = FIRMWARE_POLARIS11;
 170                 break;
 171         case CHIP_POLARIS12:
 172                 fw_name = FIRMWARE_POLARIS12;
 173                 break;
 174         case CHIP_VEGA10:
 175                 fw_name = FIRMWARE_VEGA10;
 176                 break;
 177         case CHIP_VEGA12:
 178                 fw_name = FIRMWARE_VEGA12;
 179                 break;
 180         case CHIP_VEGAM:
 181                 fw_name = FIRMWARE_VEGAM;
 182                 break;
 183         case CHIP_VEGA20:
 184                 fw_name = FIRMWARE_VEGA20;
 185                 break;
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 191         if (r) {
 192                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 193                         fw_name);
 194                 return r;
 195         }
 196
 197         r = amdgpu_ucode_validate(adev->uvd.fw);
 198         if (r) {
 199                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 200                         fw_name);
 201                 release_firmware(adev->uvd.fw);
 202                 adev->uvd.fw = NULL;
 203                 return r;
 204         }
 205
 206         /* Set the default UVD handles that the firmware can handle */
 207         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 208
 209         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 210         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 211
 212         if (adev->asic_type < CHIP_VEGA20) {
 213                 unsigned version_major, version_minor;
 214
 215                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 216                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 217                 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 218                         version_major, version_minor, family_id);
 219
 220                 /*
 221                  * Limit the number of UVD handles depending on microcode major
 222                  * and minor versions. The firmware version which has 40 UVD
 223                  * instances support is 1.80. So all subsequent versions should
 224                  * also have the same support.
 225                  */
 226                 if ((version_major > 0x01) ||
 227                     ((version_major == 0x01) && (version_minor >= 0x50)))
 228                         adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 229
 230                 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 231                                         (family_id << 8));
 232
 233                 if ((adev->asic_type == CHIP_POLARIS10 ||
 234                      adev->asic_type == CHIP_POLARIS11) &&
 235                     (adev->uvd.fw_version < FW_1_66_16))
 236                         DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
 237                                   version_major, version_minor);
 238         } else {
 239                 unsigned int enc_major, enc_minor, dec_minor;
 240
 241                 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 242                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
 243                 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
 244                 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
 245                         enc_major, enc_minor, dec_minor, family_id);
 246
 247                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 248
 249                 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
 250         }
 251
 252         bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 253                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 254         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 255                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 256
 257         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 258
 259                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 260                                             AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
 261                                             &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
 262                 if (r) {
 263                         dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 264                         return r;
 265                 }
 266         }
 267
 268         ring = &adev->uvd.inst[0].ring;
 269         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 270         r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
 271         if (r) {
 272                 DRM_ERROR("Failed setting up UVD kernel entity.\n");
 273                 return r;
 274         }
 275         for (i = 0; i < adev->uvd.max_handles; ++i) {
 276                 atomic_set(&adev->uvd.handles[i], 0);
 277                 adev->uvd.filp[i] = NULL;
 278         }
 279
 280         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 281         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 282                 adev->uvd.address_64_bit = true;
 283
 284         switch (adev->asic_type) {
 285         case CHIP_TONGA:
 286                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
 287                 break;
 288         case CHIP_CARRIZO:
 289                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
 290                 break;
 291         case CHIP_FIJI:
 292                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
 293                 break;
 294         case CHIP_STONEY:
 295                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
 296                 break;
 297         default:
 298                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
 299         }
 300
 301         return 0;
 302 }
 303
 304 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 305 {
 306         int i, j;
 307
 308         drm_sched_entity_destroy(&adev->uvd.entity);
 309
 310         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 311                 kfree(adev->uvd.inst[j].saved_bo);
 312
 313                 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
 314                                       &adev->uvd.inst[j].gpu_addr,
 315                                       (void **)&adev->uvd.inst[j].cpu_addr);
 316
 317                 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
 318
 319                 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
 320                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 321         }
 322         release_firmware(adev->uvd.fw);
 323
 324         return 0;
 325 }
 326
 327 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 328 {
 329         unsigned size;
 330         void *ptr;
 331         int i, j;
 332
 333         cancel_delayed_work_sync(&adev->uvd.idle_work);
 334
 335         /* only valid for physical mode */
 336         if (adev->asic_type < CHIP_POLARIS10) {
 337                 for (i = 0; i < adev->uvd.max_handles; ++i)
 338                         if (atomic_read(&adev->uvd.handles[i]))
 339                                 break;
 340
 341                 if (i == adev->uvd.max_handles)
 342                         return 0;
 343         }
 344
 345         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 346                 if (adev->uvd.inst[j].vcpu_bo == NULL)
 347                         continue;
 348
 349                 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
 350                 ptr = adev->uvd.inst[j].cpu_addr;
 351
 352                 adev->uvd.inst[j].saved_bo = kmalloc(size, GFP_KERNEL);
 353                 if (!adev->uvd.inst[j].saved_bo)
 354                         return -ENOMEM;
 355
 356                 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
 357         }
 358         return 0;
 359 }
 360
 361 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 362 {
 363         unsigned size;
 364         void *ptr;
 365         int i;
 366
 367         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 368                 if (adev->uvd.inst[i].vcpu_bo == NULL)
 369                         return -EINVAL;
 370
 371                 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
 372                 ptr = adev->uvd.inst[i].cpu_addr;
 373
 374                 if (adev->uvd.inst[i].saved_bo != NULL) {
 375                         memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
 376                         kfree(adev->uvd.inst[i].saved_bo);
 377                         adev->uvd.inst[i].saved_bo = NULL;
 378                 } else {
 379                         const struct common_firmware_header *hdr;
 380                         unsigned offset;
 381
 382                         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 383                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 384                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 385                                 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
 386                                             le32_to_cpu(hdr->ucode_size_bytes));
 387                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 388                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 389                         }
 390                         memset_io(ptr, 0, size);
 391                         /* to restore uvd fence seq */
 392                         amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
 393                 }
 394         }
 395         return 0;
 396 }
 397
 398 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 399 {
 400         struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
 401         int i, r;
 402
 403         for (i = 0; i < adev->uvd.max_handles; ++i) {
 404                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 405
 406                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 407                         struct dma_fence *fence;
 408
 409                         r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
 410                                                        &fence);
 411                         if (r) {
 412                                 DRM_ERROR("Error destroying UVD %d!\n", r);
 413                                 continue;
 414                         }
 415
 416                         dma_fence_wait(fence, false);
 417                         dma_fence_put(fence);
 418
 419                         adev->uvd.filp[i] = NULL;
 420                         atomic_set(&adev->uvd.handles[i], 0);
 421                 }
 422         }
 423 }
 424
 425 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
 426 {
 427         int i;
 428         for (i = 0; i < abo->placement.num_placement; ++i) {
 429                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 430                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 431         }
 432 }
 433
 434 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
 435 {
 436         uint32_t lo, hi;
 437         uint64_t addr;
 438
 439         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 440         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 441         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 442
 443         return addr;
 444 }
 445
 446 /**
 447  * amdgpu_uvd_cs_pass1 - first parsing round
 448  *
 449  * @ctx: UVD parser context
 450  *
 451  * Make sure UVD message and feedback buffers are in VRAM and
 452  * nobody is violating an 256MB boundary.
 453  */
 454 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 455 {
 456         struct ttm_operation_ctx tctx = { false, false };
 457         struct amdgpu_bo_va_mapping *mapping;
 458         struct amdgpu_bo *bo;
 459         uint32_t cmd;
 460         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 461         int r = 0;
 462
 463         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 464         if (r) {
 465                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 466                 return r;
 467         }
 468
 469         if (!ctx->parser->adev->uvd.address_64_bit) {
 470                 /* check if it's a message or feedback command */
 471                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 472                 if (cmd == 0x0 || cmd == 0x3) {
 473                         /* yes, force it into VRAM */
 474                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 475                         amdgpu_bo_placement_from_domain(bo, domain);
 476                 }
 477                 amdgpu_uvd_force_into_uvd_segment(bo);
 478
 479                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
 480         }
 481
 482         return r;
 483 }
 484
 485 /**
 486  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 487  *
 488  * @msg: pointer to message structure
 489  * @buf_sizes: returned buffer sizes
 490  *
 491  * Peek into the decode message and calculate the necessary buffer sizes.
 492  */
 493 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
 494         unsigned buf_sizes[])
 495 {
 496         unsigned stream_type = msg[4];
 497         unsigned width = msg[6];
 498         unsigned height = msg[7];
 499         unsigned dpb_size = msg[9];
 500         unsigned pitch = msg[28];
 501         unsigned level = msg[57];
 502
 503         unsigned width_in_mb = width / 16;
 504         unsigned height_in_mb = ALIGN(height / 16, 2);
 505         unsigned fs_in_mb = width_in_mb * height_in_mb;
 506
 507         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 508         unsigned min_ctx_size = ~0;
 509
 510         image_size = width * height;
 511         image_size += image_size / 2;
 512         image_size = ALIGN(image_size, 1024);
 513
 514         switch (stream_type) {
 515         case 0: /* H264 */
 516                 switch(level) {
 517                 case 30:
 518                         num_dpb_buffer = 8100 / fs_in_mb;
 519                         break;
 520                 case 31:
 521                         num_dpb_buffer = 18000 / fs_in_mb;
 522                         break;
 523                 case 32:
 524                         num_dpb_buffer = 20480 / fs_in_mb;
 525                         break;
 526                 case 41:
 527                         num_dpb_buffer = 32768 / fs_in_mb;
 528                         break;
 529                 case 42:
 530                         num_dpb_buffer = 34816 / fs_in_mb;
 531                         break;
 532                 case 50:
 533                         num_dpb_buffer = 110400 / fs_in_mb;
 534                         break;
 535                 case 51:
 536                         num_dpb_buffer = 184320 / fs_in_mb;
 537                         break;
 538                 default:
 539                         num_dpb_buffer = 184320 / fs_in_mb;
 540                         break;
 541                 }
 542                 num_dpb_buffer++;
 543                 if (num_dpb_buffer > 17)
 544                         num_dpb_buffer = 17;
 545
 546                 /* reference picture buffer */
 547                 min_dpb_size = image_size * num_dpb_buffer;
 548
 549                 /* macroblock context buffer */
 550                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 551
 552                 /* IT surface buffer */
 553                 min_dpb_size += width_in_mb * height_in_mb * 32;
 554                 break;
 555
 556         case 1: /* VC1 */
 557
 558                 /* reference picture buffer */
 559                 min_dpb_size = image_size * 3;
 560
 561                 /* CONTEXT_BUFFER */
 562                 min_dpb_size += width_in_mb * height_in_mb * 128;
 563
 564                 /* IT surface buffer */
 565                 min_dpb_size += width_in_mb * 64;
 566
 567                 /* DB surface buffer */
 568                 min_dpb_size += width_in_mb * 128;
 569
 570                 /* BP */
 571                 tmp = max(width_in_mb, height_in_mb);
 572                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 573                 break;
 574
 575         case 3: /* MPEG2 */
 576
 577                 /* reference picture buffer */
 578                 min_dpb_size = image_size * 3;
 579                 break;
 580
 581         case 4: /* MPEG4 */
 582
 583                 /* reference picture buffer */
 584                 min_dpb_size = image_size * 3;
 585
 586                 /* CM */
 587                 min_dpb_size += width_in_mb * height_in_mb * 64;
 588
 589                 /* IT surface buffer */
 590                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 591                 break;
 592
 593         case 7: /* H264 Perf */
 594                 switch(level) {
 595                 case 30:
 596                         num_dpb_buffer = 8100 / fs_in_mb;
 597                         break;
 598                 case 31:
 599                         num_dpb_buffer = 18000 / fs_in_mb;
 600                         break;
 601                 case 32:
 602                         num_dpb_buffer = 20480 / fs_in_mb;
 603                         break;
 604                 case 41:
 605                         num_dpb_buffer = 32768 / fs_in_mb;
 606                         break;
 607                 case 42:
 608                         num_dpb_buffer = 34816 / fs_in_mb;
 609                         break;
 610                 case 50:
 611                         num_dpb_buffer = 110400 / fs_in_mb;
 612                         break;
 613                 case 51:
 614                         num_dpb_buffer = 184320 / fs_in_mb;
 615                         break;
 616                 default:
 617                         num_dpb_buffer = 184320 / fs_in_mb;
 618                         break;
 619                 }
 620                 num_dpb_buffer++;
 621                 if (num_dpb_buffer > 17)
 622                         num_dpb_buffer = 17;
 623
 624                 /* reference picture buffer */
 625                 min_dpb_size = image_size * num_dpb_buffer;
 626
 627                 if (!adev->uvd.use_ctx_buf){
 628                         /* macroblock context buffer */
 629                         min_dpb_size +=
 630                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 631
 632                         /* IT surface buffer */
 633                         min_dpb_size += width_in_mb * height_in_mb * 32;
 634                 } else {
 635                         /* macroblock context buffer */
 636                         min_ctx_size =
 637                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 638                 }
 639                 break;
 640
 641         case 8: /* MJPEG */
 642                 min_dpb_size = 0;
 643                 break;
 644
 645         case 16: /* H265 */
 646                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 647                 image_size = ALIGN(image_size, 256);
 648
 649                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 650                 min_dpb_size = image_size * num_dpb_buffer;
 651                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 652                                            * 16 * num_dpb_buffer + 52 * 1024;
 653                 break;
 654
 655         default:
 656                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 657                 return -EINVAL;
 658         }
 659
 660         if (width > pitch) {
 661                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 662                 return -EINVAL;
 663         }
 664
 665         if (dpb_size < min_dpb_size) {
 666                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 667                           dpb_size, min_dpb_size);
 668                 return -EINVAL;
 669         }
 670
 671         buf_sizes[0x1] = dpb_size;
 672         buf_sizes[0x2] = image_size;
 673         buf_sizes[0x4] = min_ctx_size;
 674         return 0;
 675 }
 676
 677 /**
 678  * amdgpu_uvd_cs_msg - handle UVD message
 679  *
 680  * @ctx: UVD parser context
 681  * @bo: buffer object containing the message
 682  * @offset: offset into the buffer object
 683  *
 684  * Peek into the UVD message and extract the session id.
 685  * Make sure that we don't open up to many sessions.
 686  */
 687 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 688                              struct amdgpu_bo *bo, unsigned offset)
 689 {
 690         struct amdgpu_device *adev = ctx->parser->adev;
 691         int32_t *msg, msg_type, handle;
 692         void *ptr;
 693         long r;
 694         int i;
 695
 696         if (offset & 0x3F) {
 697                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 698                 return -EINVAL;
 699         }
 700
 701         r = amdgpu_bo_kmap(bo, &ptr);
 702         if (r) {
 703                 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
 704                 return r;
 705         }
 706
 707         msg = ptr + offset;
 708
 709         msg_type = msg[1];
 710         handle = msg[2];
 711
 712         if (handle == 0) {
 713                 DRM_ERROR("Invalid UVD handle!\n");
 714                 return -EINVAL;
 715         }
 716
 717         switch (msg_type) {
 718         case 0:
 719                 /* it's a create msg, calc image size (width * height) */
 720                 amdgpu_bo_kunmap(bo);
 721
 722                 /* try to alloc a new handle */
 723                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 724                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 725                                 DRM_ERROR(")Handle 0x%x already in use!\n",
 726                                           handle);
 727                                 return -EINVAL;
 728                         }
 729
 730                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 731                                 adev->uvd.filp[i] = ctx->parser->filp;
 732                                 return 0;
 733                         }
 734                 }
 735
 736                 DRM_ERROR("No more free UVD handles!\n");
 737                 return -ENOSPC;
 738
 739         case 1:
 740                 /* it's a decode msg, calc buffer sizes */
 741                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
 742                 amdgpu_bo_kunmap(bo);
 743                 if (r)
 744                         return r;
 745
 746                 /* validate the handle */
 747                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 748                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 749                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 750                                         DRM_ERROR("UVD handle collision detected!\n");
 751                                         return -EINVAL;
 752                                 }
 753                                 return 0;
 754                         }
 755                 }
 756
 757                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 758                 return -ENOENT;
 759
 760         case 2:
 761                 /* it's a destroy msg, free the handle */
 762                 for (i = 0; i < adev->uvd.max_handles; ++i)
 763                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 764                 amdgpu_bo_kunmap(bo);
 765                 return 0;
 766
 767         default:
 768                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 769                 return -EINVAL;
 770         }
 771         BUG();
 772         return -EINVAL;
 773 }
 774
 775 /**
 776  * amdgpu_uvd_cs_pass2 - second parsing round
 777  *
 778  * @ctx: UVD parser context
 779  *
 780  * Patch buffer addresses, make sure buffer sizes are correct.
 781  */
 782 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 783 {
 784         struct amdgpu_bo_va_mapping *mapping;
 785         struct amdgpu_bo *bo;
 786         uint32_t cmd;
 787         uint64_t start, end;
 788         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 789         int r;
 790
 791         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 792         if (r) {
 793                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 794                 return r;
 795         }
 796
 797         start = amdgpu_bo_gpu_offset(bo);
 798
 799         end = (mapping->last + 1 - mapping->start);
 800         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 801
 802         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 803         start += addr;
 804
 805         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 806                             lower_32_bits(start));
 807         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 808                             upper_32_bits(start));
 809
 810         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 811         if (cmd < 0x4) {
 812                 if ((end - start) < ctx->buf_sizes[cmd]) {
 813                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 814                                   (unsigned)(end - start),
 815                                   ctx->buf_sizes[cmd]);
 816                         return -EINVAL;
 817                 }
 818
 819         } else if (cmd == 0x206) {
 820                 if ((end - start) < ctx->buf_sizes[4]) {
 821                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 822                                           (unsigned)(end - start),
 823                                           ctx->buf_sizes[4]);
 824                         return -EINVAL;
 825                 }
 826         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 827                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 828                 return -EINVAL;
 829         }
 830
 831         if (!ctx->parser->adev->uvd.address_64_bit) {
 832                 if ((start >> 28) != ((end - 1) >> 28)) {
 833                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 834                                   start, end);
 835                         return -EINVAL;
 836                 }
 837
 838                 if ((cmd == 0 || cmd == 0x3) &&
 839                     (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
 840                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 841                                   start, end);
 842                         return -EINVAL;
 843                 }
 844         }
 845
 846         if (cmd == 0) {
 847                 ctx->has_msg_cmd = true;
 848                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 849                 if (r)
 850                         return r;
 851         } else if (!ctx->has_msg_cmd) {
 852                 DRM_ERROR("Message needed before other commands are send!\n");
 853                 return -EINVAL;
 854         }
 855
 856         return 0;
 857 }
 858
 859 /**
 860  * amdgpu_uvd_cs_reg - parse register writes
 861  *
 862  * @ctx: UVD parser context
 863  * @cb: callback function
 864  *
 865  * Parse the register writes, call cb on each complete command.
 866  */
 867 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 868                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 869 {
 870         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 871         int i, r;
 872
 873         ctx->idx++;
 874         for (i = 0; i <= ctx->count; ++i) {
 875                 unsigned reg = ctx->reg + i;
 876
 877                 if (ctx->idx >= ib->length_dw) {
 878                         DRM_ERROR("Register command after end of CS!\n");
 879                         return -EINVAL;
 880                 }
 881
 882                 switch (reg) {
 883                 case mmUVD_GPCOM_VCPU_DATA0:
 884                         ctx->data0 = ctx->idx;
 885                         break;
 886                 case mmUVD_GPCOM_VCPU_DATA1:
 887                         ctx->data1 = ctx->idx;
 888                         break;
 889                 case mmUVD_GPCOM_VCPU_CMD:
 890                         r = cb(ctx);
 891                         if (r)
 892                                 return r;
 893                         break;
 894                 case mmUVD_ENGINE_CNTL:
 895                 case mmUVD_NO_OP:
 896                         break;
 897                 default:
 898                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 899                         return -EINVAL;
 900                 }
 901                 ctx->idx++;
 902         }
 903         return 0;
 904 }
 905
 906 /**
 907  * amdgpu_uvd_cs_packets - parse UVD packets
 908  *
 909  * @ctx: UVD parser context
 910  * @cb: callback function
 911  *
 912  * Parse the command stream packets.
 913  */
 914 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 915                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 916 {
 917         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 918         int r;
 919
 920         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 921                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 922                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 923                 switch (type) {
 924                 case PACKET_TYPE0:
 925                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 926                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 927                         r = amdgpu_uvd_cs_reg(ctx, cb);
 928                         if (r)
 929                                 return r;
 930                         break;
 931                 case PACKET_TYPE2:
 932                         ++ctx->idx;
 933                         break;
 934                 default:
 935                         DRM_ERROR("Unknown packet type %d !\n", type);
 936                         return -EINVAL;
 937                 }
 938         }
 939         return 0;
 940 }
 941
 942 /**
 943  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 944  *
 945  * @parser: Command submission parser context
 946  *
 947  * Parse the command stream, patch in addresses as necessary.
 948  */
 949 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 950 {
 951         struct amdgpu_uvd_cs_ctx ctx = {};
 952         unsigned buf_sizes[] = {
 953                 [0x00000000]    =       2048,
 954                 [0x00000001]    =       0xFFFFFFFF,
 955                 [0x00000002]    =       0xFFFFFFFF,
 956                 [0x00000003]    =       2048,
 957                 [0x00000004]    =       0xFFFFFFFF,
 958         };
 959         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 960         int r;
 961
 962         parser->job->vm = NULL;
 963         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 964
 965         if (ib->length_dw % 16) {
 966                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 967                           ib->length_dw);
 968                 return -EINVAL;
 969         }
 970
 971         ctx.parser = parser;
 972         ctx.buf_sizes = buf_sizes;
 973         ctx.ib_idx = ib_idx;
 974
 975         /* first round only required on chips without UVD 64 bit address support */
 976         if (!parser->adev->uvd.address_64_bit) {
 977                 /* first round, make sure the buffers are actually in the UVD segment */
 978                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 979                 if (r)
 980                         return r;
 981         }
 982
 983         /* second round, patch buffer addresses into the command stream */
 984         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 985         if (r)
 986                 return r;
 987
 988         if (!ctx.has_msg_cmd) {
 989                 DRM_ERROR("UVD-IBs need a msg command!\n");
 990                 return -EINVAL;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 997                                bool direct, struct dma_fence **fence)
 998 {
 999         struct amdgpu_device *adev = ring->adev;
1000         struct dma_fence *f = NULL;
1001         struct amdgpu_job *job;
1002         struct amdgpu_ib *ib;
1003         uint32_t data[4];
1004         uint64_t addr;
1005         long r;
1006         int i;
1007         unsigned offset_idx = 0;
1008         unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1009
1010         amdgpu_bo_kunmap(bo);
1011         amdgpu_bo_unpin(bo);
1012
1013         if (!ring->adev->uvd.address_64_bit) {
1014                 struct ttm_operation_ctx ctx = { true, false };
1015
1016                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1017                 amdgpu_uvd_force_into_uvd_segment(bo);
1018                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1019                 if (r)
1020                         goto err;
1021         }
1022
1023         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1024         if (r)
1025                 goto err;
1026
1027         if (adev->asic_type >= CHIP_VEGA10) {
1028                 offset_idx = 1 + ring->me;
1029                 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1030                 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1031         }
1032
1033         data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1034         data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1035         data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1036         data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1037
1038         ib = &job->ibs[0];
1039         addr = amdgpu_bo_gpu_offset(bo);
1040         ib->ptr[0] = data[0];
1041         ib->ptr[1] = addr;
1042         ib->ptr[2] = data[1];
1043         ib->ptr[3] = addr >> 32;
1044         ib->ptr[4] = data[2];
1045         ib->ptr[5] = 0;
1046         for (i = 6; i < 16; i += 2) {
1047                 ib->ptr[i] = data[3];
1048                 ib->ptr[i+1] = 0;
1049         }
1050         ib->length_dw = 16;
1051
1052         if (direct) {
1053                 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1054                                                         true, false,
1055                                                         msecs_to_jiffies(10));
1056                 if (r == 0)
1057                         r = -ETIMEDOUT;
1058                 if (r < 0)
1059                         goto err_free;
1060
1061                 r = amdgpu_job_submit_direct(job, ring, &f);
1062                 if (r)
1063                         goto err_free;
1064         } else {
1065                 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1066                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1067                 if (r)
1068                         goto err_free;
1069
1070                 r = amdgpu_job_submit(job, &adev->uvd.entity,
1071                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1072                 if (r)
1073                         goto err_free;
1074         }
1075
1076         amdgpu_bo_fence(bo, f, false);
1077         amdgpu_bo_unreserve(bo);
1078         amdgpu_bo_unref(&bo);
1079
1080         if (fence)
1081                 *fence = dma_fence_get(f);
1082         dma_fence_put(f);
1083
1084         return 0;
1085
1086 err_free:
1087         amdgpu_job_free(job);
1088
1089 err:
1090         amdgpu_bo_unreserve(bo);
1091         amdgpu_bo_unref(&bo);
1092         return r;
1093 }
1094
1095 /* multiple fence commands without any stream commands in between can
1096    crash the vcpu so just try to emmit a dummy create/destroy msg to
1097    avoid this */
1098 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1099                               struct dma_fence **fence)
1100 {
1101         struct amdgpu_device *adev = ring->adev;
1102         struct amdgpu_bo *bo = NULL;
1103         uint32_t *msg;
1104         int r, i;
1105
1106         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1107                                       AMDGPU_GEM_DOMAIN_VRAM,
1108                                       &bo, NULL, (void **)&msg);
1109         if (r)
1110                 return r;
1111
1112         /* stitch together an UVD create msg */
1113         msg[0] = cpu_to_le32(0x00000de4);
1114         msg[1] = cpu_to_le32(0x00000000);
1115         msg[2] = cpu_to_le32(handle);
1116         msg[3] = cpu_to_le32(0x00000000);
1117         msg[4] = cpu_to_le32(0x00000000);
1118         msg[5] = cpu_to_le32(0x00000000);
1119         msg[6] = cpu_to_le32(0x00000000);
1120         msg[7] = cpu_to_le32(0x00000780);
1121         msg[8] = cpu_to_le32(0x00000440);
1122         msg[9] = cpu_to_le32(0x00000000);
1123         msg[10] = cpu_to_le32(0x01b37000);
1124         for (i = 11; i < 1024; ++i)
1125                 msg[i] = cpu_to_le32(0x0);
1126
1127         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1128 }
1129
1130 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1131                                bool direct, struct dma_fence **fence)
1132 {
1133         struct amdgpu_device *adev = ring->adev;
1134         struct amdgpu_bo *bo = NULL;
1135         uint32_t *msg;
1136         int r, i;
1137
1138         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1139                                       AMDGPU_GEM_DOMAIN_VRAM,
1140                                       &bo, NULL, (void **)&msg);
1141         if (r)
1142                 return r;
1143
1144         /* stitch together an UVD destroy msg */
1145         msg[0] = cpu_to_le32(0x00000de4);
1146         msg[1] = cpu_to_le32(0x00000002);
1147         msg[2] = cpu_to_le32(handle);
1148         msg[3] = cpu_to_le32(0x00000000);
1149         for (i = 4; i < 1024; ++i)
1150                 msg[i] = cpu_to_le32(0x0);
1151
1152         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1153 }
1154
1155 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1156 {
1157         struct amdgpu_device *adev =
1158                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1159         unsigned fences = 0, i, j;
1160
1161         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1162                 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1163                 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1164                         fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1165                 }
1166         }
1167
1168         if (fences == 0) {
1169                 if (adev->pm.dpm_enabled) {
1170                         amdgpu_dpm_enable_uvd(adev, false);
1171                 } else {
1172                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1173                         /* shutdown the UVD block */
1174                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1175                                                                AMD_PG_STATE_GATE);
1176                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1177                                                                AMD_CG_STATE_GATE);
1178                 }
1179         } else {
1180                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1181         }
1182 }
1183
1184 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1185 {
1186         struct amdgpu_device *adev = ring->adev;
1187         bool set_clocks;
1188
1189         if (amdgpu_sriov_vf(adev))
1190                 return;
1191
1192         set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1193         if (set_clocks) {
1194                 if (adev->pm.dpm_enabled) {
1195                         amdgpu_dpm_enable_uvd(adev, true);
1196                 } else {
1197                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1198                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1199                                                                AMD_CG_STATE_UNGATE);
1200                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1201                                                                AMD_PG_STATE_UNGATE);
1202                 }
1203         }
1204 }
1205
1206 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1207 {
1208         if (!amdgpu_sriov_vf(ring->adev))
1209                 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1210 }
1211
1212 /**
1213  * amdgpu_uvd_ring_test_ib - test ib execution
1214  *
1215  * @ring: amdgpu_ring pointer
1216  *
1217  * Test if we can successfully execute an IB
1218  */
1219 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1220 {
1221         struct dma_fence *fence;
1222         long r;
1223         uint32_t ip_instance = ring->me;
1224
1225         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1226         if (r) {
1227                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
1228                 goto error;
1229         }
1230
1231         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1232         if (r) {
1233                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
1234                 goto error;
1235         }
1236
1237         r = dma_fence_wait_timeout(fence, false, timeout);
1238         if (r == 0) {
1239                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
1240                 r = -ETIMEDOUT;
1241         } else if (r < 0) {
1242                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
1243         } else {
1244                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
1245                 r = 0;
1246         }
1247
1248         dma_fence_put(fence);
1249
1250 error:
1251         return r;
1252 }
1253
1254 /**
1255  * amdgpu_uvd_used_handles - returns used UVD handles
1256  *
1257  * @adev: amdgpu_device pointer
1258  *
1259  * Returns the number of UVD handles in use
1260  */
1261 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1262 {
1263         unsigned i;
1264         uint32_t used_handles = 0;
1265
1266         for (i = 0; i < adev->uvd.max_handles; ++i) {
1267                 /*
1268                  * Handles can be freed in any order, and not
1269                  * necessarily linear. So we need to count
1270                  * all non-zero handles.
1271                  */
1272                 if (atomic_read(&adev->uvd.handles[i]))
1273                         used_handles++;
1274         }
1275
1276         return used_handles;
1277 }