drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 114
 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 119
 120 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 139
 140 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 142 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 144 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 146 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 148 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 150 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 152
 153 #define mmCPG_PSP_DEBUG                         0x5c10
 154 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 155 #define mmCPC_PSP_DEBUG                         0x5c11
 156 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 159
 160 //CC_GC_SA_UNIT_DISABLE
 161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 165 //GC_USER_SA_UNIT_DISABLE
 166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 170 //PA_SC_ENHANCE_3
 171 #define mmPA_SC_ENHANCE_3                       0x1085
 172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 175
 176 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 178
 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 183
 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 186
 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 189
 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 196
 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 222
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 229
 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 236
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 243
 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 250
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 257
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 264
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 271
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 278
 279 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 320 };
 321
 322 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
 323         /* Pending on emulation bring up */
 324 };
 325
 326 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1379 };
1380
1381 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1420 };
1421
1422 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1468         /* Pending on emulation bring up */
1469 };
1470
1471 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2092 };
2093
2094 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2095         /* Pending on emulation bring up */
2096 };
2097
2098 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3151 };
3152
3153 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3197 };
3198
3199 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3200         /* Pending on emulation bring up */
3201 };
3202
3203 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3245
3246         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3248 };
3249
3250 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3275
3276         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3278 };
3279
3280 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3301 };
3302
3303 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3340 };
3341
3342 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3375 };
3376
3377 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3412 };
3413
3414 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3437 };
3438
3439 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3462 };
3463
3464 #define DEFAULT_SH_MEM_CONFIG \
3465         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3466          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3467          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3468          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3469
3470 /* TODO: pending on golden setting value of gb address config */
3471 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3472
3473 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3474 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3475 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3476 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3477 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3478 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3479                                  struct amdgpu_cu_info *cu_info);
3480 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3481 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3482                                    u32 sh_num, u32 instance, int xcc_id);
3483 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3484
3485 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3486 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3487 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3488 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3489 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3490 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3491 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3492 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3493 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3494 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3495 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3496                                            uint16_t pasid, uint32_t flush_type,
3497                                            bool all_hub, uint8_t dst_sel);
3498 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3499                                                unsigned int vmid);
3500
3501 static int gfx_v10_0_set_powergating_state(void *handle,
3502                                           enum amd_powergating_state state);
3503 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3504 {
3505         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3506         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3507                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3508         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3509         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3510         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3511         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3512         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3513         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3514 }
3515
3516 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3517                                  struct amdgpu_ring *ring)
3518 {
3519         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3520         uint64_t wptr_addr = ring->wptr_gpu_addr;
3521         uint32_t eng_sel = 0;
3522
3523         switch (ring->funcs->type) {
3524         case AMDGPU_RING_TYPE_COMPUTE:
3525                 eng_sel = 0;
3526                 break;
3527         case AMDGPU_RING_TYPE_GFX:
3528                 eng_sel = 4;
3529                 break;
3530         case AMDGPU_RING_TYPE_MES:
3531                 eng_sel = 5;
3532                 break;
3533         default:
3534                 WARN_ON(1);
3535         }
3536
3537         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3538         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3539         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3540                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3541                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3542                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3543                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3544                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3545                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3546                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3547                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3548                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3549         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3550         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3551         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3552         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3553         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3554 }
3555
3556 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3557                                    struct amdgpu_ring *ring,
3558                                    enum amdgpu_unmap_queues_action action,
3559                                    u64 gpu_addr, u64 seq)
3560 {
3561         struct amdgpu_device *adev = kiq_ring->adev;
3562         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3563
3564         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3565                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3566                 return;
3567         }
3568
3569         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3570         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3571                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3572                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3573                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3574                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3575         amdgpu_ring_write(kiq_ring,
3576                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3577
3578         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3579                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3580                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3581                 amdgpu_ring_write(kiq_ring, seq);
3582         } else {
3583                 amdgpu_ring_write(kiq_ring, 0);
3584                 amdgpu_ring_write(kiq_ring, 0);
3585                 amdgpu_ring_write(kiq_ring, 0);
3586         }
3587 }
3588
3589 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3590                                    struct amdgpu_ring *ring,
3591                                    u64 addr,
3592                                    u64 seq)
3593 {
3594         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3595
3596         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3597         amdgpu_ring_write(kiq_ring,
3598                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3599                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3600                           PACKET3_QUERY_STATUS_COMMAND(2));
3601         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3602                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3603                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3604         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3605         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3606         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3607         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3608 }
3609
3610 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3611                                 uint16_t pasid, uint32_t flush_type,
3612                                 bool all_hub)
3613 {
3614         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3615 }
3616
3617 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3618         .kiq_set_resources = gfx10_kiq_set_resources,
3619         .kiq_map_queues = gfx10_kiq_map_queues,
3620         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3621         .kiq_query_status = gfx10_kiq_query_status,
3622         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3623         .set_resources_size = 8,
3624         .map_queues_size = 7,
3625         .unmap_queues_size = 6,
3626         .query_status_size = 7,
3627         .invalidate_tlbs_size = 2,
3628 };
3629
3630 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3631 {
3632         adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3633 }
3634
3635 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3636 {
3637         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3638         case IP_VERSION(10, 1, 10):
3639                 soc15_program_register_sequence(adev,
3640                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3641                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3642                 break;
3643         case IP_VERSION(10, 1, 1):
3644                 soc15_program_register_sequence(adev,
3645                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3646                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3647                 break;
3648         case IP_VERSION(10, 1, 2):
3649                 soc15_program_register_sequence(adev,
3650                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3651                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3659 {
3660         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3661         case IP_VERSION(10, 1, 10):
3662                 soc15_program_register_sequence(adev,
3663                                                 golden_settings_gc_10_1,
3664                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3665                 soc15_program_register_sequence(adev,
3666                                                 golden_settings_gc_10_0_nv10,
3667                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3668                 break;
3669         case IP_VERSION(10, 1, 1):
3670                 soc15_program_register_sequence(adev,
3671                                                 golden_settings_gc_10_1_1,
3672                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3673                 soc15_program_register_sequence(adev,
3674                                                 golden_settings_gc_10_1_nv14,
3675                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3676                 break;
3677         case IP_VERSION(10, 1, 2):
3678                 soc15_program_register_sequence(adev,
3679                                                 golden_settings_gc_10_1_2,
3680                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3681                 soc15_program_register_sequence(adev,
3682                                                 golden_settings_gc_10_1_2_nv12,
3683                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3684                 break;
3685         case IP_VERSION(10, 3, 0):
3686                 soc15_program_register_sequence(adev,
3687                                                 golden_settings_gc_10_3,
3688                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3689                 soc15_program_register_sequence(adev,
3690                                                 golden_settings_gc_10_3_sienna_cichlid,
3691                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3692                 break;
3693         case IP_VERSION(10, 3, 2):
3694                 soc15_program_register_sequence(adev,
3695                                                 golden_settings_gc_10_3_2,
3696                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3697                 break;
3698         case IP_VERSION(10, 3, 1):
3699                 soc15_program_register_sequence(adev,
3700                                                 golden_settings_gc_10_3_vangogh,
3701                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3702                 break;
3703         case IP_VERSION(10, 3, 3):
3704                 soc15_program_register_sequence(adev,
3705                                                 golden_settings_gc_10_3_3,
3706                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3707                 break;
3708         case IP_VERSION(10, 3, 4):
3709                 soc15_program_register_sequence(adev,
3710                                                 golden_settings_gc_10_3_4,
3711                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3712                 break;
3713         case IP_VERSION(10, 3, 5):
3714                 soc15_program_register_sequence(adev,
3715                                                 golden_settings_gc_10_3_5,
3716                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3717                 break;
3718         case IP_VERSION(10, 1, 3):
3719         case IP_VERSION(10, 1, 4):
3720                 soc15_program_register_sequence(adev,
3721                                                 golden_settings_gc_10_0_cyan_skillfish,
3722                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3723                 break;
3724         case IP_VERSION(10, 3, 6):
3725                 soc15_program_register_sequence(adev,
3726                                                 golden_settings_gc_10_3_6,
3727                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3728                 break;
3729         case IP_VERSION(10, 3, 7):
3730                 soc15_program_register_sequence(adev,
3731                                                 golden_settings_gc_10_3_7,
3732                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3733                 break;
3734         default:
3735                 break;
3736         }
3737         gfx_v10_0_init_spm_golden_registers(adev);
3738 }
3739
3740 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3741                                        bool wc, uint32_t reg, uint32_t val)
3742 {
3743         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3744         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3745                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3746         amdgpu_ring_write(ring, reg);
3747         amdgpu_ring_write(ring, 0);
3748         amdgpu_ring_write(ring, val);
3749 }
3750
3751 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3752                                   int mem_space, int opt, uint32_t addr0,
3753                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3754                                   uint32_t inv)
3755 {
3756         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3757         amdgpu_ring_write(ring,
3758                           /* memory (1) or register (0) */
3759                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3760                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3761                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3762                            WAIT_REG_MEM_ENGINE(eng_sel)));
3763
3764         if (mem_space)
3765                 BUG_ON(addr0 & 0x3); /* Dword align */
3766         amdgpu_ring_write(ring, addr0);
3767         amdgpu_ring_write(ring, addr1);
3768         amdgpu_ring_write(ring, ref);
3769         amdgpu_ring_write(ring, mask);
3770         amdgpu_ring_write(ring, inv); /* poll interval */
3771 }
3772
3773 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3774 {
3775         struct amdgpu_device *adev = ring->adev;
3776         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3777         uint32_t tmp = 0;
3778         unsigned int i;
3779         int r;
3780
3781         WREG32(scratch, 0xCAFEDEAD);
3782         r = amdgpu_ring_alloc(ring, 3);
3783         if (r) {
3784                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3785                           ring->idx, r);
3786                 return r;
3787         }
3788
3789         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3790         amdgpu_ring_write(ring, scratch -
3791                           PACKET3_SET_UCONFIG_REG_START);
3792         amdgpu_ring_write(ring, 0xDEADBEEF);
3793         amdgpu_ring_commit(ring);
3794
3795         for (i = 0; i < adev->usec_timeout; i++) {
3796                 tmp = RREG32(scratch);
3797                 if (tmp == 0xDEADBEEF)
3798                         break;
3799                 if (amdgpu_emu_mode == 1)
3800                         msleep(1);
3801                 else
3802                         udelay(1);
3803         }
3804
3805         if (i >= adev->usec_timeout)
3806                 r = -ETIMEDOUT;
3807
3808         return r;
3809 }
3810
3811 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3812 {
3813         struct amdgpu_device *adev = ring->adev;
3814         struct amdgpu_ib ib;
3815         struct dma_fence *f = NULL;
3816         unsigned int index;
3817         uint64_t gpu_addr;
3818         volatile uint32_t *cpu_ptr;
3819         long r;
3820
3821         memset(&ib, 0, sizeof(ib));
3822
3823         if (ring->is_mes_queue) {
3824                 uint32_t padding, offset;
3825
3826                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3827                 padding = amdgpu_mes_ctx_get_offs(ring,
3828                                                   AMDGPU_MES_CTX_PADDING_OFFS);
3829
3830                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3831                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3832
3833                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3834                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3835                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3836         } else {
3837                 r = amdgpu_device_wb_get(adev, &index);
3838                 if (r)
3839                         return r;
3840
3841                 gpu_addr = adev->wb.gpu_addr + (index * 4);
3842                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3843                 cpu_ptr = &adev->wb.wb[index];
3844
3845                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3846                 if (r) {
3847                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3848                         goto err1;
3849                 }
3850         }
3851
3852         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3853         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3854         ib.ptr[2] = lower_32_bits(gpu_addr);
3855         ib.ptr[3] = upper_32_bits(gpu_addr);
3856         ib.ptr[4] = 0xDEADBEEF;
3857         ib.length_dw = 5;
3858
3859         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3860         if (r)
3861                 goto err2;
3862
3863         r = dma_fence_wait_timeout(f, false, timeout);
3864         if (r == 0) {
3865                 r = -ETIMEDOUT;
3866                 goto err2;
3867         } else if (r < 0) {
3868                 goto err2;
3869         }
3870
3871         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3872                 r = 0;
3873         else
3874                 r = -EINVAL;
3875 err2:
3876         if (!ring->is_mes_queue)
3877                 amdgpu_ib_free(adev, &ib, NULL);
3878         dma_fence_put(f);
3879 err1:
3880         if (!ring->is_mes_queue)
3881                 amdgpu_device_wb_free(adev, index);
3882         return r;
3883 }
3884
3885 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3886 {
3887         amdgpu_ucode_release(&adev->gfx.pfp_fw);
3888         amdgpu_ucode_release(&adev->gfx.me_fw);
3889         amdgpu_ucode_release(&adev->gfx.ce_fw);
3890         amdgpu_ucode_release(&adev->gfx.rlc_fw);
3891         amdgpu_ucode_release(&adev->gfx.mec_fw);
3892         amdgpu_ucode_release(&adev->gfx.mec2_fw);
3893
3894         kfree(adev->gfx.rlc.register_list_format);
3895 }
3896
3897 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3898 {
3899         adev->gfx.cp_fw_write_wait = false;
3900
3901         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3902         case IP_VERSION(10, 1, 10):
3903         case IP_VERSION(10, 1, 2):
3904         case IP_VERSION(10, 1, 1):
3905         case IP_VERSION(10, 1, 3):
3906         case IP_VERSION(10, 1, 4):
3907                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3908                     (adev->gfx.me_feature_version >= 27) &&
3909                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3910                     (adev->gfx.pfp_feature_version >= 27) &&
3911                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3912                     (adev->gfx.mec_feature_version >= 27))
3913                         adev->gfx.cp_fw_write_wait = true;
3914                 break;
3915         case IP_VERSION(10, 3, 0):
3916         case IP_VERSION(10, 3, 2):
3917         case IP_VERSION(10, 3, 1):
3918         case IP_VERSION(10, 3, 4):
3919         case IP_VERSION(10, 3, 5):
3920         case IP_VERSION(10, 3, 6):
3921         case IP_VERSION(10, 3, 3):
3922         case IP_VERSION(10, 3, 7):
3923                 adev->gfx.cp_fw_write_wait = true;
3924                 break;
3925         default:
3926                 break;
3927         }
3928
3929         if (!adev->gfx.cp_fw_write_wait)
3930                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3931 }
3932
3933 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3934 {
3935         bool ret = false;
3936
3937         switch (adev->pdev->revision) {
3938         case 0xc2:
3939         case 0xc3:
3940                 ret = true;
3941                 break;
3942         default:
3943                 ret = false;
3944                 break;
3945         }
3946
3947         return ret;
3948 }
3949
3950 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3951 {
3952         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3953         case IP_VERSION(10, 1, 10):
3954                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3955                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3956                 break;
3957         default:
3958                 break;
3959         }
3960 }
3961
3962 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3963 {
3964         char fw_name[40];
3965         char ucode_prefix[30];
3966         const char *wks = "";
3967         int err;
3968         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3969         uint16_t version_major;
3970         uint16_t version_minor;
3971
3972         DRM_DEBUG("\n");
3973
3974         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
3975             (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
3976                 wks = "_wks";
3977         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
3978
3979         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
3980         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
3981         if (err)
3982                 goto out;
3983         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
3984
3985         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
3986         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
3987         if (err)
3988                 goto out;
3989         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
3990
3991         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
3992         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
3993         if (err)
3994                 goto out;
3995         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
3996
3997         if (!amdgpu_sriov_vf(adev)) {
3998                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
3999                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4000                 if (err)
4001                         goto out;
4002
4003                 /* don't validate this firmware. There are apparently firmwares
4004                  * in the wild with incorrect size in the header
4005                  */
4006                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4007                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4008                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4009                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4010                 if (err)
4011                         goto out;
4012         }
4013
4014         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4015         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4016         if (err)
4017                 goto out;
4018         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4019         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4020
4021         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4022         err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4023         if (!err) {
4024                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4025                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4026         } else {
4027                 err = 0;
4028                 adev->gfx.mec2_fw = NULL;
4029         }
4030
4031         gfx_v10_0_check_fw_write_wait(adev);
4032 out:
4033         if (err) {
4034                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4035                 amdgpu_ucode_release(&adev->gfx.me_fw);
4036                 amdgpu_ucode_release(&adev->gfx.ce_fw);
4037                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4038                 amdgpu_ucode_release(&adev->gfx.mec_fw);
4039                 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4040         }
4041
4042         gfx_v10_0_check_gfxoff_flag(adev);
4043
4044         return err;
4045 }
4046
4047 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4048 {
4049         u32 count = 0;
4050         const struct cs_section_def *sect = NULL;
4051         const struct cs_extent_def *ext = NULL;
4052
4053         /* begin clear state */
4054         count += 2;
4055         /* context control state */
4056         count += 3;
4057
4058         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4059                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4060                         if (sect->id == SECT_CONTEXT)
4061                                 count += 2 + ext->reg_count;
4062                         else
4063                                 return 0;
4064                 }
4065         }
4066
4067         /* set PA_SC_TILE_STEERING_OVERRIDE */
4068         count += 3;
4069         /* end clear state */
4070         count += 2;
4071         /* clear state */
4072         count += 2;
4073
4074         return count;
4075 }
4076
4077 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4078                                     volatile u32 *buffer)
4079 {
4080         u32 count = 0, i;
4081         const struct cs_section_def *sect = NULL;
4082         const struct cs_extent_def *ext = NULL;
4083         int ctx_reg_offset;
4084
4085         if (adev->gfx.rlc.cs_data == NULL)
4086                 return;
4087         if (buffer == NULL)
4088                 return;
4089
4090         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4091         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4092
4093         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4094         buffer[count++] = cpu_to_le32(0x80000000);
4095         buffer[count++] = cpu_to_le32(0x80000000);
4096
4097         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4098                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4099                         if (sect->id == SECT_CONTEXT) {
4100                                 buffer[count++] =
4101                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4102                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4103                                                 PACKET3_SET_CONTEXT_REG_START);
4104                                 for (i = 0; i < ext->reg_count; i++)
4105                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4106                         } else {
4107                                 return;
4108                         }
4109                 }
4110         }
4111
4112         ctx_reg_offset =
4113                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4114         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4115         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4116         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4117
4118         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4119         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4120
4121         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4122         buffer[count++] = cpu_to_le32(0);
4123 }
4124
4125 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4126 {
4127         /* clear state block */
4128         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4129                         &adev->gfx.rlc.clear_state_gpu_addr,
4130                         (void **)&adev->gfx.rlc.cs_ptr);
4131
4132         /* jump table block */
4133         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4134                         &adev->gfx.rlc.cp_table_gpu_addr,
4135                         (void **)&adev->gfx.rlc.cp_table_ptr);
4136 }
4137
4138 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4139 {
4140         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4141
4142         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4143         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4144         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4145         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4146         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4147         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4148         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4149         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4150         case IP_VERSION(10, 3, 0):
4151                 reg_access_ctrl->spare_int =
4152                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4153                 break;
4154         default:
4155                 reg_access_ctrl->spare_int =
4156                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4157                 break;
4158         }
4159         adev->gfx.rlc.rlcg_reg_access_supported = true;
4160 }
4161
4162 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4163 {
4164         const struct cs_section_def *cs_data;
4165         int r;
4166
4167         adev->gfx.rlc.cs_data = gfx10_cs_data;
4168
4169         cs_data = adev->gfx.rlc.cs_data;
4170
4171         if (cs_data) {
4172                 /* init clear state block */
4173                 r = amdgpu_gfx_rlc_init_csb(adev);
4174                 if (r)
4175                         return r;
4176         }
4177
4178         return 0;
4179 }
4180
4181 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4182 {
4183         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4184         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4185 }
4186
4187 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4188 {
4189         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4190
4191         amdgpu_gfx_graphics_queue_acquire(adev);
4192 }
4193
4194 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4195 {
4196         int r;
4197         u32 *hpd;
4198         const __le32 *fw_data = NULL;
4199         unsigned int fw_size;
4200         u32 *fw = NULL;
4201         size_t mec_hpd_size;
4202
4203         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4204
4205         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4206
4207         /* take ownership of the relevant compute queues */
4208         amdgpu_gfx_compute_queue_acquire(adev);
4209         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4210
4211         if (mec_hpd_size) {
4212                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4213                                               AMDGPU_GEM_DOMAIN_GTT,
4214                                               &adev->gfx.mec.hpd_eop_obj,
4215                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4216                                               (void **)&hpd);
4217                 if (r) {
4218                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4219                         gfx_v10_0_mec_fini(adev);
4220                         return r;
4221                 }
4222
4223                 memset(hpd, 0, mec_hpd_size);
4224
4225                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4226                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4227         }
4228
4229         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4230                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4231
4232                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4233                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4234                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4235
4236                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4237                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4238                                               &adev->gfx.mec.mec_fw_obj,
4239                                               &adev->gfx.mec.mec_fw_gpu_addr,
4240                                               (void **)&fw);
4241                 if (r) {
4242                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4243                         gfx_v10_0_mec_fini(adev);
4244                         return r;
4245                 }
4246
4247                 memcpy(fw, fw_data, fw_size);
4248
4249                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4250                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4251         }
4252
4253         return 0;
4254 }
4255
4256 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4257 {
4258         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4259                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4260                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4261         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4262 }
4263
4264 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4265                            uint32_t thread, uint32_t regno,
4266                            uint32_t num, uint32_t *out)
4267 {
4268         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4269                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4270                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4271                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4272                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4273         while (num--)
4274                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4275 }
4276
4277 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4278 {
4279         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4280          * field when performing a select_se_sh so it should be
4281          * zero here
4282          */
4283         WARN_ON(simd != 0);
4284
4285         /* type 2 wave data */
4286         dst[(*no_fields)++] = 2;
4287         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4288         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4289         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4290         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4291         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4292         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4293         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4294         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4295         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4296         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4297         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4298         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4299         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4300         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4301         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4302         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4303 }
4304
4305 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4306                                      uint32_t wave, uint32_t start,
4307                                      uint32_t size, uint32_t *dst)
4308 {
4309         WARN_ON(simd != 0);
4310
4311         wave_read_regs(
4312                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4313                 dst);
4314 }
4315
4316 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4317                                       uint32_t wave, uint32_t thread,
4318                                       uint32_t start, uint32_t size,
4319                                       uint32_t *dst)
4320 {
4321         wave_read_regs(
4322                 adev, wave, thread,
4323                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4324 }
4325
4326 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4327                                        u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4328 {
4329         nv_grbm_select(adev, me, pipe, q, vm);
4330 }
4331
4332 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4333                                           bool enable)
4334 {
4335         uint32_t data, def;
4336
4337         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4338
4339         if (enable)
4340                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4341         else
4342                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4343
4344         if (data != def)
4345                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4346 }
4347
4348 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4349         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4350         .select_se_sh = &gfx_v10_0_select_se_sh,
4351         .read_wave_data = &gfx_v10_0_read_wave_data,
4352         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4353         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4354         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4355         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4356         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4357 };
4358
4359 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4360 {
4361         u32 gb_addr_config;
4362
4363         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4364         case IP_VERSION(10, 1, 10):
4365         case IP_VERSION(10, 1, 1):
4366         case IP_VERSION(10, 1, 2):
4367                 adev->gfx.config.max_hw_contexts = 8;
4368                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4369                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4370                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4371                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4372                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4373                 break;
4374         case IP_VERSION(10, 3, 0):
4375         case IP_VERSION(10, 3, 2):
4376         case IP_VERSION(10, 3, 1):
4377         case IP_VERSION(10, 3, 4):
4378         case IP_VERSION(10, 3, 5):
4379         case IP_VERSION(10, 3, 6):
4380         case IP_VERSION(10, 3, 3):
4381         case IP_VERSION(10, 3, 7):
4382                 adev->gfx.config.max_hw_contexts = 8;
4383                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4384                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4385                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4386                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4387                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4388                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4389                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4390                 break;
4391         case IP_VERSION(10, 1, 3):
4392         case IP_VERSION(10, 1, 4):
4393                 adev->gfx.config.max_hw_contexts = 8;
4394                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4395                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4396                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4397                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4398                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4399                 break;
4400         default:
4401                 BUG();
4402                 break;
4403         }
4404
4405         adev->gfx.config.gb_addr_config = gb_addr_config;
4406
4407         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4408                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4409                                       GB_ADDR_CONFIG, NUM_PIPES);
4410
4411         adev->gfx.config.max_tile_pipes =
4412                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4413
4414         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4415                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4416                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4417         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4418                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4419                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4420         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4421                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4422                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4423         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4424                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4425                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4426 }
4427
4428 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4429                                    int me, int pipe, int queue)
4430 {
4431         struct amdgpu_ring *ring;
4432         unsigned int irq_type;
4433         unsigned int hw_prio;
4434
4435         ring = &adev->gfx.gfx_ring[ring_id];
4436
4437         ring->me = me;
4438         ring->pipe = pipe;
4439         ring->queue = queue;
4440
4441         ring->ring_obj = NULL;
4442         ring->use_doorbell = true;
4443
4444         if (!ring_id)
4445                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4446         else
4447                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4448         ring->vm_hub = AMDGPU_GFXHUB(0);
4449         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4450
4451         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4452         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4453                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4454         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4455                                 hw_prio, NULL);
4456 }
4457
4458 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4459                                        int mec, int pipe, int queue)
4460 {
4461         unsigned int irq_type;
4462         struct amdgpu_ring *ring;
4463         unsigned int hw_prio;
4464
4465         ring = &adev->gfx.compute_ring[ring_id];
4466
4467         /* mec0 is me1 */
4468         ring->me = mec + 1;
4469         ring->pipe = pipe;
4470         ring->queue = queue;
4471
4472         ring->ring_obj = NULL;
4473         ring->use_doorbell = true;
4474         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4475         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4476                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4477         ring->vm_hub = AMDGPU_GFXHUB(0);
4478         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4479
4480         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4481                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4482                 + ring->pipe;
4483         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4484                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4485         /* type-2 packets are deprecated on MEC, use type-3 instead */
4486         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4487                              hw_prio, NULL);
4488 }
4489
4490 static int gfx_v10_0_sw_init(void *handle)
4491 {
4492         int i, j, k, r, ring_id = 0;
4493         int xcc_id = 0;
4494         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4495
4496         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4497         case IP_VERSION(10, 1, 10):
4498         case IP_VERSION(10, 1, 1):
4499         case IP_VERSION(10, 1, 2):
4500         case IP_VERSION(10, 1, 3):
4501         case IP_VERSION(10, 1, 4):
4502                 adev->gfx.me.num_me = 1;
4503                 adev->gfx.me.num_pipe_per_me = 1;
4504                 adev->gfx.me.num_queue_per_pipe = 1;
4505                 adev->gfx.mec.num_mec = 2;
4506                 adev->gfx.mec.num_pipe_per_mec = 4;
4507                 adev->gfx.mec.num_queue_per_pipe = 8;
4508                 break;
4509         case IP_VERSION(10, 3, 0):
4510         case IP_VERSION(10, 3, 2):
4511         case IP_VERSION(10, 3, 1):
4512         case IP_VERSION(10, 3, 4):
4513         case IP_VERSION(10, 3, 5):
4514         case IP_VERSION(10, 3, 6):
4515         case IP_VERSION(10, 3, 3):
4516         case IP_VERSION(10, 3, 7):
4517                 adev->gfx.me.num_me = 1;
4518                 adev->gfx.me.num_pipe_per_me = 1;
4519                 adev->gfx.me.num_queue_per_pipe = 1;
4520                 adev->gfx.mec.num_mec = 2;
4521                 adev->gfx.mec.num_pipe_per_mec = 4;
4522                 adev->gfx.mec.num_queue_per_pipe = 4;
4523                 break;
4524         default:
4525                 adev->gfx.me.num_me = 1;
4526                 adev->gfx.me.num_pipe_per_me = 1;
4527                 adev->gfx.me.num_queue_per_pipe = 1;
4528                 adev->gfx.mec.num_mec = 1;
4529                 adev->gfx.mec.num_pipe_per_mec = 4;
4530                 adev->gfx.mec.num_queue_per_pipe = 8;
4531                 break;
4532         }
4533
4534         /* KIQ event */
4535         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4536                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4537                               &adev->gfx.kiq[0].irq);
4538         if (r)
4539                 return r;
4540
4541         /* EOP Event */
4542         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4543                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4544                               &adev->gfx.eop_irq);
4545         if (r)
4546                 return r;
4547
4548         /* Privileged reg */
4549         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4550                               &adev->gfx.priv_reg_irq);
4551         if (r)
4552                 return r;
4553
4554         /* Privileged inst */
4555         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4556                               &adev->gfx.priv_inst_irq);
4557         if (r)
4558                 return r;
4559
4560         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4561
4562         gfx_v10_0_me_init(adev);
4563
4564         if (adev->gfx.rlc.funcs) {
4565                 if (adev->gfx.rlc.funcs->init) {
4566                         r = adev->gfx.rlc.funcs->init(adev);
4567                         if (r) {
4568                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4569                                 return r;
4570                         }
4571                 }
4572         }
4573
4574         r = gfx_v10_0_mec_init(adev);
4575         if (r) {
4576                 DRM_ERROR("Failed to init MEC BOs!\n");
4577                 return r;
4578         }
4579
4580         /* set up the gfx ring */
4581         for (i = 0; i < adev->gfx.me.num_me; i++) {
4582                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4583                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4584                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4585                                         continue;
4586
4587                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4588                                                             i, k, j);
4589                                 if (r)
4590                                         return r;
4591                                 ring_id++;
4592                         }
4593                 }
4594         }
4595
4596         ring_id = 0;
4597         /* set up the compute queues - allocate horizontally across pipes */
4598         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4599                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4600                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4601                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4602                                                                      k, j))
4603                                         continue;
4604
4605                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4606                                                                 i, k, j);
4607                                 if (r)
4608                                         return r;
4609
4610                                 ring_id++;
4611                         }
4612                 }
4613         }
4614
4615         if (!adev->enable_mes_kiq) {
4616                 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4617                 if (r) {
4618                         DRM_ERROR("Failed to init KIQ BOs!\n");
4619                         return r;
4620                 }
4621
4622                 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4623                 if (r)
4624                         return r;
4625         }
4626
4627         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4628         if (r)
4629                 return r;
4630
4631         /* allocate visible FB for rlc auto-loading fw */
4632         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4633                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4634                 if (r)
4635                         return r;
4636         }
4637
4638         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4639
4640         gfx_v10_0_gpu_early_init(adev);
4641
4642         return 0;
4643 }
4644
4645 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4646 {
4647         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4648                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4649                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4650 }
4651
4652 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4653 {
4654         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4655                               &adev->gfx.ce.ce_fw_gpu_addr,
4656                               (void **)&adev->gfx.ce.ce_fw_ptr);
4657 }
4658
4659 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4660 {
4661         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4662                               &adev->gfx.me.me_fw_gpu_addr,
4663                               (void **)&adev->gfx.me.me_fw_ptr);
4664 }
4665
4666 static int gfx_v10_0_sw_fini(void *handle)
4667 {
4668         int i;
4669         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4670
4671         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4672                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4673         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4674                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4675
4676         amdgpu_gfx_mqd_sw_fini(adev, 0);
4677
4678         if (!adev->enable_mes_kiq) {
4679                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4680                 amdgpu_gfx_kiq_fini(adev, 0);
4681         }
4682
4683         gfx_v10_0_pfp_fini(adev);
4684         gfx_v10_0_ce_fini(adev);
4685         gfx_v10_0_me_fini(adev);
4686         gfx_v10_0_rlc_fini(adev);
4687         gfx_v10_0_mec_fini(adev);
4688
4689         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4690                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4691
4692         gfx_v10_0_free_microcode(adev);
4693
4694         return 0;
4695 }
4696
4697 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4698                                    u32 sh_num, u32 instance, int xcc_id)
4699 {
4700         u32 data;
4701
4702         if (instance == 0xffffffff)
4703                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4704                                      INSTANCE_BROADCAST_WRITES, 1);
4705         else
4706                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4707                                      instance);
4708
4709         if (se_num == 0xffffffff)
4710                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4711                                      1);
4712         else
4713                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4714
4715         if (sh_num == 0xffffffff)
4716                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4717                                      1);
4718         else
4719                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4720
4721         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4722 }
4723
4724 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4725 {
4726         u32 data, mask;
4727
4728         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4729         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4730
4731         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4732         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4733
4734         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4735                                          adev->gfx.config.max_sh_per_se);
4736
4737         return (~data) & mask;
4738 }
4739
4740 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4741 {
4742         int i, j;
4743         u32 data;
4744         u32 active_rbs = 0;
4745         u32 bitmap;
4746         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4747                                         adev->gfx.config.max_sh_per_se;
4748
4749         mutex_lock(&adev->grbm_idx_mutex);
4750         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4751                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4752                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4753                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4754                               IP_VERSION(10, 3, 0)) ||
4755                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4756                               IP_VERSION(10, 3, 3)) ||
4757                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4758                               IP_VERSION(10, 3, 6))) &&
4759                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4760                                 continue;
4761                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4762                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4763                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4764                                                rb_bitmap_width_per_sh);
4765                 }
4766         }
4767         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4768         mutex_unlock(&adev->grbm_idx_mutex);
4769
4770         adev->gfx.config.backend_enable_mask = active_rbs;
4771         adev->gfx.config.num_rbs = hweight32(active_rbs);
4772 }
4773
4774 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4775 {
4776         uint32_t num_sc;
4777         uint32_t enabled_rb_per_sh;
4778         uint32_t active_rb_bitmap;
4779         uint32_t num_rb_per_sc;
4780         uint32_t num_packer_per_sc;
4781         uint32_t pa_sc_tile_steering_override;
4782
4783         /* for ASICs that integrates GFX v10.3
4784          * pa_sc_tile_steering_override should be set to 0
4785          */
4786         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4787                 return 0;
4788
4789         /* init num_sc */
4790         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4791                         adev->gfx.config.num_sc_per_sh;
4792         /* init num_rb_per_sc */
4793         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4794         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4795         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4796         /* init num_packer_per_sc */
4797         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4798
4799         pa_sc_tile_steering_override = 0;
4800         pa_sc_tile_steering_override |=
4801                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4802                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4803         pa_sc_tile_steering_override |=
4804                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4805                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4806         pa_sc_tile_steering_override |=
4807                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4808                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4809
4810         return pa_sc_tile_steering_override;
4811 }
4812
4813 #define DEFAULT_SH_MEM_BASES    (0x6000)
4814
4815 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
4816                                 uint32_t first_vmid,
4817                                 uint32_t last_vmid)
4818 {
4819         uint32_t data;
4820         uint32_t trap_config_vmid_mask = 0;
4821         int i;
4822
4823         /* Calculate trap config vmid mask */
4824         for (i = first_vmid; i < last_vmid; i++)
4825                 trap_config_vmid_mask |= (1 << i);
4826
4827         data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
4828                         VMID_SEL, trap_config_vmid_mask);
4829         data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
4830                         TRAP_EN, 1);
4831         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
4832         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
4833
4834         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
4835         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
4836 }
4837
4838 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4839 {
4840         int i;
4841         uint32_t sh_mem_bases;
4842
4843         /*
4844          * Configure apertures:
4845          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4846          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4847          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4848          */
4849         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4850
4851         mutex_lock(&adev->srbm_mutex);
4852         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4853                 nv_grbm_select(adev, 0, 0, 0, i);
4854                 /* CP and shaders */
4855                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4856                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4857         }
4858         nv_grbm_select(adev, 0, 0, 0, 0);
4859         mutex_unlock(&adev->srbm_mutex);
4860
4861         /*
4862          * Initialize all compute VMIDs to have no GDS, GWS, or OA
4863          * access. These should be enabled by FW for target VMIDs.
4864          */
4865         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4866                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4867                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4868                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4869                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4870         }
4871
4872         gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
4873                                         AMDGPU_NUM_VMID);
4874 }
4875
4876 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4877 {
4878         int vmid;
4879
4880         /*
4881          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4882          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4883          * the driver can enable them for graphics. VMID0 should maintain
4884          * access so that HWS firmware can save/restore entries.
4885          */
4886         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4887                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4888                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4889                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4890                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4891         }
4892 }
4893
4894
4895 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4896 {
4897         int i, j, k;
4898         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4899         u32 tmp, wgp_active_bitmap = 0;
4900         u32 gcrd_targets_disable_tcp = 0;
4901         u32 utcl_invreq_disable = 0;
4902         /*
4903          * GCRD_TARGETS_DISABLE field contains
4904          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4905          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4906          */
4907         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4908                 2 * max_wgp_per_sh + /* TCP */
4909                 max_wgp_per_sh + /* SQC */
4910                 4); /* GL1C */
4911         /*
4912          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4913          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4914          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4915          */
4916         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4917                 2 * max_wgp_per_sh + /* TCP */
4918                 2 * max_wgp_per_sh + /* SQC */
4919                 4 + /* RMI */
4920                 1); /* SQG */
4921
4922         mutex_lock(&adev->grbm_idx_mutex);
4923         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4924                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4925                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4926                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4927                         /*
4928                          * Set corresponding TCP bits for the inactive WGPs in
4929                          * GCRD_SA_TARGETS_DISABLE
4930                          */
4931                         gcrd_targets_disable_tcp = 0;
4932                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4933                         utcl_invreq_disable = 0;
4934
4935                         for (k = 0; k < max_wgp_per_sh; k++) {
4936                                 if (!(wgp_active_bitmap & (1 << k))) {
4937                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
4938                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
4939                                         utcl_invreq_disable |= (3 << (2 * k)) |
4940                                                 (3 << (2 * (max_wgp_per_sh + k)));
4941                                 }
4942                         }
4943
4944                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4945                         /* only override TCP & SQC bits */
4946                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
4947                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4948                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4949
4950                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4951                         /* only override TCP & SQC bits */
4952                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
4953                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4954                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4955                 }
4956         }
4957
4958         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4959         mutex_unlock(&adev->grbm_idx_mutex);
4960 }
4961
4962 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4963 {
4964         /* TCCs are global (not instanced). */
4965         uint32_t tcc_disable;
4966
4967         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
4968                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
4969                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
4970         } else {
4971                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4972                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4973         }
4974
4975         adev->gfx.config.tcc_disabled_mask =
4976                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4977                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4978 }
4979
4980 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4981 {
4982         u32 tmp;
4983         int i;
4984
4985         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4986
4987         gfx_v10_0_setup_rb(adev);
4988         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4989         gfx_v10_0_get_tcc_info(adev);
4990         adev->gfx.config.pa_sc_tile_steering_override =
4991                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4992
4993         /* XXX SH_MEM regs */
4994         /* where to put LDS, scratch, GPUVM in FSA64 space */
4995         mutex_lock(&adev->srbm_mutex);
4996         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
4997                 nv_grbm_select(adev, 0, 0, 0, i);
4998                 /* CP and shaders */
4999                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5000                 if (i != 0) {
5001                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5002                                 (adev->gmc.private_aperture_start >> 48));
5003                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5004                                 (adev->gmc.shared_aperture_start >> 48));
5005                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5006                 }
5007         }
5008         nv_grbm_select(adev, 0, 0, 0, 0);
5009
5010         mutex_unlock(&adev->srbm_mutex);
5011
5012         gfx_v10_0_init_compute_vmid(adev);
5013         gfx_v10_0_init_gds_vmid(adev);
5014
5015 }
5016
5017 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5018                                                bool enable)
5019 {
5020         u32 tmp;
5021
5022         if (amdgpu_sriov_vf(adev))
5023                 return;
5024
5025         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5026
5027         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5028                             enable ? 1 : 0);
5029         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5030                             enable ? 1 : 0);
5031         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5032                             enable ? 1 : 0);
5033         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5034                             enable ? 1 : 0);
5035
5036         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5037 }
5038
5039 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5040 {
5041         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5042
5043         /* csib */
5044         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5045                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5046                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5047                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5048                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5049                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5050         } else {
5051                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5052                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5053                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5054                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5055                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5056         }
5057         return 0;
5058 }
5059
5060 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5061 {
5062         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5063
5064         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5065         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5066 }
5067
5068 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5069 {
5070         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5071         udelay(50);
5072         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5073         udelay(50);
5074 }
5075
5076 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5077                                              bool enable)
5078 {
5079         uint32_t rlc_pg_cntl;
5080
5081         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5082
5083         if (!enable) {
5084                 /* RLC_PG_CNTL[23] = 0 (default)
5085                  * RLC will wait for handshake acks with SMU
5086                  * GFXOFF will be enabled
5087                  * RLC_PG_CNTL[23] = 1
5088                  * RLC will not issue any message to SMU
5089                  * hence no handshake between SMU & RLC
5090                  * GFXOFF will be disabled
5091                  */
5092                 rlc_pg_cntl |= 0x800000;
5093         } else
5094                 rlc_pg_cntl &= ~0x800000;
5095         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5096 }
5097
5098 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5099 {
5100         /*
5101          * TODO: enable rlc & smu handshake until smu
5102          * and gfxoff feature works as expected
5103          */
5104         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5105                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5106
5107         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5108         udelay(50);
5109 }
5110
5111 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5112 {
5113         uint32_t tmp;
5114
5115         /* enable Save Restore Machine */
5116         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5117         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5118         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5119         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5120 }
5121
5122 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5123 {
5124         const struct rlc_firmware_header_v2_0 *hdr;
5125         const __le32 *fw_data;
5126         unsigned int i, fw_size;
5127
5128         if (!adev->gfx.rlc_fw)
5129                 return -EINVAL;
5130
5131         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5132         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5133
5134         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5135                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5136         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5137
5138         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5139                      RLCG_UCODE_LOADING_START_ADDRESS);
5140
5141         for (i = 0; i < fw_size; i++)
5142                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5143                              le32_to_cpup(fw_data++));
5144
5145         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5146
5147         return 0;
5148 }
5149
5150 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5151 {
5152         int r;
5153
5154         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5155                 adev->psp.autoload_supported) {
5156
5157                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5158                 if (r)
5159                         return r;
5160
5161                 gfx_v10_0_init_csb(adev);
5162
5163                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5164
5165                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5166                         gfx_v10_0_rlc_enable_srm(adev);
5167         } else {
5168                 if (amdgpu_sriov_vf(adev)) {
5169                         gfx_v10_0_init_csb(adev);
5170                         return 0;
5171                 }
5172
5173                 adev->gfx.rlc.funcs->stop(adev);
5174
5175                 /* disable CG */
5176                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5177
5178                 /* disable PG */
5179                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5180
5181                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5182                         /* legacy rlc firmware loading */
5183                         r = gfx_v10_0_rlc_load_microcode(adev);
5184                         if (r)
5185                                 return r;
5186                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5187                         /* rlc backdoor autoload firmware */
5188                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5189                         if (r)
5190                                 return r;
5191                 }
5192
5193                 gfx_v10_0_init_csb(adev);
5194
5195                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5196
5197                 adev->gfx.rlc.funcs->start(adev);
5198
5199                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5200                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5201                         if (r)
5202                                 return r;
5203                 }
5204         }
5205
5206         return 0;
5207 }
5208
5209 static struct {
5210         FIRMWARE_ID     id;
5211         unsigned int    offset;
5212         unsigned int    size;
5213 } rlc_autoload_info[FIRMWARE_ID_MAX];
5214
5215 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5216 {
5217         int ret;
5218         RLC_TABLE_OF_CONTENT *rlc_toc;
5219
5220         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5221                                         AMDGPU_GEM_DOMAIN_GTT,
5222                                         &adev->gfx.rlc.rlc_toc_bo,
5223                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5224                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5225         if (ret) {
5226                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5227                 return ret;
5228         }
5229
5230         /* Copy toc from psp sos fw to rlc toc buffer */
5231         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5232
5233         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5234         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5235                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5236                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5237                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5238                         /* Offset needs 4KB alignment */
5239                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5240                 }
5241
5242                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5243                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5244                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5245
5246                 rlc_toc++;
5247         }
5248
5249         return 0;
5250 }
5251
5252 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5253 {
5254         uint32_t total_size = 0;
5255         FIRMWARE_ID id;
5256         int ret;
5257
5258         ret = gfx_v10_0_parse_rlc_toc(adev);
5259         if (ret) {
5260                 dev_err(adev->dev, "failed to parse rlc toc\n");
5261                 return 0;
5262         }
5263
5264         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5265                 total_size += rlc_autoload_info[id].size;
5266
5267         /* In case the offset in rlc toc ucode is aligned */
5268         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5269                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5270                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5271
5272         return total_size;
5273 }
5274
5275 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5276 {
5277         int r;
5278         uint32_t total_size;
5279
5280         total_size = gfx_v10_0_calc_toc_total_size(adev);
5281
5282         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5283                                       AMDGPU_GEM_DOMAIN_GTT,
5284                                       &adev->gfx.rlc.rlc_autoload_bo,
5285                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5286                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5287         if (r) {
5288                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5289                 return r;
5290         }
5291
5292         return 0;
5293 }
5294
5295 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5296 {
5297         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5298                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5299                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5300         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5301                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5302                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5303 }
5304
5305 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5306                                                        FIRMWARE_ID id,
5307                                                        const void *fw_data,
5308                                                        uint32_t fw_size)
5309 {
5310         uint32_t toc_offset;
5311         uint32_t toc_fw_size;
5312         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5313
5314         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5315                 return;
5316
5317         toc_offset = rlc_autoload_info[id].offset;
5318         toc_fw_size = rlc_autoload_info[id].size;
5319
5320         if (fw_size == 0)
5321                 fw_size = toc_fw_size;
5322
5323         if (fw_size > toc_fw_size)
5324                 fw_size = toc_fw_size;
5325
5326         memcpy(ptr + toc_offset, fw_data, fw_size);
5327
5328         if (fw_size < toc_fw_size)
5329                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5330 }
5331
5332 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5333 {
5334         void *data;
5335         uint32_t size;
5336
5337         data = adev->gfx.rlc.rlc_toc_buf;
5338         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5339
5340         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5341                                                    FIRMWARE_ID_RLC_TOC,
5342                                                    data, size);
5343 }
5344
5345 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5346 {
5347         const __le32 *fw_data;
5348         uint32_t fw_size;
5349         const struct gfx_firmware_header_v1_0 *cp_hdr;
5350         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5351
5352         /* pfp ucode */
5353         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5354                 adev->gfx.pfp_fw->data;
5355         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5356                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5357         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5358         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5359                                                    FIRMWARE_ID_CP_PFP,
5360                                                    fw_data, fw_size);
5361
5362         /* ce ucode */
5363         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5364                 adev->gfx.ce_fw->data;
5365         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5366                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5367         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5368         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5369                                                    FIRMWARE_ID_CP_CE,
5370                                                    fw_data, fw_size);
5371
5372         /* me ucode */
5373         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5374                 adev->gfx.me_fw->data;
5375         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5376                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5377         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5378         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5379                                                    FIRMWARE_ID_CP_ME,
5380                                                    fw_data, fw_size);
5381
5382         /* rlc ucode */
5383         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5384                 adev->gfx.rlc_fw->data;
5385         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5386                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5387         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5388         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5389                                                    FIRMWARE_ID_RLC_G_UCODE,
5390                                                    fw_data, fw_size);
5391
5392         /* mec1 ucode */
5393         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5394                 adev->gfx.mec_fw->data;
5395         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5396                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5397         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5398                 cp_hdr->jt_size * 4;
5399         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5400                                                    FIRMWARE_ID_CP_MEC,
5401                                                    fw_data, fw_size);
5402         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5403 }
5404
5405 /* Temporarily put sdma part here */
5406 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5407 {
5408         const __le32 *fw_data;
5409         uint32_t fw_size;
5410         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5411         int i;
5412
5413         for (i = 0; i < adev->sdma.num_instances; i++) {
5414                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5415                         adev->sdma.instance[i].fw->data;
5416                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5417                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5418                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5419
5420                 if (i == 0) {
5421                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5422                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5423                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5424                                 FIRMWARE_ID_SDMA0_JT,
5425                                 (uint32_t *)fw_data +
5426                                 sdma_hdr->jt_offset,
5427                                 sdma_hdr->jt_size * 4);
5428                 } else if (i == 1) {
5429                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5430                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5431                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5432                                 FIRMWARE_ID_SDMA1_JT,
5433                                 (uint32_t *)fw_data +
5434                                 sdma_hdr->jt_offset,
5435                                 sdma_hdr->jt_size * 4);
5436                 }
5437         }
5438 }
5439
5440 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5441 {
5442         uint32_t rlc_g_offset, rlc_g_size, tmp;
5443         uint64_t gpu_addr;
5444
5445         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5446         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5447         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5448
5449         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5450         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5451         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5452
5453         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5454         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5455         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5456
5457         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5458         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5459                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5460                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5461                 return -EINVAL;
5462         }
5463
5464         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5465         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5466                 DRM_ERROR("RLC ROM should halt itself\n");
5467                 return -EINVAL;
5468         }
5469
5470         return 0;
5471 }
5472
5473 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5474 {
5475         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5476         uint32_t tmp;
5477         int i;
5478         uint64_t addr;
5479
5480         /* Trigger an invalidation of the L1 instruction caches */
5481         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5482         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5483         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5484
5485         /* Wait for invalidation complete */
5486         for (i = 0; i < usec_timeout; i++) {
5487                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5488                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5489                         INVALIDATE_CACHE_COMPLETE))
5490                         break;
5491                 udelay(1);
5492         }
5493
5494         if (i >= usec_timeout) {
5495                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5496                 return -EINVAL;
5497         }
5498
5499         /* Program me ucode address into intruction cache address register */
5500         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5501                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5502         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5503                         lower_32_bits(addr) & 0xFFFFF000);
5504         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5505                         upper_32_bits(addr));
5506
5507         return 0;
5508 }
5509
5510 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5511 {
5512         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5513         uint32_t tmp;
5514         int i;
5515         uint64_t addr;
5516
5517         /* Trigger an invalidation of the L1 instruction caches */
5518         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5519         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5520         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5521
5522         /* Wait for invalidation complete */
5523         for (i = 0; i < usec_timeout; i++) {
5524                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5525                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5526                         INVALIDATE_CACHE_COMPLETE))
5527                         break;
5528                 udelay(1);
5529         }
5530
5531         if (i >= usec_timeout) {
5532                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5533                 return -EINVAL;
5534         }
5535
5536         /* Program ce ucode address into intruction cache address register */
5537         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5538                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5539         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5540                         lower_32_bits(addr) & 0xFFFFF000);
5541         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5542                         upper_32_bits(addr));
5543
5544         return 0;
5545 }
5546
5547 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5548 {
5549         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5550         uint32_t tmp;
5551         int i;
5552         uint64_t addr;
5553
5554         /* Trigger an invalidation of the L1 instruction caches */
5555         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5556         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5557         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5558
5559         /* Wait for invalidation complete */
5560         for (i = 0; i < usec_timeout; i++) {
5561                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5562                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5563                         INVALIDATE_CACHE_COMPLETE))
5564                         break;
5565                 udelay(1);
5566         }
5567
5568         if (i >= usec_timeout) {
5569                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5570                 return -EINVAL;
5571         }
5572
5573         /* Program pfp ucode address into intruction cache address register */
5574         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5575                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5576         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5577                         lower_32_bits(addr) & 0xFFFFF000);
5578         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5579                         upper_32_bits(addr));
5580
5581         return 0;
5582 }
5583
5584 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5585 {
5586         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5587         uint32_t tmp;
5588         int i;
5589         uint64_t addr;
5590
5591         /* Trigger an invalidation of the L1 instruction caches */
5592         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5593         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5594         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5595
5596         /* Wait for invalidation complete */
5597         for (i = 0; i < usec_timeout; i++) {
5598                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5599                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5600                         INVALIDATE_CACHE_COMPLETE))
5601                         break;
5602                 udelay(1);
5603         }
5604
5605         if (i >= usec_timeout) {
5606                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5607                 return -EINVAL;
5608         }
5609
5610         /* Program mec1 ucode address into intruction cache address register */
5611         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5612                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5613         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5614                         lower_32_bits(addr) & 0xFFFFF000);
5615         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5616                         upper_32_bits(addr));
5617
5618         return 0;
5619 }
5620
5621 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5622 {
5623         uint32_t cp_status;
5624         uint32_t bootload_status;
5625         int i, r;
5626
5627         for (i = 0; i < adev->usec_timeout; i++) {
5628                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5629                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5630                 if ((cp_status == 0) &&
5631                     (REG_GET_FIELD(bootload_status,
5632                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5633                         break;
5634                 }
5635                 udelay(1);
5636         }
5637
5638         if (i >= adev->usec_timeout) {
5639                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5640                 return -ETIMEDOUT;
5641         }
5642
5643         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5644                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5645                 if (r)
5646                         return r;
5647
5648                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5649                 if (r)
5650                         return r;
5651
5652                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5653                 if (r)
5654                         return r;
5655
5656                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5657                 if (r)
5658                         return r;
5659         }
5660
5661         return 0;
5662 }
5663
5664 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5665 {
5666         int i;
5667         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5668
5669         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5670         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5671         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5672
5673         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5674                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5675         else
5676                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5677
5678         if (adev->job_hang && !enable)
5679                 return 0;
5680
5681         for (i = 0; i < adev->usec_timeout; i++) {
5682                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5683                         break;
5684                 udelay(1);
5685         }
5686
5687         if (i >= adev->usec_timeout)
5688                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5689
5690         return 0;
5691 }
5692
5693 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5694 {
5695         int r;
5696         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5697         const __le32 *fw_data;
5698         unsigned int i, fw_size;
5699         uint32_t tmp;
5700         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5701
5702         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5703                 adev->gfx.pfp_fw->data;
5704
5705         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5706
5707         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5708                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5709         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5710
5711         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5712                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5713                                       &adev->gfx.pfp.pfp_fw_obj,
5714                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5715                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5716         if (r) {
5717                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5718                 gfx_v10_0_pfp_fini(adev);
5719                 return r;
5720         }
5721
5722         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5723
5724         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5725         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5726
5727         /* Trigger an invalidation of the L1 instruction caches */
5728         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5729         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5730         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5731
5732         /* Wait for invalidation complete */
5733         for (i = 0; i < usec_timeout; i++) {
5734                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5735                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5736                         INVALIDATE_CACHE_COMPLETE))
5737                         break;
5738                 udelay(1);
5739         }
5740
5741         if (i >= usec_timeout) {
5742                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5743                 return -EINVAL;
5744         }
5745
5746         if (amdgpu_emu_mode == 1)
5747                 adev->hdp.funcs->flush_hdp(adev, NULL);
5748
5749         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5750         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5751         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5752         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5753         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5754         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5755         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5756                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5757         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5758                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5759
5760         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5761
5762         for (i = 0; i < pfp_hdr->jt_size; i++)
5763                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5764                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5765
5766         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5767
5768         return 0;
5769 }
5770
5771 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5772 {
5773         int r;
5774         const struct gfx_firmware_header_v1_0 *ce_hdr;
5775         const __le32 *fw_data;
5776         unsigned int i, fw_size;
5777         uint32_t tmp;
5778         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5779
5780         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5781                 adev->gfx.ce_fw->data;
5782
5783         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5784
5785         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5786                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5787         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5788
5789         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5790                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5791                                       &adev->gfx.ce.ce_fw_obj,
5792                                       &adev->gfx.ce.ce_fw_gpu_addr,
5793                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5794         if (r) {
5795                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5796                 gfx_v10_0_ce_fini(adev);
5797                 return r;
5798         }
5799
5800         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5801
5802         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5803         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5804
5805         /* Trigger an invalidation of the L1 instruction caches */
5806         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5807         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5808         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5809
5810         /* Wait for invalidation complete */
5811         for (i = 0; i < usec_timeout; i++) {
5812                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5813                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5814                         INVALIDATE_CACHE_COMPLETE))
5815                         break;
5816                 udelay(1);
5817         }
5818
5819         if (i >= usec_timeout) {
5820                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5821                 return -EINVAL;
5822         }
5823
5824         if (amdgpu_emu_mode == 1)
5825                 adev->hdp.funcs->flush_hdp(adev, NULL);
5826
5827         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5828         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5829         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5830         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5831         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5832         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5833                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5834         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5835                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5836
5837         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5838
5839         for (i = 0; i < ce_hdr->jt_size; i++)
5840                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5841                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5842
5843         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5844
5845         return 0;
5846 }
5847
5848 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5849 {
5850         int r;
5851         const struct gfx_firmware_header_v1_0 *me_hdr;
5852         const __le32 *fw_data;
5853         unsigned int i, fw_size;
5854         uint32_t tmp;
5855         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5856
5857         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5858                 adev->gfx.me_fw->data;
5859
5860         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5861
5862         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5863                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5864         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5865
5866         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5867                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5868                                       &adev->gfx.me.me_fw_obj,
5869                                       &adev->gfx.me.me_fw_gpu_addr,
5870                                       (void **)&adev->gfx.me.me_fw_ptr);
5871         if (r) {
5872                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5873                 gfx_v10_0_me_fini(adev);
5874                 return r;
5875         }
5876
5877         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5878
5879         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5880         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5881
5882         /* Trigger an invalidation of the L1 instruction caches */
5883         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5884         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5885         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5886
5887         /* Wait for invalidation complete */
5888         for (i = 0; i < usec_timeout; i++) {
5889                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5890                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5891                         INVALIDATE_CACHE_COMPLETE))
5892                         break;
5893                 udelay(1);
5894         }
5895
5896         if (i >= usec_timeout) {
5897                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5898                 return -EINVAL;
5899         }
5900
5901         if (amdgpu_emu_mode == 1)
5902                 adev->hdp.funcs->flush_hdp(adev, NULL);
5903
5904         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5905         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5906         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5907         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5908         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5909         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5910                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5911         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5912                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5913
5914         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5915
5916         for (i = 0; i < me_hdr->jt_size; i++)
5917                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5918                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5919
5920         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5921
5922         return 0;
5923 }
5924
5925 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5926 {
5927         int r;
5928
5929         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5930                 return -EINVAL;
5931
5932         gfx_v10_0_cp_gfx_enable(adev, false);
5933
5934         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5935         if (r) {
5936                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5937                 return r;
5938         }
5939
5940         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5941         if (r) {
5942                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5943                 return r;
5944         }
5945
5946         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5947         if (r) {
5948                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5949                 return r;
5950         }
5951
5952         return 0;
5953 }
5954
5955 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5956 {
5957         struct amdgpu_ring *ring;
5958         const struct cs_section_def *sect = NULL;
5959         const struct cs_extent_def *ext = NULL;
5960         int r, i;
5961         int ctx_reg_offset;
5962
5963         /* init the CP */
5964         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5965                      adev->gfx.config.max_hw_contexts - 1);
5966         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5967
5968         gfx_v10_0_cp_gfx_enable(adev, true);
5969
5970         ring = &adev->gfx.gfx_ring[0];
5971         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5972         if (r) {
5973                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5974                 return r;
5975         }
5976
5977         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5978         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5979
5980         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5981         amdgpu_ring_write(ring, 0x80000000);
5982         amdgpu_ring_write(ring, 0x80000000);
5983
5984         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5985                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5986                         if (sect->id == SECT_CONTEXT) {
5987                                 amdgpu_ring_write(ring,
5988                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5989                                                           ext->reg_count));
5990                                 amdgpu_ring_write(ring, ext->reg_index -
5991                                                   PACKET3_SET_CONTEXT_REG_START);
5992                                 for (i = 0; i < ext->reg_count; i++)
5993                                         amdgpu_ring_write(ring, ext->extent[i]);
5994                         }
5995                 }
5996         }
5997
5998         ctx_reg_offset =
5999                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6000         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6001         amdgpu_ring_write(ring, ctx_reg_offset);
6002         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6003
6004         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6005         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6006
6007         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6008         amdgpu_ring_write(ring, 0);
6009
6010         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6011         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6012         amdgpu_ring_write(ring, 0x8000);
6013         amdgpu_ring_write(ring, 0x8000);
6014
6015         amdgpu_ring_commit(ring);
6016
6017         /* submit cs packet to copy state 0 to next available state */
6018         if (adev->gfx.num_gfx_rings > 1) {
6019                 /* maximum supported gfx ring is 2 */
6020                 ring = &adev->gfx.gfx_ring[1];
6021                 r = amdgpu_ring_alloc(ring, 2);
6022                 if (r) {
6023                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6024                         return r;
6025                 }
6026
6027                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6028                 amdgpu_ring_write(ring, 0);
6029
6030                 amdgpu_ring_commit(ring);
6031         }
6032         return 0;
6033 }
6034
6035 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6036                                          CP_PIPE_ID pipe)
6037 {
6038         u32 tmp;
6039
6040         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6041         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6042
6043         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6044 }
6045
6046 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6047                                           struct amdgpu_ring *ring)
6048 {
6049         u32 tmp;
6050
6051         if (!amdgpu_async_gfx_ring) {
6052                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6053                 if (ring->use_doorbell) {
6054                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6055                                                 DOORBELL_OFFSET, ring->doorbell_index);
6056                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6057                                                 DOORBELL_EN, 1);
6058                 } else {
6059                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6060                                                 DOORBELL_EN, 0);
6061                 }
6062                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6063         }
6064         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6065         case IP_VERSION(10, 3, 0):
6066         case IP_VERSION(10, 3, 2):
6067         case IP_VERSION(10, 3, 1):
6068         case IP_VERSION(10, 3, 4):
6069         case IP_VERSION(10, 3, 5):
6070         case IP_VERSION(10, 3, 6):
6071         case IP_VERSION(10, 3, 3):
6072         case IP_VERSION(10, 3, 7):
6073                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6074                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6075                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6076
6077                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6078                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6079                 break;
6080         default:
6081                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6082                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6083                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6084
6085                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6086                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6087                 break;
6088         }
6089 }
6090
6091 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6092 {
6093         struct amdgpu_ring *ring;
6094         u32 tmp;
6095         u32 rb_bufsz;
6096         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6097
6098         /* Set the write pointer delay */
6099         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6100
6101         /* set the RB to use vmid 0 */
6102         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6103
6104         /* Init gfx ring 0 for pipe 0 */
6105         mutex_lock(&adev->srbm_mutex);
6106         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6107
6108         /* Set ring buffer size */
6109         ring = &adev->gfx.gfx_ring[0];
6110         rb_bufsz = order_base_2(ring->ring_size / 8);
6111         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6112         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6113 #ifdef __BIG_ENDIAN
6114         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6115 #endif
6116         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6117
6118         /* Initialize the ring buffer's write pointers */
6119         ring->wptr = 0;
6120         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6121         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6122
6123         /* set the wb address wether it's enabled or not */
6124         rptr_addr = ring->rptr_gpu_addr;
6125         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6126         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6127                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6128
6129         wptr_gpu_addr = ring->wptr_gpu_addr;
6130         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6131                      lower_32_bits(wptr_gpu_addr));
6132         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6133                      upper_32_bits(wptr_gpu_addr));
6134
6135         mdelay(1);
6136         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6137
6138         rb_addr = ring->gpu_addr >> 8;
6139         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6140         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6141
6142         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6143
6144         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6145         mutex_unlock(&adev->srbm_mutex);
6146
6147         /* Init gfx ring 1 for pipe 1 */
6148         if (adev->gfx.num_gfx_rings > 1) {
6149                 mutex_lock(&adev->srbm_mutex);
6150                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6151                 /* maximum supported gfx ring is 2 */
6152                 ring = &adev->gfx.gfx_ring[1];
6153                 rb_bufsz = order_base_2(ring->ring_size / 8);
6154                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6155                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6156                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6157                 /* Initialize the ring buffer's write pointers */
6158                 ring->wptr = 0;
6159                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6160                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6161                 /* Set the wb address wether it's enabled or not */
6162                 rptr_addr = ring->rptr_gpu_addr;
6163                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6164                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6165                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6166                 wptr_gpu_addr = ring->wptr_gpu_addr;
6167                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6168                              lower_32_bits(wptr_gpu_addr));
6169                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6170                              upper_32_bits(wptr_gpu_addr));
6171
6172                 mdelay(1);
6173                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6174
6175                 rb_addr = ring->gpu_addr >> 8;
6176                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6177                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6178                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6179
6180                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6181                 mutex_unlock(&adev->srbm_mutex);
6182         }
6183         /* Switch to pipe 0 */
6184         mutex_lock(&adev->srbm_mutex);
6185         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6186         mutex_unlock(&adev->srbm_mutex);
6187
6188         /* start the ring */
6189         gfx_v10_0_cp_gfx_start(adev);
6190
6191         return 0;
6192 }
6193
6194 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6195 {
6196         if (enable) {
6197                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6198                 case IP_VERSION(10, 3, 0):
6199                 case IP_VERSION(10, 3, 2):
6200                 case IP_VERSION(10, 3, 1):
6201                 case IP_VERSION(10, 3, 4):
6202                 case IP_VERSION(10, 3, 5):
6203                 case IP_VERSION(10, 3, 6):
6204                 case IP_VERSION(10, 3, 3):
6205                 case IP_VERSION(10, 3, 7):
6206                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6207                         break;
6208                 default:
6209                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6210                         break;
6211                 }
6212         } else {
6213                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6214                 case IP_VERSION(10, 3, 0):
6215                 case IP_VERSION(10, 3, 2):
6216                 case IP_VERSION(10, 3, 1):
6217                 case IP_VERSION(10, 3, 4):
6218                 case IP_VERSION(10, 3, 5):
6219                 case IP_VERSION(10, 3, 6):
6220                 case IP_VERSION(10, 3, 3):
6221                 case IP_VERSION(10, 3, 7):
6222                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6223                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6224                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6225                         break;
6226                 default:
6227                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6228                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6229                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6230                         break;
6231                 }
6232                 adev->gfx.kiq[0].ring.sched.ready = false;
6233         }
6234         udelay(50);
6235 }
6236
6237 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6238 {
6239         const struct gfx_firmware_header_v1_0 *mec_hdr;
6240         const __le32 *fw_data;
6241         unsigned int i;
6242         u32 tmp;
6243         u32 usec_timeout = 50000; /* Wait for 50 ms */
6244
6245         if (!adev->gfx.mec_fw)
6246                 return -EINVAL;
6247
6248         gfx_v10_0_cp_compute_enable(adev, false);
6249
6250         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6251         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6252
6253         fw_data = (const __le32 *)
6254                 (adev->gfx.mec_fw->data +
6255                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6256
6257         /* Trigger an invalidation of the L1 instruction caches */
6258         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6259         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6260         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6261
6262         /* Wait for invalidation complete */
6263         for (i = 0; i < usec_timeout; i++) {
6264                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6265                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6266                                        INVALIDATE_CACHE_COMPLETE))
6267                         break;
6268                 udelay(1);
6269         }
6270
6271         if (i >= usec_timeout) {
6272                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6273                 return -EINVAL;
6274         }
6275
6276         if (amdgpu_emu_mode == 1)
6277                 adev->hdp.funcs->flush_hdp(adev, NULL);
6278
6279         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6280         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6281         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6282         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6283         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6284
6285         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6286                      0xFFFFF000);
6287         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6288                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6289
6290         /* MEC1 */
6291         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6292
6293         for (i = 0; i < mec_hdr->jt_size; i++)
6294                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6295                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6296
6297         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6298
6299         /*
6300          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6301          * different microcode than MEC1.
6302          */
6303
6304         return 0;
6305 }
6306
6307 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6308 {
6309         uint32_t tmp;
6310         struct amdgpu_device *adev = ring->adev;
6311
6312         /* tell RLC which is KIQ queue */
6313         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6314         case IP_VERSION(10, 3, 0):
6315         case IP_VERSION(10, 3, 2):
6316         case IP_VERSION(10, 3, 1):
6317         case IP_VERSION(10, 3, 4):
6318         case IP_VERSION(10, 3, 5):
6319         case IP_VERSION(10, 3, 6):
6320         case IP_VERSION(10, 3, 3):
6321         case IP_VERSION(10, 3, 7):
6322                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6323                 tmp &= 0xffffff00;
6324                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6325                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6326                 tmp |= 0x80;
6327                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6328                 break;
6329         default:
6330                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6331                 tmp &= 0xffffff00;
6332                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6333                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6334                 tmp |= 0x80;
6335                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6336                 break;
6337         }
6338 }
6339
6340 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6341                                            struct v10_gfx_mqd *mqd,
6342                                            struct amdgpu_mqd_prop *prop)
6343 {
6344         bool priority = 0;
6345         u32 tmp;
6346
6347         /* set up default queue priority level
6348          * 0x0 = low priority, 0x1 = high priority
6349          */
6350         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6351                 priority = 1;
6352
6353         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6354         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6355         mqd->cp_gfx_hqd_queue_priority = tmp;
6356 }
6357
6358 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6359                                   struct amdgpu_mqd_prop *prop)
6360 {
6361         struct v10_gfx_mqd *mqd = m;
6362         uint64_t hqd_gpu_addr, wb_gpu_addr;
6363         uint32_t tmp;
6364         uint32_t rb_bufsz;
6365
6366         /* set up gfx hqd wptr */
6367         mqd->cp_gfx_hqd_wptr = 0;
6368         mqd->cp_gfx_hqd_wptr_hi = 0;
6369
6370         /* set the pointer to the MQD */
6371         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6372         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6373
6374         /* set up mqd control */
6375         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6376         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6377         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6378         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6379         mqd->cp_gfx_mqd_control = tmp;
6380
6381         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6382         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6383         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6384         mqd->cp_gfx_hqd_vmid = 0;
6385
6386         /* set up gfx queue priority */
6387         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6388
6389         /* set up time quantum */
6390         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6391         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6392         mqd->cp_gfx_hqd_quantum = tmp;
6393
6394         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6395         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6396         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6397         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6398
6399         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6400         wb_gpu_addr = prop->rptr_gpu_addr;
6401         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6402         mqd->cp_gfx_hqd_rptr_addr_hi =
6403                 upper_32_bits(wb_gpu_addr) & 0xffff;
6404
6405         /* set up rb_wptr_poll addr */
6406         wb_gpu_addr = prop->wptr_gpu_addr;
6407         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6408         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6409
6410         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6411         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6412         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6413         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6414         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6415 #ifdef __BIG_ENDIAN
6416         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6417 #endif
6418         mqd->cp_gfx_hqd_cntl = tmp;
6419
6420         /* set up cp_doorbell_control */
6421         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6422         if (prop->use_doorbell) {
6423                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6424                                     DOORBELL_OFFSET, prop->doorbell_index);
6425                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6426                                     DOORBELL_EN, 1);
6427         } else
6428                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6429                                     DOORBELL_EN, 0);
6430         mqd->cp_rb_doorbell_control = tmp;
6431
6432         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6433         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6434
6435         /* active the queue */
6436         mqd->cp_gfx_hqd_active = 1;
6437
6438         return 0;
6439 }
6440
6441 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6442 {
6443         struct amdgpu_device *adev = ring->adev;
6444         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6445         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6446
6447         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6448                 memset((void *)mqd, 0, sizeof(*mqd));
6449                 mutex_lock(&adev->srbm_mutex);
6450                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6451                 amdgpu_ring_init_mqd(ring);
6452
6453                 /*
6454                  * if there are 2 gfx rings, set the lower doorbell
6455                  * range of the first ring, otherwise the range of
6456                  * the second ring will override the first ring
6457                  */
6458                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6459                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6460
6461                 nv_grbm_select(adev, 0, 0, 0, 0);
6462                 mutex_unlock(&adev->srbm_mutex);
6463                 if (adev->gfx.me.mqd_backup[mqd_idx])
6464                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6465         } else {
6466                 mutex_lock(&adev->srbm_mutex);
6467                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6468                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6469                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6470
6471                 nv_grbm_select(adev, 0, 0, 0, 0);
6472                 mutex_unlock(&adev->srbm_mutex);
6473                 /* restore mqd with the backup copy */
6474                 if (adev->gfx.me.mqd_backup[mqd_idx])
6475                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6476                 /* reset the ring */
6477                 ring->wptr = 0;
6478                 *ring->wptr_cpu_addr = 0;
6479                 amdgpu_ring_clear_ring(ring);
6480         }
6481
6482         return 0;
6483 }
6484
6485 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6486 {
6487         int r, i;
6488         struct amdgpu_ring *ring;
6489
6490         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6491                 ring = &adev->gfx.gfx_ring[i];
6492
6493                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6494                 if (unlikely(r != 0))
6495                         return r;
6496
6497                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6498                 if (!r) {
6499                         r = gfx_v10_0_gfx_init_queue(ring);
6500                         amdgpu_bo_kunmap(ring->mqd_obj);
6501                         ring->mqd_ptr = NULL;
6502                 }
6503                 amdgpu_bo_unreserve(ring->mqd_obj);
6504                 if (r)
6505                         return r;
6506         }
6507
6508         r = amdgpu_gfx_enable_kgq(adev, 0);
6509         if (r)
6510                 return r;
6511
6512         return gfx_v10_0_cp_gfx_start(adev);
6513 }
6514
6515 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6516                                       struct amdgpu_mqd_prop *prop)
6517 {
6518         struct v10_compute_mqd *mqd = m;
6519         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6520         uint32_t tmp;
6521
6522         mqd->header = 0xC0310800;
6523         mqd->compute_pipelinestat_enable = 0x00000001;
6524         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6525         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6526         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6527         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6528         mqd->compute_misc_reserved = 0x00000003;
6529
6530         eop_base_addr = prop->eop_gpu_addr >> 8;
6531         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6532         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6533
6534         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6535         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6536         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6537                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6538
6539         mqd->cp_hqd_eop_control = tmp;
6540
6541         /* enable doorbell? */
6542         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6543
6544         if (prop->use_doorbell) {
6545                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6546                                     DOORBELL_OFFSET, prop->doorbell_index);
6547                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6548                                     DOORBELL_EN, 1);
6549                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6550                                     DOORBELL_SOURCE, 0);
6551                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6552                                     DOORBELL_HIT, 0);
6553         } else {
6554                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6555                                     DOORBELL_EN, 0);
6556         }
6557
6558         mqd->cp_hqd_pq_doorbell_control = tmp;
6559
6560         /* disable the queue if it's active */
6561         mqd->cp_hqd_dequeue_request = 0;
6562         mqd->cp_hqd_pq_rptr = 0;
6563         mqd->cp_hqd_pq_wptr_lo = 0;
6564         mqd->cp_hqd_pq_wptr_hi = 0;
6565
6566         /* set the pointer to the MQD */
6567         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6568         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6569
6570         /* set MQD vmid to 0 */
6571         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6572         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6573         mqd->cp_mqd_control = tmp;
6574
6575         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6576         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6577         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6578         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6579
6580         /* set up the HQD, this is similar to CP_RB0_CNTL */
6581         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6582         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6583                             (order_base_2(prop->queue_size / 4) - 1));
6584         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6585                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6586 #ifdef __BIG_ENDIAN
6587         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6588 #endif
6589         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6590         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6591                             prop->allow_tunneling);
6592         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6593         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6594         mqd->cp_hqd_pq_control = tmp;
6595
6596         /* set the wb address whether it's enabled or not */
6597         wb_gpu_addr = prop->rptr_gpu_addr;
6598         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6599         mqd->cp_hqd_pq_rptr_report_addr_hi =
6600                 upper_32_bits(wb_gpu_addr) & 0xffff;
6601
6602         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6603         wb_gpu_addr = prop->wptr_gpu_addr;
6604         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6605         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6606
6607         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6608         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6609
6610         /* set the vmid for the queue */
6611         mqd->cp_hqd_vmid = 0;
6612
6613         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6614         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6615         mqd->cp_hqd_persistent_state = tmp;
6616
6617         /* set MIN_IB_AVAIL_SIZE */
6618         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6619         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6620         mqd->cp_hqd_ib_control = tmp;
6621
6622         /* set static priority for a compute queue/ring */
6623         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6624         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6625
6626         mqd->cp_hqd_active = prop->hqd_active;
6627
6628         return 0;
6629 }
6630
6631 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6632 {
6633         struct amdgpu_device *adev = ring->adev;
6634         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6635         int j;
6636
6637         /* inactivate the queue */
6638         if (amdgpu_sriov_vf(adev))
6639                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6640
6641         /* disable wptr polling */
6642         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6643
6644         /* disable the queue if it's active */
6645         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6646                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6647                 for (j = 0; j < adev->usec_timeout; j++) {
6648                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6649                                 break;
6650                         udelay(1);
6651                 }
6652                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6653                        mqd->cp_hqd_dequeue_request);
6654                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6655                        mqd->cp_hqd_pq_rptr);
6656                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6657                        mqd->cp_hqd_pq_wptr_lo);
6658                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6659                        mqd->cp_hqd_pq_wptr_hi);
6660         }
6661
6662         /* disable doorbells */
6663         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6664
6665         /* write the EOP addr */
6666         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6667                mqd->cp_hqd_eop_base_addr_lo);
6668         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6669                mqd->cp_hqd_eop_base_addr_hi);
6670
6671         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6672         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6673                mqd->cp_hqd_eop_control);
6674
6675         /* set the pointer to the MQD */
6676         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6677                mqd->cp_mqd_base_addr_lo);
6678         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6679                mqd->cp_mqd_base_addr_hi);
6680
6681         /* set MQD vmid to 0 */
6682         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6683                mqd->cp_mqd_control);
6684
6685         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6686         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6687                mqd->cp_hqd_pq_base_lo);
6688         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6689                mqd->cp_hqd_pq_base_hi);
6690
6691         /* set up the HQD, this is similar to CP_RB0_CNTL */
6692         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6693                mqd->cp_hqd_pq_control);
6694
6695         /* set the wb address whether it's enabled or not */
6696         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6697                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6698         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6699                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6700
6701         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6702         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6703                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6704         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6705                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6706
6707         /* enable the doorbell if requested */
6708         if (ring->use_doorbell) {
6709                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6710                         (adev->doorbell_index.kiq * 2) << 2);
6711                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6712                         (adev->doorbell_index.userqueue_end * 2) << 2);
6713         }
6714
6715         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6716                mqd->cp_hqd_pq_doorbell_control);
6717
6718         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6719         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6720                mqd->cp_hqd_pq_wptr_lo);
6721         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6722                mqd->cp_hqd_pq_wptr_hi);
6723
6724         /* set the vmid for the queue */
6725         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6726
6727         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6728                mqd->cp_hqd_persistent_state);
6729
6730         /* activate the queue */
6731         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6732                mqd->cp_hqd_active);
6733
6734         if (ring->use_doorbell)
6735                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6736
6737         return 0;
6738 }
6739
6740 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6741 {
6742         struct amdgpu_device *adev = ring->adev;
6743         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6744
6745         gfx_v10_0_kiq_setting(ring);
6746
6747         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6748                 /* reset MQD to a clean status */
6749                 if (adev->gfx.kiq[0].mqd_backup)
6750                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6751
6752                 /* reset ring buffer */
6753                 ring->wptr = 0;
6754                 amdgpu_ring_clear_ring(ring);
6755
6756                 mutex_lock(&adev->srbm_mutex);
6757                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6758                 gfx_v10_0_kiq_init_register(ring);
6759                 nv_grbm_select(adev, 0, 0, 0, 0);
6760                 mutex_unlock(&adev->srbm_mutex);
6761         } else {
6762                 memset((void *)mqd, 0, sizeof(*mqd));
6763                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6764                         amdgpu_ring_clear_ring(ring);
6765                 mutex_lock(&adev->srbm_mutex);
6766                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6767                 amdgpu_ring_init_mqd(ring);
6768                 gfx_v10_0_kiq_init_register(ring);
6769                 nv_grbm_select(adev, 0, 0, 0, 0);
6770                 mutex_unlock(&adev->srbm_mutex);
6771
6772                 if (adev->gfx.kiq[0].mqd_backup)
6773                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6774         }
6775
6776         return 0;
6777 }
6778
6779 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6780 {
6781         struct amdgpu_device *adev = ring->adev;
6782         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6783         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6784
6785         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6786                 memset((void *)mqd, 0, sizeof(*mqd));
6787                 mutex_lock(&adev->srbm_mutex);
6788                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6789                 amdgpu_ring_init_mqd(ring);
6790                 nv_grbm_select(adev, 0, 0, 0, 0);
6791                 mutex_unlock(&adev->srbm_mutex);
6792
6793                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6794                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6795         } else {
6796                 /* restore MQD to a clean status */
6797                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6798                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6799                 /* reset ring buffer */
6800                 ring->wptr = 0;
6801                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6802                 amdgpu_ring_clear_ring(ring);
6803         }
6804
6805         return 0;
6806 }
6807
6808 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6809 {
6810         struct amdgpu_ring *ring;
6811         int r;
6812
6813         ring = &adev->gfx.kiq[0].ring;
6814
6815         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6816         if (unlikely(r != 0))
6817                 return r;
6818
6819         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6820         if (unlikely(r != 0)) {
6821                 amdgpu_bo_unreserve(ring->mqd_obj);
6822                 return r;
6823         }
6824
6825         gfx_v10_0_kiq_init_queue(ring);
6826         amdgpu_bo_kunmap(ring->mqd_obj);
6827         ring->mqd_ptr = NULL;
6828         amdgpu_bo_unreserve(ring->mqd_obj);
6829         return 0;
6830 }
6831
6832 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6833 {
6834         struct amdgpu_ring *ring = NULL;
6835         int r = 0, i;
6836
6837         gfx_v10_0_cp_compute_enable(adev, true);
6838
6839         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6840                 ring = &adev->gfx.compute_ring[i];
6841
6842                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6843                 if (unlikely(r != 0))
6844                         goto done;
6845                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6846                 if (!r) {
6847                         r = gfx_v10_0_kcq_init_queue(ring);
6848                         amdgpu_bo_kunmap(ring->mqd_obj);
6849                         ring->mqd_ptr = NULL;
6850                 }
6851                 amdgpu_bo_unreserve(ring->mqd_obj);
6852                 if (r)
6853                         goto done;
6854         }
6855
6856         r = amdgpu_gfx_enable_kcq(adev, 0);
6857 done:
6858         return r;
6859 }
6860
6861 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6862 {
6863         int r, i;
6864         struct amdgpu_ring *ring;
6865
6866         if (!(adev->flags & AMD_IS_APU))
6867                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6868
6869         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6870                 /* legacy firmware loading */
6871                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6872                 if (r)
6873                         return r;
6874
6875                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6876                 if (r)
6877                         return r;
6878         }
6879
6880         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
6881                 r = amdgpu_mes_kiq_hw_init(adev);
6882         else
6883                 r = gfx_v10_0_kiq_resume(adev);
6884         if (r)
6885                 return r;
6886
6887         r = gfx_v10_0_kcq_resume(adev);
6888         if (r)
6889                 return r;
6890
6891         if (!amdgpu_async_gfx_ring) {
6892                 r = gfx_v10_0_cp_gfx_resume(adev);
6893                 if (r)
6894                         return r;
6895         } else {
6896                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6897                 if (r)
6898                         return r;
6899         }
6900
6901         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6902                 ring = &adev->gfx.gfx_ring[i];
6903                 r = amdgpu_ring_test_helper(ring);
6904                 if (r)
6905                         return r;
6906         }
6907
6908         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6909                 ring = &adev->gfx.compute_ring[i];
6910                 r = amdgpu_ring_test_helper(ring);
6911                 if (r)
6912                         return r;
6913         }
6914
6915         return 0;
6916 }
6917
6918 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6919 {
6920         gfx_v10_0_cp_gfx_enable(adev, enable);
6921         gfx_v10_0_cp_compute_enable(adev, enable);
6922 }
6923
6924 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6925 {
6926         uint32_t data, pattern = 0xDEADBEEF;
6927
6928         /*
6929          * check if mmVGT_ESGS_RING_SIZE_UMD
6930          * has been remapped to mmVGT_ESGS_RING_SIZE
6931          */
6932         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6933         case IP_VERSION(10, 3, 0):
6934         case IP_VERSION(10, 3, 2):
6935         case IP_VERSION(10, 3, 4):
6936         case IP_VERSION(10, 3, 5):
6937                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6938                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6939                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6940
6941                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6942                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6943                         return true;
6944                 }
6945                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6946                 break;
6947         case IP_VERSION(10, 3, 1):
6948         case IP_VERSION(10, 3, 3):
6949         case IP_VERSION(10, 3, 6):
6950         case IP_VERSION(10, 3, 7):
6951                 return true;
6952         default:
6953                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6954                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6955                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6956
6957                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6958                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6959                         return true;
6960                 }
6961                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6962                 break;
6963         }
6964
6965         return false;
6966 }
6967
6968 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6969 {
6970         uint32_t data;
6971
6972         if (amdgpu_sriov_vf(adev))
6973                 return;
6974
6975         /*
6976          * Initialize cam_index to 0
6977          * index will auto-inc after each data writing
6978          */
6979         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6980
6981         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6982         case IP_VERSION(10, 3, 0):
6983         case IP_VERSION(10, 3, 2):
6984         case IP_VERSION(10, 3, 1):
6985         case IP_VERSION(10, 3, 4):
6986         case IP_VERSION(10, 3, 5):
6987         case IP_VERSION(10, 3, 6):
6988         case IP_VERSION(10, 3, 3):
6989         case IP_VERSION(10, 3, 7):
6990                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6991                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6992                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6993                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6994                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6995                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6996                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6997
6998                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6999                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7000                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7001                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7002                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7003                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7004                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7005
7006                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7007                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7008                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7009                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7010                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7011                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7012                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7013
7014                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7015                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7016                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7017                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7018                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7019                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7020                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7021
7022                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7023                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7024                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7025                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7026                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7027                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7028                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7029
7030                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7031                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7032                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7033                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7034                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7035                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7036                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7037
7038                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7039                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7040                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7041                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7042                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7043                 break;
7044         default:
7045                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7046                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7047                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7048                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7049                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7050                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7051                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7052
7053                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7054                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7055                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7056                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7057                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7058                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7059                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7060
7061                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7062                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7063                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7064                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7065                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7066                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7067                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7068
7069                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7070                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7071                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7072                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7073                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7074                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7075                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7076
7077                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7078                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7079                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7080                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7081                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7082                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7083                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7084
7085                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7086                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7087                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7088                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7089                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7090                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7091                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7092
7093                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7094                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7095                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7096                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7097                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7098                 break;
7099         }
7100
7101         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7102         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7103 }
7104
7105 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7106 {
7107         uint32_t data;
7108
7109         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7110         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7111         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7112
7113         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7114         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7115         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7116 }
7117
7118 static int gfx_v10_0_hw_init(void *handle)
7119 {
7120         int r;
7121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7122
7123         if (!amdgpu_emu_mode)
7124                 gfx_v10_0_init_golden_registers(adev);
7125
7126         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7127                 /**
7128                  * For gfx 10, rlc firmware loading relies on smu firmware is
7129                  * loaded firstly, so in direct type, it has to load smc ucode
7130                  * here before rlc.
7131                  */
7132                 if (!(adev->flags & AMD_IS_APU)) {
7133                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7134                         if (r)
7135                                 return r;
7136                 }
7137                 gfx_v10_0_disable_gpa_mode(adev);
7138         }
7139
7140         /* if GRBM CAM not remapped, set up the remapping */
7141         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7142                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7143
7144         gfx_v10_0_constants_init(adev);
7145
7146         r = gfx_v10_0_rlc_resume(adev);
7147         if (r)
7148                 return r;
7149
7150         /*
7151          * init golden registers and rlc resume may override some registers,
7152          * reconfig them here
7153          */
7154         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7155             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7156             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7157                 gfx_v10_0_tcp_harvest(adev);
7158
7159         r = gfx_v10_0_cp_resume(adev);
7160         if (r)
7161                 return r;
7162
7163         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7164                 gfx_v10_3_program_pbb_mode(adev);
7165
7166         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
7167                 gfx_v10_3_set_power_brake_sequence(adev);
7168
7169         return r;
7170 }
7171
7172 static int gfx_v10_0_hw_fini(void *handle)
7173 {
7174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7175
7176         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7177         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7178
7179         /* WA added for Vangogh asic fixing the SMU suspend failure
7180          * It needs to set power gating again during gfxoff control
7181          * otherwise the gfxoff disallowing will be failed to set.
7182          */
7183         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7184                 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
7185
7186         if (!adev->no_hw_access) {
7187                 if (amdgpu_async_gfx_ring) {
7188                         if (amdgpu_gfx_disable_kgq(adev, 0))
7189                                 DRM_ERROR("KGQ disable failed\n");
7190                 }
7191
7192                 if (amdgpu_gfx_disable_kcq(adev, 0))
7193                         DRM_ERROR("KCQ disable failed\n");
7194         }
7195
7196         if (amdgpu_sriov_vf(adev)) {
7197                 gfx_v10_0_cp_gfx_enable(adev, false);
7198                 /* Remove the steps of clearing KIQ position.
7199                  * It causes GFX hang when another Win guest is rendering.
7200                  */
7201                 return 0;
7202         }
7203         gfx_v10_0_cp_enable(adev, false);
7204         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7205
7206         return 0;
7207 }
7208
7209 static int gfx_v10_0_suspend(void *handle)
7210 {
7211         return gfx_v10_0_hw_fini(handle);
7212 }
7213
7214 static int gfx_v10_0_resume(void *handle)
7215 {
7216         return gfx_v10_0_hw_init(handle);
7217 }
7218
7219 static bool gfx_v10_0_is_idle(void *handle)
7220 {
7221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7222
7223         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7224                                 GRBM_STATUS, GUI_ACTIVE))
7225                 return false;
7226         else
7227                 return true;
7228 }
7229
7230 static int gfx_v10_0_wait_for_idle(void *handle)
7231 {
7232         unsigned int i;
7233         u32 tmp;
7234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7235
7236         for (i = 0; i < adev->usec_timeout; i++) {
7237                 /* read MC_STATUS */
7238                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7239                         GRBM_STATUS__GUI_ACTIVE_MASK;
7240
7241                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7242                         return 0;
7243                 udelay(1);
7244         }
7245         return -ETIMEDOUT;
7246 }
7247
7248 static int gfx_v10_0_soft_reset(void *handle)
7249 {
7250         u32 grbm_soft_reset = 0;
7251         u32 tmp;
7252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7253
7254         /* GRBM_STATUS */
7255         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7256         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7257                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7258                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7259                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7260                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7261                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7262                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7263                                                 1);
7264                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7265                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7266                                                 1);
7267         }
7268
7269         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7270                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7271                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7272                                                 1);
7273         }
7274
7275         /* GRBM_STATUS2 */
7276         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7277         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7278         case IP_VERSION(10, 3, 0):
7279         case IP_VERSION(10, 3, 2):
7280         case IP_VERSION(10, 3, 1):
7281         case IP_VERSION(10, 3, 4):
7282         case IP_VERSION(10, 3, 5):
7283         case IP_VERSION(10, 3, 6):
7284         case IP_VERSION(10, 3, 3):
7285                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7286                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7287                                                         GRBM_SOFT_RESET,
7288                                                         SOFT_RESET_RLC,
7289                                                         1);
7290                 break;
7291         default:
7292                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7293                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7294                                                         GRBM_SOFT_RESET,
7295                                                         SOFT_RESET_RLC,
7296                                                         1);
7297                 break;
7298         }
7299
7300         if (grbm_soft_reset) {
7301                 /* stop the rlc */
7302                 gfx_v10_0_rlc_stop(adev);
7303
7304                 /* Disable GFX parsing/prefetching */
7305                 gfx_v10_0_cp_gfx_enable(adev, false);
7306
7307                 /* Disable MEC parsing/prefetching */
7308                 gfx_v10_0_cp_compute_enable(adev, false);
7309
7310                 if (grbm_soft_reset) {
7311                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7312                         tmp |= grbm_soft_reset;
7313                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7314                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7315                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7316
7317                         udelay(50);
7318
7319                         tmp &= ~grbm_soft_reset;
7320                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7321                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7322                 }
7323
7324                 /* Wait a little for things to settle down */
7325                 udelay(50);
7326         }
7327         return 0;
7328 }
7329
7330 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7331 {
7332         uint64_t clock, clock_lo, clock_hi, hi_check;
7333
7334         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7335         case IP_VERSION(10, 1, 3):
7336         case IP_VERSION(10, 1, 4):
7337                 preempt_disable();
7338                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7339                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7340                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7341                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7342                  * roughly every 42 seconds.
7343                  */
7344                 if (hi_check != clock_hi) {
7345                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7346                         clock_hi = hi_check;
7347                 }
7348                 preempt_enable();
7349                 clock = clock_lo | (clock_hi << 32ULL);
7350                 break;
7351         case IP_VERSION(10, 3, 1):
7352         case IP_VERSION(10, 3, 3):
7353         case IP_VERSION(10, 3, 7):
7354                 preempt_disable();
7355                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7356                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7357                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7358                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7359                  * roughly every 42 seconds.
7360                  */
7361                 if (hi_check != clock_hi) {
7362                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7363                         clock_hi = hi_check;
7364                 }
7365                 preempt_enable();
7366                 clock = clock_lo | (clock_hi << 32ULL);
7367                 break;
7368         case IP_VERSION(10, 3, 6):
7369                 preempt_disable();
7370                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7371                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7372                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7373                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7374                  * roughly every 42 seconds.
7375                  */
7376                 if (hi_check != clock_hi) {
7377                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7378                         clock_hi = hi_check;
7379                 }
7380                 preempt_enable();
7381                 clock = clock_lo | (clock_hi << 32ULL);
7382                 break;
7383         default:
7384                 preempt_disable();
7385                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7386                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7387                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7388                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7389                  * roughly every 42 seconds.
7390                  */
7391                 if (hi_check != clock_hi) {
7392                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7393                         clock_hi = hi_check;
7394                 }
7395                 preempt_enable();
7396                 clock = clock_lo | (clock_hi << 32ULL);
7397                 break;
7398         }
7399         return clock;
7400 }
7401
7402 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7403                                            uint32_t vmid,
7404                                            uint32_t gds_base, uint32_t gds_size,
7405                                            uint32_t gws_base, uint32_t gws_size,
7406                                            uint32_t oa_base, uint32_t oa_size)
7407 {
7408         struct amdgpu_device *adev = ring->adev;
7409
7410         /* GDS Base */
7411         gfx_v10_0_write_data_to_reg(ring, 0, false,
7412                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7413                                     gds_base);
7414
7415         /* GDS Size */
7416         gfx_v10_0_write_data_to_reg(ring, 0, false,
7417                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7418                                     gds_size);
7419
7420         /* GWS */
7421         gfx_v10_0_write_data_to_reg(ring, 0, false,
7422                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7423                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7424
7425         /* OA */
7426         gfx_v10_0_write_data_to_reg(ring, 0, false,
7427                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7428                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7429 }
7430
7431 static int gfx_v10_0_early_init(void *handle)
7432 {
7433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7434
7435         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7436
7437         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7438         case IP_VERSION(10, 1, 10):
7439         case IP_VERSION(10, 1, 1):
7440         case IP_VERSION(10, 1, 2):
7441         case IP_VERSION(10, 1, 3):
7442         case IP_VERSION(10, 1, 4):
7443                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7444                 break;
7445         case IP_VERSION(10, 3, 0):
7446         case IP_VERSION(10, 3, 2):
7447         case IP_VERSION(10, 3, 1):
7448         case IP_VERSION(10, 3, 4):
7449         case IP_VERSION(10, 3, 5):
7450         case IP_VERSION(10, 3, 6):
7451         case IP_VERSION(10, 3, 3):
7452         case IP_VERSION(10, 3, 7):
7453                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7454                 break;
7455         default:
7456                 break;
7457         }
7458
7459         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7460                                           AMDGPU_MAX_COMPUTE_RINGS);
7461
7462         gfx_v10_0_set_kiq_pm4_funcs(adev);
7463         gfx_v10_0_set_ring_funcs(adev);
7464         gfx_v10_0_set_irq_funcs(adev);
7465         gfx_v10_0_set_gds_init(adev);
7466         gfx_v10_0_set_rlc_funcs(adev);
7467         gfx_v10_0_set_mqd_funcs(adev);
7468
7469         /* init rlcg reg access ctrl */
7470         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7471
7472         return gfx_v10_0_init_microcode(adev);
7473 }
7474
7475 static int gfx_v10_0_late_init(void *handle)
7476 {
7477         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7478         int r;
7479
7480         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7481         if (r)
7482                 return r;
7483
7484         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7485         if (r)
7486                 return r;
7487
7488         return 0;
7489 }
7490
7491 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7492 {
7493         uint32_t rlc_cntl;
7494
7495         /* if RLC is not enabled, do nothing */
7496         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7497         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7498 }
7499
7500 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7501 {
7502         uint32_t data;
7503         unsigned int i;
7504
7505         data = RLC_SAFE_MODE__CMD_MASK;
7506         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7507
7508         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7509         case IP_VERSION(10, 3, 0):
7510         case IP_VERSION(10, 3, 2):
7511         case IP_VERSION(10, 3, 1):
7512         case IP_VERSION(10, 3, 4):
7513         case IP_VERSION(10, 3, 5):
7514         case IP_VERSION(10, 3, 6):
7515         case IP_VERSION(10, 3, 3):
7516         case IP_VERSION(10, 3, 7):
7517                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7518
7519                 /* wait for RLC_SAFE_MODE */
7520                 for (i = 0; i < adev->usec_timeout; i++) {
7521                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7522                                            RLC_SAFE_MODE, CMD))
7523                                 break;
7524                         udelay(1);
7525                 }
7526                 break;
7527         default:
7528                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7529
7530                 /* wait for RLC_SAFE_MODE */
7531                 for (i = 0; i < adev->usec_timeout; i++) {
7532                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7533                                            RLC_SAFE_MODE, CMD))
7534                                 break;
7535                         udelay(1);
7536                 }
7537                 break;
7538         }
7539 }
7540
7541 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7542 {
7543         uint32_t data;
7544
7545         data = RLC_SAFE_MODE__CMD_MASK;
7546         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7547         case IP_VERSION(10, 3, 0):
7548         case IP_VERSION(10, 3, 2):
7549         case IP_VERSION(10, 3, 1):
7550         case IP_VERSION(10, 3, 4):
7551         case IP_VERSION(10, 3, 5):
7552         case IP_VERSION(10, 3, 6):
7553         case IP_VERSION(10, 3, 3):
7554         case IP_VERSION(10, 3, 7):
7555                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7556                 break;
7557         default:
7558                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7559                 break;
7560         }
7561 }
7562
7563 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7564                                                       bool enable)
7565 {
7566         uint32_t data, def;
7567
7568         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7569                 return;
7570
7571         /* It is disabled by HW by default */
7572         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7573                 /* 0 - Disable some blocks' MGCG */
7574                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7575                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7576                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7577                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7578
7579                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7580                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7581                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7582                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7583                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7584                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7585                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7586                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7587
7588                 if (def != data)
7589                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7590
7591                 /* MGLS is a global flag to control all MGLS in GFX */
7592                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7593                         /* 2 - RLC memory Light sleep */
7594                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7595                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7596                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7597                                 if (def != data)
7598                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7599                         }
7600                         /* 3 - CP memory Light sleep */
7601                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7602                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7603                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7604                                 if (def != data)
7605                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7606                         }
7607                 }
7608         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7609                 /* 1 - MGCG_OVERRIDE */
7610                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7611                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7612                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7613                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7614                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7615                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7616                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7617                 if (def != data)
7618                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7619
7620                 /* 2 - disable MGLS in CP */
7621                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7622                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7623                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7624                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7625                 }
7626
7627                 /* 3 - disable MGLS in RLC */
7628                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7629                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7630                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7631                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7632                 }
7633
7634         }
7635 }
7636
7637 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7638                                            bool enable)
7639 {
7640         uint32_t data, def;
7641
7642         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7643                 return;
7644
7645         /* Enable 3D CGCG/CGLS */
7646         if (enable) {
7647                 /* write cmd to clear cgcg/cgls ov */
7648                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7649
7650                 /* unset CGCG override */
7651                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7652                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7653
7654                 /* update CGCG and CGLS override bits */
7655                 if (def != data)
7656                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7657
7658                 /* enable 3Dcgcg FSM(0x0000363f) */
7659                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7660                 data = 0;
7661
7662                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7663                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7664                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7665
7666                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7667                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7668                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7669
7670                 if (def != data)
7671                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7672
7673                 /* set IDLE_POLL_COUNT(0x00900100) */
7674                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7675                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7676                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7677                 if (def != data)
7678                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7679         } else {
7680                 /* Disable CGCG/CGLS */
7681                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7682
7683                 /* disable cgcg, cgls should be disabled */
7684                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7685                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7686
7687                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7688                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7689
7690                 /* disable cgcg and cgls in FSM */
7691                 if (def != data)
7692                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7693         }
7694 }
7695
7696 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7697                                                       bool enable)
7698 {
7699         uint32_t def, data;
7700
7701         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7702                 return;
7703
7704         if (enable) {
7705                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7706
7707                 /* unset CGCG override */
7708                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7709                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7710
7711                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7712                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7713
7714                 /* update CGCG and CGLS override bits */
7715                 if (def != data)
7716                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7717
7718                 /* enable cgcg FSM(0x0000363F) */
7719                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7720                 data = 0;
7721
7722                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7723                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7724                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7725
7726                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7727                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7728                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7729
7730                 if (def != data)
7731                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7732
7733                 /* set IDLE_POLL_COUNT(0x00900100) */
7734                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7735                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7736                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7737                 if (def != data)
7738                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7739         } else {
7740                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7741
7742                 /* reset CGCG/CGLS bits */
7743                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7744                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7745
7746                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7747                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7748
7749                 /* disable cgcg and cgls in FSM */
7750                 if (def != data)
7751                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7752         }
7753 }
7754
7755 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7756                                                       bool enable)
7757 {
7758         uint32_t def, data;
7759
7760         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7761                 return;
7762
7763         if (enable) {
7764                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7765                 /* unset FGCG override */
7766                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7767                 /* update FGCG override bits */
7768                 if (def != data)
7769                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7770
7771                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7772                 /* unset RLC SRAM CLK GATER override */
7773                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7774                 /* update RLC SRAM CLK GATER override bits */
7775                 if (def != data)
7776                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7777         } else {
7778                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7779                 /* reset FGCG bits */
7780                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7781                 /* disable FGCG*/
7782                 if (def != data)
7783                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7784
7785                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7786                 /* reset RLC SRAM CLK GATER bits */
7787                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7788                 /* disable RLC SRAM CLK*/
7789                 if (def != data)
7790                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7791         }
7792 }
7793
7794 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7795 {
7796         uint32_t reg_data = 0;
7797         uint32_t reg_idx = 0;
7798         uint32_t i;
7799
7800         const uint32_t tcp_ctrl_regs[] = {
7801                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7802                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7803                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7804                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7805                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7806                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7807                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7808                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7809                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7810                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7811                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
7812                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
7813                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7814                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7815                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7816                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7817                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7818                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7819                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7820                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7821                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7822                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7823                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
7824                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
7825         };
7826
7827         const uint32_t tcp_ctrl_regs_nv12[] = {
7828                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7829                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7830                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7831                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7832                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7833                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7834                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7835                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7836                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7837                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7838                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7839                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7840                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7841                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7842                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7843                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7844                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7845                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7846                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7847                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7848         };
7849
7850         const uint32_t sm_ctlr_regs[] = {
7851                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
7852                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
7853                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
7854                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
7855         };
7856
7857         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
7858                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
7859                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7860                                   tcp_ctrl_regs_nv12[i];
7861                         reg_data = RREG32(reg_idx);
7862                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7863                         WREG32(reg_idx, reg_data);
7864                 }
7865         } else {
7866                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
7867                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7868                                   tcp_ctrl_regs[i];
7869                         reg_data = RREG32(reg_idx);
7870                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7871                         WREG32(reg_idx, reg_data);
7872                 }
7873         }
7874
7875         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
7876                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
7877                           sm_ctlr_regs[i];
7878                 reg_data = RREG32(reg_idx);
7879                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
7880                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
7881                 WREG32(reg_idx, reg_data);
7882         }
7883 }
7884
7885 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7886                                             bool enable)
7887 {
7888         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
7889
7890         if (enable) {
7891                 /* enable FGCG firstly*/
7892                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7893                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7894                  * ===  MGCG + MGLS ===
7895                  */
7896                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7897                 /* ===  CGCG /CGLS for GFX 3D Only === */
7898                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7899                 /* ===  CGCG + CGLS === */
7900                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7901
7902                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
7903                      IP_VERSION(10, 1, 10)) ||
7904                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7905                      IP_VERSION(10, 1, 1)) ||
7906                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7907                      IP_VERSION(10, 1, 2)))
7908                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
7909         } else {
7910                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7911                  * ===  CGCG + CGLS ===
7912                  */
7913                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7914                 /* ===  CGCG /CGLS for GFX 3D Only === */
7915                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7916                 /* ===  MGCG + MGLS === */
7917                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7918                 /* disable fgcg at last*/
7919                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7920         }
7921
7922         if (adev->cg_flags &
7923             (AMD_CG_SUPPORT_GFX_MGCG |
7924              AMD_CG_SUPPORT_GFX_CGLS |
7925              AMD_CG_SUPPORT_GFX_CGCG |
7926              AMD_CG_SUPPORT_GFX_3D_CGCG |
7927              AMD_CG_SUPPORT_GFX_3D_CGLS))
7928                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7929
7930         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
7931
7932         return 0;
7933 }
7934
7935 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
7936                                                unsigned int vmid)
7937 {
7938         u32 data;
7939
7940         /* not for *_SOC15 */
7941         data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
7942
7943         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7944         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7945
7946         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7947 }
7948
7949 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
7950 {
7951         amdgpu_gfx_off_ctrl(adev, false);
7952
7953         gfx_v10_0_update_spm_vmid_internal(adev, vmid);
7954
7955         amdgpu_gfx_off_ctrl(adev, true);
7956 }
7957
7958 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7959                                         uint32_t offset,
7960                                         struct soc15_reg_rlcg *entries, int arr_size)
7961 {
7962         int i;
7963         uint32_t reg;
7964
7965         if (!entries)
7966                 return false;
7967
7968         for (i = 0; i < arr_size; i++) {
7969                 const struct soc15_reg_rlcg *entry;
7970
7971                 entry = &entries[i];
7972                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7973                 if (offset == reg)
7974                         return true;
7975         }
7976
7977         return false;
7978 }
7979
7980 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7981 {
7982         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7983 }
7984
7985 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7986 {
7987         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7988
7989         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7990                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7991         else
7992                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7993
7994         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7995
7996         /*
7997          * CGPG enablement required and the register to program the hysteresis value
7998          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7999          * in refclk count. Note that RLC FW is modified to take 16 bits from
8000          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8001          *
8002          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8003          * of CGPG enablement starting point.
8004          * Power/performance team will optimize it and might give a new value later.
8005          */
8006         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8007                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8008                 case IP_VERSION(10, 3, 1):
8009                 case IP_VERSION(10, 3, 3):
8010                 case IP_VERSION(10, 3, 6):
8011                 case IP_VERSION(10, 3, 7):
8012                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8013                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8014                         break;
8015                 default:
8016                         break;
8017                 }
8018         }
8019 }
8020
8021 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8022 {
8023         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8024
8025         gfx_v10_cntl_power_gating(adev, enable);
8026
8027         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8028 }
8029
8030 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8031         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8032         .set_safe_mode = gfx_v10_0_set_safe_mode,
8033         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8034         .init = gfx_v10_0_rlc_init,
8035         .get_csb_size = gfx_v10_0_get_csb_size,
8036         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8037         .resume = gfx_v10_0_rlc_resume,
8038         .stop = gfx_v10_0_rlc_stop,
8039         .reset = gfx_v10_0_rlc_reset,
8040         .start = gfx_v10_0_rlc_start,
8041         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8042 };
8043
8044 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8045         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8046         .set_safe_mode = gfx_v10_0_set_safe_mode,
8047         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8048         .init = gfx_v10_0_rlc_init,
8049         .get_csb_size = gfx_v10_0_get_csb_size,
8050         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8051         .resume = gfx_v10_0_rlc_resume,
8052         .stop = gfx_v10_0_rlc_stop,
8053         .reset = gfx_v10_0_rlc_reset,
8054         .start = gfx_v10_0_rlc_start,
8055         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8056         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8057 };
8058
8059 static int gfx_v10_0_set_powergating_state(void *handle,
8060                                           enum amd_powergating_state state)
8061 {
8062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8063         bool enable = (state == AMD_PG_STATE_GATE);
8064
8065         if (amdgpu_sriov_vf(adev))
8066                 return 0;
8067
8068         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8069         case IP_VERSION(10, 1, 10):
8070         case IP_VERSION(10, 1, 1):
8071         case IP_VERSION(10, 1, 2):
8072         case IP_VERSION(10, 3, 0):
8073         case IP_VERSION(10, 3, 2):
8074         case IP_VERSION(10, 3, 4):
8075         case IP_VERSION(10, 3, 5):
8076                 amdgpu_gfx_off_ctrl(adev, enable);
8077                 break;
8078         case IP_VERSION(10, 3, 1):
8079         case IP_VERSION(10, 3, 3):
8080         case IP_VERSION(10, 3, 6):
8081         case IP_VERSION(10, 3, 7):
8082                 if (!enable)
8083                         amdgpu_gfx_off_ctrl(adev, false);
8084
8085                 gfx_v10_cntl_pg(adev, enable);
8086
8087                 if (enable)
8088                         amdgpu_gfx_off_ctrl(adev, true);
8089
8090                 break;
8091         default:
8092                 break;
8093         }
8094         return 0;
8095 }
8096
8097 static int gfx_v10_0_set_clockgating_state(void *handle,
8098                                           enum amd_clockgating_state state)
8099 {
8100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8101
8102         if (amdgpu_sriov_vf(adev))
8103                 return 0;
8104
8105         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8106         case IP_VERSION(10, 1, 10):
8107         case IP_VERSION(10, 1, 1):
8108         case IP_VERSION(10, 1, 2):
8109         case IP_VERSION(10, 3, 0):
8110         case IP_VERSION(10, 3, 2):
8111         case IP_VERSION(10, 3, 1):
8112         case IP_VERSION(10, 3, 4):
8113         case IP_VERSION(10, 3, 5):
8114         case IP_VERSION(10, 3, 6):
8115         case IP_VERSION(10, 3, 3):
8116         case IP_VERSION(10, 3, 7):
8117                 gfx_v10_0_update_gfx_clock_gating(adev,
8118                                                  state == AMD_CG_STATE_GATE);
8119                 break;
8120         default:
8121                 break;
8122         }
8123         return 0;
8124 }
8125
8126 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8127 {
8128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8129         int data;
8130
8131         /* AMD_CG_SUPPORT_GFX_FGCG */
8132         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8133         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8134                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8135
8136         /* AMD_CG_SUPPORT_GFX_MGCG */
8137         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8138         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8139                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8140
8141         /* AMD_CG_SUPPORT_GFX_CGCG */
8142         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8143         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8144                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8145
8146         /* AMD_CG_SUPPORT_GFX_CGLS */
8147         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8148                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8149
8150         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8151         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8152         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8153                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8154
8155         /* AMD_CG_SUPPORT_GFX_CP_LS */
8156         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8157         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8158                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8159
8160         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8161         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8162         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8163                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8164
8165         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8166         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8167                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8168 }
8169
8170 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8171 {
8172         /* gfx10 is 32bit rptr*/
8173         return *(uint32_t *)ring->rptr_cpu_addr;
8174 }
8175
8176 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8177 {
8178         struct amdgpu_device *adev = ring->adev;
8179         u64 wptr;
8180
8181         /* XXX check if swapping is necessary on BE */
8182         if (ring->use_doorbell) {
8183                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8184         } else {
8185                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8186                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8187         }
8188
8189         return wptr;
8190 }
8191
8192 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8193 {
8194         struct amdgpu_device *adev = ring->adev;
8195         uint32_t *wptr_saved;
8196         uint32_t *is_queue_unmap;
8197         uint64_t aggregated_db_index;
8198         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8199         uint64_t wptr_tmp;
8200
8201         if (ring->is_mes_queue) {
8202                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8203                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8204                                               sizeof(uint32_t));
8205                 aggregated_db_index =
8206                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8207                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8208
8209                 wptr_tmp = ring->wptr & ring->buf_mask;
8210                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8211                 *wptr_saved = wptr_tmp;
8212                 /* assume doorbell always being used by mes mapped queue */
8213                 if (*is_queue_unmap) {
8214                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8215                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8216                 } else {
8217                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8218
8219                         if (*is_queue_unmap)
8220                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8221                 }
8222         } else {
8223                 if (ring->use_doorbell) {
8224                         /* XXX check if swapping is necessary on BE */
8225                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8226                                      ring->wptr);
8227                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8228                 } else {
8229                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8230                                      lower_32_bits(ring->wptr));
8231                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8232                                      upper_32_bits(ring->wptr));
8233                 }
8234         }
8235 }
8236
8237 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8238 {
8239         /* gfx10 hardware is 32bit rptr */
8240         return *(uint32_t *)ring->rptr_cpu_addr;
8241 }
8242
8243 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8244 {
8245         u64 wptr;
8246
8247         /* XXX check if swapping is necessary on BE */
8248         if (ring->use_doorbell)
8249                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8250         else
8251                 BUG();
8252         return wptr;
8253 }
8254
8255 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8256 {
8257         struct amdgpu_device *adev = ring->adev;
8258         uint32_t *wptr_saved;
8259         uint32_t *is_queue_unmap;
8260         uint64_t aggregated_db_index;
8261         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8262         uint64_t wptr_tmp;
8263
8264         if (ring->is_mes_queue) {
8265                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8266                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8267                                               sizeof(uint32_t));
8268                 aggregated_db_index =
8269                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8270                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8271
8272                 wptr_tmp = ring->wptr & ring->buf_mask;
8273                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8274                 *wptr_saved = wptr_tmp;
8275                 /* assume doorbell always used by mes mapped queue */
8276                 if (*is_queue_unmap) {
8277                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8278                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8279                 } else {
8280                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8281
8282                         if (*is_queue_unmap)
8283                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8284                 }
8285         } else {
8286                 /* XXX check if swapping is necessary on BE */
8287                 if (ring->use_doorbell) {
8288                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8289                                      ring->wptr);
8290                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8291                 } else {
8292                         BUG(); /* only DOORBELL method supported on gfx10 now */
8293                 }
8294         }
8295 }
8296
8297 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8298 {
8299         struct amdgpu_device *adev = ring->adev;
8300         u32 ref_and_mask, reg_mem_engine;
8301         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8302
8303         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8304                 switch (ring->me) {
8305                 case 1:
8306                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8307                         break;
8308                 case 2:
8309                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8310                         break;
8311                 default:
8312                         return;
8313                 }
8314                 reg_mem_engine = 0;
8315         } else {
8316                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8317                 reg_mem_engine = 1; /* pfp */
8318         }
8319
8320         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8321                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8322                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8323                                ref_and_mask, ref_and_mask, 0x20);
8324 }
8325
8326 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8327                                        struct amdgpu_job *job,
8328                                        struct amdgpu_ib *ib,
8329                                        uint32_t flags)
8330 {
8331         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8332         u32 header, control = 0;
8333
8334         if (ib->flags & AMDGPU_IB_FLAG_CE)
8335                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8336         else
8337                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8338
8339         control |= ib->length_dw | (vmid << 24);
8340
8341         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8342                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8343
8344                 if (flags & AMDGPU_IB_PREEMPTED)
8345                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8346
8347                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8348                         gfx_v10_0_ring_emit_de_meta(ring,
8349                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8350         }
8351
8352         if (ring->is_mes_queue)
8353                 /* inherit vmid from mqd */
8354                 control |= 0x400000;
8355
8356         amdgpu_ring_write(ring, header);
8357         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8358         amdgpu_ring_write(ring,
8359 #ifdef __BIG_ENDIAN
8360                 (2 << 0) |
8361 #endif
8362                 lower_32_bits(ib->gpu_addr));
8363         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8364         amdgpu_ring_write(ring, control);
8365 }
8366
8367 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8368                                            struct amdgpu_job *job,
8369                                            struct amdgpu_ib *ib,
8370                                            uint32_t flags)
8371 {
8372         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8373         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8374
8375         if (ring->is_mes_queue)
8376                 /* inherit vmid from mqd */
8377                 control |= 0x40000000;
8378
8379         /* Currently, there is a high possibility to get wave ID mismatch
8380          * between ME and GDS, leading to a hw deadlock, because ME generates
8381          * different wave IDs than the GDS expects. This situation happens
8382          * randomly when at least 5 compute pipes use GDS ordered append.
8383          * The wave IDs generated by ME are also wrong after suspend/resume.
8384          * Those are probably bugs somewhere else in the kernel driver.
8385          *
8386          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8387          * GDS to 0 for this ring (me/pipe).
8388          */
8389         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8390                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8391                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8392                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8393         }
8394
8395         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8396         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8397         amdgpu_ring_write(ring,
8398 #ifdef __BIG_ENDIAN
8399                                 (2 << 0) |
8400 #endif
8401                                 lower_32_bits(ib->gpu_addr));
8402         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8403         amdgpu_ring_write(ring, control);
8404 }
8405
8406 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8407                                      u64 seq, unsigned int flags)
8408 {
8409         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8410         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8411
8412         /* RELEASE_MEM - flush caches, send int */
8413         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8414         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8415                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8416                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8417                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8418                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8419                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8420                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8421         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8422                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8423
8424         /*
8425          * the address should be Qword aligned if 64bit write, Dword
8426          * aligned if only send 32bit data low (discard data high)
8427          */
8428         if (write64bit)
8429                 BUG_ON(addr & 0x7);
8430         else
8431                 BUG_ON(addr & 0x3);
8432         amdgpu_ring_write(ring, lower_32_bits(addr));
8433         amdgpu_ring_write(ring, upper_32_bits(addr));
8434         amdgpu_ring_write(ring, lower_32_bits(seq));
8435         amdgpu_ring_write(ring, upper_32_bits(seq));
8436         amdgpu_ring_write(ring, ring->is_mes_queue ?
8437                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8438 }
8439
8440 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8441 {
8442         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8443         uint32_t seq = ring->fence_drv.sync_seq;
8444         uint64_t addr = ring->fence_drv.gpu_addr;
8445
8446         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8447                                upper_32_bits(addr), seq, 0xffffffff, 4);
8448 }
8449
8450 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8451                                    uint16_t pasid, uint32_t flush_type,
8452                                    bool all_hub, uint8_t dst_sel)
8453 {
8454         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8455         amdgpu_ring_write(ring,
8456                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8457                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8458                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8459                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8460 }
8461
8462 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8463                                          unsigned int vmid, uint64_t pd_addr)
8464 {
8465         if (ring->is_mes_queue)
8466                 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8467         else
8468                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8469
8470         /* compute doesn't have PFP */
8471         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8472                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8473                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8474                 amdgpu_ring_write(ring, 0x0);
8475         }
8476 }
8477
8478 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8479                                           u64 seq, unsigned int flags)
8480 {
8481         struct amdgpu_device *adev = ring->adev;
8482
8483         /* we only allocate 32bit for each seq wb address */
8484         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8485
8486         /* write fence seq to the "addr" */
8487         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8488         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8489                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8490         amdgpu_ring_write(ring, lower_32_bits(addr));
8491         amdgpu_ring_write(ring, upper_32_bits(addr));
8492         amdgpu_ring_write(ring, lower_32_bits(seq));
8493
8494         if (flags & AMDGPU_FENCE_FLAG_INT) {
8495                 /* set register to trigger INT */
8496                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8497                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8498                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8499                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8500                 amdgpu_ring_write(ring, 0);
8501                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8502         }
8503 }
8504
8505 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8506 {
8507         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8508         amdgpu_ring_write(ring, 0);
8509 }
8510
8511 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8512                                          uint32_t flags)
8513 {
8514         uint32_t dw2 = 0;
8515
8516         if (ring->adev->gfx.mcbp)
8517                 gfx_v10_0_ring_emit_ce_meta(ring,
8518                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8519
8520         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8521         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8522                 /* set load_global_config & load_global_uconfig */
8523                 dw2 |= 0x8001;
8524                 /* set load_cs_sh_regs */
8525                 dw2 |= 0x01000000;
8526                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8527                 dw2 |= 0x10002;
8528
8529                 /* set load_ce_ram if preamble presented */
8530                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8531                         dw2 |= 0x10000000;
8532         } else {
8533                 /* still load_ce_ram if this is the first time preamble presented
8534                  * although there is no context switch happens.
8535                  */
8536                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8537                         dw2 |= 0x10000000;
8538         }
8539
8540         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8541         amdgpu_ring_write(ring, dw2);
8542         amdgpu_ring_write(ring, 0);
8543 }
8544
8545 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8546                                                        uint64_t addr)
8547 {
8548         unsigned int ret;
8549
8550         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8551         amdgpu_ring_write(ring, lower_32_bits(addr));
8552         amdgpu_ring_write(ring, upper_32_bits(addr));
8553         /* discard following DWs if *cond_exec_gpu_addr==0 */
8554         amdgpu_ring_write(ring, 0);
8555         ret = ring->wptr & ring->buf_mask;
8556         /* patch dummy value later */
8557         amdgpu_ring_write(ring, 0);
8558
8559         return ret;
8560 }
8561
8562 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8563 {
8564         int i, r = 0;
8565         struct amdgpu_device *adev = ring->adev;
8566         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8567         struct amdgpu_ring *kiq_ring = &kiq->ring;
8568         unsigned long flags;
8569
8570         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8571                 return -EINVAL;
8572
8573         spin_lock_irqsave(&kiq->ring_lock, flags);
8574
8575         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8576                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8577                 return -ENOMEM;
8578         }
8579
8580         /* assert preemption condition */
8581         amdgpu_ring_set_preempt_cond_exec(ring, false);
8582
8583         /* assert IB preemption, emit the trailing fence */
8584         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8585                                    ring->trail_fence_gpu_addr,
8586                                    ++ring->trail_seq);
8587         amdgpu_ring_commit(kiq_ring);
8588
8589         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8590
8591         /* poll the trailing fence */
8592         for (i = 0; i < adev->usec_timeout; i++) {
8593                 if (ring->trail_seq ==
8594                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8595                         break;
8596                 udelay(1);
8597         }
8598
8599         if (i >= adev->usec_timeout) {
8600                 r = -EINVAL;
8601                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8602         }
8603
8604         /* deassert preemption condition */
8605         amdgpu_ring_set_preempt_cond_exec(ring, true);
8606         return r;
8607 }
8608
8609 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8610 {
8611         struct amdgpu_device *adev = ring->adev;
8612         struct v10_ce_ib_state ce_payload = {0};
8613         uint64_t offset, ce_payload_gpu_addr;
8614         void *ce_payload_cpu_addr;
8615         int cnt;
8616
8617         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8618
8619         if (ring->is_mes_queue) {
8620                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8621                                   gfx[0].gfx_meta_data) +
8622                         offsetof(struct v10_gfx_meta_data, ce_payload);
8623                 ce_payload_gpu_addr =
8624                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8625                 ce_payload_cpu_addr =
8626                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8627         } else {
8628                 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8629                 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8630                 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8631         }
8632
8633         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8634         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8635                                  WRITE_DATA_DST_SEL(8) |
8636                                  WR_CONFIRM) |
8637                                  WRITE_DATA_CACHE_POLICY(0));
8638         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8639         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8640
8641         if (resume)
8642                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8643                                            sizeof(ce_payload) >> 2);
8644         else
8645                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8646                                            sizeof(ce_payload) >> 2);
8647 }
8648
8649 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8650 {
8651         struct amdgpu_device *adev = ring->adev;
8652         struct v10_de_ib_state de_payload = {0};
8653         uint64_t offset, gds_addr, de_payload_gpu_addr;
8654         void *de_payload_cpu_addr;
8655         int cnt;
8656
8657         if (ring->is_mes_queue) {
8658                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8659                                   gfx[0].gfx_meta_data) +
8660                         offsetof(struct v10_gfx_meta_data, de_payload);
8661                 de_payload_gpu_addr =
8662                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8663                 de_payload_cpu_addr =
8664                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8665
8666                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8667                                   gfx[0].gds_backup) +
8668                         offsetof(struct v10_gfx_meta_data, de_payload);
8669                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8670         } else {
8671                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8672                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8673                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8674
8675                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8676                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
8677                                  PAGE_SIZE);
8678         }
8679
8680         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8681         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8682
8683         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8684         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8685         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8686                                  WRITE_DATA_DST_SEL(8) |
8687                                  WR_CONFIRM) |
8688                                  WRITE_DATA_CACHE_POLICY(0));
8689         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8690         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8691
8692         if (resume)
8693                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8694                                            sizeof(de_payload) >> 2);
8695         else
8696                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8697                                            sizeof(de_payload) >> 2);
8698 }
8699
8700 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8701                                     bool secure)
8702 {
8703         uint32_t v = secure ? FRAME_TMZ : 0;
8704
8705         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8706         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8707 }
8708
8709 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8710                                      uint32_t reg_val_offs)
8711 {
8712         struct amdgpu_device *adev = ring->adev;
8713
8714         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8715         amdgpu_ring_write(ring, 0 |     /* src: register*/
8716                                 (5 << 8) |      /* dst: memory */
8717                                 (1 << 20));     /* write confirm */
8718         amdgpu_ring_write(ring, reg);
8719         amdgpu_ring_write(ring, 0);
8720         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8721                                 reg_val_offs * 4));
8722         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8723                                 reg_val_offs * 4));
8724 }
8725
8726 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8727                                    uint32_t val)
8728 {
8729         uint32_t cmd = 0;
8730
8731         switch (ring->funcs->type) {
8732         case AMDGPU_RING_TYPE_GFX:
8733                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8734                 break;
8735         case AMDGPU_RING_TYPE_KIQ:
8736                 cmd = (1 << 16); /* no inc addr */
8737                 break;
8738         default:
8739                 cmd = WR_CONFIRM;
8740                 break;
8741         }
8742         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8743         amdgpu_ring_write(ring, cmd);
8744         amdgpu_ring_write(ring, reg);
8745         amdgpu_ring_write(ring, 0);
8746         amdgpu_ring_write(ring, val);
8747 }
8748
8749 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8750                                         uint32_t val, uint32_t mask)
8751 {
8752         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8753 }
8754
8755 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8756                                                    uint32_t reg0, uint32_t reg1,
8757                                                    uint32_t ref, uint32_t mask)
8758 {
8759         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8760         struct amdgpu_device *adev = ring->adev;
8761         bool fw_version_ok = false;
8762
8763         fw_version_ok = adev->gfx.cp_fw_write_wait;
8764
8765         if (fw_version_ok)
8766                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8767                                        ref, mask, 0x20);
8768         else
8769                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8770                                                            ref, mask);
8771 }
8772
8773 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8774                                          unsigned int vmid)
8775 {
8776         struct amdgpu_device *adev = ring->adev;
8777         uint32_t value = 0;
8778
8779         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8780         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8781         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8782         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8783         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8784 }
8785
8786 static void
8787 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8788                                       uint32_t me, uint32_t pipe,
8789                                       enum amdgpu_interrupt_state state)
8790 {
8791         uint32_t cp_int_cntl, cp_int_cntl_reg;
8792
8793         if (!me) {
8794                 switch (pipe) {
8795                 case 0:
8796                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8797                         break;
8798                 case 1:
8799                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8800                         break;
8801                 default:
8802                         DRM_DEBUG("invalid pipe %d\n", pipe);
8803                         return;
8804                 }
8805         } else {
8806                 DRM_DEBUG("invalid me %d\n", me);
8807                 return;
8808         }
8809
8810         switch (state) {
8811         case AMDGPU_IRQ_STATE_DISABLE:
8812                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8813                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8814                                             TIME_STAMP_INT_ENABLE, 0);
8815                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8816                 break;
8817         case AMDGPU_IRQ_STATE_ENABLE:
8818                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8819                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8820                                             TIME_STAMP_INT_ENABLE, 1);
8821                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8822                 break;
8823         default:
8824                 break;
8825         }
8826 }
8827
8828 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8829                                                      int me, int pipe,
8830                                                      enum amdgpu_interrupt_state state)
8831 {
8832         u32 mec_int_cntl, mec_int_cntl_reg;
8833
8834         /*
8835          * amdgpu controls only the first MEC. That's why this function only
8836          * handles the setting of interrupts for this specific MEC. All other
8837          * pipes' interrupts are set by amdkfd.
8838          */
8839
8840         if (me == 1) {
8841                 switch (pipe) {
8842                 case 0:
8843                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8844                         break;
8845                 case 1:
8846                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8847                         break;
8848                 case 2:
8849                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8850                         break;
8851                 case 3:
8852                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8853                         break;
8854                 default:
8855                         DRM_DEBUG("invalid pipe %d\n", pipe);
8856                         return;
8857                 }
8858         } else {
8859                 DRM_DEBUG("invalid me %d\n", me);
8860                 return;
8861         }
8862
8863         switch (state) {
8864         case AMDGPU_IRQ_STATE_DISABLE:
8865                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8866                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8867                                              TIME_STAMP_INT_ENABLE, 0);
8868                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8869                 break;
8870         case AMDGPU_IRQ_STATE_ENABLE:
8871                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8872                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8873                                              TIME_STAMP_INT_ENABLE, 1);
8874                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8875                 break;
8876         default:
8877                 break;
8878         }
8879 }
8880
8881 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8882                                             struct amdgpu_irq_src *src,
8883                                             unsigned int type,
8884                                             enum amdgpu_interrupt_state state)
8885 {
8886         switch (type) {
8887         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8888                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8889                 break;
8890         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8891                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8892                 break;
8893         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8894                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8895                 break;
8896         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8897                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8898                 break;
8899         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8900                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8901                 break;
8902         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8903                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8904                 break;
8905         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8906                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8907                 break;
8908         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8909                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8910                 break;
8911         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8912                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8913                 break;
8914         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8915                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8916                 break;
8917         default:
8918                 break;
8919         }
8920         return 0;
8921 }
8922
8923 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8924                              struct amdgpu_irq_src *source,
8925                              struct amdgpu_iv_entry *entry)
8926 {
8927         int i;
8928         u8 me_id, pipe_id, queue_id;
8929         struct amdgpu_ring *ring;
8930         uint32_t mes_queue_id = entry->src_data[0];
8931
8932         DRM_DEBUG("IH: CP EOP\n");
8933
8934         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
8935                 struct amdgpu_mes_queue *queue;
8936
8937                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
8938
8939                 spin_lock(&adev->mes.queue_id_lock);
8940                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
8941                 if (queue) {
8942                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
8943                         amdgpu_fence_process(queue->ring);
8944                 }
8945                 spin_unlock(&adev->mes.queue_id_lock);
8946         } else {
8947                 me_id = (entry->ring_id & 0x0c) >> 2;
8948                 pipe_id = (entry->ring_id & 0x03) >> 0;
8949                 queue_id = (entry->ring_id & 0x70) >> 4;
8950
8951                 switch (me_id) {
8952                 case 0:
8953                         if (pipe_id == 0)
8954                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8955                         else
8956                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8957                         break;
8958                 case 1:
8959                 case 2:
8960                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8961                                 ring = &adev->gfx.compute_ring[i];
8962                                 /* Per-queue interrupt is supported for MEC starting from VI.
8963                                  * The interrupt can only be enabled/disabled per pipe instead
8964                                  * of per queue.
8965                                  */
8966                                 if ((ring->me == me_id) &&
8967                                     (ring->pipe == pipe_id) &&
8968                                     (ring->queue == queue_id))
8969                                         amdgpu_fence_process(ring);
8970                         }
8971                         break;
8972                 }
8973         }
8974
8975         return 0;
8976 }
8977
8978 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8979                                               struct amdgpu_irq_src *source,
8980                                               unsigned int type,
8981                                               enum amdgpu_interrupt_state state)
8982 {
8983         switch (state) {
8984         case AMDGPU_IRQ_STATE_DISABLE:
8985         case AMDGPU_IRQ_STATE_ENABLE:
8986                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8987                                PRIV_REG_INT_ENABLE,
8988                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8989                 break;
8990         default:
8991                 break;
8992         }
8993
8994         return 0;
8995 }
8996
8997 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8998                                                struct amdgpu_irq_src *source,
8999                                                unsigned int type,
9000                                                enum amdgpu_interrupt_state state)
9001 {
9002         switch (state) {
9003         case AMDGPU_IRQ_STATE_DISABLE:
9004         case AMDGPU_IRQ_STATE_ENABLE:
9005                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9006                                PRIV_INSTR_INT_ENABLE,
9007                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9008                 break;
9009         default:
9010                 break;
9011         }
9012
9013         return 0;
9014 }
9015
9016 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9017                                         struct amdgpu_iv_entry *entry)
9018 {
9019         u8 me_id, pipe_id, queue_id;
9020         struct amdgpu_ring *ring;
9021         int i;
9022
9023         me_id = (entry->ring_id & 0x0c) >> 2;
9024         pipe_id = (entry->ring_id & 0x03) >> 0;
9025         queue_id = (entry->ring_id & 0x70) >> 4;
9026
9027         switch (me_id) {
9028         case 0:
9029                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9030                         ring = &adev->gfx.gfx_ring[i];
9031                         /* we only enabled 1 gfx queue per pipe for now */
9032                         if (ring->me == me_id && ring->pipe == pipe_id)
9033                                 drm_sched_fault(&ring->sched);
9034                 }
9035                 break;
9036         case 1:
9037         case 2:
9038                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9039                         ring = &adev->gfx.compute_ring[i];
9040                         if (ring->me == me_id && ring->pipe == pipe_id &&
9041                             ring->queue == queue_id)
9042                                 drm_sched_fault(&ring->sched);
9043                 }
9044                 break;
9045         default:
9046                 BUG();
9047         }
9048 }
9049
9050 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9051                                   struct amdgpu_irq_src *source,
9052                                   struct amdgpu_iv_entry *entry)
9053 {
9054         DRM_ERROR("Illegal register access in command stream\n");
9055         gfx_v10_0_handle_priv_fault(adev, entry);
9056         return 0;
9057 }
9058
9059 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9060                                    struct amdgpu_irq_src *source,
9061                                    struct amdgpu_iv_entry *entry)
9062 {
9063         DRM_ERROR("Illegal instruction in command stream\n");
9064         gfx_v10_0_handle_priv_fault(adev, entry);
9065         return 0;
9066 }
9067
9068 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9069                                              struct amdgpu_irq_src *src,
9070                                              unsigned int type,
9071                                              enum amdgpu_interrupt_state state)
9072 {
9073         uint32_t tmp, target;
9074         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9075
9076         if (ring->me == 1)
9077                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9078         else
9079                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9080         target += ring->pipe;
9081
9082         switch (type) {
9083         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9084                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9085                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9086                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9087                                             GENERIC2_INT_ENABLE, 0);
9088                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9089
9090                         tmp = RREG32_SOC15_IP(GC, target);
9091                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9092                                             GENERIC2_INT_ENABLE, 0);
9093                         WREG32_SOC15_IP(GC, target, tmp);
9094                 } else {
9095                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9096                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9097                                             GENERIC2_INT_ENABLE, 1);
9098                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9099
9100                         tmp = RREG32_SOC15_IP(GC, target);
9101                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9102                                             GENERIC2_INT_ENABLE, 1);
9103                         WREG32_SOC15_IP(GC, target, tmp);
9104                 }
9105                 break;
9106         default:
9107                 BUG(); /* kiq only support GENERIC2_INT now */
9108                 break;
9109         }
9110         return 0;
9111 }
9112
9113 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9114                              struct amdgpu_irq_src *source,
9115                              struct amdgpu_iv_entry *entry)
9116 {
9117         u8 me_id, pipe_id, queue_id;
9118         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9119
9120         me_id = (entry->ring_id & 0x0c) >> 2;
9121         pipe_id = (entry->ring_id & 0x03) >> 0;
9122         queue_id = (entry->ring_id & 0x70) >> 4;
9123         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9124                    me_id, pipe_id, queue_id);
9125
9126         amdgpu_fence_process(ring);
9127         return 0;
9128 }
9129
9130 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9131 {
9132         const unsigned int gcr_cntl =
9133                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9134                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9135                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9136                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9137                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9138                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9139                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9140                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9141
9142         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9143         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9144         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9145         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9146         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9147         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9148         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9149         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9150         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9151 }
9152
9153 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9154         .name = "gfx_v10_0",
9155         .early_init = gfx_v10_0_early_init,
9156         .late_init = gfx_v10_0_late_init,
9157         .sw_init = gfx_v10_0_sw_init,
9158         .sw_fini = gfx_v10_0_sw_fini,
9159         .hw_init = gfx_v10_0_hw_init,
9160         .hw_fini = gfx_v10_0_hw_fini,
9161         .suspend = gfx_v10_0_suspend,
9162         .resume = gfx_v10_0_resume,
9163         .is_idle = gfx_v10_0_is_idle,
9164         .wait_for_idle = gfx_v10_0_wait_for_idle,
9165         .soft_reset = gfx_v10_0_soft_reset,
9166         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9167         .set_powergating_state = gfx_v10_0_set_powergating_state,
9168         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9169 };
9170
9171 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9172         .type = AMDGPU_RING_TYPE_GFX,
9173         .align_mask = 0xff,
9174         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9175         .support_64bit_ptrs = true,
9176         .secure_submission_supported = true,
9177         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9178         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9179         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9180         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9181                 5 + /* COND_EXEC */
9182                 7 + /* PIPELINE_SYNC */
9183                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9184                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9185                 2 + /* VM_FLUSH */
9186                 8 + /* FENCE for VM_FLUSH */
9187                 20 + /* GDS switch */
9188                 4 + /* double SWITCH_BUFFER,
9189                      * the first COND_EXEC jump to the place
9190                      * just prior to this double SWITCH_BUFFER
9191                      */
9192                 5 + /* COND_EXEC */
9193                 7 + /* HDP_flush */
9194                 4 + /* VGT_flush */
9195                 14 + /* CE_META */
9196                 31 + /* DE_META */
9197                 3 + /* CNTX_CTRL */
9198                 5 + /* HDP_INVL */
9199                 8 + 8 + /* FENCE x2 */
9200                 2 + /* SWITCH_BUFFER */
9201                 8, /* gfx_v10_0_emit_mem_sync */
9202         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9203         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9204         .emit_fence = gfx_v10_0_ring_emit_fence,
9205         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9206         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9207         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9208         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9209         .test_ring = gfx_v10_0_ring_test_ring,
9210         .test_ib = gfx_v10_0_ring_test_ib,
9211         .insert_nop = amdgpu_ring_insert_nop,
9212         .pad_ib = amdgpu_ring_generic_pad_ib,
9213         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9214         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9215         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9216         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9217         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9218         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9219         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9220         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9221         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9222         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9223 };
9224
9225 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9226         .type = AMDGPU_RING_TYPE_COMPUTE,
9227         .align_mask = 0xff,
9228         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9229         .support_64bit_ptrs = true,
9230         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9231         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9232         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9233         .emit_frame_size =
9234                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9235                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9236                 5 + /* hdp invalidate */
9237                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9238                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9239                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9240                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9241                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9242                 8, /* gfx_v10_0_emit_mem_sync */
9243         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9244         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9245         .emit_fence = gfx_v10_0_ring_emit_fence,
9246         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9247         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9248         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9249         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9250         .test_ring = gfx_v10_0_ring_test_ring,
9251         .test_ib = gfx_v10_0_ring_test_ib,
9252         .insert_nop = amdgpu_ring_insert_nop,
9253         .pad_ib = amdgpu_ring_generic_pad_ib,
9254         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9255         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9256         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9257         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9258 };
9259
9260 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9261         .type = AMDGPU_RING_TYPE_KIQ,
9262         .align_mask = 0xff,
9263         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9264         .support_64bit_ptrs = true,
9265         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9266         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9267         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9268         .emit_frame_size =
9269                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9270                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9271                 5 + /*hdp invalidate */
9272                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9273                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9274                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9275                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9276                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9277         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9278         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9279         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9280         .test_ring = gfx_v10_0_ring_test_ring,
9281         .test_ib = gfx_v10_0_ring_test_ib,
9282         .insert_nop = amdgpu_ring_insert_nop,
9283         .pad_ib = amdgpu_ring_generic_pad_ib,
9284         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9285         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9286         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9287         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9288 };
9289
9290 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9291 {
9292         int i;
9293
9294         adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9295
9296         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9297                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9298
9299         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9300                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9301 }
9302
9303 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9304         .set = gfx_v10_0_set_eop_interrupt_state,
9305         .process = gfx_v10_0_eop_irq,
9306 };
9307
9308 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9309         .set = gfx_v10_0_set_priv_reg_fault_state,
9310         .process = gfx_v10_0_priv_reg_irq,
9311 };
9312
9313 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9314         .set = gfx_v10_0_set_priv_inst_fault_state,
9315         .process = gfx_v10_0_priv_inst_irq,
9316 };
9317
9318 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9319         .set = gfx_v10_0_kiq_set_interrupt_state,
9320         .process = gfx_v10_0_kiq_irq,
9321 };
9322
9323 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9324 {
9325         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9326         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9327
9328         adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9329         adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9330
9331         adev->gfx.priv_reg_irq.num_types = 1;
9332         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9333
9334         adev->gfx.priv_inst_irq.num_types = 1;
9335         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9336 }
9337
9338 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9339 {
9340         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9341         case IP_VERSION(10, 1, 10):
9342         case IP_VERSION(10, 1, 1):
9343         case IP_VERSION(10, 1, 3):
9344         case IP_VERSION(10, 1, 4):
9345         case IP_VERSION(10, 3, 2):
9346         case IP_VERSION(10, 3, 1):
9347         case IP_VERSION(10, 3, 4):
9348         case IP_VERSION(10, 3, 5):
9349         case IP_VERSION(10, 3, 6):
9350         case IP_VERSION(10, 3, 3):
9351         case IP_VERSION(10, 3, 7):
9352                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9353                 break;
9354         case IP_VERSION(10, 1, 2):
9355         case IP_VERSION(10, 3, 0):
9356                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9357                 break;
9358         default:
9359                 break;
9360         }
9361 }
9362
9363 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9364 {
9365         unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9366                             adev->gfx.config.max_sh_per_se *
9367                             adev->gfx.config.max_shader_engines;
9368
9369         adev->gds.gds_size = 0x10000;
9370         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9371         adev->gds.gws_size = 64;
9372         adev->gds.oa_size = 16;
9373 }
9374
9375 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9376 {
9377         /* set gfx eng mqd */
9378         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9379                 sizeof(struct v10_gfx_mqd);
9380         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9381                 gfx_v10_0_gfx_mqd_init;
9382         /* set compute eng mqd */
9383         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9384                 sizeof(struct v10_compute_mqd);
9385         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9386                 gfx_v10_0_compute_mqd_init;
9387 }
9388
9389 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9390                                                           u32 bitmap)
9391 {
9392         u32 data;
9393
9394         if (!bitmap)
9395                 return;
9396
9397         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9398         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9399
9400         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9401 }
9402
9403 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9404 {
9405         u32 disabled_mask =
9406                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9407         u32 efuse_setting = 0;
9408         u32 vbios_setting = 0;
9409
9410         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9411         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9412         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9413
9414         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9415         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9416         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9417
9418         disabled_mask |= efuse_setting | vbios_setting;
9419
9420         return (~disabled_mask);
9421 }
9422
9423 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9424 {
9425         u32 wgp_idx, wgp_active_bitmap;
9426         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9427
9428         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9429         cu_active_bitmap = 0;
9430
9431         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9432                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9433                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9434                 if (wgp_active_bitmap & (1 << wgp_idx))
9435                         cu_active_bitmap |= cu_bitmap_per_wgp;
9436         }
9437
9438         return cu_active_bitmap;
9439 }
9440
9441 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9442                                  struct amdgpu_cu_info *cu_info)
9443 {
9444         int i, j, k, counter, active_cu_number = 0;
9445         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9446         unsigned int disable_masks[4 * 2];
9447
9448         if (!adev || !cu_info)
9449                 return -EINVAL;
9450
9451         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9452
9453         mutex_lock(&adev->grbm_idx_mutex);
9454         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9455                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9456                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9457                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
9458                               IP_VERSION(10, 3, 0)) ||
9459                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9460                               IP_VERSION(10, 3, 3)) ||
9461                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9462                               IP_VERSION(10, 3, 6)) ||
9463                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9464                               IP_VERSION(10, 3, 7))) &&
9465                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9466                                 continue;
9467                         mask = 1;
9468                         ao_bitmap = 0;
9469                         counter = 0;
9470                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9471                         if (i < 4 && j < 2)
9472                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9473                                         adev, disable_masks[i * 2 + j]);
9474                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9475                         cu_info->bitmap[0][i][j] = bitmap;
9476
9477                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9478                                 if (bitmap & mask) {
9479                                         if (counter < adev->gfx.config.max_cu_per_sh)
9480                                                 ao_bitmap |= mask;
9481                                         counter++;
9482                                 }
9483                                 mask <<= 1;
9484                         }
9485                         active_cu_number += counter;
9486                         if (i < 2 && j < 2)
9487                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9488                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9489                 }
9490         }
9491         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9492         mutex_unlock(&adev->grbm_idx_mutex);
9493
9494         cu_info->number = active_cu_number;
9495         cu_info->ao_cu_mask = ao_cu_mask;
9496         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9497
9498         return 0;
9499 }
9500
9501 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9502 {
9503         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9504
9505         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9506         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9507         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9508
9509         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9510         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9511         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9512
9513         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9514                                                 adev->gfx.config.max_shader_engines);
9515         disabled_sa = efuse_setting | vbios_setting;
9516         disabled_sa &= max_sa_mask;
9517
9518         return disabled_sa;
9519 }
9520
9521 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9522 {
9523         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9524         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9525
9526         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9527
9528         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9529         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9530         max_shader_engines = adev->gfx.config.max_shader_engines;
9531
9532         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9533                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9534                 disabled_sa_per_se &= max_sa_per_se_mask;
9535                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9536                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9537                         break;
9538                 }
9539         }
9540 }
9541
9542 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9543 {
9544         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9545                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9546                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9547                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9548
9549         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9550         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9551                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9552                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9553                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9554                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9555
9556         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9557                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9558                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9559                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9560
9561         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9562
9563         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9564                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9565 }
9566
9567 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9568         .type = AMD_IP_BLOCK_TYPE_GFX,
9569         .major = 10,
9570         .minor = 0,
9571         .rev = 0,
9572         .funcs = &gfx_v10_0_ip_funcs,
9573 };