drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *    Mika Kuoppala <[email protected]>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include <linux/stop_machine.h>
  32 #include <linux/zlib.h>
  33 #include <drm/drm_print.h>
  34
  35 #include "i915_drv.h"
  36
  37 static inline const struct intel_engine_cs *
  38 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
  39 {
  40         if (id >= I915_NUM_ENGINES)
  41                 return NULL;
  42
  43         return i915->engine[id];
  44 }
  45
  46 static inline const char *
  47 __engine_name(const struct intel_engine_cs *engine)
  48 {
  49         return engine ? engine->name : "";
  50 }
  51
  52 static const char *
  53 engine_name(const struct drm_i915_private *i915, unsigned int id)
  54 {
  55         return __engine_name(engine_lookup(i915, id));
  56 }
  57
  58 static const char *tiling_flag(int tiling)
  59 {
  60         switch (tiling) {
  61         default:
  62         case I915_TILING_NONE: return "";
  63         case I915_TILING_X: return " X";
  64         case I915_TILING_Y: return " Y";
  65         }
  66 }
  67
  68 static const char *dirty_flag(int dirty)
  69 {
  70         return dirty ? " dirty" : "";
  71 }
  72
  73 static const char *purgeable_flag(int purgeable)
  74 {
  75         return purgeable ? " purgeable" : "";
  76 }
  77
  78 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  79 {
  80
  81         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  82                 e->err = -ENOSPC;
  83                 return false;
  84         }
  85
  86         if (e->bytes == e->size - 1 || e->err)
  87                 return false;
  88
  89         return true;
  90 }
  91
  92 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  93                               unsigned len)
  94 {
  95         if (e->pos + len <= e->start) {
  96                 e->pos += len;
  97                 return false;
  98         }
  99
 100         /* First vsnprintf needs to fit in its entirety for memmove */
 101         if (len >= e->size) {
 102                 e->err = -EIO;
 103                 return false;
 104         }
 105
 106         return true;
 107 }
 108
 109 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 110                                  unsigned len)
 111 {
 112         /* If this is first printf in this window, adjust it so that
 113          * start position matches start of the buffer
 114          */
 115
 116         if (e->pos < e->start) {
 117                 const size_t off = e->start - e->pos;
 118
 119                 /* Should not happen but be paranoid */
 120                 if (off > len || e->bytes) {
 121                         e->err = -EIO;
 122                         return;
 123                 }
 124
 125                 memmove(e->buf, e->buf + off, len - off);
 126                 e->bytes = len - off;
 127                 e->pos = e->start;
 128                 return;
 129         }
 130
 131         e->bytes += len;
 132         e->pos += len;
 133 }
 134
 135 __printf(2, 0)
 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 137                                const char *f, va_list args)
 138 {
 139         unsigned len;
 140
 141         if (!__i915_error_ok(e))
 142                 return;
 143
 144         /* Seek the first printf which is hits start position */
 145         if (e->pos < e->start) {
 146                 va_list tmp;
 147
 148                 va_copy(tmp, args);
 149                 len = vsnprintf(NULL, 0, f, tmp);
 150                 va_end(tmp);
 151
 152                 if (!__i915_error_seek(e, len))
 153                         return;
 154         }
 155
 156         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 157         if (len >= e->size - e->bytes)
 158                 len = e->size - e->bytes - 1;
 159
 160         __i915_error_advance(e, len);
 161 }
 162
 163 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 164                             const char *str)
 165 {
 166         unsigned len;
 167
 168         if (!__i915_error_ok(e))
 169                 return;
 170
 171         len = strlen(str);
 172
 173         /* Seek the first printf which is hits start position */
 174         if (e->pos < e->start) {
 175                 if (!__i915_error_seek(e, len))
 176                         return;
 177         }
 178
 179         if (len >= e->size - e->bytes)
 180                 len = e->size - e->bytes - 1;
 181         memcpy(e->buf + e->bytes, str, len);
 182
 183         __i915_error_advance(e, len);
 184 }
 185
 186 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 187 #define err_puts(e, s) i915_error_puts(e, s)
 188
 189 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 190 {
 191         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 192 }
 193
 194 static inline struct drm_printer
 195 i915_error_printer(struct drm_i915_error_state_buf *e)
 196 {
 197         struct drm_printer p = {
 198                 .printfn = __i915_printfn_error,
 199                 .arg = e,
 200         };
 201         return p;
 202 }
 203
 204 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 205
 206 struct compress {
 207         struct z_stream_s zstream;
 208         void *tmp;
 209 };
 210
 211 static bool compress_init(struct compress *c)
 212 {
 213         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
 214
 215         zstream->workspace =
 216                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 217                         GFP_ATOMIC | __GFP_NOWARN);
 218         if (!zstream->workspace)
 219                 return false;
 220
 221         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 222                 kfree(zstream->workspace);
 223                 return false;
 224         }
 225
 226         c->tmp = NULL;
 227         if (i915_has_memcpy_from_wc())
 228                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 229
 230         return true;
 231 }
 232
 233 static int compress_page(struct compress *c,
 234                          void *src,
 235                          struct drm_i915_error_object *dst)
 236 {
 237         struct z_stream_s *zstream = &c->zstream;
 238
 239         zstream->next_in = src;
 240         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 241                 zstream->next_in = c->tmp;
 242         zstream->avail_in = PAGE_SIZE;
 243
 244         do {
 245                 if (zstream->avail_out == 0) {
 246                         unsigned long page;
 247
 248                         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 249                         if (!page)
 250                                 return -ENOMEM;
 251
 252                         dst->pages[dst->page_count++] = (void *)page;
 253
 254                         zstream->next_out = (void *)page;
 255                         zstream->avail_out = PAGE_SIZE;
 256                 }
 257
 258                 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
 259                         return -EIO;
 260         } while (zstream->avail_in);
 261
 262         /* Fallback to uncompressed if we increase size? */
 263         if (0 && zstream->total_out > zstream->total_in)
 264                 return -E2BIG;
 265
 266         return 0;
 267 }
 268
 269 static void compress_fini(struct compress *c,
 270                           struct drm_i915_error_object *dst)
 271 {
 272         struct z_stream_s *zstream = &c->zstream;
 273
 274         if (dst) {
 275                 zlib_deflate(zstream, Z_FINISH);
 276                 dst->unused = zstream->avail_out;
 277         }
 278
 279         zlib_deflateEnd(zstream);
 280         kfree(zstream->workspace);
 281
 282         if (c->tmp)
 283                 free_page((unsigned long)c->tmp);
 284 }
 285
 286 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 287 {
 288         err_puts(m, ":");
 289 }
 290
 291 #else
 292
 293 struct compress {
 294 };
 295
 296 static bool compress_init(struct compress *c)
 297 {
 298         return true;
 299 }
 300
 301 static int compress_page(struct compress *c,
 302                          void *src,
 303                          struct drm_i915_error_object *dst)
 304 {
 305         unsigned long page;
 306         void *ptr;
 307
 308         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 309         if (!page)
 310                 return -ENOMEM;
 311
 312         ptr = (void *)page;
 313         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 314                 memcpy(ptr, src, PAGE_SIZE);
 315         dst->pages[dst->page_count++] = ptr;
 316
 317         return 0;
 318 }
 319
 320 static void compress_fini(struct compress *c,
 321                           struct drm_i915_error_object *dst)
 322 {
 323 }
 324
 325 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 326 {
 327         err_puts(m, "~");
 328 }
 329
 330 #endif
 331
 332 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 333                                 const char *name,
 334                                 struct drm_i915_error_buffer *err,
 335                                 int count)
 336 {
 337         int i;
 338
 339         err_printf(m, "%s [%d]:\n", name, count);
 340
 341         while (count--) {
 342                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 343                            upper_32_bits(err->gtt_offset),
 344                            lower_32_bits(err->gtt_offset),
 345                            err->size,
 346                            err->read_domains,
 347                            err->write_domain);
 348                 for (i = 0; i < I915_NUM_ENGINES; i++)
 349                         err_printf(m, "%02x ", err->rseqno[i]);
 350
 351                 err_printf(m, "] %02x", err->wseqno);
 352                 err_puts(m, tiling_flag(err->tiling));
 353                 err_puts(m, dirty_flag(err->dirty));
 354                 err_puts(m, purgeable_flag(err->purgeable));
 355                 err_puts(m, err->userptr ? " userptr" : "");
 356                 err_puts(m, err->engine != -1 ? " " : "");
 357                 err_puts(m, engine_name(m->i915, err->engine));
 358                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 359
 360                 if (err->name)
 361                         err_printf(m, " (name: %d)", err->name);
 362                 if (err->fence_reg != I915_FENCE_REG_NONE)
 363                         err_printf(m, " (fence: %d)", err->fence_reg);
 364
 365                 err_puts(m, "\n");
 366                 err++;
 367         }
 368 }
 369
 370 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 371                                  const struct drm_i915_error_engine *ee)
 372 {
 373         int slice;
 374         int subslice;
 375
 376         err_printf(m, "  INSTDONE: 0x%08x\n",
 377                    ee->instdone.instdone);
 378
 379         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 380                 return;
 381
 382         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 383                    ee->instdone.slice_common);
 384
 385         if (INTEL_GEN(m->i915) <= 6)
 386                 return;
 387
 388         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 389                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 390                            slice, subslice,
 391                            ee->instdone.sampler[slice][subslice]);
 392
 393         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 394                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 395                            slice, subslice,
 396                            ee->instdone.row[slice][subslice]);
 397 }
 398
 399 static const char *bannable(const struct drm_i915_error_context *ctx)
 400 {
 401         return ctx->bannable ? "" : " (unbannable)";
 402 }
 403
 404 static void error_print_request(struct drm_i915_error_state_buf *m,
 405                                 const char *prefix,
 406                                 const struct drm_i915_error_request *erq)
 407 {
 408         if (!erq->seqno)
 409                 return;
 410
 411         err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms ago, head %08x, tail %08x\n",
 412                    prefix, erq->pid, erq->ban_score,
 413                    erq->context, erq->seqno, erq->priority,
 414                    jiffies_to_msecs(jiffies - erq->jiffies),
 415                    erq->head, erq->tail);
 416 }
 417
 418 static void error_print_context(struct drm_i915_error_state_buf *m,
 419                                 const char *header,
 420                                 const struct drm_i915_error_context *ctx)
 421 {
 422         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
 423                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
 424                    ctx->priority, ctx->ban_score, bannable(ctx),
 425                    ctx->guilty, ctx->active);
 426 }
 427
 428 static void error_print_engine(struct drm_i915_error_state_buf *m,
 429                                const struct drm_i915_error_engine *ee)
 430 {
 431         int n;
 432
 433         err_printf(m, "%s command stream:\n",
 434                    engine_name(m->i915, ee->engine_id));
 435         err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
 436         err_printf(m, "  START: 0x%08x\n", ee->start);
 437         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 438         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 439                    ee->tail, ee->rq_post, ee->rq_tail);
 440         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 441         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 442         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 443         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 444                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 445         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 446         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 447
 448         error_print_instdone(m, ee);
 449
 450         if (ee->batchbuffer) {
 451                 u64 start = ee->batchbuffer->gtt_offset;
 452                 u64 end = start + ee->batchbuffer->gtt_size;
 453
 454                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 455                            upper_32_bits(start), lower_32_bits(start),
 456                            upper_32_bits(end), lower_32_bits(end));
 457         }
 458         if (INTEL_GEN(m->i915) >= 4) {
 459                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 460                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 461                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 462                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 463         }
 464         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 465         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 466                    lower_32_bits(ee->faddr));
 467         if (INTEL_GEN(m->i915) >= 6) {
 468                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 469                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 470                 err_printf(m, "  SYNC_0: 0x%08x\n",
 471                            ee->semaphore_mboxes[0]);
 472                 err_printf(m, "  SYNC_1: 0x%08x\n",
 473                            ee->semaphore_mboxes[1]);
 474                 if (HAS_VEBOX(m->i915))
 475                         err_printf(m, "  SYNC_2: 0x%08x\n",
 476                                    ee->semaphore_mboxes[2]);
 477         }
 478         if (USES_PPGTT(m->i915)) {
 479                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 480
 481                 if (INTEL_GEN(m->i915) >= 8) {
 482                         int i;
 483                         for (i = 0; i < 4; i++)
 484                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 485                                            i, ee->vm_info.pdp[i]);
 486                 } else {
 487                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 488                                    ee->vm_info.pp_dir_base);
 489                 }
 490         }
 491         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 492         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 493         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 494         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 495         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 496         err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
 497         err_printf(m, "  hangcheck action: %s\n",
 498                    hangcheck_action_to_str(ee->hangcheck_action));
 499         err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
 500                    ee->hangcheck_timestamp,
 501                    jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
 502         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 503
 504         for (n = 0; n < ee->num_ports; n++) {
 505                 err_printf(m, "  ELSP[%d]:", n);
 506                 error_print_request(m, " ", &ee->execlist[n]);
 507         }
 508
 509         error_print_context(m, "  Active context: ", &ee->context);
 510 }
 511
 512 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 513 {
 514         va_list args;
 515
 516         va_start(args, f);
 517         i915_error_vprintf(e, f, args);
 518         va_end(args);
 519 }
 520
 521 static int
 522 ascii85_encode_len(int len)
 523 {
 524         return DIV_ROUND_UP(len, 4);
 525 }
 526
 527 static bool
 528 ascii85_encode(u32 in, char *out)
 529 {
 530         int i;
 531
 532         if (in == 0)
 533                 return false;
 534
 535         out[5] = '\0';
 536         for (i = 5; i--; ) {
 537                 out[i] = '!' + in % 85;
 538                 in /= 85;
 539         }
 540
 541         return true;
 542 }
 543
 544 static void print_error_obj(struct drm_i915_error_state_buf *m,
 545                             struct intel_engine_cs *engine,
 546                             const char *name,
 547                             struct drm_i915_error_object *obj)
 548 {
 549         char out[6];
 550         int page;
 551
 552         if (!obj)
 553                 return;
 554
 555         if (name) {
 556                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 557                            engine ? engine->name : "global", name,
 558                            upper_32_bits(obj->gtt_offset),
 559                            lower_32_bits(obj->gtt_offset));
 560         }
 561
 562         err_compression_marker(m);
 563         for (page = 0; page < obj->page_count; page++) {
 564                 int i, len;
 565
 566                 len = PAGE_SIZE;
 567                 if (page == obj->page_count - 1)
 568                         len -= obj->unused;
 569                 len = ascii85_encode_len(len);
 570
 571                 for (i = 0; i < len; i++) {
 572                         if (ascii85_encode(obj->pages[page][i], out))
 573                                 err_puts(m, out);
 574                         else
 575                                 err_puts(m, "z");
 576                 }
 577         }
 578         err_puts(m, "\n");
 579 }
 580
 581 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 582                                    const struct intel_device_info *info,
 583                                    const struct intel_driver_caps *caps)
 584 {
 585         struct drm_printer p = i915_error_printer(m);
 586
 587         intel_device_info_dump_flags(info, &p);
 588         intel_driver_caps_print(caps, &p);
 589         intel_device_info_dump_topology(&info->sseu, &p);
 590 }
 591
 592 static void err_print_params(struct drm_i915_error_state_buf *m,
 593                              const struct i915_params *params)
 594 {
 595         struct drm_printer p = i915_error_printer(m);
 596
 597         i915_params_dump(params, &p);
 598 }
 599
 600 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 601                             struct drm_i915_private *i915)
 602 {
 603         struct pci_dev *pdev = i915->drm.pdev;
 604
 605         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 606         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 607         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 608                    pdev->subsystem_vendor,
 609                    pdev->subsystem_device);
 610 }
 611
 612 static void err_print_uc(struct drm_i915_error_state_buf *m,
 613                          const struct i915_error_uc *error_uc)
 614 {
 615         struct drm_printer p = i915_error_printer(m);
 616         const struct i915_gpu_state *error =
 617                 container_of(error_uc, typeof(*error), uc);
 618
 619         if (!error->device_info.has_guc)
 620                 return;
 621
 622         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 623         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 624         print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 625 }
 626
 627 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 628                             const struct i915_gpu_state *error)
 629 {
 630         struct drm_i915_private *dev_priv = m->i915;
 631         struct drm_i915_error_object *obj;
 632         struct timespec64 ts;
 633         int i, j;
 634
 635         if (!error) {
 636                 err_printf(m, "No error state collected\n");
 637                 return 0;
 638         }
 639
 640         if (*error->error_msg)
 641                 err_printf(m, "%s\n", error->error_msg);
 642         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 643         ts = ktime_to_timespec64(error->time);
 644         err_printf(m, "Time: %lld s %ld us\n",
 645                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 646         ts = ktime_to_timespec64(error->boottime);
 647         err_printf(m, "Boottime: %lld s %ld us\n",
 648                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 649         ts = ktime_to_timespec64(error->uptime);
 650         err_printf(m, "Uptime: %lld s %ld us\n",
 651                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 652
 653         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 654                 if (error->engine[i].hangcheck_stalled &&
 655                     error->engine[i].context.pid) {
 656                         err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
 657                                    engine_name(m->i915, i),
 658                                    error->engine[i].context.comm,
 659                                    error->engine[i].context.pid,
 660                                    error->engine[i].context.ban_score,
 661                                    bannable(&error->engine[i].context));
 662                 }
 663         }
 664         err_printf(m, "Reset count: %u\n", error->reset_count);
 665         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 666         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 667         err_print_pciid(m, error->i915);
 668
 669         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 670
 671         if (HAS_CSR(dev_priv)) {
 672                 struct intel_csr *csr = &dev_priv->csr;
 673
 674                 err_printf(m, "DMC loaded: %s\n",
 675                            yesno(csr->dmc_payload != NULL));
 676                 err_printf(m, "DMC fw version: %d.%d\n",
 677                            CSR_VERSION_MAJOR(csr->version),
 678                            CSR_VERSION_MINOR(csr->version));
 679         }
 680
 681         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 682         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 683         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 684         err_printf(m, "EIR: 0x%08x\n", error->eir);
 685         err_printf(m, "IER: 0x%08x\n", error->ier);
 686         for (i = 0; i < error->ngtier; i++)
 687                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 688         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 689         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 690         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 691         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 692         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 693
 694         for (i = 0; i < error->nfence; i++)
 695                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 696
 697         if (INTEL_GEN(dev_priv) >= 6) {
 698                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 699
 700                 if (INTEL_GEN(dev_priv) >= 8)
 701                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 702                                    error->fault_data1, error->fault_data0);
 703
 704                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 705         }
 706
 707         if (IS_GEN7(dev_priv))
 708                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 709
 710         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 711                 if (error->engine[i].engine_id != -1)
 712                         error_print_engine(m, &error->engine[i]);
 713         }
 714
 715         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 716                 char buf[128];
 717                 int len, first = 1;
 718
 719                 if (!error->active_vm[i])
 720                         break;
 721
 722                 len = scnprintf(buf, sizeof(buf), "Active (");
 723                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 724                         if (error->engine[j].vm != error->active_vm[i])
 725                                 continue;
 726
 727                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 728                                          first ? "" : ", ",
 729                                          dev_priv->engine[j]->name);
 730                         first = 0;
 731                 }
 732                 scnprintf(buf + len, sizeof(buf), ")");
 733                 print_error_buffers(m, buf,
 734                                     error->active_bo[i],
 735                                     error->active_bo_count[i]);
 736         }
 737
 738         print_error_buffers(m, "Pinned (global)",
 739                             error->pinned_bo,
 740                             error->pinned_bo_count);
 741
 742         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 743                 const struct drm_i915_error_engine *ee = &error->engine[i];
 744
 745                 obj = ee->batchbuffer;
 746                 if (obj) {
 747                         err_puts(m, dev_priv->engine[i]->name);
 748                         if (ee->context.pid)
 749                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
 750                                            ee->context.comm,
 751                                            ee->context.pid,
 752                                            ee->context.handle,
 753                                            ee->context.hw_id,
 754                                            ee->context.ban_score,
 755                                            bannable(&ee->context));
 756                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 757                                    upper_32_bits(obj->gtt_offset),
 758                                    lower_32_bits(obj->gtt_offset));
 759                         print_error_obj(m, dev_priv->engine[i], NULL, obj);
 760                 }
 761
 762                 for (j = 0; j < ee->user_bo_count; j++)
 763                         print_error_obj(m, dev_priv->engine[i],
 764                                         "user", ee->user_bo[j]);
 765
 766                 if (ee->num_requests) {
 767                         err_printf(m, "%s --- %d requests\n",
 768                                    dev_priv->engine[i]->name,
 769                                    ee->num_requests);
 770                         for (j = 0; j < ee->num_requests; j++)
 771                                 error_print_request(m, " ", &ee->requests[j]);
 772                 }
 773
 774                 if (IS_ERR(ee->waiters)) {
 775                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 776                                    dev_priv->engine[i]->name);
 777                 } else if (ee->num_waiters) {
 778                         err_printf(m, "%s --- %d waiters\n",
 779                                    dev_priv->engine[i]->name,
 780                                    ee->num_waiters);
 781                         for (j = 0; j < ee->num_waiters; j++) {
 782                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 783                                            ee->waiters[j].seqno,
 784                                            ee->waiters[j].comm,
 785                                            ee->waiters[j].pid);
 786                         }
 787                 }
 788
 789                 print_error_obj(m, dev_priv->engine[i],
 790                                 "ringbuffer", ee->ringbuffer);
 791
 792                 print_error_obj(m, dev_priv->engine[i],
 793                                 "HW Status", ee->hws_page);
 794
 795                 print_error_obj(m, dev_priv->engine[i],
 796                                 "HW context", ee->ctx);
 797
 798                 print_error_obj(m, dev_priv->engine[i],
 799                                 "WA context", ee->wa_ctx);
 800
 801                 print_error_obj(m, dev_priv->engine[i],
 802                                 "WA batchbuffer", ee->wa_batchbuffer);
 803
 804                 print_error_obj(m, dev_priv->engine[i],
 805                                 "NULL context", ee->default_state);
 806         }
 807
 808         if (error->overlay)
 809                 intel_overlay_print_error_state(m, error->overlay);
 810
 811         if (error->display)
 812                 intel_display_print_error_state(m, error->display);
 813
 814         err_print_capabilities(m, &error->device_info, &error->driver_caps);
 815         err_print_params(m, &error->params);
 816         err_print_uc(m, &error->uc);
 817
 818         if (m->bytes == 0 && m->err)
 819                 return m->err;
 820
 821         return 0;
 822 }
 823
 824 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 825                               struct drm_i915_private *i915,
 826                               size_t count, loff_t pos)
 827 {
 828         memset(ebuf, 0, sizeof(*ebuf));
 829         ebuf->i915 = i915;
 830
 831         /* We need to have enough room to store any i915_error_state printf
 832          * so that we can move it to start position.
 833          */
 834         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 835         ebuf->buf = kmalloc(ebuf->size,
 836                                 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
 837
 838         if (ebuf->buf == NULL) {
 839                 ebuf->size = PAGE_SIZE;
 840                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 841         }
 842
 843         if (ebuf->buf == NULL) {
 844                 ebuf->size = 128;
 845                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 846         }
 847
 848         if (ebuf->buf == NULL)
 849                 return -ENOMEM;
 850
 851         ebuf->start = pos;
 852
 853         return 0;
 854 }
 855
 856 static void i915_error_object_free(struct drm_i915_error_object *obj)
 857 {
 858         int page;
 859
 860         if (obj == NULL)
 861                 return;
 862
 863         for (page = 0; page < obj->page_count; page++)
 864                 free_page((unsigned long)obj->pages[page]);
 865
 866         kfree(obj);
 867 }
 868
 869 static __always_inline void free_param(const char *type, void *x)
 870 {
 871         if (!__builtin_strcmp(type, "char *"))
 872                 kfree(*(void **)x);
 873 }
 874
 875 static void cleanup_params(struct i915_gpu_state *error)
 876 {
 877 #define FREE(T, x, ...) free_param(#T, &error->params.x);
 878         I915_PARAMS_FOR_EACH(FREE);
 879 #undef FREE
 880 }
 881
 882 static void cleanup_uc_state(struct i915_gpu_state *error)
 883 {
 884         struct i915_error_uc *error_uc = &error->uc;
 885
 886         kfree(error_uc->guc_fw.path);
 887         kfree(error_uc->huc_fw.path);
 888         i915_error_object_free(error_uc->guc_log);
 889 }
 890
 891 void __i915_gpu_state_free(struct kref *error_ref)
 892 {
 893         struct i915_gpu_state *error =
 894                 container_of(error_ref, typeof(*error), ref);
 895         long i, j;
 896
 897         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 898                 struct drm_i915_error_engine *ee = &error->engine[i];
 899
 900                 for (j = 0; j < ee->user_bo_count; j++)
 901                         i915_error_object_free(ee->user_bo[j]);
 902                 kfree(ee->user_bo);
 903
 904                 i915_error_object_free(ee->batchbuffer);
 905                 i915_error_object_free(ee->wa_batchbuffer);
 906                 i915_error_object_free(ee->ringbuffer);
 907                 i915_error_object_free(ee->hws_page);
 908                 i915_error_object_free(ee->ctx);
 909                 i915_error_object_free(ee->wa_ctx);
 910
 911                 kfree(ee->requests);
 912                 if (!IS_ERR_OR_NULL(ee->waiters))
 913                         kfree(ee->waiters);
 914         }
 915
 916         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
 917                 kfree(error->active_bo[i]);
 918         kfree(error->pinned_bo);
 919
 920         kfree(error->overlay);
 921         kfree(error->display);
 922
 923         cleanup_params(error);
 924         cleanup_uc_state(error);
 925
 926         kfree(error);
 927 }
 928
 929 static struct drm_i915_error_object *
 930 i915_error_object_create(struct drm_i915_private *i915,
 931                          struct i915_vma *vma)
 932 {
 933         struct i915_ggtt *ggtt = &i915->ggtt;
 934         const u64 slot = ggtt->error_capture.start;
 935         struct drm_i915_error_object *dst;
 936         struct compress compress;
 937         unsigned long num_pages;
 938         struct sgt_iter iter;
 939         dma_addr_t dma;
 940
 941         if (!vma)
 942                 return NULL;
 943
 944         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 945         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 946         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
 947                       GFP_ATOMIC | __GFP_NOWARN);
 948         if (!dst)
 949                 return NULL;
 950
 951         dst->gtt_offset = vma->node.start;
 952         dst->gtt_size = vma->node.size;
 953         dst->page_count = 0;
 954         dst->unused = 0;
 955
 956         if (!compress_init(&compress)) {
 957                 kfree(dst);
 958                 return NULL;
 959         }
 960
 961         for_each_sgt_dma(dma, iter, vma->pages) {
 962                 void __iomem *s;
 963                 int ret;
 964
 965                 ggtt->base.insert_page(&ggtt->base, dma, slot,
 966                                        I915_CACHE_NONE, 0);
 967
 968                 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
 969                 ret = compress_page(&compress, (void  __force *)s, dst);
 970                 io_mapping_unmap_atomic(s);
 971
 972                 if (ret)
 973                         goto unwind;
 974         }
 975         goto out;
 976
 977 unwind:
 978         while (dst->page_count--)
 979                 free_page((unsigned long)dst->pages[dst->page_count]);
 980         kfree(dst);
 981         dst = NULL;
 982
 983 out:
 984         compress_fini(&compress, dst);
 985         ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
 986         return dst;
 987 }
 988
 989 /* The error capture is special as tries to run underneath the normal
 990  * locking rules - so we use the raw version of the i915_gem_active lookup.
 991  */
 992 static inline uint32_t
 993 __active_get_seqno(struct i915_gem_active *active)
 994 {
 995         struct i915_request *request;
 996
 997         request = __i915_gem_active_peek(active);
 998         return request ? request->global_seqno : 0;
 999 }
1000
1001 static inline int
1002 __active_get_engine_id(struct i915_gem_active *active)
1003 {
1004         struct i915_request *request;
1005
1006         request = __i915_gem_active_peek(active);
1007         return request ? request->engine->id : -1;
1008 }
1009
1010 static void capture_bo(struct drm_i915_error_buffer *err,
1011                        struct i915_vma *vma)
1012 {
1013         struct drm_i915_gem_object *obj = vma->obj;
1014         int i;
1015
1016         err->size = obj->base.size;
1017         err->name = obj->base.name;
1018
1019         for (i = 0; i < I915_NUM_ENGINES; i++)
1020                 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
1021         err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1022         err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1023
1024         err->gtt_offset = vma->node.start;
1025         err->read_domains = obj->read_domains;
1026         err->write_domain = obj->write_domain;
1027         err->fence_reg = vma->fence ? vma->fence->id : -1;
1028         err->tiling = i915_gem_object_get_tiling(obj);
1029         err->dirty = obj->mm.dirty;
1030         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1031         err->userptr = obj->userptr.mm != NULL;
1032         err->cache_level = obj->cache_level;
1033 }
1034
1035 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1036                             int count, struct list_head *head,
1037                             bool pinned_only)
1038 {
1039         struct i915_vma *vma;
1040         int i = 0;
1041
1042         list_for_each_entry(vma, head, vm_link) {
1043                 if (pinned_only && !i915_vma_is_pinned(vma))
1044                         continue;
1045
1046                 capture_bo(err++, vma);
1047                 if (++i == count)
1048                         break;
1049         }
1050
1051         return i;
1052 }
1053
1054 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1055  * code's only purpose is to try to prevent false duplicated bug reports by
1056  * grossly estimating a GPU error state.
1057  *
1058  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1059  * the hang if we could strip the GTT offset information from it.
1060  *
1061  * It's only a small step better than a random number in its current form.
1062  */
1063 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1064                                          struct i915_gpu_state *error,
1065                                          int *engine_id)
1066 {
1067         uint32_t error_code = 0;
1068         int i;
1069
1070         /* IPEHR would be an ideal way to detect errors, as it's the gross
1071          * measure of "the command that hung." However, has some very common
1072          * synchronization commands which almost always appear in the case
1073          * strictly a client bug. Use instdone to differentiate those some.
1074          */
1075         for (i = 0; i < I915_NUM_ENGINES; i++) {
1076                 if (error->engine[i].hangcheck_stalled) {
1077                         if (engine_id)
1078                                 *engine_id = i;
1079
1080                         return error->engine[i].ipehr ^
1081                                error->engine[i].instdone.instdone;
1082                 }
1083         }
1084
1085         return error_code;
1086 }
1087
1088 static void gem_record_fences(struct i915_gpu_state *error)
1089 {
1090         struct drm_i915_private *dev_priv = error->i915;
1091         int i;
1092
1093         if (INTEL_GEN(dev_priv) >= 6) {
1094                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1095                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1096         } else if (INTEL_GEN(dev_priv) >= 4) {
1097                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1098                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1099         } else {
1100                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1101                         error->fence[i] = I915_READ(FENCE_REG(i));
1102         }
1103         error->nfence = i;
1104 }
1105
1106 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1107                                         struct drm_i915_error_engine *ee)
1108 {
1109         struct drm_i915_private *dev_priv = engine->i915;
1110
1111         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1112         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1113         if (HAS_VEBOX(dev_priv))
1114                 ee->semaphore_mboxes[2] =
1115                         I915_READ(RING_SYNC_2(engine->mmio_base));
1116 }
1117
1118 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1119                                         struct drm_i915_error_engine *ee)
1120 {
1121         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1122         struct drm_i915_error_waiter *waiter;
1123         struct rb_node *rb;
1124         int count;
1125
1126         ee->num_waiters = 0;
1127         ee->waiters = NULL;
1128
1129         if (RB_EMPTY_ROOT(&b->waiters))
1130                 return;
1131
1132         if (!spin_trylock_irq(&b->rb_lock)) {
1133                 ee->waiters = ERR_PTR(-EDEADLK);
1134                 return;
1135         }
1136
1137         count = 0;
1138         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1139                 count++;
1140         spin_unlock_irq(&b->rb_lock);
1141
1142         waiter = NULL;
1143         if (count)
1144                 waiter = kmalloc_array(count,
1145                                        sizeof(struct drm_i915_error_waiter),
1146                                        GFP_ATOMIC);
1147         if (!waiter)
1148                 return;
1149
1150         if (!spin_trylock_irq(&b->rb_lock)) {
1151                 kfree(waiter);
1152                 ee->waiters = ERR_PTR(-EDEADLK);
1153                 return;
1154         }
1155
1156         ee->waiters = waiter;
1157         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1158                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1159
1160                 strcpy(waiter->comm, w->tsk->comm);
1161                 waiter->pid = w->tsk->pid;
1162                 waiter->seqno = w->seqno;
1163                 waiter++;
1164
1165                 if (++ee->num_waiters == count)
1166                         break;
1167         }
1168         spin_unlock_irq(&b->rb_lock);
1169 }
1170
1171 static void error_record_engine_registers(struct i915_gpu_state *error,
1172                                           struct intel_engine_cs *engine,
1173                                           struct drm_i915_error_engine *ee)
1174 {
1175         struct drm_i915_private *dev_priv = engine->i915;
1176
1177         if (INTEL_GEN(dev_priv) >= 6) {
1178                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1179                 if (INTEL_GEN(dev_priv) >= 8) {
1180                         ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1181                 } else {
1182                         gen6_record_semaphore_state(engine, ee);
1183                         ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1184                 }
1185         }
1186
1187         if (INTEL_GEN(dev_priv) >= 4) {
1188                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1189                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1190                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1191                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1192                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1193                 if (INTEL_GEN(dev_priv) >= 8) {
1194                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1195                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1196                 }
1197                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1198         } else {
1199                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1200                 ee->ipeir = I915_READ(IPEIR);
1201                 ee->ipehr = I915_READ(IPEHR);
1202         }
1203
1204         intel_engine_get_instdone(engine, &ee->instdone);
1205
1206         ee->waiting = intel_engine_has_waiter(engine);
1207         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1208         ee->acthd = intel_engine_get_active_head(engine);
1209         ee->seqno = intel_engine_get_seqno(engine);
1210         ee->last_seqno = intel_engine_last_submit(engine);
1211         ee->start = I915_READ_START(engine);
1212         ee->head = I915_READ_HEAD(engine);
1213         ee->tail = I915_READ_TAIL(engine);
1214         ee->ctl = I915_READ_CTL(engine);
1215         if (INTEL_GEN(dev_priv) > 2)
1216                 ee->mode = I915_READ_MODE(engine);
1217
1218         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1219                 i915_reg_t mmio;
1220
1221                 if (IS_GEN7(dev_priv)) {
1222                         switch (engine->id) {
1223                         default:
1224                         case RCS:
1225                                 mmio = RENDER_HWS_PGA_GEN7;
1226                                 break;
1227                         case BCS:
1228                                 mmio = BLT_HWS_PGA_GEN7;
1229                                 break;
1230                         case VCS:
1231                                 mmio = BSD_HWS_PGA_GEN7;
1232                                 break;
1233                         case VECS:
1234                                 mmio = VEBOX_HWS_PGA_GEN7;
1235                                 break;
1236                         }
1237                 } else if (IS_GEN6(engine->i915)) {
1238                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1239                 } else {
1240                         /* XXX: gen8 returns to sanity */
1241                         mmio = RING_HWS_PGA(engine->mmio_base);
1242                 }
1243
1244                 ee->hws = I915_READ(mmio);
1245         }
1246
1247         ee->idle = intel_engine_is_idle(engine);
1248         ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1249         ee->hangcheck_action = engine->hangcheck.action;
1250         ee->hangcheck_stalled = engine->hangcheck.stalled;
1251         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1252                                                   engine);
1253
1254         if (USES_PPGTT(dev_priv)) {
1255                 int i;
1256
1257                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1258
1259                 if (IS_GEN6(dev_priv))
1260                         ee->vm_info.pp_dir_base =
1261                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1262                 else if (IS_GEN7(dev_priv))
1263                         ee->vm_info.pp_dir_base =
1264                                 I915_READ(RING_PP_DIR_BASE(engine));
1265                 else if (INTEL_GEN(dev_priv) >= 8)
1266                         for (i = 0; i < 4; i++) {
1267                                 ee->vm_info.pdp[i] =
1268                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1269                                 ee->vm_info.pdp[i] <<= 32;
1270                                 ee->vm_info.pdp[i] |=
1271                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1272                         }
1273         }
1274 }
1275
1276 static void record_request(struct i915_request *request,
1277                            struct drm_i915_error_request *erq)
1278 {
1279         erq->context = request->ctx->hw_id;
1280         erq->priority = request->priotree.priority;
1281         erq->ban_score = atomic_read(&request->ctx->ban_score);
1282         erq->seqno = request->global_seqno;
1283         erq->jiffies = request->emitted_jiffies;
1284         erq->head = request->head;
1285         erq->tail = request->tail;
1286
1287         rcu_read_lock();
1288         erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1289         rcu_read_unlock();
1290 }
1291
1292 static void engine_record_requests(struct intel_engine_cs *engine,
1293                                    struct i915_request *first,
1294                                    struct drm_i915_error_engine *ee)
1295 {
1296         struct i915_request *request;
1297         int count;
1298
1299         count = 0;
1300         request = first;
1301         list_for_each_entry_from(request, &engine->timeline->requests, link)
1302                 count++;
1303         if (!count)
1304                 return;
1305
1306         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1307         if (!ee->requests)
1308                 return;
1309
1310         ee->num_requests = count;
1311
1312         count = 0;
1313         request = first;
1314         list_for_each_entry_from(request, &engine->timeline->requests, link) {
1315                 if (count >= ee->num_requests) {
1316                         /*
1317                          * If the ring request list was changed in
1318                          * between the point where the error request
1319                          * list was created and dimensioned and this
1320                          * point then just exit early to avoid crashes.
1321                          *
1322                          * We don't need to communicate that the
1323                          * request list changed state during error
1324                          * state capture and that the error state is
1325                          * slightly incorrect as a consequence since we
1326                          * are typically only interested in the request
1327                          * list state at the point of error state
1328                          * capture, not in any changes happening during
1329                          * the capture.
1330                          */
1331                         break;
1332                 }
1333
1334                 record_request(request, &ee->requests[count++]);
1335         }
1336         ee->num_requests = count;
1337 }
1338
1339 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1340                                           struct drm_i915_error_engine *ee)
1341 {
1342         const struct intel_engine_execlists * const execlists = &engine->execlists;
1343         unsigned int n;
1344
1345         for (n = 0; n < execlists_num_ports(execlists); n++) {
1346                 struct i915_request *rq = port_request(&execlists->port[n]);
1347
1348                 if (!rq)
1349                         break;
1350
1351                 record_request(rq, &ee->execlist[n]);
1352         }
1353
1354         ee->num_ports = n;
1355 }
1356
1357 static void record_context(struct drm_i915_error_context *e,
1358                            struct i915_gem_context *ctx)
1359 {
1360         if (ctx->pid) {
1361                 struct task_struct *task;
1362
1363                 rcu_read_lock();
1364                 task = pid_task(ctx->pid, PIDTYPE_PID);
1365                 if (task) {
1366                         strcpy(e->comm, task->comm);
1367                         e->pid = task->pid;
1368                 }
1369                 rcu_read_unlock();
1370         }
1371
1372         e->handle = ctx->user_handle;
1373         e->hw_id = ctx->hw_id;
1374         e->priority = ctx->priority;
1375         e->ban_score = atomic_read(&ctx->ban_score);
1376         e->bannable = i915_gem_context_is_bannable(ctx);
1377         e->guilty = atomic_read(&ctx->guilty_count);
1378         e->active = atomic_read(&ctx->active_count);
1379 }
1380
1381 static void request_record_user_bo(struct i915_request *request,
1382                                    struct drm_i915_error_engine *ee)
1383 {
1384         struct i915_capture_list *c;
1385         struct drm_i915_error_object **bo;
1386         long count;
1387
1388         count = 0;
1389         for (c = request->capture_list; c; c = c->next)
1390                 count++;
1391
1392         bo = NULL;
1393         if (count)
1394                 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1395         if (!bo)
1396                 return;
1397
1398         count = 0;
1399         for (c = request->capture_list; c; c = c->next) {
1400                 bo[count] = i915_error_object_create(request->i915, c->vma);
1401                 if (!bo[count])
1402                         break;
1403                 count++;
1404         }
1405
1406         ee->user_bo = bo;
1407         ee->user_bo_count = count;
1408 }
1409
1410 static struct drm_i915_error_object *
1411 capture_object(struct drm_i915_private *dev_priv,
1412                struct drm_i915_gem_object *obj)
1413 {
1414         if (obj && i915_gem_object_has_pages(obj)) {
1415                 struct i915_vma fake = {
1416                         .node = { .start = U64_MAX, .size = obj->base.size },
1417                         .size = obj->base.size,
1418                         .pages = obj->mm.pages,
1419                         .obj = obj,
1420                 };
1421
1422                 return i915_error_object_create(dev_priv, &fake);
1423         } else {
1424                 return NULL;
1425         }
1426 }
1427
1428 static void gem_record_rings(struct i915_gpu_state *error)
1429 {
1430         struct drm_i915_private *i915 = error->i915;
1431         struct i915_ggtt *ggtt = &i915->ggtt;
1432         int i;
1433
1434         for (i = 0; i < I915_NUM_ENGINES; i++) {
1435                 struct intel_engine_cs *engine = i915->engine[i];
1436                 struct drm_i915_error_engine *ee = &error->engine[i];
1437                 struct i915_request *request;
1438
1439                 ee->engine_id = -1;
1440
1441                 if (!engine)
1442                         continue;
1443
1444                 ee->engine_id = i;
1445
1446                 error_record_engine_registers(error, engine, ee);
1447                 error_record_engine_waiters(engine, ee);
1448                 error_record_engine_execlists(engine, ee);
1449
1450                 request = i915_gem_find_active_request(engine);
1451                 if (request) {
1452                         struct intel_ring *ring;
1453
1454                         ee->vm = request->ctx->ppgtt ?
1455                                 &request->ctx->ppgtt->base : &ggtt->base;
1456
1457                         record_context(&ee->context, request->ctx);
1458
1459                         /* We need to copy these to an anonymous buffer
1460                          * as the simplest method to avoid being overwritten
1461                          * by userspace.
1462                          */
1463                         ee->batchbuffer =
1464                                 i915_error_object_create(i915, request->batch);
1465
1466                         if (HAS_BROKEN_CS_TLB(i915))
1467                                 ee->wa_batchbuffer =
1468                                         i915_error_object_create(i915,
1469                                                                  engine->scratch);
1470                         request_record_user_bo(request, ee);
1471
1472                         ee->ctx =
1473                                 i915_error_object_create(i915,
1474                                                          request->ctx->engine[i].state);
1475
1476                         error->simulated |=
1477                                 i915_gem_context_no_error_capture(request->ctx);
1478
1479                         ee->rq_head = request->head;
1480                         ee->rq_post = request->postfix;
1481                         ee->rq_tail = request->tail;
1482
1483                         ring = request->ring;
1484                         ee->cpu_ring_head = ring->head;
1485                         ee->cpu_ring_tail = ring->tail;
1486                         ee->ringbuffer =
1487                                 i915_error_object_create(i915, ring->vma);
1488
1489                         engine_record_requests(engine, request, ee);
1490                 }
1491
1492                 ee->hws_page =
1493                         i915_error_object_create(i915,
1494                                                  engine->status_page.vma);
1495
1496                 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1497
1498                 ee->default_state = capture_object(i915, engine->default_state);
1499         }
1500 }
1501
1502 static void gem_capture_vm(struct i915_gpu_state *error,
1503                            struct i915_address_space *vm,
1504                            int idx)
1505 {
1506         struct drm_i915_error_buffer *active_bo;
1507         struct i915_vma *vma;
1508         int count;
1509
1510         count = 0;
1511         list_for_each_entry(vma, &vm->active_list, vm_link)
1512                 count++;
1513
1514         active_bo = NULL;
1515         if (count)
1516                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1517         if (active_bo)
1518                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1519         else
1520                 count = 0;
1521
1522         error->active_vm[idx] = vm;
1523         error->active_bo[idx] = active_bo;
1524         error->active_bo_count[idx] = count;
1525 }
1526
1527 static void capture_active_buffers(struct i915_gpu_state *error)
1528 {
1529         int cnt = 0, i, j;
1530
1531         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1532         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1533         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1534
1535         /* Scan each engine looking for unique active contexts/vm */
1536         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1537                 struct drm_i915_error_engine *ee = &error->engine[i];
1538                 bool found;
1539
1540                 if (!ee->vm)
1541                         continue;
1542
1543                 found = false;
1544                 for (j = 0; j < i && !found; j++)
1545                         found = error->engine[j].vm == ee->vm;
1546                 if (!found)
1547                         gem_capture_vm(error, ee->vm, cnt++);
1548         }
1549 }
1550
1551 static void capture_pinned_buffers(struct i915_gpu_state *error)
1552 {
1553         struct i915_address_space *vm = &error->i915->ggtt.base;
1554         struct drm_i915_error_buffer *bo;
1555         struct i915_vma *vma;
1556         int count_inactive, count_active;
1557
1558         count_inactive = 0;
1559         list_for_each_entry(vma, &vm->active_list, vm_link)
1560                 count_inactive++;
1561
1562         count_active = 0;
1563         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1564                 count_active++;
1565
1566         bo = NULL;
1567         if (count_inactive + count_active)
1568                 bo = kcalloc(count_inactive + count_active,
1569                              sizeof(*bo), GFP_ATOMIC);
1570         if (!bo)
1571                 return;
1572
1573         count_inactive = capture_error_bo(bo, count_inactive,
1574                                           &vm->active_list, true);
1575         count_active = capture_error_bo(bo + count_inactive, count_active,
1576                                         &vm->inactive_list, true);
1577         error->pinned_bo_count = count_inactive + count_active;
1578         error->pinned_bo = bo;
1579 }
1580
1581 static void capture_uc_state(struct i915_gpu_state *error)
1582 {
1583         struct drm_i915_private *i915 = error->i915;
1584         struct i915_error_uc *error_uc = &error->uc;
1585
1586         /* Capturing uC state won't be useful if there is no GuC */
1587         if (!error->device_info.has_guc)
1588                 return;
1589
1590         error_uc->guc_fw = i915->guc.fw;
1591         error_uc->huc_fw = i915->huc.fw;
1592
1593         /* Non-default firmware paths will be specified by the modparam.
1594          * As modparams are generally accesible from the userspace make
1595          * explicit copies of the firmware paths.
1596          */
1597         error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1598         error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1599         error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1600 }
1601
1602 /* Capture all registers which don't fit into another category. */
1603 static void capture_reg_state(struct i915_gpu_state *error)
1604 {
1605         struct drm_i915_private *dev_priv = error->i915;
1606         int i;
1607
1608         /* General organization
1609          * 1. Registers specific to a single generation
1610          * 2. Registers which belong to multiple generations
1611          * 3. Feature specific registers.
1612          * 4. Everything else
1613          * Please try to follow the order.
1614          */
1615
1616         /* 1: Registers specific to a single generation */
1617         if (IS_VALLEYVIEW(dev_priv)) {
1618                 error->gtier[0] = I915_READ(GTIER);
1619                 error->ier = I915_READ(VLV_IER);
1620                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1621         }
1622
1623         if (IS_GEN7(dev_priv))
1624                 error->err_int = I915_READ(GEN7_ERR_INT);
1625
1626         if (INTEL_GEN(dev_priv) >= 8) {
1627                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1628                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1629         }
1630
1631         if (IS_GEN6(dev_priv)) {
1632                 error->forcewake = I915_READ_FW(FORCEWAKE);
1633                 error->gab_ctl = I915_READ(GAB_CTL);
1634                 error->gfx_mode = I915_READ(GFX_MODE);
1635         }
1636
1637         /* 2: Registers which belong to multiple generations */
1638         if (INTEL_GEN(dev_priv) >= 7)
1639                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1640
1641         if (INTEL_GEN(dev_priv) >= 6) {
1642                 error->derrmr = I915_READ(DERRMR);
1643                 error->error = I915_READ(ERROR_GEN6);
1644                 error->done_reg = I915_READ(DONE_REG);
1645         }
1646
1647         if (INTEL_GEN(dev_priv) >= 5)
1648                 error->ccid = I915_READ(CCID);
1649
1650         /* 3: Feature specific registers */
1651         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1652                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1653                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1654         }
1655
1656         /* 4: Everything else */
1657         if (INTEL_GEN(dev_priv) >= 8) {
1658                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1659                 for (i = 0; i < 4; i++)
1660                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1661                 error->ngtier = 4;
1662         } else if (HAS_PCH_SPLIT(dev_priv)) {
1663                 error->ier = I915_READ(DEIER);
1664                 error->gtier[0] = I915_READ(GTIER);
1665                 error->ngtier = 1;
1666         } else if (IS_GEN2(dev_priv)) {
1667                 error->ier = I915_READ16(IER);
1668         } else if (!IS_VALLEYVIEW(dev_priv)) {
1669                 error->ier = I915_READ(IER);
1670         }
1671         error->eir = I915_READ(EIR);
1672         error->pgtbl_er = I915_READ(PGTBL_ER);
1673 }
1674
1675 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1676                                    struct i915_gpu_state *error,
1677                                    u32 engine_mask,
1678                                    const char *error_msg)
1679 {
1680         u32 ecode;
1681         int engine_id = -1, len;
1682
1683         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1684
1685         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1686                         "GPU HANG: ecode %d:%d:0x%08x",
1687                         INTEL_GEN(dev_priv), engine_id, ecode);
1688
1689         if (engine_id != -1 && error->engine[engine_id].context.pid)
1690                 len += scnprintf(error->error_msg + len,
1691                                  sizeof(error->error_msg) - len,
1692                                  ", in %s [%d]",
1693                                  error->engine[engine_id].context.comm,
1694                                  error->engine[engine_id].context.pid);
1695
1696         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1697                   ", reason: %s, action: %s",
1698                   error_msg,
1699                   engine_mask ? "reset" : "continue");
1700 }
1701
1702 static void capture_gen_state(struct i915_gpu_state *error)
1703 {
1704         struct drm_i915_private *i915 = error->i915;
1705
1706         error->awake = i915->gt.awake;
1707         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1708         error->suspended = i915->runtime_pm.suspended;
1709
1710         error->iommu = -1;
1711 #ifdef CONFIG_INTEL_IOMMU
1712         error->iommu = intel_iommu_gfx_mapped;
1713 #endif
1714         error->reset_count = i915_reset_count(&i915->gpu_error);
1715         error->suspend_count = i915->suspend_count;
1716
1717         memcpy(&error->device_info,
1718                INTEL_INFO(i915),
1719                sizeof(error->device_info));
1720         error->driver_caps = i915->caps;
1721 }
1722
1723 static __always_inline void dup_param(const char *type, void *x)
1724 {
1725         if (!__builtin_strcmp(type, "char *"))
1726                 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1727 }
1728
1729 static void capture_params(struct i915_gpu_state *error)
1730 {
1731         error->params = i915_modparams;
1732 #define DUP(T, x, ...) dup_param(#T, &error->params.x);
1733         I915_PARAMS_FOR_EACH(DUP);
1734 #undef DUP
1735 }
1736
1737 static int capture(void *data)
1738 {
1739         struct i915_gpu_state *error = data;
1740
1741         error->time = ktime_get_real();
1742         error->boottime = ktime_get_boottime();
1743         error->uptime = ktime_sub(ktime_get(),
1744                                   error->i915->gt.last_init_time);
1745
1746         capture_params(error);
1747         capture_gen_state(error);
1748         capture_uc_state(error);
1749         capture_reg_state(error);
1750         gem_record_fences(error);
1751         gem_record_rings(error);
1752         capture_active_buffers(error);
1753         capture_pinned_buffers(error);
1754
1755         error->overlay = intel_overlay_capture_error_state(error->i915);
1756         error->display = intel_display_capture_error_state(error->i915);
1757
1758         return 0;
1759 }
1760
1761 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1762
1763 struct i915_gpu_state *
1764 i915_capture_gpu_state(struct drm_i915_private *i915)
1765 {
1766         struct i915_gpu_state *error;
1767
1768         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1769         if (!error)
1770                 return NULL;
1771
1772         kref_init(&error->ref);
1773         error->i915 = i915;
1774
1775         stop_machine(capture, error, NULL);
1776
1777         return error;
1778 }
1779
1780 /**
1781  * i915_capture_error_state - capture an error record for later analysis
1782  * @i915: i915 device
1783  * @engine_mask: the mask of engines triggering the hang
1784  * @error_msg: a message to insert into the error capture header
1785  *
1786  * Should be called when an error is detected (either a hang or an error
1787  * interrupt) to capture error state from the time of the error.  Fills
1788  * out a structure which becomes available in debugfs for user level tools
1789  * to pick up.
1790  */
1791 void i915_capture_error_state(struct drm_i915_private *i915,
1792                               u32 engine_mask,
1793                               const char *error_msg)
1794 {
1795         static bool warned;
1796         struct i915_gpu_state *error;
1797         unsigned long flags;
1798
1799         if (!i915_modparams.error_capture)
1800                 return;
1801
1802         if (READ_ONCE(i915->gpu_error.first_error))
1803                 return;
1804
1805         error = i915_capture_gpu_state(i915);
1806         if (!error) {
1807                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1808                 return;
1809         }
1810
1811         i915_error_capture_msg(i915, error, engine_mask, error_msg);
1812         DRM_INFO("%s\n", error->error_msg);
1813
1814         if (!error->simulated) {
1815                 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1816                 if (!i915->gpu_error.first_error) {
1817                         i915->gpu_error.first_error = error;
1818                         error = NULL;
1819                 }
1820                 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1821         }
1822
1823         if (error) {
1824                 __i915_gpu_state_free(&error->ref);
1825                 return;
1826         }
1827
1828         if (!warned &&
1829             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1830                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1831                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1832                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1833                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1834                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1835                          i915->drm.primary->index);
1836                 warned = true;
1837         }
1838 }
1839
1840 struct i915_gpu_state *
1841 i915_first_error_state(struct drm_i915_private *i915)
1842 {
1843         struct i915_gpu_state *error;
1844
1845         spin_lock_irq(&i915->gpu_error.lock);
1846         error = i915->gpu_error.first_error;
1847         if (error)
1848                 i915_gpu_state_get(error);
1849         spin_unlock_irq(&i915->gpu_error.lock);
1850
1851         return error;
1852 }
1853
1854 void i915_reset_error_state(struct drm_i915_private *i915)
1855 {
1856         struct i915_gpu_state *error;
1857
1858         spin_lock_irq(&i915->gpu_error.lock);
1859         error = i915->gpu_error.first_error;
1860         i915->gpu_error.first_error = NULL;
1861         spin_unlock_irq(&i915->gpu_error.lock);
1862
1863         i915_gpu_state_put(error);
1864 }