drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  41 {
  42         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  43         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  44
  45         amdgpu_bo_kunmap(bo);
  46
  47         drm_gem_object_release(&bo->gem_base);
  48         amdgpu_bo_unref(&bo->parent);
  49         if (!list_empty(&bo->shadow_list)) {
  50                 mutex_lock(&adev->shadow_list_lock);
  51                 list_del_init(&bo->shadow_list);
  52                 mutex_unlock(&adev->shadow_list_lock);
  53         }
  54         kfree(bo->metadata);
  55         kfree(bo);
  56 }
  57
  58 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  59 {
  60         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  61                 return true;
  62         return false;
  63 }
  64
  65 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  66 {
  67         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  68         struct ttm_placement *placement = &abo->placement;
  69         struct ttm_place *places = abo->placements;
  70         u64 flags = abo->flags;
  71         u32 c = 0;
  72
  73         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  74                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
  75
  76                 places[c].fpfn = 0;
  77                 places[c].lpfn = 0;
  78                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                         TTM_PL_FLAG_VRAM;
  80
  81                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  82                         places[c].lpfn = visible_pfn;
  83                 else
  84                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
  85
  86                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
  87                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
  88                 c++;
  89         }
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
  92                 places[c].fpfn = 0;
  93                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
  94                         places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT;
  95                 else
  96                         places[c].lpfn = 0;
  97                 places[c].flags = TTM_PL_FLAG_TT;
  98                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
  99                         places[c].flags |= TTM_PL_FLAG_WC |
 100                                 TTM_PL_FLAG_UNCACHED;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_CACHED;
 103                 c++;
 104         }
 105
 106         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 107                 places[c].fpfn = 0;
 108                 places[c].lpfn = 0;
 109                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 110                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 111                         places[c].flags |= TTM_PL_FLAG_WC |
 112                                 TTM_PL_FLAG_UNCACHED;
 113                 else
 114                         places[c].flags |= TTM_PL_FLAG_CACHED;
 115                 c++;
 116         }
 117
 118         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 119                 places[c].fpfn = 0;
 120                 places[c].lpfn = 0;
 121                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 122                 c++;
 123         }
 124
 125         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 126                 places[c].fpfn = 0;
 127                 places[c].lpfn = 0;
 128                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 129                 c++;
 130         }
 131
 132         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 133                 places[c].fpfn = 0;
 134                 places[c].lpfn = 0;
 135                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 136                 c++;
 137         }
 138
 139         if (!c) {
 140                 places[c].fpfn = 0;
 141                 places[c].lpfn = 0;
 142                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 143                 c++;
 144         }
 145
 146         placement->num_placement = c;
 147         placement->placement = places;
 148
 149         placement->num_busy_placement = c;
 150         placement->busy_placement = places;
 151 }
 152
 153 /**
 154  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 155  *
 156  * @adev: amdgpu device object
 157  * @size: size for the new BO
 158  * @align: alignment for the new BO
 159  * @domain: where to place it
 160  * @bo_ptr: resulting BO
 161  * @gpu_addr: GPU addr of the pinned BO
 162  * @cpu_addr: optional CPU address mapping
 163  *
 164  * Allocates and pins a BO for kernel internal use, and returns it still
 165  * reserved.
 166  *
 167  * Returns 0 on success, negative error code otherwise.
 168  */
 169 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 170                               unsigned long size, int align,
 171                               u32 domain, struct amdgpu_bo **bo_ptr,
 172                               u64 *gpu_addr, void **cpu_addr)
 173 {
 174         bool free = false;
 175         int r;
 176
 177         if (!*bo_ptr) {
 178                 r = amdgpu_bo_create(adev, size, align, true, domain,
 179                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 180                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 181                                      NULL, NULL, 0, bo_ptr);
 182                 if (r) {
 183                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 184                                 r);
 185                         return r;
 186                 }
 187                 free = true;
 188         }
 189
 190         r = amdgpu_bo_reserve(*bo_ptr, false);
 191         if (r) {
 192                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 193                 goto error_free;
 194         }
 195
 196         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 197         if (r) {
 198                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 199                 goto error_unreserve;
 200         }
 201
 202         if (cpu_addr) {
 203                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 204                 if (r) {
 205                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 206                         goto error_unreserve;
 207                 }
 208         }
 209
 210         return 0;
 211
 212 error_unreserve:
 213         amdgpu_bo_unreserve(*bo_ptr);
 214
 215 error_free:
 216         if (free)
 217                 amdgpu_bo_unref(bo_ptr);
 218
 219         return r;
 220 }
 221
 222 /**
 223  * amdgpu_bo_create_kernel - create BO for kernel use
 224  *
 225  * @adev: amdgpu device object
 226  * @size: size for the new BO
 227  * @align: alignment for the new BO
 228  * @domain: where to place it
 229  * @bo_ptr: resulting BO
 230  * @gpu_addr: GPU addr of the pinned BO
 231  * @cpu_addr: optional CPU address mapping
 232  *
 233  * Allocates and pins a BO for kernel internal use.
 234  *
 235  * Returns 0 on success, negative error code otherwise.
 236  */
 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 238                             unsigned long size, int align,
 239                             u32 domain, struct amdgpu_bo **bo_ptr,
 240                             u64 *gpu_addr, void **cpu_addr)
 241 {
 242         int r;
 243
 244         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 245                                       gpu_addr, cpu_addr);
 246
 247         if (r)
 248                 return r;
 249
 250         amdgpu_bo_unreserve(*bo_ptr);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * amdgpu_bo_free_kernel - free BO for kernel use
 257  *
 258  * @bo: amdgpu BO to free
 259  *
 260  * unmaps and unpin a BO for kernel internal use.
 261  */
 262 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 263                            void **cpu_addr)
 264 {
 265         if (*bo == NULL)
 266                 return;
 267
 268         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 269                 if (cpu_addr)
 270                         amdgpu_bo_kunmap(*bo);
 271
 272                 amdgpu_bo_unpin(*bo);
 273                 amdgpu_bo_unreserve(*bo);
 274         }
 275         amdgpu_bo_unref(bo);
 276
 277         if (gpu_addr)
 278                 *gpu_addr = 0;
 279
 280         if (cpu_addr)
 281                 *cpu_addr = NULL;
 282 }
 283
 284 /* Validate bo size is bit bigger then the request domain */
 285 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 286                                           unsigned long size, u32 domain)
 287 {
 288         struct ttm_mem_type_manager *man = NULL;
 289
 290         /*
 291          * If GTT is part of requested domains the check must succeed to
 292          * allow fall back to GTT
 293          */
 294         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 295                 man = &adev->mman.bdev.man[TTM_PL_TT];
 296
 297                 if (size < (man->size << PAGE_SHIFT))
 298                         return true;
 299                 else
 300                         goto fail;
 301         }
 302
 303         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 304                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 305
 306                 if (size < (man->size << PAGE_SHIFT))
 307                         return true;
 308                 else
 309                         goto fail;
 310         }
 311
 312
 313         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 314         return true;
 315
 316 fail:
 317         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 318                   man->size << PAGE_SHIFT);
 319         return false;
 320 }
 321
 322 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 323                                unsigned long size, int byte_align,
 324                                bool kernel, u32 domain, u64 flags,
 325                                struct sg_table *sg,
 326                                struct reservation_object *resv,
 327                                uint64_t init_value,
 328                                struct amdgpu_bo **bo_ptr)
 329 {
 330         struct ttm_operation_ctx ctx = { !kernel, false };
 331         struct amdgpu_bo *bo;
 332         enum ttm_bo_type type;
 333         unsigned long page_align;
 334         size_t acc_size;
 335         int r;
 336
 337         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 338         size = ALIGN(size, PAGE_SIZE);
 339
 340         if (!amdgpu_bo_validate_size(adev, size, domain))
 341                 return -ENOMEM;
 342
 343         if (kernel) {
 344                 type = ttm_bo_type_kernel;
 345         } else if (sg) {
 346                 type = ttm_bo_type_sg;
 347         } else {
 348                 type = ttm_bo_type_device;
 349         }
 350         *bo_ptr = NULL;
 351
 352         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 353                                        sizeof(struct amdgpu_bo));
 354
 355         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 356         if (bo == NULL)
 357                 return -ENOMEM;
 358         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 359         if (unlikely(r)) {
 360                 kfree(bo);
 361                 return r;
 362         }
 363         INIT_LIST_HEAD(&bo->shadow_list);
 364         INIT_LIST_HEAD(&bo->va);
 365         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 366                                          AMDGPU_GEM_DOMAIN_GTT |
 367                                          AMDGPU_GEM_DOMAIN_CPU |
 368                                          AMDGPU_GEM_DOMAIN_GDS |
 369                                          AMDGPU_GEM_DOMAIN_GWS |
 370                                          AMDGPU_GEM_DOMAIN_OA);
 371         bo->allowed_domains = bo->preferred_domains;
 372         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 373                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 374
 375         bo->flags = flags;
 376
 377 #ifdef CONFIG_X86_32
 378         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 379          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 380          */
 381         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 382 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 383         /* Don't try to enable write-combining when it can't work, or things
 384          * may be slow
 385          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 386          */
 387
 388 #ifndef CONFIG_COMPILE_TEST
 389 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 390          thanks to write-combining
 391 #endif
 392
 393         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 394                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 395                               "better performance thanks to write-combining\n");
 396         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 397 #else
 398         /* For architectures that don't support WC memory,
 399          * mask out the WC flag from the BO
 400          */
 401         if (!drm_arch_can_wc_memory())
 402                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 403 #endif
 404
 405         bo->tbo.bdev = &adev->mman.bdev;
 406         amdgpu_ttm_placement_from_domain(bo, domain);
 407
 408         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 409                                  &bo->placement, page_align, &ctx, NULL,
 410                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 411         if (unlikely(r != 0))
 412                 return r;
 413
 414         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 415             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 416             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 417                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 418                                              ctx.bytes_moved);
 419         else
 420                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 421
 422         if (kernel)
 423                 bo->tbo.priority = 1;
 424
 425         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 426             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 427                 struct dma_fence *fence;
 428
 429                 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence);
 430                 if (unlikely(r))
 431                         goto fail_unreserve;
 432
 433                 amdgpu_bo_fence(bo, fence, false);
 434                 dma_fence_put(bo->tbo.moving);
 435                 bo->tbo.moving = dma_fence_get(fence);
 436                 dma_fence_put(fence);
 437         }
 438         if (!resv)
 439                 amdgpu_bo_unreserve(bo);
 440         *bo_ptr = bo;
 441
 442         trace_amdgpu_bo_create(bo);
 443
 444         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 445         if (type == ttm_bo_type_device)
 446                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 447
 448         return 0;
 449
 450 fail_unreserve:
 451         if (!resv)
 452                 ww_mutex_unlock(&bo->tbo.resv->lock);
 453         amdgpu_bo_unref(&bo);
 454         return r;
 455 }
 456
 457 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 458                                    unsigned long size, int byte_align,
 459                                    struct amdgpu_bo *bo)
 460 {
 461         int r;
 462
 463         if (bo->shadow)
 464                 return 0;
 465
 466         r = amdgpu_bo_do_create(adev, size, byte_align, true,
 467                                 AMDGPU_GEM_DOMAIN_GTT,
 468                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 469                                 AMDGPU_GEM_CREATE_SHADOW,
 470                                 NULL, bo->tbo.resv, 0,
 471                                 &bo->shadow);
 472         if (!r) {
 473                 bo->shadow->parent = amdgpu_bo_ref(bo);
 474                 mutex_lock(&adev->shadow_list_lock);
 475                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 476                 mutex_unlock(&adev->shadow_list_lock);
 477         }
 478
 479         return r;
 480 }
 481
 482 /* init_value will only take effect when flags contains
 483  * AMDGPU_GEM_CREATE_VRAM_CLEARED.
 484  */
 485 int amdgpu_bo_create(struct amdgpu_device *adev,
 486                      unsigned long size, int byte_align,
 487                      bool kernel, u32 domain, u64 flags,
 488                      struct sg_table *sg,
 489                      struct reservation_object *resv,
 490                      uint64_t init_value,
 491                      struct amdgpu_bo **bo_ptr)
 492 {
 493         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 494         int r;
 495
 496         r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
 497                                 parent_flags, sg, resv, init_value, bo_ptr);
 498         if (r)
 499                 return r;
 500
 501         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 502                 if (!resv)
 503                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 504                                                         NULL));
 505
 506                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 507
 508                 if (!resv)
 509                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 510
 511                 if (r)
 512                         amdgpu_bo_unref(bo_ptr);
 513         }
 514
 515         return r;
 516 }
 517
 518 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 519                                struct amdgpu_ring *ring,
 520                                struct amdgpu_bo *bo,
 521                                struct reservation_object *resv,
 522                                struct dma_fence **fence,
 523                                bool direct)
 524
 525 {
 526         struct amdgpu_bo *shadow = bo->shadow;
 527         uint64_t bo_addr, shadow_addr;
 528         int r;
 529
 530         if (!shadow)
 531                 return -EINVAL;
 532
 533         bo_addr = amdgpu_bo_gpu_offset(bo);
 534         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 535
 536         r = reservation_object_reserve_shared(bo->tbo.resv);
 537         if (r)
 538                 goto err;
 539
 540         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 541                                amdgpu_bo_size(bo), resv, fence,
 542                                direct, false);
 543         if (!r)
 544                 amdgpu_bo_fence(bo, *fence, true);
 545
 546 err:
 547         return r;
 548 }
 549
 550 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 551 {
 552         struct ttm_operation_ctx ctx = { false, false };
 553         uint32_t domain;
 554         int r;
 555
 556         if (bo->pin_count)
 557                 return 0;
 558
 559         domain = bo->preferred_domains;
 560
 561 retry:
 562         amdgpu_ttm_placement_from_domain(bo, domain);
 563         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 564         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 565                 domain = bo->allowed_domains;
 566                 goto retry;
 567         }
 568
 569         return r;
 570 }
 571
 572 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 573                                   struct amdgpu_ring *ring,
 574                                   struct amdgpu_bo *bo,
 575                                   struct reservation_object *resv,
 576                                   struct dma_fence **fence,
 577                                   bool direct)
 578
 579 {
 580         struct amdgpu_bo *shadow = bo->shadow;
 581         uint64_t bo_addr, shadow_addr;
 582         int r;
 583
 584         if (!shadow)
 585                 return -EINVAL;
 586
 587         bo_addr = amdgpu_bo_gpu_offset(bo);
 588         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 589
 590         r = reservation_object_reserve_shared(bo->tbo.resv);
 591         if (r)
 592                 goto err;
 593
 594         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 595                                amdgpu_bo_size(bo), resv, fence,
 596                                direct, false);
 597         if (!r)
 598                 amdgpu_bo_fence(bo, *fence, true);
 599
 600 err:
 601         return r;
 602 }
 603
 604 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 605 {
 606         void *kptr;
 607         long r;
 608
 609         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 610                 return -EPERM;
 611
 612         kptr = amdgpu_bo_kptr(bo);
 613         if (kptr) {
 614                 if (ptr)
 615                         *ptr = kptr;
 616                 return 0;
 617         }
 618
 619         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 620                                                 MAX_SCHEDULE_TIMEOUT);
 621         if (r < 0)
 622                 return r;
 623
 624         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 625         if (r)
 626                 return r;
 627
 628         if (ptr)
 629                 *ptr = amdgpu_bo_kptr(bo);
 630
 631         return 0;
 632 }
 633
 634 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 635 {
 636         bool is_iomem;
 637
 638         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 639 }
 640
 641 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 642 {
 643         if (bo->kmap.bo)
 644                 ttm_bo_kunmap(&bo->kmap);
 645 }
 646
 647 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 648 {
 649         if (bo == NULL)
 650                 return NULL;
 651
 652         ttm_bo_reference(&bo->tbo);
 653         return bo;
 654 }
 655
 656 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 657 {
 658         struct ttm_buffer_object *tbo;
 659
 660         if ((*bo) == NULL)
 661                 return;
 662
 663         tbo = &((*bo)->tbo);
 664         ttm_bo_unref(&tbo);
 665         if (tbo == NULL)
 666                 *bo = NULL;
 667 }
 668
 669 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 670                              u64 min_offset, u64 max_offset,
 671                              u64 *gpu_addr)
 672 {
 673         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 674         struct ttm_operation_ctx ctx = { false, false };
 675         int r, i;
 676
 677         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 678                 return -EPERM;
 679
 680         if (WARN_ON_ONCE(min_offset > max_offset))
 681                 return -EINVAL;
 682
 683         /* A shared bo cannot be migrated to VRAM */
 684         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 685                 return -EINVAL;
 686
 687         if (bo->pin_count) {
 688                 uint32_t mem_type = bo->tbo.mem.mem_type;
 689
 690                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 691                         return -EINVAL;
 692
 693                 bo->pin_count++;
 694                 if (gpu_addr)
 695                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 696
 697                 if (max_offset != 0) {
 698                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 699                         WARN_ON_ONCE(max_offset <
 700                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 701                 }
 702
 703                 return 0;
 704         }
 705
 706         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 707         /* force to pin into visible video ram */
 708         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 709                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 710         amdgpu_ttm_placement_from_domain(bo, domain);
 711         for (i = 0; i < bo->placement.num_placement; i++) {
 712                 unsigned fpfn, lpfn;
 713
 714                 fpfn = min_offset >> PAGE_SHIFT;
 715                 lpfn = max_offset >> PAGE_SHIFT;
 716
 717                 if (fpfn > bo->placements[i].fpfn)
 718                         bo->placements[i].fpfn = fpfn;
 719                 if (!bo->placements[i].lpfn ||
 720                     (lpfn && lpfn < bo->placements[i].lpfn))
 721                         bo->placements[i].lpfn = lpfn;
 722                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 723         }
 724
 725         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 726         if (unlikely(r)) {
 727                 dev_err(adev->dev, "%p pin failed\n", bo);
 728                 goto error;
 729         }
 730
 731         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 732         if (unlikely(r)) {
 733                 dev_err(adev->dev, "%p bind failed\n", bo);
 734                 goto error;
 735         }
 736
 737         bo->pin_count = 1;
 738         if (gpu_addr != NULL)
 739                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 740
 741         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 742         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 743                 adev->vram_pin_size += amdgpu_bo_size(bo);
 744                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 745                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 746         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 747                 adev->gart_pin_size += amdgpu_bo_size(bo);
 748         }
 749
 750 error:
 751         return r;
 752 }
 753
 754 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 755 {
 756         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 757 }
 758
 759 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 760 {
 761         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 762         struct ttm_operation_ctx ctx = { false, false };
 763         int r, i;
 764
 765         if (!bo->pin_count) {
 766                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 767                 return 0;
 768         }
 769         bo->pin_count--;
 770         if (bo->pin_count)
 771                 return 0;
 772         for (i = 0; i < bo->placement.num_placement; i++) {
 773                 bo->placements[i].lpfn = 0;
 774                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 775         }
 776         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 777         if (unlikely(r)) {
 778                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 779                 goto error;
 780         }
 781
 782         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 783                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 784                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 785                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 786         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 787                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 788         }
 789
 790 error:
 791         return r;
 792 }
 793
 794 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 795 {
 796         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 797         if (0 && (adev->flags & AMD_IS_APU)) {
 798                 /* Useless to evict on IGP chips */
 799                 return 0;
 800         }
 801         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 802 }
 803
 804 static const char *amdgpu_vram_names[] = {
 805         "UNKNOWN",
 806         "GDDR1",
 807         "DDR2",
 808         "GDDR3",
 809         "GDDR4",
 810         "GDDR5",
 811         "HBM",
 812         "DDR3"
 813 };
 814
 815 int amdgpu_bo_init(struct amdgpu_device *adev)
 816 {
 817         /* reserve PAT memory space to WC for VRAM */
 818         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 819                                    adev->mc.aper_size);
 820
 821         /* Add an MTRR for the VRAM */
 822         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 823                                               adev->mc.aper_size);
 824         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 825                  adev->mc.mc_vram_size >> 20,
 826                  (unsigned long long)adev->mc.aper_size >> 20);
 827         DRM_INFO("RAM width %dbits %s\n",
 828                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 829         return amdgpu_ttm_init(adev);
 830 }
 831
 832 void amdgpu_bo_fini(struct amdgpu_device *adev)
 833 {
 834         amdgpu_ttm_fini(adev);
 835         arch_phys_wc_del(adev->mc.vram_mtrr);
 836         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 837 }
 838
 839 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 840                              struct vm_area_struct *vma)
 841 {
 842         return ttm_fbdev_mmap(vma, &bo->tbo);
 843 }
 844
 845 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 846 {
 847         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 848
 849         if (adev->family <= AMDGPU_FAMILY_CZ &&
 850             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 851                 return -EINVAL;
 852
 853         bo->tiling_flags = tiling_flags;
 854         return 0;
 855 }
 856
 857 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 858 {
 859         lockdep_assert_held(&bo->tbo.resv->lock.base);
 860
 861         if (tiling_flags)
 862                 *tiling_flags = bo->tiling_flags;
 863 }
 864
 865 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 866                             uint32_t metadata_size, uint64_t flags)
 867 {
 868         void *buffer;
 869
 870         if (!metadata_size) {
 871                 if (bo->metadata_size) {
 872                         kfree(bo->metadata);
 873                         bo->metadata = NULL;
 874                         bo->metadata_size = 0;
 875                 }
 876                 return 0;
 877         }
 878
 879         if (metadata == NULL)
 880                 return -EINVAL;
 881
 882         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 883         if (buffer == NULL)
 884                 return -ENOMEM;
 885
 886         kfree(bo->metadata);
 887         bo->metadata_flags = flags;
 888         bo->metadata = buffer;
 889         bo->metadata_size = metadata_size;
 890
 891         return 0;
 892 }
 893
 894 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 895                            size_t buffer_size, uint32_t *metadata_size,
 896                            uint64_t *flags)
 897 {
 898         if (!buffer && !metadata_size)
 899                 return -EINVAL;
 900
 901         if (buffer) {
 902                 if (buffer_size < bo->metadata_size)
 903                         return -EINVAL;
 904
 905                 if (bo->metadata_size)
 906                         memcpy(buffer, bo->metadata, bo->metadata_size);
 907         }
 908
 909         if (metadata_size)
 910                 *metadata_size = bo->metadata_size;
 911         if (flags)
 912                 *flags = bo->metadata_flags;
 913
 914         return 0;
 915 }
 916
 917 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 918                            bool evict,
 919                            struct ttm_mem_reg *new_mem)
 920 {
 921         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 922         struct amdgpu_bo *abo;
 923         struct ttm_mem_reg *old_mem = &bo->mem;
 924
 925         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 926                 return;
 927
 928         abo = ttm_to_amdgpu_bo(bo);
 929         amdgpu_vm_bo_invalidate(adev, abo, evict);
 930
 931         amdgpu_bo_kunmap(abo);
 932
 933         /* remember the eviction */
 934         if (evict)
 935                 atomic64_inc(&adev->num_evictions);
 936
 937         /* update statistics */
 938         if (!new_mem)
 939                 return;
 940
 941         /* move_notify is called before move happens */
 942         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 943 }
 944
 945 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 946 {
 947         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 948         struct ttm_operation_ctx ctx = { false, false };
 949         struct amdgpu_bo *abo;
 950         unsigned long offset, size;
 951         int r;
 952
 953         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 954                 return 0;
 955
 956         abo = ttm_to_amdgpu_bo(bo);
 957
 958         /* Remember that this BO was accessed by the CPU */
 959         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 960
 961         if (bo->mem.mem_type != TTM_PL_VRAM)
 962                 return 0;
 963
 964         size = bo->mem.num_pages << PAGE_SHIFT;
 965         offset = bo->mem.start << PAGE_SHIFT;
 966         if ((offset + size) <= adev->mc.visible_vram_size)
 967                 return 0;
 968
 969         /* Can't move a pinned BO to visible VRAM */
 970         if (abo->pin_count > 0)
 971                 return -EINVAL;
 972
 973         /* hurrah the memory is not visible ! */
 974         atomic64_inc(&adev->num_vram_cpu_page_faults);
 975         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 976                                          AMDGPU_GEM_DOMAIN_GTT);
 977
 978         /* Avoid costly evictions; only set GTT as a busy placement */
 979         abo->placement.num_busy_placement = 1;
 980         abo->placement.busy_placement = &abo->placements[1];
 981
 982         r = ttm_bo_validate(bo, &abo->placement, &ctx);
 983         if (unlikely(r != 0))
 984                 return r;
 985
 986         offset = bo->mem.start << PAGE_SHIFT;
 987         /* this should never happen */
 988         if (bo->mem.mem_type == TTM_PL_VRAM &&
 989             (offset + size) > adev->mc.visible_vram_size)
 990                 return -EINVAL;
 991
 992         return 0;
 993 }
 994
 995 /**
 996  * amdgpu_bo_fence - add fence to buffer object
 997  *
 998  * @bo: buffer object in question
 999  * @fence: fence to add
1000  * @shared: true if fence should be added shared
1001  *
1002  */
1003 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1004                      bool shared)
1005 {
1006         struct reservation_object *resv = bo->tbo.resv;
1007
1008         if (shared)
1009                 reservation_object_add_shared_fence(resv, fence);
1010         else
1011                 reservation_object_add_excl_fence(resv, fence);
1012 }
1013
1014 /**
1015  * amdgpu_bo_gpu_offset - return GPU offset of bo
1016  * @bo: amdgpu object for which we query the offset
1017  *
1018  * Returns current GPU offset of the object.
1019  *
1020  * Note: object should either be pinned or reserved when calling this
1021  * function, it might be useful to add check for this for debugging.
1022  */
1023 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1024 {
1025         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1026         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1027                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1028         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1029                      !bo->pin_count);
1030         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1031         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1032                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1033
1034         return bo->tbo.offset;
1035 }