drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44 #include <linux/module.h>
  45
  46 #include <drm/drm_drv.h>
  47 #include <drm/ttm/ttm_bo.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_range_manager.h>
  50 #include <drm/ttm/ttm_tt.h>
  51
  52 #include <drm/amdgpu_drm.h>
  53 #include <drm/drm_drv.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_hmm.h"
  62 #include "amdgpu_atomfirmware.h"
  63 #include "amdgpu_res_cursor.h"
  64 #include "bif/bif_4_1_d.h"
  65
  66 MODULE_IMPORT_NS(DMA_BUF);
  67
  68 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  69
  70 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  71                                    struct ttm_tt *ttm,
  72                                    struct ttm_resource *bo_mem);
  73 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  74                                       struct ttm_tt *ttm);
  75
  76 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  77                                     unsigned int type,
  78                                     uint64_t size_in_page)
  79 {
  80         return ttm_range_man_init(&adev->mman.bdev, type,
  81                                   false, size_in_page);
  82 }
  83
  84 /**
  85  * amdgpu_evict_flags - Compute placement flags
  86  *
  87  * @bo: The buffer object to evict
  88  * @placement: Possible destination(s) for evicted BO
  89  *
  90  * Fill in placement data when ttm_bo_evict() is called
  91  */
  92 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  93                                 struct ttm_placement *placement)
  94 {
  95         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  96         struct amdgpu_bo *abo;
  97         static const struct ttm_place placements = {
  98                 .fpfn = 0,
  99                 .lpfn = 0,
 100                 .mem_type = TTM_PL_SYSTEM,
 101                 .flags = 0
 102         };
 103
 104         /* Don't handle scatter gather BOs */
 105         if (bo->type == ttm_bo_type_sg) {
 106                 placement->num_placement = 0;
 107                 placement->num_busy_placement = 0;
 108                 return;
 109         }
 110
 111         /* Object isn't an AMDGPU object so ignore */
 112         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 113                 placement->placement = &placements;
 114                 placement->busy_placement = &placements;
 115                 placement->num_placement = 1;
 116                 placement->num_busy_placement = 1;
 117                 return;
 118         }
 119
 120         abo = ttm_to_amdgpu_bo(bo);
 121         if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
 122                 placement->num_placement = 0;
 123                 placement->num_busy_placement = 0;
 124                 return;
 125         }
 126
 127         switch (bo->resource->mem_type) {
 128         case AMDGPU_PL_GDS:
 129         case AMDGPU_PL_GWS:
 130         case AMDGPU_PL_OA:
 131                 placement->num_placement = 0;
 132                 placement->num_busy_placement = 0;
 133                 return;
 134
 135         case TTM_PL_VRAM:
 136                 if (!adev->mman.buffer_funcs_enabled) {
 137                         /* Move to system memory */
 138                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 139                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 140                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 141                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 142
 143                         /* Try evicting to the CPU inaccessible part of VRAM
 144                          * first, but only set GTT as busy placement, so this
 145                          * BO will be evicted to GTT rather than causing other
 146                          * BOs to be evicted from VRAM
 147                          */
 148                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 149                                                         AMDGPU_GEM_DOMAIN_GTT |
 150                                                         AMDGPU_GEM_DOMAIN_CPU);
 151                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 152                         abo->placements[0].lpfn = 0;
 153                         abo->placement.busy_placement = &abo->placements[1];
 154                         abo->placement.num_busy_placement = 1;
 155                 } else {
 156                         /* Move to GTT memory */
 157                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
 158                                                         AMDGPU_GEM_DOMAIN_CPU);
 159                 }
 160                 break;
 161         case TTM_PL_TT:
 162         case AMDGPU_PL_PREEMPT:
 163         default:
 164                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 165                 break;
 166         }
 167         *placement = abo->placement;
 168 }
 169
 170 /**
 171  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 172  * @bo: buffer object to map
 173  * @mem: memory object to map
 174  * @mm_cur: range to map
 175  * @window: which GART window to use
 176  * @ring: DMA ring to use for the copy
 177  * @tmz: if we should setup a TMZ enabled mapping
 178  * @size: in number of bytes to map, out number of bytes mapped
 179  * @addr: resulting address inside the MC address space
 180  *
 181  * Setup one of the GART windows to access a specific piece of memory or return
 182  * the physical address for local memory.
 183  */
 184 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 185                                  struct ttm_resource *mem,
 186                                  struct amdgpu_res_cursor *mm_cur,
 187                                  unsigned window, struct amdgpu_ring *ring,
 188                                  bool tmz, uint64_t *size, uint64_t *addr)
 189 {
 190         struct amdgpu_device *adev = ring->adev;
 191         unsigned offset, num_pages, num_dw, num_bytes;
 192         uint64_t src_addr, dst_addr;
 193         struct amdgpu_job *job;
 194         void *cpu_addr;
 195         uint64_t flags;
 196         unsigned int i;
 197         int r;
 198
 199         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 200                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 201
 202         if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
 203                 return -EINVAL;
 204
 205         /* Map only what can't be accessed directly */
 206         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 207                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 208                         mm_cur->start;
 209                 return 0;
 210         }
 211
 212
 213         /*
 214          * If start begins at an offset inside the page, then adjust the size
 215          * and addr accordingly
 216          */
 217         offset = mm_cur->start & ~PAGE_MASK;
 218
 219         num_pages = PFN_UP(*size + offset);
 220         num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
 221
 222         *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
 223
 224         *addr = adev->gmc.gart_start;
 225         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 226                 AMDGPU_GPU_PAGE_SIZE;
 227         *addr += offset;
 228
 229         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 230         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 231
 232         r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
 233                                      AMDGPU_FENCE_OWNER_UNDEFINED,
 234                                      num_dw * 4 + num_bytes,
 235                                      AMDGPU_IB_POOL_DELAYED, &job);
 236         if (r)
 237                 return r;
 238
 239         src_addr = num_dw * 4;
 240         src_addr += job->ibs[0].gpu_addr;
 241
 242         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 243         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 244         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 245                                 dst_addr, num_bytes, false);
 246
 247         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 248         WARN_ON(job->ibs[0].length_dw > num_dw);
 249
 250         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 251         if (tmz)
 252                 flags |= AMDGPU_PTE_TMZ;
 253
 254         cpu_addr = &job->ibs[0].ptr[num_dw];
 255
 256         if (mem->mem_type == TTM_PL_TT) {
 257                 dma_addr_t *dma_addr;
 258
 259                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 260                 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
 261         } else {
 262                 dma_addr_t dma_address;
 263
 264                 dma_address = mm_cur->start;
 265                 dma_address += adev->vm_manager.vram_base_offset;
 266
 267                 for (i = 0; i < num_pages; ++i) {
 268                         amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
 269                                         flags, cpu_addr);
 270                         dma_address += PAGE_SIZE;
 271                 }
 272         }
 273
 274         dma_fence_put(amdgpu_job_submit(job));
 275         return 0;
 276 }
 277
 278 /**
 279  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 280  * @adev: amdgpu device
 281  * @src: buffer/address where to read from
 282  * @dst: buffer/address where to write to
 283  * @size: number of bytes to copy
 284  * @tmz: if a secure copy should be used
 285  * @resv: resv object to sync to
 286  * @f: Returns the last fence if multiple jobs are submitted.
 287  *
 288  * The function copies @size bytes from {src->mem + src->offset} to
 289  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 290  * move and different for a BO to BO copy.
 291  *
 292  */
 293 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 294                                const struct amdgpu_copy_mem *src,
 295                                const struct amdgpu_copy_mem *dst,
 296                                uint64_t size, bool tmz,
 297                                struct dma_resv *resv,
 298                                struct dma_fence **f)
 299 {
 300         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 301         struct amdgpu_res_cursor src_mm, dst_mm;
 302         struct dma_fence *fence = NULL;
 303         int r = 0;
 304
 305         if (!adev->mman.buffer_funcs_enabled) {
 306                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 307                 return -EINVAL;
 308         }
 309
 310         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 311         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 312
 313         mutex_lock(&adev->mman.gtt_window_lock);
 314         while (src_mm.remaining) {
 315                 uint64_t from, to, cur_size;
 316                 struct dma_fence *next;
 317
 318                 /* Never copy more than 256MiB at once to avoid a timeout */
 319                 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
 320
 321                 /* Map src to window 0 and dst to window 1. */
 322                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 323                                           0, ring, tmz, &cur_size, &from);
 324                 if (r)
 325                         goto error;
 326
 327                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 328                                           1, ring, tmz, &cur_size, &to);
 329                 if (r)
 330                         goto error;
 331
 332                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 333                                        resv, &next, false, true, tmz);
 334                 if (r)
 335                         goto error;
 336
 337                 dma_fence_put(fence);
 338                 fence = next;
 339
 340                 amdgpu_res_next(&src_mm, cur_size);
 341                 amdgpu_res_next(&dst_mm, cur_size);
 342         }
 343 error:
 344         mutex_unlock(&adev->mman.gtt_window_lock);
 345         if (f)
 346                 *f = dma_fence_get(fence);
 347         dma_fence_put(fence);
 348         return r;
 349 }
 350
 351 /*
 352  * amdgpu_move_blit - Copy an entire buffer to another buffer
 353  *
 354  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 355  * help move buffers to and from VRAM.
 356  */
 357 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 358                             bool evict,
 359                             struct ttm_resource *new_mem,
 360                             struct ttm_resource *old_mem)
 361 {
 362         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 363         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 364         struct amdgpu_copy_mem src, dst;
 365         struct dma_fence *fence = NULL;
 366         int r;
 367
 368         src.bo = bo;
 369         dst.bo = bo;
 370         src.mem = old_mem;
 371         dst.mem = new_mem;
 372         src.offset = 0;
 373         dst.offset = 0;
 374
 375         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 376                                        new_mem->size,
 377                                        amdgpu_bo_encrypted(abo),
 378                                        bo->base.resv, &fence);
 379         if (r)
 380                 goto error;
 381
 382         /* clear the space being freed */
 383         if (old_mem->mem_type == TTM_PL_VRAM &&
 384             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 385                 struct dma_fence *wipe_fence = NULL;
 386
 387                 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
 388                 if (r) {
 389                         goto error;
 390                 } else if (wipe_fence) {
 391                         dma_fence_put(fence);
 392                         fence = wipe_fence;
 393                 }
 394         }
 395
 396         /* Always block for VM page tables before committing the new location */
 397         if (bo->type == ttm_bo_type_kernel)
 398                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 399         else
 400                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 401         dma_fence_put(fence);
 402         return r;
 403
 404 error:
 405         if (fence)
 406                 dma_fence_wait(fence, false);
 407         dma_fence_put(fence);
 408         return r;
 409 }
 410
 411 /*
 412  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 413  *
 414  * Called by amdgpu_bo_move()
 415  */
 416 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 417                                struct ttm_resource *mem)
 418 {
 419         u64 mem_size = (u64)mem->size;
 420         struct amdgpu_res_cursor cursor;
 421         u64 end;
 422
 423         if (mem->mem_type == TTM_PL_SYSTEM ||
 424             mem->mem_type == TTM_PL_TT)
 425                 return true;
 426         if (mem->mem_type != TTM_PL_VRAM)
 427                 return false;
 428
 429         amdgpu_res_first(mem, 0, mem_size, &cursor);
 430         end = cursor.start + cursor.size;
 431         while (cursor.remaining) {
 432                 amdgpu_res_next(&cursor, cursor.size);
 433
 434                 if (!cursor.remaining)
 435                         break;
 436
 437                 /* ttm_resource_ioremap only supports contiguous memory */
 438                 if (end != cursor.start)
 439                         return false;
 440
 441                 end = cursor.start + cursor.size;
 442         }
 443
 444         return end <= adev->gmc.visible_vram_size;
 445 }
 446
 447 /*
 448  * amdgpu_bo_move - Move a buffer object to a new memory location
 449  *
 450  * Called by ttm_bo_handle_move_mem()
 451  */
 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 453                           struct ttm_operation_ctx *ctx,
 454                           struct ttm_resource *new_mem,
 455                           struct ttm_place *hop)
 456 {
 457         struct amdgpu_device *adev;
 458         struct amdgpu_bo *abo;
 459         struct ttm_resource *old_mem = bo->resource;
 460         int r;
 461
 462         if (new_mem->mem_type == TTM_PL_TT ||
 463             new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 464                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 465                 if (r)
 466                         return r;
 467         }
 468
 469         abo = ttm_to_amdgpu_bo(bo);
 470         adev = amdgpu_ttm_adev(bo->bdev);
 471
 472         if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 473                          bo->ttm == NULL)) {
 474                 ttm_bo_move_null(bo, new_mem);
 475                 goto out;
 476         }
 477         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 478             (new_mem->mem_type == TTM_PL_TT ||
 479              new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 480                 ttm_bo_move_null(bo, new_mem);
 481                 goto out;
 482         }
 483         if ((old_mem->mem_type == TTM_PL_TT ||
 484              old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 485             new_mem->mem_type == TTM_PL_SYSTEM) {
 486                 r = ttm_bo_wait_ctx(bo, ctx);
 487                 if (r)
 488                         return r;
 489
 490                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 491                 ttm_resource_free(bo, &bo->resource);
 492                 ttm_bo_assign_mem(bo, new_mem);
 493                 goto out;
 494         }
 495
 496         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 497             old_mem->mem_type == AMDGPU_PL_GWS ||
 498             old_mem->mem_type == AMDGPU_PL_OA ||
 499             new_mem->mem_type == AMDGPU_PL_GDS ||
 500             new_mem->mem_type == AMDGPU_PL_GWS ||
 501             new_mem->mem_type == AMDGPU_PL_OA) {
 502                 /* Nothing to save here */
 503                 ttm_bo_move_null(bo, new_mem);
 504                 goto out;
 505         }
 506
 507         if (bo->type == ttm_bo_type_device &&
 508             new_mem->mem_type == TTM_PL_VRAM &&
 509             old_mem->mem_type != TTM_PL_VRAM) {
 510                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 511                  * accesses the BO after it's moved.
 512                  */
 513                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 514         }
 515
 516         if (adev->mman.buffer_funcs_enabled) {
 517                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 518                       new_mem->mem_type == TTM_PL_VRAM) ||
 519                      (old_mem->mem_type == TTM_PL_VRAM &&
 520                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 521                         hop->fpfn = 0;
 522                         hop->lpfn = 0;
 523                         hop->mem_type = TTM_PL_TT;
 524                         hop->flags = TTM_PL_FLAG_TEMPORARY;
 525                         return -EMULTIHOP;
 526                 }
 527
 528                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 529         } else {
 530                 r = -ENODEV;
 531         }
 532
 533         if (r) {
 534                 /* Check that all memory is CPU accessible */
 535                 if (!amdgpu_mem_visible(adev, old_mem) ||
 536                     !amdgpu_mem_visible(adev, new_mem)) {
 537                         pr_err("Move buffer fallback to memcpy unavailable\n");
 538                         return r;
 539                 }
 540
 541                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 542                 if (r)
 543                         return r;
 544         }
 545
 546 out:
 547         /* update statistics */
 548         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 549         amdgpu_bo_move_notify(bo, evict, new_mem);
 550         return 0;
 551 }
 552
 553 /*
 554  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 555  *
 556  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 557  */
 558 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 559                                      struct ttm_resource *mem)
 560 {
 561         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 562         size_t bus_size = (size_t)mem->size;
 563
 564         switch (mem->mem_type) {
 565         case TTM_PL_SYSTEM:
 566                 /* system memory */
 567                 return 0;
 568         case TTM_PL_TT:
 569         case AMDGPU_PL_PREEMPT:
 570                 break;
 571         case TTM_PL_VRAM:
 572                 mem->bus.offset = mem->start << PAGE_SHIFT;
 573                 /* check if it's visible */
 574                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 575                         return -EINVAL;
 576
 577                 if (adev->mman.aper_base_kaddr &&
 578                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 579                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 580                                         mem->bus.offset;
 581
 582                 mem->bus.offset += adev->gmc.aper_base;
 583                 mem->bus.is_iomem = true;
 584                 break;
 585         default:
 586                 return -EINVAL;
 587         }
 588         return 0;
 589 }
 590
 591 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 592                                            unsigned long page_offset)
 593 {
 594         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 595         struct amdgpu_res_cursor cursor;
 596
 597         amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 598                          &cursor);
 599         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 600 }
 601
 602 /**
 603  * amdgpu_ttm_domain_start - Returns GPU start address
 604  * @adev: amdgpu device object
 605  * @type: type of the memory
 606  *
 607  * Returns:
 608  * GPU start address of a memory domain
 609  */
 610
 611 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 612 {
 613         switch (type) {
 614         case TTM_PL_TT:
 615                 return adev->gmc.gart_start;
 616         case TTM_PL_VRAM:
 617                 return adev->gmc.vram_start;
 618         }
 619
 620         return 0;
 621 }
 622
 623 /*
 624  * TTM backend functions.
 625  */
 626 struct amdgpu_ttm_tt {
 627         struct ttm_tt   ttm;
 628         struct drm_gem_object   *gobj;
 629         u64                     offset;
 630         uint64_t                userptr;
 631         struct task_struct      *usertask;
 632         uint32_t                userflags;
 633         bool                    bound;
 634         int32_t                 pool_id;
 635 };
 636
 637 #define ttm_to_amdgpu_ttm_tt(ptr)       container_of(ptr, struct amdgpu_ttm_tt, ttm)
 638
 639 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 640 /*
 641  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 642  * memory and start HMM tracking CPU page table update
 643  *
 644  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 645  * once afterwards to stop HMM tracking
 646  */
 647 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
 648                                  struct hmm_range **range)
 649 {
 650         struct ttm_tt *ttm = bo->tbo.ttm;
 651         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 652         unsigned long start = gtt->userptr;
 653         struct vm_area_struct *vma;
 654         struct mm_struct *mm;
 655         bool readonly;
 656         int r = 0;
 657
 658         /* Make sure get_user_pages_done() can cleanup gracefully */
 659         *range = NULL;
 660
 661         mm = bo->notifier.mm;
 662         if (unlikely(!mm)) {
 663                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 664                 return -EFAULT;
 665         }
 666
 667         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 668                 return -ESRCH;
 669
 670         mmap_read_lock(mm);
 671         vma = vma_lookup(mm, start);
 672         if (unlikely(!vma)) {
 673                 r = -EFAULT;
 674                 goto out_unlock;
 675         }
 676         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 677                 vma->vm_file)) {
 678                 r = -EPERM;
 679                 goto out_unlock;
 680         }
 681
 682         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 683         r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
 684                                        readonly, NULL, pages, range);
 685 out_unlock:
 686         mmap_read_unlock(mm);
 687         if (r)
 688                 pr_debug("failed %d to get user pages 0x%lx\n", r, start);
 689
 690         mmput(mm);
 691
 692         return r;
 693 }
 694
 695 /* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
 696  */
 697 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
 698                                       struct hmm_range *range)
 699 {
 700         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 701
 702         if (gtt && gtt->userptr && range)
 703                 amdgpu_hmm_range_get_pages_done(range);
 704 }
 705
 706 /*
 707  * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
 708  * Check if the pages backing this ttm range have been invalidated
 709  *
 710  * Returns: true if pages are still valid
 711  */
 712 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 713                                        struct hmm_range *range)
 714 {
 715         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 716
 717         if (!gtt || !gtt->userptr || !range)
 718                 return false;
 719
 720         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 721                 gtt->userptr, ttm->num_pages);
 722
 723         WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
 724
 725         return !amdgpu_hmm_range_get_pages_done(range);
 726 }
 727 #endif
 728
 729 /*
 730  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 731  *
 732  * Called by amdgpu_cs_list_validate(). This creates the page list
 733  * that backs user memory and will ultimately be mapped into the device
 734  * address space.
 735  */
 736 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 737 {
 738         unsigned long i;
 739
 740         for (i = 0; i < ttm->num_pages; ++i)
 741                 ttm->pages[i] = pages ? pages[i] : NULL;
 742 }
 743
 744 /*
 745  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 746  *
 747  * Called by amdgpu_ttm_backend_bind()
 748  **/
 749 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 750                                      struct ttm_tt *ttm)
 751 {
 752         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 753         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 754         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 755         enum dma_data_direction direction = write ?
 756                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 757         int r;
 758
 759         /* Allocate an SG array and squash pages into it */
 760         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 761                                       (u64)ttm->num_pages << PAGE_SHIFT,
 762                                       GFP_KERNEL);
 763         if (r)
 764                 goto release_sg;
 765
 766         /* Map SG to device */
 767         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 768         if (r)
 769                 goto release_sg;
 770
 771         /* convert SG to linear array of pages and dma addresses */
 772         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 773                                        ttm->num_pages);
 774
 775         return 0;
 776
 777 release_sg:
 778         kfree(ttm->sg);
 779         ttm->sg = NULL;
 780         return r;
 781 }
 782
 783 /*
 784  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 785  */
 786 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 787                                         struct ttm_tt *ttm)
 788 {
 789         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 790         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 791         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 792         enum dma_data_direction direction = write ?
 793                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 794
 795         /* double check that we don't free the table twice */
 796         if (!ttm->sg || !ttm->sg->sgl)
 797                 return;
 798
 799         /* unmap the pages mapped to the device */
 800         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 801         sg_free_table(ttm->sg);
 802 }
 803
 804 /*
 805  * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ...
 806  * MQDn+CtrlStackn where n is the number of XCCs per partition.
 807  * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD
 808  * and uses memory type default, UC. The rest of pages_per_xcc are
 809  * Ctrl stack and modify their memory type to NC.
 810  */
 811 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
 812                                 struct ttm_tt *ttm, uint64_t flags)
 813 {
 814         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 815         uint64_t total_pages = ttm->num_pages;
 816         int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
 817         uint64_t page_idx, pages_per_xcc = total_pages / num_xcc;
 818         int i;
 819         uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
 820                         AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 821
 822         for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
 823                 /* MQD page: use default flags */
 824                 amdgpu_gart_bind(adev,
 825                                 gtt->offset + (page_idx << PAGE_SHIFT),
 826                                 1, &gtt->ttm.dma_address[page_idx], flags);
 827                 /*
 828                  * Ctrl pages - modify the memory type to NC (ctrl_flags) from
 829                  * the second page of the BO onward.
 830                  */
 831                 amdgpu_gart_bind(adev,
 832                                 gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
 833                                 pages_per_xcc - 1,
 834                                 &gtt->ttm.dma_address[page_idx + 1],
 835                                 ctrl_flags);
 836         }
 837 }
 838
 839 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 840                                  struct ttm_buffer_object *tbo,
 841                                  uint64_t flags)
 842 {
 843         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 844         struct ttm_tt *ttm = tbo->ttm;
 845         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 846
 847         if (amdgpu_bo_encrypted(abo))
 848                 flags |= AMDGPU_PTE_TMZ;
 849
 850         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 851                 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
 852         } else {
 853                 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 854                                  gtt->ttm.dma_address, flags);
 855         }
 856 }
 857
 858 /*
 859  * amdgpu_ttm_backend_bind - Bind GTT memory
 860  *
 861  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 862  * This handles binding GTT memory to the device address space.
 863  */
 864 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 865                                    struct ttm_tt *ttm,
 866                                    struct ttm_resource *bo_mem)
 867 {
 868         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 869         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 870         uint64_t flags;
 871         int r;
 872
 873         if (!bo_mem)
 874                 return -EINVAL;
 875
 876         if (gtt->bound)
 877                 return 0;
 878
 879         if (gtt->userptr) {
 880                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 881                 if (r) {
 882                         DRM_ERROR("failed to pin userptr\n");
 883                         return r;
 884                 }
 885         } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
 886                 if (!ttm->sg) {
 887                         struct dma_buf_attachment *attach;
 888                         struct sg_table *sgt;
 889
 890                         attach = gtt->gobj->import_attach;
 891                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 892                         if (IS_ERR(sgt))
 893                                 return PTR_ERR(sgt);
 894
 895                         ttm->sg = sgt;
 896                 }
 897
 898                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 899                                                ttm->num_pages);
 900         }
 901
 902         if (!ttm->num_pages) {
 903                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 904                      ttm->num_pages, bo_mem, ttm);
 905         }
 906
 907         if (bo_mem->mem_type != TTM_PL_TT ||
 908             !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 909                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 910                 return 0;
 911         }
 912
 913         /* compute PTE flags relevant to this BO memory */
 914         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 915
 916         /* bind pages into GART page tables */
 917         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 918         amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 919                          gtt->ttm.dma_address, flags);
 920         gtt->bound = true;
 921         return 0;
 922 }
 923
 924 /*
 925  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 926  * through AGP or GART aperture.
 927  *
 928  * If bo is accessible through AGP aperture, then use AGP aperture
 929  * to access bo; otherwise allocate logical space in GART aperture
 930  * and map bo to GART aperture.
 931  */
 932 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 933 {
 934         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 935         struct ttm_operation_ctx ctx = { false, false };
 936         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
 937         struct ttm_placement placement;
 938         struct ttm_place placements;
 939         struct ttm_resource *tmp;
 940         uint64_t addr, flags;
 941         int r;
 942
 943         if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 944                 return 0;
 945
 946         addr = amdgpu_gmc_agp_addr(bo);
 947         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 948                 bo->resource->start = addr >> PAGE_SHIFT;
 949                 return 0;
 950         }
 951
 952         /* allocate GART space */
 953         placement.num_placement = 1;
 954         placement.placement = &placements;
 955         placement.num_busy_placement = 1;
 956         placement.busy_placement = &placements;
 957         placements.fpfn = 0;
 958         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 959         placements.mem_type = TTM_PL_TT;
 960         placements.flags = bo->resource->placement;
 961
 962         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 963         if (unlikely(r))
 964                 return r;
 965
 966         /* compute PTE flags for this buffer object */
 967         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 968
 969         /* Bind pages */
 970         gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 971         amdgpu_ttm_gart_bind(adev, bo, flags);
 972         amdgpu_gart_invalidate_tlb(adev);
 973         ttm_resource_free(bo, &bo->resource);
 974         ttm_bo_assign_mem(bo, tmp);
 975
 976         return 0;
 977 }
 978
 979 /*
 980  * amdgpu_ttm_recover_gart - Rebind GTT pages
 981  *
 982  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
 983  * rebind GTT pages during a GPU reset.
 984  */
 985 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 986 {
 987         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 988         uint64_t flags;
 989
 990         if (!tbo->ttm)
 991                 return;
 992
 993         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
 994         amdgpu_ttm_gart_bind(adev, tbo, flags);
 995 }
 996
 997 /*
 998  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
 999  *
1000  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1001  * ttm_tt_destroy().
1002  */
1003 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1004                                       struct ttm_tt *ttm)
1005 {
1006         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1007         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1008
1009         /* if the pages have userptr pinning then clear that first */
1010         if (gtt->userptr) {
1011                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1012         } else if (ttm->sg && gtt->gobj->import_attach) {
1013                 struct dma_buf_attachment *attach;
1014
1015                 attach = gtt->gobj->import_attach;
1016                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1017                 ttm->sg = NULL;
1018         }
1019
1020         if (!gtt->bound)
1021                 return;
1022
1023         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1024                 return;
1025
1026         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1027         amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1028         gtt->bound = false;
1029 }
1030
1031 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1032                                        struct ttm_tt *ttm)
1033 {
1034         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1035
1036         if (gtt->usertask)
1037                 put_task_struct(gtt->usertask);
1038
1039         ttm_tt_fini(&gtt->ttm);
1040         kfree(gtt);
1041 }
1042
1043 /**
1044  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1045  *
1046  * @bo: The buffer object to create a GTT ttm_tt object around
1047  * @page_flags: Page flags to be added to the ttm_tt object
1048  *
1049  * Called by ttm_tt_create().
1050  */
1051 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1052                                            uint32_t page_flags)
1053 {
1054         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1055         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1056         struct amdgpu_ttm_tt *gtt;
1057         enum ttm_caching caching;
1058
1059         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1060         if (gtt == NULL) {
1061                 return NULL;
1062         }
1063         gtt->gobj = &bo->base;
1064         if (adev->gmc.mem_partitions && abo->xcp_id >= 0)
1065                 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
1066         else
1067                 gtt->pool_id = abo->xcp_id;
1068
1069         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1070                 caching = ttm_write_combined;
1071         else
1072                 caching = ttm_cached;
1073
1074         /* allocate space for the uninitialized page entries */
1075         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1076                 kfree(gtt);
1077                 return NULL;
1078         }
1079         return &gtt->ttm;
1080 }
1081
1082 /*
1083  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1084  *
1085  * Map the pages of a ttm_tt object to an address space visible
1086  * to the underlying device.
1087  */
1088 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1089                                   struct ttm_tt *ttm,
1090                                   struct ttm_operation_ctx *ctx)
1091 {
1092         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1093         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1094         struct ttm_pool *pool;
1095         pgoff_t i;
1096         int ret;
1097
1098         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1099         if (gtt->userptr) {
1100                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1101                 if (!ttm->sg)
1102                         return -ENOMEM;
1103                 return 0;
1104         }
1105
1106         if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1107                 return 0;
1108
1109         if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1110                 pool = &adev->mman.ttm_pools[gtt->pool_id];
1111         else
1112                 pool = &adev->mman.bdev.pool;
1113         ret = ttm_pool_alloc(pool, ttm, ctx);
1114         if (ret)
1115                 return ret;
1116
1117         for (i = 0; i < ttm->num_pages; ++i)
1118                 ttm->pages[i]->mapping = bdev->dev_mapping;
1119
1120         return 0;
1121 }
1122
1123 /*
1124  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1125  *
1126  * Unmaps pages of a ttm_tt object from the device address space and
1127  * unpopulates the page array backing it.
1128  */
1129 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1130                                      struct ttm_tt *ttm)
1131 {
1132         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1133         struct amdgpu_device *adev;
1134         struct ttm_pool *pool;
1135         pgoff_t i;
1136
1137         amdgpu_ttm_backend_unbind(bdev, ttm);
1138
1139         if (gtt->userptr) {
1140                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1141                 kfree(ttm->sg);
1142                 ttm->sg = NULL;
1143                 return;
1144         }
1145
1146         if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1147                 return;
1148
1149         for (i = 0; i < ttm->num_pages; ++i)
1150                 ttm->pages[i]->mapping = NULL;
1151
1152         adev = amdgpu_ttm_adev(bdev);
1153
1154         if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1155                 pool = &adev->mman.ttm_pools[gtt->pool_id];
1156         else
1157                 pool = &adev->mman.bdev.pool;
1158
1159         return ttm_pool_free(pool, ttm);
1160 }
1161
1162 /**
1163  * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1164  * task
1165  *
1166  * @tbo: The ttm_buffer_object that contains the userptr
1167  * @user_addr:  The returned value
1168  */
1169 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1170                               uint64_t *user_addr)
1171 {
1172         struct amdgpu_ttm_tt *gtt;
1173
1174         if (!tbo->ttm)
1175                 return -EINVAL;
1176
1177         gtt = (void *)tbo->ttm;
1178         *user_addr = gtt->userptr;
1179         return 0;
1180 }
1181
1182 /**
1183  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1184  * task
1185  *
1186  * @bo: The ttm_buffer_object to bind this userptr to
1187  * @addr:  The address in the current tasks VM space to use
1188  * @flags: Requirements of userptr object.
1189  *
1190  * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1191  * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1192  * initialize GPU VM for a KFD process.
1193  */
1194 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1195                               uint64_t addr, uint32_t flags)
1196 {
1197         struct amdgpu_ttm_tt *gtt;
1198
1199         if (!bo->ttm) {
1200                 /* TODO: We want a separate TTM object type for userptrs */
1201                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1202                 if (bo->ttm == NULL)
1203                         return -ENOMEM;
1204         }
1205
1206         /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1207         bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1208
1209         gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1210         gtt->userptr = addr;
1211         gtt->userflags = flags;
1212
1213         if (gtt->usertask)
1214                 put_task_struct(gtt->usertask);
1215         gtt->usertask = current->group_leader;
1216         get_task_struct(gtt->usertask);
1217
1218         return 0;
1219 }
1220
1221 /*
1222  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1223  */
1224 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1225 {
1226         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1227
1228         if (gtt == NULL)
1229                 return NULL;
1230
1231         if (gtt->usertask == NULL)
1232                 return NULL;
1233
1234         return gtt->usertask->mm;
1235 }
1236
1237 /*
1238  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1239  * address range for the current task.
1240  *
1241  */
1242 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1243                                   unsigned long end, unsigned long *userptr)
1244 {
1245         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1246         unsigned long size;
1247
1248         if (gtt == NULL || !gtt->userptr)
1249                 return false;
1250
1251         /* Return false if no part of the ttm_tt object lies within
1252          * the range
1253          */
1254         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1255         if (gtt->userptr > end || gtt->userptr + size <= start)
1256                 return false;
1257
1258         if (userptr)
1259                 *userptr = gtt->userptr;
1260         return true;
1261 }
1262
1263 /*
1264  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1265  */
1266 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1267 {
1268         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1269
1270         if (gtt == NULL || !gtt->userptr)
1271                 return false;
1272
1273         return true;
1274 }
1275
1276 /*
1277  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1278  */
1279 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1280 {
1281         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1282
1283         if (gtt == NULL)
1284                 return false;
1285
1286         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1287 }
1288
1289 /**
1290  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1291  *
1292  * @ttm: The ttm_tt object to compute the flags for
1293  * @mem: The memory registry backing this ttm_tt object
1294  *
1295  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1296  */
1297 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1298 {
1299         uint64_t flags = 0;
1300
1301         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1302                 flags |= AMDGPU_PTE_VALID;
1303
1304         if (mem && (mem->mem_type == TTM_PL_TT ||
1305                     mem->mem_type == AMDGPU_PL_PREEMPT)) {
1306                 flags |= AMDGPU_PTE_SYSTEM;
1307
1308                 if (ttm->caching == ttm_cached)
1309                         flags |= AMDGPU_PTE_SNOOPED;
1310         }
1311
1312         if (mem && mem->mem_type == TTM_PL_VRAM &&
1313                         mem->bus.caching == ttm_cached)
1314                 flags |= AMDGPU_PTE_SNOOPED;
1315
1316         return flags;
1317 }
1318
1319 /**
1320  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1321  *
1322  * @adev: amdgpu_device pointer
1323  * @ttm: The ttm_tt object to compute the flags for
1324  * @mem: The memory registry backing this ttm_tt object
1325  *
1326  * Figure out the flags to use for a VM PTE (Page Table Entry).
1327  */
1328 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1329                                  struct ttm_resource *mem)
1330 {
1331         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1332
1333         flags |= adev->gart.gart_pte_flags;
1334         flags |= AMDGPU_PTE_READABLE;
1335
1336         if (!amdgpu_ttm_tt_is_readonly(ttm))
1337                 flags |= AMDGPU_PTE_WRITEABLE;
1338
1339         return flags;
1340 }
1341
1342 /*
1343  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1344  * object.
1345  *
1346  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1347  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1348  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1349  * used to clean out a memory space.
1350  */
1351 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1352                                             const struct ttm_place *place)
1353 {
1354         struct dma_resv_iter resv_cursor;
1355         struct dma_fence *f;
1356
1357         if (!amdgpu_bo_is_amdgpu_bo(bo))
1358                 return ttm_bo_eviction_valuable(bo, place);
1359
1360         /* Swapout? */
1361         if (bo->resource->mem_type == TTM_PL_SYSTEM)
1362                 return true;
1363
1364         if (bo->type == ttm_bo_type_kernel &&
1365             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1366                 return false;
1367
1368         /* If bo is a KFD BO, check if the bo belongs to the current process.
1369          * If true, then return false as any KFD process needs all its BOs to
1370          * be resident to run successfully
1371          */
1372         dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1373                                 DMA_RESV_USAGE_BOOKKEEP, f) {
1374                 if (amdkfd_fence_check_mm(f, current->mm))
1375                         return false;
1376         }
1377
1378         /* Preemptible BOs don't own system resources managed by the
1379          * driver (pages, VRAM, GART space). They point to resources
1380          * owned by someone else (e.g. pageable memory in user mode
1381          * or a DMABuf). They are used in a preemptible context so we
1382          * can guarantee no deadlocks and good QoS in case of MMU
1383          * notifiers or DMABuf move notifiers from the resource owner.
1384          */
1385         if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1386                 return false;
1387
1388         if (bo->resource->mem_type == TTM_PL_TT &&
1389             amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1390                 return false;
1391
1392         return ttm_bo_eviction_valuable(bo, place);
1393 }
1394
1395 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1396                                       void *buf, size_t size, bool write)
1397 {
1398         while (size) {
1399                 uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1400                 uint64_t bytes = 4 - (pos & 0x3);
1401                 uint32_t shift = (pos & 0x3) * 8;
1402                 uint32_t mask = 0xffffffff << shift;
1403                 uint32_t value = 0;
1404
1405                 if (size < bytes) {
1406                         mask &= 0xffffffff >> (bytes - size) * 8;
1407                         bytes = size;
1408                 }
1409
1410                 if (mask != 0xffffffff) {
1411                         amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1412                         if (write) {
1413                                 value &= ~mask;
1414                                 value |= (*(uint32_t *)buf << shift) & mask;
1415                                 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1416                         } else {
1417                                 value = (value & mask) >> shift;
1418                                 memcpy(buf, &value, bytes);
1419                         }
1420                 } else {
1421                         amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1422                 }
1423
1424                 pos += bytes;
1425                 buf += bytes;
1426                 size -= bytes;
1427         }
1428 }
1429
1430 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1431                                         unsigned long offset, void *buf,
1432                                         int len, int write)
1433 {
1434         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1435         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1436         struct amdgpu_res_cursor src_mm;
1437         struct amdgpu_job *job;
1438         struct dma_fence *fence;
1439         uint64_t src_addr, dst_addr;
1440         unsigned int num_dw;
1441         int r, idx;
1442
1443         if (len != PAGE_SIZE)
1444                 return -EINVAL;
1445
1446         if (!adev->mman.sdma_access_ptr)
1447                 return -EACCES;
1448
1449         if (!drm_dev_enter(adev_to_drm(adev), &idx))
1450                 return -ENODEV;
1451
1452         if (write)
1453                 memcpy(adev->mman.sdma_access_ptr, buf, len);
1454
1455         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1456         r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
1457                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1458                                      num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1459                                      &job);
1460         if (r)
1461                 goto out;
1462
1463         amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1464         src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1465                 src_mm.start;
1466         dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1467         if (write)
1468                 swap(src_addr, dst_addr);
1469
1470         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1471                                 PAGE_SIZE, false);
1472
1473         amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1474         WARN_ON(job->ibs[0].length_dw > num_dw);
1475
1476         fence = amdgpu_job_submit(job);
1477
1478         if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1479                 r = -ETIMEDOUT;
1480         dma_fence_put(fence);
1481
1482         if (!(r || write))
1483                 memcpy(buf, adev->mman.sdma_access_ptr, len);
1484 out:
1485         drm_dev_exit(idx);
1486         return r;
1487 }
1488
1489 /**
1490  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1491  *
1492  * @bo:  The buffer object to read/write
1493  * @offset:  Offset into buffer object
1494  * @buf:  Secondary buffer to write/read from
1495  * @len: Length in bytes of access
1496  * @write:  true if writing
1497  *
1498  * This is used to access VRAM that backs a buffer object via MMIO
1499  * access for debugging purposes.
1500  */
1501 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1502                                     unsigned long offset, void *buf, int len,
1503                                     int write)
1504 {
1505         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1506         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1507         struct amdgpu_res_cursor cursor;
1508         int ret = 0;
1509
1510         if (bo->resource->mem_type != TTM_PL_VRAM)
1511                 return -EIO;
1512
1513         if (amdgpu_device_has_timeouts_enabled(adev) &&
1514                         !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1515                 return len;
1516
1517         amdgpu_res_first(bo->resource, offset, len, &cursor);
1518         while (cursor.remaining) {
1519                 size_t count, size = cursor.size;
1520                 loff_t pos = cursor.start;
1521
1522                 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1523                 size -= count;
1524                 if (size) {
1525                         /* using MM to access rest vram and handle un-aligned address */
1526                         pos += count;
1527                         buf += count;
1528                         amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1529                 }
1530
1531                 ret += cursor.size;
1532                 buf += cursor.size;
1533                 amdgpu_res_next(&cursor, cursor.size);
1534         }
1535
1536         return ret;
1537 }
1538
1539 static void
1540 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1541 {
1542         amdgpu_bo_move_notify(bo, false, NULL);
1543 }
1544
1545 static struct ttm_device_funcs amdgpu_bo_driver = {
1546         .ttm_tt_create = &amdgpu_ttm_tt_create,
1547         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1548         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1549         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1550         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1551         .evict_flags = &amdgpu_evict_flags,
1552         .move = &amdgpu_bo_move,
1553         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1554         .release_notify = &amdgpu_bo_release_notify,
1555         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1556         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1557         .access_memory = &amdgpu_ttm_access_memory,
1558 };
1559
1560 /*
1561  * Firmware Reservation functions
1562  */
1563 /**
1564  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1565  *
1566  * @adev: amdgpu_device pointer
1567  *
1568  * free fw reserved vram if it has been reserved.
1569  */
1570 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1571 {
1572         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1573                 NULL, &adev->mman.fw_vram_usage_va);
1574 }
1575
1576 /*
1577  * Driver Reservation functions
1578  */
1579 /**
1580  * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1581  *
1582  * @adev: amdgpu_device pointer
1583  *
1584  * free drv reserved vram if it has been reserved.
1585  */
1586 static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1587 {
1588         amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1589                                                   NULL,
1590                                                   &adev->mman.drv_vram_usage_va);
1591 }
1592
1593 /**
1594  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1595  *
1596  * @adev: amdgpu_device pointer
1597  *
1598  * create bo vram reservation from fw.
1599  */
1600 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1601 {
1602         uint64_t vram_size = adev->gmc.visible_vram_size;
1603
1604         adev->mman.fw_vram_usage_va = NULL;
1605         adev->mman.fw_vram_usage_reserved_bo = NULL;
1606
1607         if (adev->mman.fw_vram_usage_size == 0 ||
1608             adev->mman.fw_vram_usage_size > vram_size)
1609                 return 0;
1610
1611         return amdgpu_bo_create_kernel_at(adev,
1612                                           adev->mman.fw_vram_usage_start_offset,
1613                                           adev->mman.fw_vram_usage_size,
1614                                           &adev->mman.fw_vram_usage_reserved_bo,
1615                                           &adev->mman.fw_vram_usage_va);
1616 }
1617
1618 /**
1619  * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1620  *
1621  * @adev: amdgpu_device pointer
1622  *
1623  * create bo vram reservation from drv.
1624  */
1625 static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1626 {
1627         u64 vram_size = adev->gmc.visible_vram_size;
1628
1629         adev->mman.drv_vram_usage_va = NULL;
1630         adev->mman.drv_vram_usage_reserved_bo = NULL;
1631
1632         if (adev->mman.drv_vram_usage_size == 0 ||
1633             adev->mman.drv_vram_usage_size > vram_size)
1634                 return 0;
1635
1636         return amdgpu_bo_create_kernel_at(adev,
1637                                           adev->mman.drv_vram_usage_start_offset,
1638                                           adev->mman.drv_vram_usage_size,
1639                                           &adev->mman.drv_vram_usage_reserved_bo,
1640                                           &adev->mman.drv_vram_usage_va);
1641 }
1642
1643 /*
1644  * Memoy training reservation functions
1645  */
1646
1647 /**
1648  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1649  *
1650  * @adev: amdgpu_device pointer
1651  *
1652  * free memory training reserved vram if it has been reserved.
1653  */
1654 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1655 {
1656         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1657
1658         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1659         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1660         ctx->c2p_bo = NULL;
1661
1662         return 0;
1663 }
1664
1665 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev,
1666                                                 uint32_t reserve_size)
1667 {
1668         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1669
1670         memset(ctx, 0, sizeof(*ctx));
1671
1672         ctx->c2p_train_data_offset =
1673                 ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M);
1674         ctx->p2c_train_data_offset =
1675                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1676         ctx->train_data_size =
1677                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1678
1679         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1680                         ctx->train_data_size,
1681                         ctx->p2c_train_data_offset,
1682                         ctx->c2p_train_data_offset);
1683 }
1684
1685 /*
1686  * reserve TMR memory at the top of VRAM which holds
1687  * IP Discovery data and is protected by PSP.
1688  */
1689 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1690 {
1691         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1692         bool mem_train_support = false;
1693         uint32_t reserve_size = 0;
1694         int ret;
1695
1696         if (!amdgpu_sriov_vf(adev)) {
1697                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1698                         mem_train_support = true;
1699                 else
1700                         DRM_DEBUG("memory training does not support!\n");
1701         }
1702
1703         /*
1704          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1705          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1706          *
1707          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1708          * discovery data and G6 memory training data respectively
1709          */
1710         if (adev->bios)
1711                 reserve_size =
1712                         amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1713         if (!reserve_size)
1714                 reserve_size = DISCOVERY_TMR_OFFSET;
1715
1716         if (mem_train_support) {
1717                 /* reserve vram for mem train according to TMR location */
1718                 amdgpu_ttm_training_data_block_init(adev, reserve_size);
1719                 ret = amdgpu_bo_create_kernel_at(adev,
1720                                                  ctx->c2p_train_data_offset,
1721                                                  ctx->train_data_size,
1722                                                  &ctx->c2p_bo,
1723                                                  NULL);
1724                 if (ret) {
1725                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1726                         amdgpu_ttm_training_reserve_vram_fini(adev);
1727                         return ret;
1728                 }
1729                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1730         }
1731
1732         if (!adev->gmc.is_app_apu) {
1733                 ret = amdgpu_bo_create_kernel_at(
1734                         adev, adev->gmc.real_vram_size - reserve_size,
1735                         reserve_size, &adev->mman.fw_reserved_memory, NULL);
1736                 if (ret) {
1737                         DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1738                         amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory,
1739                                               NULL, NULL);
1740                         return ret;
1741                 }
1742         } else {
1743                 DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n");
1744         }
1745
1746         return 0;
1747 }
1748
1749 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
1750 {
1751         int i;
1752
1753         if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
1754                 return 0;
1755
1756         adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
1757                                        sizeof(*adev->mman.ttm_pools),
1758                                        GFP_KERNEL);
1759         if (!adev->mman.ttm_pools)
1760                 return -ENOMEM;
1761
1762         for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
1763                 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
1764                               adev->gmc.mem_partitions[i].numa.node,
1765                               false, false);
1766         }
1767         return 0;
1768 }
1769
1770 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
1771 {
1772         int i;
1773
1774         if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
1775                 return;
1776
1777         for (i = 0; i < adev->gmc.num_mem_partitions; i++)
1778                 ttm_pool_fini(&adev->mman.ttm_pools[i]);
1779
1780         kfree(adev->mman.ttm_pools);
1781         adev->mman.ttm_pools = NULL;
1782 }
1783
1784 /*
1785  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1786  * gtt/vram related fields.
1787  *
1788  * This initializes all of the memory space pools that the TTM layer
1789  * will need such as the GTT space (system memory mapped to the device),
1790  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1791  * can be mapped per VMID.
1792  */
1793 int amdgpu_ttm_init(struct amdgpu_device *adev)
1794 {
1795         uint64_t gtt_size;
1796         int r;
1797
1798         mutex_init(&adev->mman.gtt_window_lock);
1799
1800         /* No others user of address space so set it to 0 */
1801         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1802                                adev_to_drm(adev)->anon_inode->i_mapping,
1803                                adev_to_drm(adev)->vma_offset_manager,
1804                                adev->need_swiotlb,
1805                                dma_addressing_limited(adev->dev));
1806         if (r) {
1807                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1808                 return r;
1809         }
1810
1811         r = amdgpu_ttm_pools_init(adev);
1812         if (r) {
1813                 DRM_ERROR("failed to init ttm pools(%d).\n", r);
1814                 return r;
1815         }
1816         adev->mman.initialized = true;
1817
1818         /* Initialize VRAM pool with all of VRAM divided into pages */
1819         r = amdgpu_vram_mgr_init(adev);
1820         if (r) {
1821                 DRM_ERROR("Failed initializing VRAM heap.\n");
1822                 return r;
1823         }
1824
1825         /* Change the size here instead of the init above so only lpfn is affected */
1826         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1827 #ifdef CONFIG_64BIT
1828 #ifdef CONFIG_X86
1829         if (adev->gmc.xgmi.connected_to_cpu)
1830                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1831                                 adev->gmc.visible_vram_size);
1832
1833         else if (adev->gmc.is_app_apu)
1834                 DRM_DEBUG_DRIVER(
1835                         "No need to ioremap when real vram size is 0\n");
1836         else
1837 #endif
1838                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1839                                 adev->gmc.visible_vram_size);
1840 #endif
1841
1842         /*
1843          *The reserved vram for firmware must be pinned to the specified
1844          *place on the VRAM, so reserve it early.
1845          */
1846         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1847         if (r) {
1848                 return r;
1849         }
1850
1851         /*
1852          *The reserved vram for driver must be pinned to the specified
1853          *place on the VRAM, so reserve it early.
1854          */
1855         r = amdgpu_ttm_drv_reserve_vram_init(adev);
1856         if (r)
1857                 return r;
1858
1859         /*
1860          * only NAVI10 and onwards ASIC support for IP discovery.
1861          * If IP discovery enabled, a block of memory should be
1862          * reserved for IP discovey.
1863          */
1864         if (adev->mman.discovery_bin) {
1865                 r = amdgpu_ttm_reserve_tmr(adev);
1866                 if (r)
1867                         return r;
1868         }
1869
1870         /* allocate memory as required for VGA
1871          * This is used for VGA emulation and pre-OS scanout buffers to
1872          * avoid display artifacts while transitioning between pre-OS
1873          * and driver.  */
1874         if (!adev->gmc.is_app_apu) {
1875                 r = amdgpu_bo_create_kernel_at(adev, 0,
1876                                                adev->mman.stolen_vga_size,
1877                                                &adev->mman.stolen_vga_memory,
1878                                                NULL);
1879                 if (r)
1880                         return r;
1881
1882                 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1883                                                adev->mman.stolen_extended_size,
1884                                                &adev->mman.stolen_extended_memory,
1885                                                NULL);
1886
1887                 if (r)
1888                         return r;
1889
1890                 r = amdgpu_bo_create_kernel_at(adev,
1891                                                adev->mman.stolen_reserved_offset,
1892                                                adev->mman.stolen_reserved_size,
1893                                                &adev->mman.stolen_reserved_memory,
1894                                                NULL);
1895                 if (r)
1896                         return r;
1897         } else {
1898                 DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");
1899         }
1900
1901         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1902                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1903
1904         /* Compute GTT size, either based on TTM limit
1905          * or whatever the user passed on module init.
1906          */
1907         if (amdgpu_gtt_size == -1)
1908                 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT;
1909         else
1910                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1911
1912         /* Initialize GTT memory pool */
1913         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1914         if (r) {
1915                 DRM_ERROR("Failed initializing GTT heap.\n");
1916                 return r;
1917         }
1918         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1919                  (unsigned)(gtt_size / (1024 * 1024)));
1920
1921         /* Initialize preemptible memory pool */
1922         r = amdgpu_preempt_mgr_init(adev);
1923         if (r) {
1924                 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1925                 return r;
1926         }
1927
1928         /* Initialize various on-chip memory pools */
1929         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1930         if (r) {
1931                 DRM_ERROR("Failed initializing GDS heap.\n");
1932                 return r;
1933         }
1934
1935         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1936         if (r) {
1937                 DRM_ERROR("Failed initializing gws heap.\n");
1938                 return r;
1939         }
1940
1941         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1942         if (r) {
1943                 DRM_ERROR("Failed initializing oa heap.\n");
1944                 return r;
1945         }
1946         if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1947                                 AMDGPU_GEM_DOMAIN_GTT,
1948                                 &adev->mman.sdma_access_bo, NULL,
1949                                 &adev->mman.sdma_access_ptr))
1950                 DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1951
1952         return 0;
1953 }
1954
1955 /*
1956  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1957  */
1958 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1959 {
1960         int idx;
1961         if (!adev->mman.initialized)
1962                 return;
1963
1964         amdgpu_ttm_pools_fini(adev);
1965
1966         amdgpu_ttm_training_reserve_vram_fini(adev);
1967         /* return the stolen vga memory back to VRAM */
1968         if (!adev->gmc.is_app_apu) {
1969                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1970                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1971                 /* return the FW reserved memory back to VRAM */
1972                 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
1973                                       NULL);
1974                 if (adev->mman.stolen_reserved_size)
1975                         amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1976                                               NULL, NULL);
1977         }
1978         amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1979                                         &adev->mman.sdma_access_ptr);
1980         amdgpu_ttm_fw_reserve_vram_fini(adev);
1981         amdgpu_ttm_drv_reserve_vram_fini(adev);
1982
1983         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1984
1985                 if (adev->mman.aper_base_kaddr)
1986                         iounmap(adev->mman.aper_base_kaddr);
1987                 adev->mman.aper_base_kaddr = NULL;
1988
1989                 drm_dev_exit(idx);
1990         }
1991
1992         amdgpu_vram_mgr_fini(adev);
1993         amdgpu_gtt_mgr_fini(adev);
1994         amdgpu_preempt_mgr_fini(adev);
1995         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1996         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1997         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1998         ttm_device_fini(&adev->mman.bdev);
1999         adev->mman.initialized = false;
2000         DRM_INFO("amdgpu: ttm finalized\n");
2001 }
2002
2003 /**
2004  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2005  *
2006  * @adev: amdgpu_device pointer
2007  * @enable: true when we can use buffer functions.
2008  *
2009  * Enable/disable use of buffer functions during suspend/resume. This should
2010  * only be called at bootup or when userspace isn't running.
2011  */
2012 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2013 {
2014         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2015         uint64_t size;
2016         int r;
2017
2018         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2019             adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
2020                 return;
2021
2022         if (enable) {
2023                 struct amdgpu_ring *ring;
2024                 struct drm_gpu_scheduler *sched;
2025
2026                 ring = adev->mman.buffer_funcs_ring;
2027                 sched = &ring->sched;
2028                 r = drm_sched_entity_init(&adev->mman.entity,
2029                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2030                                           1, NULL);
2031                 if (r) {
2032                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2033                                   r);
2034                         return;
2035                 }
2036         } else {
2037                 drm_sched_entity_destroy(&adev->mman.entity);
2038                 dma_fence_put(man->move);
2039                 man->move = NULL;
2040         }
2041
2042         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2043         if (enable)
2044                 size = adev->gmc.real_vram_size;
2045         else
2046                 size = adev->gmc.visible_vram_size;
2047         man->size = size;
2048         adev->mman.buffer_funcs_enabled = enable;
2049 }
2050
2051 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
2052                                   bool direct_submit,
2053                                   unsigned int num_dw,
2054                                   struct dma_resv *resv,
2055                                   bool vm_needs_flush,
2056                                   struct amdgpu_job **job)
2057 {
2058         enum amdgpu_ib_pool_type pool = direct_submit ?
2059                 AMDGPU_IB_POOL_DIRECT :
2060                 AMDGPU_IB_POOL_DELAYED;
2061         int r;
2062
2063         r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
2064                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2065                                      num_dw * 4, pool, job);
2066         if (r)
2067                 return r;
2068
2069         if (vm_needs_flush) {
2070                 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2071                                                         adev->gmc.pdb0_bo :
2072                                                         adev->gart.bo);
2073                 (*job)->vm_needs_flush = true;
2074         }
2075         if (!resv)
2076                 return 0;
2077
2078         return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2079                                                    DMA_RESV_USAGE_BOOKKEEP);
2080 }
2081
2082 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2083                        uint64_t dst_offset, uint32_t byte_count,
2084                        struct dma_resv *resv,
2085                        struct dma_fence **fence, bool direct_submit,
2086                        bool vm_needs_flush, bool tmz)
2087 {
2088         struct amdgpu_device *adev = ring->adev;
2089         unsigned num_loops, num_dw;
2090         struct amdgpu_job *job;
2091         uint32_t max_bytes;
2092         unsigned i;
2093         int r;
2094
2095         if (!direct_submit && !ring->sched.ready) {
2096                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2097                 return -EINVAL;
2098         }
2099
2100         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2101         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2102         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2103         r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2104                                    resv, vm_needs_flush, &job);
2105         if (r)
2106                 return r;
2107
2108         for (i = 0; i < num_loops; i++) {
2109                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2110
2111                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2112                                         dst_offset, cur_size_in_bytes, tmz);
2113
2114                 src_offset += cur_size_in_bytes;
2115                 dst_offset += cur_size_in_bytes;
2116                 byte_count -= cur_size_in_bytes;
2117         }
2118
2119         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2120         WARN_ON(job->ibs[0].length_dw > num_dw);
2121         if (direct_submit)
2122                 r = amdgpu_job_submit_direct(job, ring, fence);
2123         else
2124                 *fence = amdgpu_job_submit(job);
2125         if (r)
2126                 goto error_free;
2127
2128         return r;
2129
2130 error_free:
2131         amdgpu_job_free(job);
2132         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2133         return r;
2134 }
2135
2136 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2137                                uint64_t dst_addr, uint32_t byte_count,
2138                                struct dma_resv *resv,
2139                                struct dma_fence **fence,
2140                                bool vm_needs_flush)
2141 {
2142         struct amdgpu_device *adev = ring->adev;
2143         unsigned int num_loops, num_dw;
2144         struct amdgpu_job *job;
2145         uint32_t max_bytes;
2146         unsigned int i;
2147         int r;
2148
2149         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2150         num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2151         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2152         r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2153                                    &job);
2154         if (r)
2155                 return r;
2156
2157         for (i = 0; i < num_loops; i++) {
2158                 uint32_t cur_size = min(byte_count, max_bytes);
2159
2160                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2161                                         cur_size);
2162
2163                 dst_addr += cur_size;
2164                 byte_count -= cur_size;
2165         }
2166
2167         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2168         WARN_ON(job->ibs[0].length_dw > num_dw);
2169         *fence = amdgpu_job_submit(job);
2170         return 0;
2171 }
2172
2173 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2174                         uint32_t src_data,
2175                         struct dma_resv *resv,
2176                         struct dma_fence **f)
2177 {
2178         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2179         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2180         struct dma_fence *fence = NULL;
2181         struct amdgpu_res_cursor dst;
2182         int r;
2183
2184         if (!adev->mman.buffer_funcs_enabled) {
2185                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2186                 return -EINVAL;
2187         }
2188
2189         amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2190
2191         mutex_lock(&adev->mman.gtt_window_lock);
2192         while (dst.remaining) {
2193                 struct dma_fence *next;
2194                 uint64_t cur_size, to;
2195
2196                 /* Never fill more than 256MiB at once to avoid timeouts */
2197                 cur_size = min(dst.size, 256ULL << 20);
2198
2199                 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2200                                           1, ring, false, &cur_size, &to);
2201                 if (r)
2202                         goto error;
2203
2204                 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2205                                         &next, true);
2206                 if (r)
2207                         goto error;
2208
2209                 dma_fence_put(fence);
2210                 fence = next;
2211
2212                 amdgpu_res_next(&dst, cur_size);
2213         }
2214 error:
2215         mutex_unlock(&adev->mman.gtt_window_lock);
2216         if (f)
2217                 *f = dma_fence_get(fence);
2218         dma_fence_put(fence);
2219         return r;
2220 }
2221
2222 /**
2223  * amdgpu_ttm_evict_resources - evict memory buffers
2224  * @adev: amdgpu device object
2225  * @mem_type: evicted BO's memory type
2226  *
2227  * Evicts all @mem_type buffers on the lru list of the memory type.
2228  *
2229  * Returns:
2230  * 0 for success or a negative error code on failure.
2231  */
2232 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2233 {
2234         struct ttm_resource_manager *man;
2235
2236         switch (mem_type) {
2237         case TTM_PL_VRAM:
2238         case TTM_PL_TT:
2239         case AMDGPU_PL_GWS:
2240         case AMDGPU_PL_GDS:
2241         case AMDGPU_PL_OA:
2242                 man = ttm_manager_type(&adev->mman.bdev, mem_type);
2243                 break;
2244         default:
2245                 DRM_ERROR("Trying to evict invalid memory type\n");
2246                 return -EINVAL;
2247         }
2248
2249         return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2250 }
2251
2252 #if defined(CONFIG_DEBUG_FS)
2253
2254 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2255 {
2256         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2257
2258         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2259 }
2260
2261 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2262
2263 /*
2264  * amdgpu_ttm_vram_read - Linear read access to VRAM
2265  *
2266  * Accesses VRAM via MMIO for debugging purposes.
2267  */
2268 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2269                                     size_t size, loff_t *pos)
2270 {
2271         struct amdgpu_device *adev = file_inode(f)->i_private;
2272         ssize_t result = 0;
2273
2274         if (size & 0x3 || *pos & 0x3)
2275                 return -EINVAL;
2276
2277         if (*pos >= adev->gmc.mc_vram_size)
2278                 return -ENXIO;
2279
2280         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2281         while (size) {
2282                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2283                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2284
2285                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2286                 if (copy_to_user(buf, value, bytes))
2287                         return -EFAULT;
2288
2289                 result += bytes;
2290                 buf += bytes;
2291                 *pos += bytes;
2292                 size -= bytes;
2293         }
2294
2295         return result;
2296 }
2297
2298 /*
2299  * amdgpu_ttm_vram_write - Linear write access to VRAM
2300  *
2301  * Accesses VRAM via MMIO for debugging purposes.
2302  */
2303 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2304                                     size_t size, loff_t *pos)
2305 {
2306         struct amdgpu_device *adev = file_inode(f)->i_private;
2307         ssize_t result = 0;
2308         int r;
2309
2310         if (size & 0x3 || *pos & 0x3)
2311                 return -EINVAL;
2312
2313         if (*pos >= adev->gmc.mc_vram_size)
2314                 return -ENXIO;
2315
2316         while (size) {
2317                 uint32_t value;
2318
2319                 if (*pos >= adev->gmc.mc_vram_size)
2320                         return result;
2321
2322                 r = get_user(value, (uint32_t *)buf);
2323                 if (r)
2324                         return r;
2325
2326                 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2327
2328                 result += 4;
2329                 buf += 4;
2330                 *pos += 4;
2331                 size -= 4;
2332         }
2333
2334         return result;
2335 }
2336
2337 static const struct file_operations amdgpu_ttm_vram_fops = {
2338         .owner = THIS_MODULE,
2339         .read = amdgpu_ttm_vram_read,
2340         .write = amdgpu_ttm_vram_write,
2341         .llseek = default_llseek,
2342 };
2343
2344 /*
2345  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2346  *
2347  * This function is used to read memory that has been mapped to the
2348  * GPU and the known addresses are not physical addresses but instead
2349  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2350  */
2351 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2352                                  size_t size, loff_t *pos)
2353 {
2354         struct amdgpu_device *adev = file_inode(f)->i_private;
2355         struct iommu_domain *dom;
2356         ssize_t result = 0;
2357         int r;
2358
2359         /* retrieve the IOMMU domain if any for this device */
2360         dom = iommu_get_domain_for_dev(adev->dev);
2361
2362         while (size) {
2363                 phys_addr_t addr = *pos & PAGE_MASK;
2364                 loff_t off = *pos & ~PAGE_MASK;
2365                 size_t bytes = PAGE_SIZE - off;
2366                 unsigned long pfn;
2367                 struct page *p;
2368                 void *ptr;
2369
2370                 bytes = bytes < size ? bytes : size;
2371
2372                 /* Translate the bus address to a physical address.  If
2373                  * the domain is NULL it means there is no IOMMU active
2374                  * and the address translation is the identity
2375                  */
2376                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2377
2378                 pfn = addr >> PAGE_SHIFT;
2379                 if (!pfn_valid(pfn))
2380                         return -EPERM;
2381
2382                 p = pfn_to_page(pfn);
2383                 if (p->mapping != adev->mman.bdev.dev_mapping)
2384                         return -EPERM;
2385
2386                 ptr = kmap_local_page(p);
2387                 r = copy_to_user(buf, ptr + off, bytes);
2388                 kunmap_local(ptr);
2389                 if (r)
2390                         return -EFAULT;
2391
2392                 size -= bytes;
2393                 *pos += bytes;
2394                 result += bytes;
2395         }
2396
2397         return result;
2398 }
2399
2400 /*
2401  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2402  *
2403  * This function is used to write memory that has been mapped to the
2404  * GPU and the known addresses are not physical addresses but instead
2405  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2406  */
2407 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2408                                  size_t size, loff_t *pos)
2409 {
2410         struct amdgpu_device *adev = file_inode(f)->i_private;
2411         struct iommu_domain *dom;
2412         ssize_t result = 0;
2413         int r;
2414
2415         dom = iommu_get_domain_for_dev(adev->dev);
2416
2417         while (size) {
2418                 phys_addr_t addr = *pos & PAGE_MASK;
2419                 loff_t off = *pos & ~PAGE_MASK;
2420                 size_t bytes = PAGE_SIZE - off;
2421                 unsigned long pfn;
2422                 struct page *p;
2423                 void *ptr;
2424
2425                 bytes = bytes < size ? bytes : size;
2426
2427                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2428
2429                 pfn = addr >> PAGE_SHIFT;
2430                 if (!pfn_valid(pfn))
2431                         return -EPERM;
2432
2433                 p = pfn_to_page(pfn);
2434                 if (p->mapping != adev->mman.bdev.dev_mapping)
2435                         return -EPERM;
2436
2437                 ptr = kmap_local_page(p);
2438                 r = copy_from_user(ptr + off, buf, bytes);
2439                 kunmap_local(ptr);
2440                 if (r)
2441                         return -EFAULT;
2442
2443                 size -= bytes;
2444                 *pos += bytes;
2445                 result += bytes;
2446         }
2447
2448         return result;
2449 }
2450
2451 static const struct file_operations amdgpu_ttm_iomem_fops = {
2452         .owner = THIS_MODULE,
2453         .read = amdgpu_iomem_read,
2454         .write = amdgpu_iomem_write,
2455         .llseek = default_llseek
2456 };
2457
2458 #endif
2459
2460 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2461 {
2462 #if defined(CONFIG_DEBUG_FS)
2463         struct drm_minor *minor = adev_to_drm(adev)->primary;
2464         struct dentry *root = minor->debugfs_root;
2465
2466         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2467                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2468         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2469                             &amdgpu_ttm_iomem_fops);
2470         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2471                             &amdgpu_ttm_page_pool_fops);
2472         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2473                                                              TTM_PL_VRAM),
2474                                             root, "amdgpu_vram_mm");
2475         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2476                                                              TTM_PL_TT),
2477                                             root, "amdgpu_gtt_mm");
2478         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2479                                                              AMDGPU_PL_GDS),
2480                                             root, "amdgpu_gds_mm");
2481         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2482                                                              AMDGPU_PL_GWS),
2483                                             root, "amdgpu_gws_mm");
2484         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2485                                                              AMDGPU_PL_OA),
2486                                             root, "amdgpu_oa_mm");
2487
2488 #endif
2489 }