drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "df_v4_3.h"
  37 #include "nbio_v6_1.h"
  38 #include "nbio_v7_0.h"
  39 #include "nbio_v7_4.h"
  40 #include "nbio_v7_9.h"
  41 #include "hdp_v4_0.h"
  42 #include "vega10_ih.h"
  43 #include "vega20_ih.h"
  44 #include "sdma_v4_0.h"
  45 #include "sdma_v4_4_2.h"
  46 #include "uvd_v7_0.h"
  47 #include "vce_v4_0.h"
  48 #include "vcn_v1_0.h"
  49 #include "vcn_v2_5.h"
  50 #include "jpeg_v2_5.h"
  51 #include "smuio_v9_0.h"
  52 #include "gmc_v10_0.h"
  53 #include "gmc_v11_0.h"
  54 #include "gfxhub_v2_0.h"
  55 #include "mmhub_v2_0.h"
  56 #include "nbio_v2_3.h"
  57 #include "nbio_v4_3.h"
  58 #include "nbio_v7_2.h"
  59 #include "nbio_v7_7.h"
  60 #include "hdp_v5_0.h"
  61 #include "hdp_v5_2.h"
  62 #include "hdp_v6_0.h"
  63 #include "nv.h"
  64 #include "soc21.h"
  65 #include "navi10_ih.h"
  66 #include "ih_v6_0.h"
  67 #include "gfx_v10_0.h"
  68 #include "gfx_v11_0.h"
  69 #include "sdma_v5_0.h"
  70 #include "sdma_v5_2.h"
  71 #include "sdma_v6_0.h"
  72 #include "lsdma_v6_0.h"
  73 #include "vcn_v2_0.h"
  74 #include "jpeg_v2_0.h"
  75 #include "vcn_v3_0.h"
  76 #include "jpeg_v3_0.h"
  77 #include "vcn_v4_0.h"
  78 #include "jpeg_v4_0.h"
  79 #include "vcn_v4_0_3.h"
  80 #include "jpeg_v4_0_3.h"
  81 #include "amdgpu_vkms.h"
  82 #include "mes_v10_1.h"
  83 #include "mes_v11_0.h"
  84 #include "smuio_v11_0.h"
  85 #include "smuio_v11_0_6.h"
  86 #include "smuio_v13_0.h"
  87 #include "smuio_v13_0_3.h"
  88 #include "smuio_v13_0_6.h"
  89
  90 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  91 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  92
  93 #define mmRCC_CONFIG_MEMSIZE    0xde3
  94 #define mmMM_INDEX              0x0
  95 #define mmMM_INDEX_HI           0x6
  96 #define mmMM_DATA               0x1
  97
  98 static const char *hw_id_names[HW_ID_MAX] = {
  99         [MP1_HWID]              = "MP1",
 100         [MP2_HWID]              = "MP2",
 101         [THM_HWID]              = "THM",
 102         [SMUIO_HWID]            = "SMUIO",
 103         [FUSE_HWID]             = "FUSE",
 104         [CLKA_HWID]             = "CLKA",
 105         [PWR_HWID]              = "PWR",
 106         [GC_HWID]               = "GC",
 107         [UVD_HWID]              = "UVD",
 108         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
 109         [ACP_HWID]              = "ACP",
 110         [DCI_HWID]              = "DCI",
 111         [DMU_HWID]              = "DMU",
 112         [DCO_HWID]              = "DCO",
 113         [DIO_HWID]              = "DIO",
 114         [XDMA_HWID]             = "XDMA",
 115         [DCEAZ_HWID]            = "DCEAZ",
 116         [DAZ_HWID]              = "DAZ",
 117         [SDPMUX_HWID]           = "SDPMUX",
 118         [NTB_HWID]              = "NTB",
 119         [IOHC_HWID]             = "IOHC",
 120         [L2IMU_HWID]            = "L2IMU",
 121         [VCE_HWID]              = "VCE",
 122         [MMHUB_HWID]            = "MMHUB",
 123         [ATHUB_HWID]            = "ATHUB",
 124         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 125         [DFX_HWID]              = "DFX",
 126         [DBGU0_HWID]            = "DBGU0",
 127         [DBGU1_HWID]            = "DBGU1",
 128         [OSSSYS_HWID]           = "OSSSYS",
 129         [HDP_HWID]              = "HDP",
 130         [SDMA0_HWID]            = "SDMA0",
 131         [SDMA1_HWID]            = "SDMA1",
 132         [SDMA2_HWID]            = "SDMA2",
 133         [SDMA3_HWID]            = "SDMA3",
 134         [LSDMA_HWID]            = "LSDMA",
 135         [ISP_HWID]              = "ISP",
 136         [DBGU_IO_HWID]          = "DBGU_IO",
 137         [DF_HWID]               = "DF",
 138         [CLKB_HWID]             = "CLKB",
 139         [FCH_HWID]              = "FCH",
 140         [DFX_DAP_HWID]          = "DFX_DAP",
 141         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 142         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 143         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 144         [L1IMU3_HWID]           = "L1IMU3",
 145         [L1IMU4_HWID]           = "L1IMU4",
 146         [L1IMU5_HWID]           = "L1IMU5",
 147         [L1IMU6_HWID]           = "L1IMU6",
 148         [L1IMU7_HWID]           = "L1IMU7",
 149         [L1IMU8_HWID]           = "L1IMU8",
 150         [L1IMU9_HWID]           = "L1IMU9",
 151         [L1IMU10_HWID]          = "L1IMU10",
 152         [L1IMU11_HWID]          = "L1IMU11",
 153         [L1IMU12_HWID]          = "L1IMU12",
 154         [L1IMU13_HWID]          = "L1IMU13",
 155         [L1IMU14_HWID]          = "L1IMU14",
 156         [L1IMU15_HWID]          = "L1IMU15",
 157         [WAFLC_HWID]            = "WAFLC",
 158         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 159         [PCIE_HWID]             = "PCIE",
 160         [PCS_HWID]              = "PCS",
 161         [DDCL_HWID]             = "DDCL",
 162         [SST_HWID]              = "SST",
 163         [IOAGR_HWID]            = "IOAGR",
 164         [NBIF_HWID]             = "NBIF",
 165         [IOAPIC_HWID]           = "IOAPIC",
 166         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 167         [NTBCCP_HWID]           = "NTBCCP",
 168         [UMC_HWID]              = "UMC",
 169         [SATA_HWID]             = "SATA",
 170         [USB_HWID]              = "USB",
 171         [CCXSEC_HWID]           = "CCXSEC",
 172         [XGMI_HWID]             = "XGMI",
 173         [XGBE_HWID]             = "XGBE",
 174         [MP0_HWID]              = "MP0",
 175 };
 176
 177 static int hw_id_map[MAX_HWIP] = {
 178         [GC_HWIP]       = GC_HWID,
 179         [HDP_HWIP]      = HDP_HWID,
 180         [SDMA0_HWIP]    = SDMA0_HWID,
 181         [SDMA1_HWIP]    = SDMA1_HWID,
 182         [SDMA2_HWIP]    = SDMA2_HWID,
 183         [SDMA3_HWIP]    = SDMA3_HWID,
 184         [LSDMA_HWIP]    = LSDMA_HWID,
 185         [MMHUB_HWIP]    = MMHUB_HWID,
 186         [ATHUB_HWIP]    = ATHUB_HWID,
 187         [NBIO_HWIP]     = NBIF_HWID,
 188         [MP0_HWIP]      = MP0_HWID,
 189         [MP1_HWIP]      = MP1_HWID,
 190         [UVD_HWIP]      = UVD_HWID,
 191         [VCE_HWIP]      = VCE_HWID,
 192         [DF_HWIP]       = DF_HWID,
 193         [DCE_HWIP]      = DMU_HWID,
 194         [OSSSYS_HWIP]   = OSSSYS_HWID,
 195         [SMUIO_HWIP]    = SMUIO_HWID,
 196         [PWR_HWIP]      = PWR_HWID,
 197         [NBIF_HWIP]     = NBIF_HWID,
 198         [THM_HWIP]      = THM_HWID,
 199         [CLK_HWIP]      = CLKA_HWID,
 200         [UMC_HWIP]      = UMC_HWID,
 201         [XGMI_HWIP]     = XGMI_HWID,
 202         [DCI_HWIP]      = DCI_HWID,
 203         [PCIE_HWIP]     = PCIE_HWID,
 204 };
 205
 206 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
 207 {
 208         u64 tmr_offset, tmr_size, pos;
 209         void *discv_regn;
 210         int ret;
 211
 212         ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
 213         if (ret)
 214                 return ret;
 215
 216         pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
 217
 218         /* This region is read-only and reserved from system use */
 219         discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);
 220         if (discv_regn) {
 221                 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);
 222                 memunmap(discv_regn);
 223                 return 0;
 224         }
 225
 226         return -ENOENT;
 227 }
 228
 229 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
 230                                                  uint8_t *binary)
 231 {
 232         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 233         int ret = 0;
 234
 235         if (vram_size) {
 236                 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 237                 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 238                                           adev->mman.discovery_tmr_size, false);
 239         } else {
 240                 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
 241         }
 242
 243         return ret;
 244 }
 245
 246 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 247 {
 248         const struct firmware *fw;
 249         const char *fw_name;
 250         int r;
 251
 252         switch (amdgpu_discovery) {
 253         case 2:
 254                 fw_name = FIRMWARE_IP_DISCOVERY;
 255                 break;
 256         default:
 257                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 258                 return -EINVAL;
 259         }
 260
 261         r = request_firmware(&fw, fw_name, adev->dev);
 262         if (r) {
 263                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 264                         fw_name);
 265                 return r;
 266         }
 267
 268         memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
 269         release_firmware(fw);
 270
 271         return 0;
 272 }
 273
 274 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 275 {
 276         uint16_t checksum = 0;
 277         int i;
 278
 279         for (i = 0; i < size; i++)
 280                 checksum += data[i];
 281
 282         return checksum;
 283 }
 284
 285 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 286                                                     uint16_t expected)
 287 {
 288         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 289 }
 290
 291 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 292 {
 293         struct binary_header *bhdr;
 294         bhdr = (struct binary_header *)binary;
 295
 296         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 297 }
 298
 299 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 300 {
 301         /*
 302          * So far, apply this quirk only on those Navy Flounder boards which
 303          * have a bad harvest table of VCN config.
 304          */
 305         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 306                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 307                 switch (adev->pdev->revision) {
 308                 case 0xC1:
 309                 case 0xC2:
 310                 case 0xC3:
 311                 case 0xC5:
 312                 case 0xC7:
 313                 case 0xCF:
 314                 case 0xDF:
 315                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 316                         adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
 317                         break;
 318                 default:
 319                         break;
 320                 }
 321         }
 322 }
 323
 324 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 325 {
 326         struct table_info *info;
 327         struct binary_header *bhdr;
 328         uint16_t offset;
 329         uint16_t size;
 330         uint16_t checksum;
 331         int r;
 332
 333         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 334         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 335         if (!adev->mman.discovery_bin)
 336                 return -ENOMEM;
 337
 338         /* Read from file if it is the preferred option */
 339         if (amdgpu_discovery == 2) {
 340                 dev_info(adev->dev, "use ip discovery information from file");
 341                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 342
 343                 if (r) {
 344                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 345                         r = -EINVAL;
 346                         goto out;
 347                 }
 348
 349         } else {
 350                 r = amdgpu_discovery_read_binary_from_mem(
 351                         adev, adev->mman.discovery_bin);
 352                 if (r)
 353                         goto out;
 354         }
 355
 356         /* check the ip discovery binary signature */
 357         if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 358                 dev_err(adev->dev,
 359                         "get invalid ip discovery binary signature\n");
 360                 r = -EINVAL;
 361                 goto out;
 362         }
 363
 364         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 365
 366         offset = offsetof(struct binary_header, binary_checksum) +
 367                 sizeof(bhdr->binary_checksum);
 368         size = le16_to_cpu(bhdr->binary_size) - offset;
 369         checksum = le16_to_cpu(bhdr->binary_checksum);
 370
 371         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 372                                               size, checksum)) {
 373                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 374                 r = -EINVAL;
 375                 goto out;
 376         }
 377
 378         info = &bhdr->table_list[IP_DISCOVERY];
 379         offset = le16_to_cpu(info->offset);
 380         checksum = le16_to_cpu(info->checksum);
 381
 382         if (offset) {
 383                 struct ip_discovery_header *ihdr =
 384                         (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 385                 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 386                         dev_err(adev->dev, "invalid ip discovery data table signature\n");
 387                         r = -EINVAL;
 388                         goto out;
 389                 }
 390
 391                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 392                                                       le16_to_cpu(ihdr->size), checksum)) {
 393                         dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 394                         r = -EINVAL;
 395                         goto out;
 396                 }
 397         }
 398
 399         info = &bhdr->table_list[GC];
 400         offset = le16_to_cpu(info->offset);
 401         checksum = le16_to_cpu(info->checksum);
 402
 403         if (offset) {
 404                 struct gpu_info_header *ghdr =
 405                         (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 406
 407                 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
 408                         dev_err(adev->dev, "invalid ip discovery gc table id\n");
 409                         r = -EINVAL;
 410                         goto out;
 411                 }
 412
 413                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 414                                                       le32_to_cpu(ghdr->size), checksum)) {
 415                         dev_err(adev->dev, "invalid gc data table checksum\n");
 416                         r = -EINVAL;
 417                         goto out;
 418                 }
 419         }
 420
 421         info = &bhdr->table_list[HARVEST_INFO];
 422         offset = le16_to_cpu(info->offset);
 423         checksum = le16_to_cpu(info->checksum);
 424
 425         if (offset) {
 426                 struct harvest_info_header *hhdr =
 427                         (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
 428
 429                 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
 430                         dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
 431                         r = -EINVAL;
 432                         goto out;
 433                 }
 434
 435                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 436                                                       sizeof(struct harvest_table), checksum)) {
 437                         dev_err(adev->dev, "invalid harvest data table checksum\n");
 438                         r = -EINVAL;
 439                         goto out;
 440                 }
 441         }
 442
 443         info = &bhdr->table_list[VCN_INFO];
 444         offset = le16_to_cpu(info->offset);
 445         checksum = le16_to_cpu(info->checksum);
 446
 447         if (offset) {
 448                 struct vcn_info_header *vhdr =
 449                         (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
 450
 451                 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
 452                         dev_err(adev->dev, "invalid ip discovery vcn table id\n");
 453                         r = -EINVAL;
 454                         goto out;
 455                 }
 456
 457                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 458                                                       le32_to_cpu(vhdr->size_bytes), checksum)) {
 459                         dev_err(adev->dev, "invalid vcn data table checksum\n");
 460                         r = -EINVAL;
 461                         goto out;
 462                 }
 463         }
 464
 465         info = &bhdr->table_list[MALL_INFO];
 466         offset = le16_to_cpu(info->offset);
 467         checksum = le16_to_cpu(info->checksum);
 468
 469         if (0 && offset) {
 470                 struct mall_info_header *mhdr =
 471                         (struct mall_info_header *)(adev->mman.discovery_bin + offset);
 472
 473                 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
 474                         dev_err(adev->dev, "invalid ip discovery mall table id\n");
 475                         r = -EINVAL;
 476                         goto out;
 477                 }
 478
 479                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 480                                                       le32_to_cpu(mhdr->size_bytes), checksum)) {
 481                         dev_err(adev->dev, "invalid mall data table checksum\n");
 482                         r = -EINVAL;
 483                         goto out;
 484                 }
 485         }
 486
 487         return 0;
 488
 489 out:
 490         kfree(adev->mman.discovery_bin);
 491         adev->mman.discovery_bin = NULL;
 492
 493         return r;
 494 }
 495
 496 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 497
 498 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 499 {
 500         amdgpu_discovery_sysfs_fini(adev);
 501         kfree(adev->mman.discovery_bin);
 502         adev->mman.discovery_bin = NULL;
 503 }
 504
 505 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)
 506 {
 507         if (ip->instance_number >= HWIP_MAX_INSTANCE) {
 508                 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n",
 509                           ip->instance_number);
 510                 return -EINVAL;
 511         }
 512         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 513                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 514                           le16_to_cpu(ip->hw_id));
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 522                                                 uint32_t *vcn_harvest_count)
 523 {
 524         struct binary_header *bhdr;
 525         struct ip_discovery_header *ihdr;
 526         struct die_header *dhdr;
 527         struct ip_v4 *ip;
 528         uint16_t die_offset, ip_offset, num_dies, num_ips;
 529         int i, j;
 530
 531         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 532         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 533                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 534         num_dies = le16_to_cpu(ihdr->num_dies);
 535
 536         /* scan harvest bit of all IP data structures */
 537         for (i = 0; i < num_dies; i++) {
 538                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 539                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 540                 num_ips = le16_to_cpu(dhdr->num_ips);
 541                 ip_offset = die_offset + sizeof(*dhdr);
 542
 543                 for (j = 0; j < num_ips; j++) {
 544                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
 545
 546                         if (amdgpu_discovery_validate_ip(ip))
 547                                 goto next_ip;
 548
 549                         if (le16_to_cpu(ip->variant) == 1) {
 550                                 switch (le16_to_cpu(ip->hw_id)) {
 551                                 case VCN_HWID:
 552                                         (*vcn_harvest_count)++;
 553                                         if (ip->instance_number == 0) {
 554                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 555                                                 adev->vcn.inst_mask &=
 556                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 557                                                 adev->jpeg.inst_mask &=
 558                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 559                                         } else {
 560                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 561                                                 adev->vcn.inst_mask &=
 562                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 563                                                 adev->jpeg.inst_mask &=
 564                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 565                                         }
 566                                         break;
 567                                 case DMU_HWID:
 568                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 569                                         break;
 570                                 default:
 571                                         break;
 572                                 }
 573                         }
 574 next_ip:
 575                         if (ihdr->base_addr_64_bit)
 576                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
 577                         else
 578                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
 579                 }
 580         }
 581 }
 582
 583 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 584                                                      uint32_t *vcn_harvest_count,
 585                                                      uint32_t *umc_harvest_count)
 586 {
 587         struct binary_header *bhdr;
 588         struct harvest_table *harvest_info;
 589         u16 offset;
 590         int i;
 591         uint32_t umc_harvest_config = 0;
 592
 593         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 594         offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
 595
 596         if (!offset) {
 597                 dev_err(adev->dev, "invalid harvest table offset\n");
 598                 return;
 599         }
 600
 601         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
 602
 603         for (i = 0; i < 32; i++) {
 604                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 605                         break;
 606
 607                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 608                 case VCN_HWID:
 609                         (*vcn_harvest_count)++;
 610                         adev->vcn.harvest_config |=
 611                                 (1 << harvest_info->list[i].number_instance);
 612                         adev->jpeg.harvest_config |=
 613                                 (1 << harvest_info->list[i].number_instance);
 614
 615                         adev->vcn.inst_mask &=
 616                                 ~(1U << harvest_info->list[i].number_instance);
 617                         adev->jpeg.inst_mask &=
 618                                 ~(1U << harvest_info->list[i].number_instance);
 619                         break;
 620                 case DMU_HWID:
 621                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 622                         break;
 623                 case UMC_HWID:
 624                         umc_harvest_config |=
 625                                 1 << (le16_to_cpu(harvest_info->list[i].number_instance));
 626                         (*umc_harvest_count)++;
 627                         break;
 628                 case GC_HWID:
 629                         adev->gfx.xcc_mask &=
 630                                 ~(1U << harvest_info->list[i].number_instance);
 631                         break;
 632                 case SDMA0_HWID:
 633                         adev->sdma.sdma_mask &=
 634                                 ~(1U << harvest_info->list[i].number_instance);
 635                         break;
 636                 default:
 637                         break;
 638                 }
 639         }
 640
 641         adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
 642                                 ~umc_harvest_config;
 643 }
 644
 645 /* ================================================== */
 646
 647 struct ip_hw_instance {
 648         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 649
 650         int hw_id;
 651         u8  num_instance;
 652         u8  major, minor, revision;
 653         u8  harvest;
 654
 655         int num_base_addresses;
 656         u32 base_addr[];
 657 };
 658
 659 struct ip_hw_id {
 660         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 661         int hw_id;
 662 };
 663
 664 struct ip_die_entry {
 665         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 666         u16 num_ips;
 667 };
 668
 669 /* -------------------------------------------------- */
 670
 671 struct ip_hw_instance_attr {
 672         struct attribute attr;
 673         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 674 };
 675
 676 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 677 {
 678         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 679 }
 680
 681 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 682 {
 683         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 684 }
 685
 686 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 687 {
 688         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 689 }
 690
 691 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 692 {
 693         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 694 }
 695
 696 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 697 {
 698         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 699 }
 700
 701 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 702 {
 703         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 704 }
 705
 706 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 707 {
 708         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 709 }
 710
 711 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 712 {
 713         ssize_t res, at;
 714         int ii;
 715
 716         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 717                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 718                  */
 719                 if (at + 12 > PAGE_SIZE)
 720                         break;
 721                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 722                                     ip_hw_instance->base_addr[ii]);
 723                 if (res <= 0)
 724                         break;
 725                 at += res;
 726         }
 727
 728         return res < 0 ? res : at;
 729 }
 730
 731 static struct ip_hw_instance_attr ip_hw_attr[] = {
 732         __ATTR_RO(hw_id),
 733         __ATTR_RO(num_instance),
 734         __ATTR_RO(major),
 735         __ATTR_RO(minor),
 736         __ATTR_RO(revision),
 737         __ATTR_RO(harvest),
 738         __ATTR_RO(num_base_addresses),
 739         __ATTR_RO(base_addr),
 740 };
 741
 742 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 743 ATTRIBUTE_GROUPS(ip_hw_instance);
 744
 745 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 746 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 747
 748 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 749                                         struct attribute *attr,
 750                                         char *buf)
 751 {
 752         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 753         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 754
 755         if (!ip_hw_attr->show)
 756                 return -EIO;
 757
 758         return ip_hw_attr->show(ip_hw_instance, buf);
 759 }
 760
 761 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 762         .show = ip_hw_instance_attr_show,
 763 };
 764
 765 static void ip_hw_instance_release(struct kobject *kobj)
 766 {
 767         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 768
 769         kfree(ip_hw_instance);
 770 }
 771
 772 static const struct kobj_type ip_hw_instance_ktype = {
 773         .release = ip_hw_instance_release,
 774         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 775         .default_groups = ip_hw_instance_groups,
 776 };
 777
 778 /* -------------------------------------------------- */
 779
 780 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 781
 782 static void ip_hw_id_release(struct kobject *kobj)
 783 {
 784         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 785
 786         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 787                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 788         kfree(ip_hw_id);
 789 }
 790
 791 static const struct kobj_type ip_hw_id_ktype = {
 792         .release = ip_hw_id_release,
 793         .sysfs_ops = &kobj_sysfs_ops,
 794 };
 795
 796 /* -------------------------------------------------- */
 797
 798 static void die_kobj_release(struct kobject *kobj);
 799 static void ip_disc_release(struct kobject *kobj);
 800
 801 struct ip_die_entry_attribute {
 802         struct attribute attr;
 803         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 804 };
 805
 806 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 807
 808 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 809 {
 810         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 811 }
 812
 813 /* If there are more ip_die_entry attrs, other than the number of IPs,
 814  * we can make this intro an array of attrs, and then initialize
 815  * ip_die_entry_attrs in a loop.
 816  */
 817 static struct ip_die_entry_attribute num_ips_attr =
 818         __ATTR_RO(num_ips);
 819
 820 static struct attribute *ip_die_entry_attrs[] = {
 821         &num_ips_attr.attr,
 822         NULL,
 823 };
 824 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 825
 826 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 827
 828 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 829                                       struct attribute *attr,
 830                                       char *buf)
 831 {
 832         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 833         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 834
 835         if (!ip_die_entry_attr->show)
 836                 return -EIO;
 837
 838         return ip_die_entry_attr->show(ip_die_entry, buf);
 839 }
 840
 841 static void ip_die_entry_release(struct kobject *kobj)
 842 {
 843         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 844
 845         if (!list_empty(&ip_die_entry->ip_kset.list))
 846                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 847         kfree(ip_die_entry);
 848 }
 849
 850 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 851         .show = ip_die_entry_attr_show,
 852 };
 853
 854 static const struct kobj_type ip_die_entry_ktype = {
 855         .release = ip_die_entry_release,
 856         .sysfs_ops = &ip_die_entry_sysfs_ops,
 857         .default_groups = ip_die_entry_groups,
 858 };
 859
 860 static const struct kobj_type die_kobj_ktype = {
 861         .release = die_kobj_release,
 862         .sysfs_ops = &kobj_sysfs_ops,
 863 };
 864
 865 static const struct kobj_type ip_discovery_ktype = {
 866         .release = ip_disc_release,
 867         .sysfs_ops = &kobj_sysfs_ops,
 868 };
 869
 870 struct ip_discovery_top {
 871         struct kobject kobj;    /* ip_discovery/ */
 872         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 873         struct amdgpu_device *adev;
 874 };
 875
 876 static void die_kobj_release(struct kobject *kobj)
 877 {
 878         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 879                                                        struct ip_discovery_top,
 880                                                        die_kset);
 881         if (!list_empty(&ip_top->die_kset.list))
 882                 DRM_ERROR("ip_top->die_kset is not empty");
 883 }
 884
 885 static void ip_disc_release(struct kobject *kobj)
 886 {
 887         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 888                                                        kobj);
 889         struct amdgpu_device *adev = ip_top->adev;
 890
 891         adev->ip_top = NULL;
 892         kfree(ip_top);
 893 }
 894
 895 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
 896                                                  uint16_t hw_id, uint8_t inst)
 897 {
 898         uint8_t harvest = 0;
 899
 900         /* Until a uniform way is figured, get mask based on hwid */
 901         switch (hw_id) {
 902         case VCN_HWID:
 903                 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
 904                 break;
 905         case DMU_HWID:
 906                 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
 907                         harvest = 0x1;
 908                 break;
 909         case UMC_HWID:
 910                 /* TODO: It needs another parsing; for now, ignore.*/
 911                 break;
 912         case GC_HWID:
 913                 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
 914                 break;
 915         case SDMA0_HWID:
 916                 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
 917                 break;
 918         default:
 919                 break;
 920         }
 921
 922         return harvest;
 923 }
 924
 925 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 926                                       struct ip_die_entry *ip_die_entry,
 927                                       const size_t _ip_offset, const int num_ips,
 928                                       bool reg_base_64)
 929 {
 930         int ii, jj, kk, res;
 931
 932         DRM_DEBUG("num_ips:%d", num_ips);
 933
 934         /* Find all IPs of a given HW ID, and add their instance to
 935          * #die/#hw_id/#instance/<attributes>
 936          */
 937         for (ii = 0; ii < HW_ID_MAX; ii++) {
 938                 struct ip_hw_id *ip_hw_id = NULL;
 939                 size_t ip_offset = _ip_offset;
 940
 941                 for (jj = 0; jj < num_ips; jj++) {
 942                         struct ip_v4 *ip;
 943                         struct ip_hw_instance *ip_hw_instance;
 944
 945                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
 946                         if (amdgpu_discovery_validate_ip(ip) ||
 947                             le16_to_cpu(ip->hw_id) != ii)
 948                                 goto next_ip;
 949
 950                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 951
 952                         /* We have a hw_id match; register the hw
 953                          * block if not yet registered.
 954                          */
 955                         if (!ip_hw_id) {
 956                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 957                                 if (!ip_hw_id)
 958                                         return -ENOMEM;
 959                                 ip_hw_id->hw_id = ii;
 960
 961                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 962                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 963                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 964                                 res = kset_register(&ip_hw_id->hw_id_kset);
 965                                 if (res) {
 966                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 967                                         kfree(ip_hw_id);
 968                                         return res;
 969                                 }
 970                                 if (hw_id_names[ii]) {
 971                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 972                                                                 &ip_hw_id->hw_id_kset.kobj,
 973                                                                 hw_id_names[ii]);
 974                                         if (res) {
 975                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 976                                                           hw_id_names[ii],
 977                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 978                                         }
 979                                 }
 980                         }
 981
 982                         /* Now register its instance.
 983                          */
 984                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 985                                                              base_addr,
 986                                                              ip->num_base_address),
 987                                                  GFP_KERNEL);
 988                         if (!ip_hw_instance) {
 989                                 DRM_ERROR("no memory for ip_hw_instance");
 990                                 return -ENOMEM;
 991                         }
 992                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 993                         ip_hw_instance->num_instance = ip->instance_number;
 994                         ip_hw_instance->major = ip->major;
 995                         ip_hw_instance->minor = ip->minor;
 996                         ip_hw_instance->revision = ip->revision;
 997                         ip_hw_instance->harvest =
 998                                 amdgpu_discovery_get_harvest_info(
 999                                         adev, ip_hw_instance->hw_id,
1000                                         ip_hw_instance->num_instance);
1001                         ip_hw_instance->num_base_addresses = ip->num_base_address;
1002
1003                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1004                                 if (reg_base_64)
1005                                         ip_hw_instance->base_addr[kk] =
1006                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1007                                 else
1008                                         ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1009                         }
1010
1011                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1012                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1013                         res = kobject_add(&ip_hw_instance->kobj, NULL,
1014                                           "%d", ip_hw_instance->num_instance);
1015 next_ip:
1016                         if (reg_base_64)
1017                                 ip_offset += struct_size(ip, base_address_64,
1018                                                          ip->num_base_address);
1019                         else
1020                                 ip_offset += struct_size(ip, base_address,
1021                                                          ip->num_base_address);
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1029 {
1030         struct binary_header *bhdr;
1031         struct ip_discovery_header *ihdr;
1032         struct die_header *dhdr;
1033         struct kset *die_kset = &adev->ip_top->die_kset;
1034         u16 num_dies, die_offset, num_ips;
1035         size_t ip_offset;
1036         int ii, res;
1037
1038         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1039         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1040                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1041         num_dies = le16_to_cpu(ihdr->num_dies);
1042
1043         DRM_DEBUG("number of dies: %d\n", num_dies);
1044
1045         for (ii = 0; ii < num_dies; ii++) {
1046                 struct ip_die_entry *ip_die_entry;
1047
1048                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1049                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1050                 num_ips = le16_to_cpu(dhdr->num_ips);
1051                 ip_offset = die_offset + sizeof(*dhdr);
1052
1053                 /* Add the die to the kset.
1054                  *
1055                  * dhdr->die_id == ii, which was checked in
1056                  * amdgpu_discovery_reg_base_init().
1057                  */
1058
1059                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
1060                 if (!ip_die_entry)
1061                         return -ENOMEM;
1062
1063                 ip_die_entry->num_ips = num_ips;
1064
1065                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1066                 ip_die_entry->ip_kset.kobj.kset = die_kset;
1067                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1068                 res = kset_register(&ip_die_entry->ip_kset);
1069                 if (res) {
1070                         DRM_ERROR("Couldn't register ip_die_entry kset");
1071                         kfree(ip_die_entry);
1072                         return res;
1073                 }
1074
1075                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1076         }
1077
1078         return 0;
1079 }
1080
1081 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1082 {
1083         struct kset *die_kset;
1084         int res, ii;
1085
1086         if (!adev->mman.discovery_bin)
1087                 return -EINVAL;
1088
1089         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
1090         if (!adev->ip_top)
1091                 return -ENOMEM;
1092
1093         adev->ip_top->adev = adev;
1094
1095         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
1096                                    &adev->dev->kobj, "ip_discovery");
1097         if (res) {
1098                 DRM_ERROR("Couldn't init and add ip_discovery/");
1099                 goto Err;
1100         }
1101
1102         die_kset = &adev->ip_top->die_kset;
1103         kobject_set_name(&die_kset->kobj, "%s", "die");
1104         die_kset->kobj.parent = &adev->ip_top->kobj;
1105         die_kset->kobj.ktype = &die_kobj_ktype;
1106         res = kset_register(&adev->ip_top->die_kset);
1107         if (res) {
1108                 DRM_ERROR("Couldn't register die_kset");
1109                 goto Err;
1110         }
1111
1112         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1113                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1114         ip_hw_instance_attrs[ii] = NULL;
1115
1116         res = amdgpu_discovery_sysfs_recurse(adev);
1117
1118         return res;
1119 Err:
1120         kobject_put(&adev->ip_top->kobj);
1121         return res;
1122 }
1123
1124 /* -------------------------------------------------- */
1125
1126 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1127
1128 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1129 {
1130         struct list_head *el, *tmp;
1131         struct kset *hw_id_kset;
1132
1133         hw_id_kset = &ip_hw_id->hw_id_kset;
1134         spin_lock(&hw_id_kset->list_lock);
1135         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1136                 list_del_init(el);
1137                 spin_unlock(&hw_id_kset->list_lock);
1138                 /* kobject is embedded in ip_hw_instance */
1139                 kobject_put(list_to_kobj(el));
1140                 spin_lock(&hw_id_kset->list_lock);
1141         }
1142         spin_unlock(&hw_id_kset->list_lock);
1143         kobject_put(&ip_hw_id->hw_id_kset.kobj);
1144 }
1145
1146 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1147 {
1148         struct list_head *el, *tmp;
1149         struct kset *ip_kset;
1150
1151         ip_kset = &ip_die_entry->ip_kset;
1152         spin_lock(&ip_kset->list_lock);
1153         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1154                 list_del_init(el);
1155                 spin_unlock(&ip_kset->list_lock);
1156                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1157                 spin_lock(&ip_kset->list_lock);
1158         }
1159         spin_unlock(&ip_kset->list_lock);
1160         kobject_put(&ip_die_entry->ip_kset.kobj);
1161 }
1162
1163 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1164 {
1165         struct list_head *el, *tmp;
1166         struct kset *die_kset;
1167
1168         die_kset = &adev->ip_top->die_kset;
1169         spin_lock(&die_kset->list_lock);
1170         list_for_each_prev_safe(el, tmp, &die_kset->list) {
1171                 list_del_init(el);
1172                 spin_unlock(&die_kset->list_lock);
1173                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1174                 spin_lock(&die_kset->list_lock);
1175         }
1176         spin_unlock(&die_kset->list_lock);
1177         kobject_put(&adev->ip_top->die_kset.kobj);
1178         kobject_put(&adev->ip_top->kobj);
1179 }
1180
1181 /* ================================================== */
1182
1183 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1184 {
1185         struct binary_header *bhdr;
1186         struct ip_discovery_header *ihdr;
1187         struct die_header *dhdr;
1188         struct ip_v4 *ip;
1189         uint16_t die_offset;
1190         uint16_t ip_offset;
1191         uint16_t num_dies;
1192         uint16_t num_ips;
1193         uint8_t num_base_address;
1194         int hw_ip;
1195         int i, j, k;
1196         int r;
1197
1198         r = amdgpu_discovery_init(adev);
1199         if (r) {
1200                 DRM_ERROR("amdgpu_discovery_init failed\n");
1201                 return r;
1202         }
1203
1204         adev->gfx.xcc_mask = 0;
1205         adev->sdma.sdma_mask = 0;
1206         adev->vcn.inst_mask = 0;
1207         adev->jpeg.inst_mask = 0;
1208         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1209         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1210                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1211         num_dies = le16_to_cpu(ihdr->num_dies);
1212
1213         DRM_DEBUG("number of dies: %d\n", num_dies);
1214
1215         for (i = 0; i < num_dies; i++) {
1216                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1217                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1218                 num_ips = le16_to_cpu(dhdr->num_ips);
1219                 ip_offset = die_offset + sizeof(*dhdr);
1220
1221                 if (le16_to_cpu(dhdr->die_id) != i) {
1222                         DRM_ERROR("invalid die id %d, expected %d\n",
1223                                         le16_to_cpu(dhdr->die_id), i);
1224                         return -EINVAL;
1225                 }
1226
1227                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1228                                 le16_to_cpu(dhdr->die_id), num_ips);
1229
1230                 for (j = 0; j < num_ips; j++) {
1231                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1232
1233                         if (amdgpu_discovery_validate_ip(ip))
1234                                 goto next_ip;
1235
1236                         num_base_address = ip->num_base_address;
1237
1238                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1239                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1240                                   le16_to_cpu(ip->hw_id),
1241                                   ip->instance_number,
1242                                   ip->major, ip->minor,
1243                                   ip->revision);
1244
1245                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1246                                 /* Bit [5:0]: original revision value
1247                                  * Bit [7:6]: en/decode capability:
1248                                  *     0b00 : VCN function normally
1249                                  *     0b10 : encode is disabled
1250                                  *     0b01 : decode is disabled
1251                                  */
1252                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1253                                         ip->revision & 0xc0;
1254                                 ip->revision &= ~0xc0;
1255                                 if (adev->vcn.num_vcn_inst <
1256                                     AMDGPU_MAX_VCN_INSTANCES) {
1257                                         adev->vcn.num_vcn_inst++;
1258                                         adev->vcn.inst_mask |=
1259                                                 (1U << ip->instance_number);
1260                                         adev->jpeg.inst_mask |=
1261                                                 (1U << ip->instance_number);
1262                                 } else {
1263                                         dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1264                                                 adev->vcn.num_vcn_inst + 1,
1265                                                 AMDGPU_MAX_VCN_INSTANCES);
1266                                 }
1267                         }
1268                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1269                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1270                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1271                             le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1272                                 if (adev->sdma.num_instances <
1273                                     AMDGPU_MAX_SDMA_INSTANCES) {
1274                                         adev->sdma.num_instances++;
1275                                         adev->sdma.sdma_mask |=
1276                                                 (1U << ip->instance_number);
1277                                 } else {
1278                                         dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1279                                                 adev->sdma.num_instances + 1,
1280                                                 AMDGPU_MAX_SDMA_INSTANCES);
1281                                 }
1282                         }
1283
1284                         if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1285                                 adev->gmc.num_umc++;
1286                                 adev->umc.node_inst_num++;
1287                         }
1288
1289                         if (le16_to_cpu(ip->hw_id) == GC_HWID)
1290                                 adev->gfx.xcc_mask |=
1291                                         (1U << ip->instance_number);
1292
1293                         for (k = 0; k < num_base_address; k++) {
1294                                 /*
1295                                  * convert the endianness of base addresses in place,
1296                                  * so that we don't need to convert them when accessing adev->reg_offset.
1297                                  */
1298                                 if (ihdr->base_addr_64_bit)
1299                                         /* Truncate the 64bit base address from ip discovery
1300                                          * and only store lower 32bit ip base in reg_offset[].
1301                                          * Bits > 32 follows ASIC specific format, thus just
1302                                          * discard them and handle it within specific ASIC.
1303                                          * By this way reg_offset[] and related helpers can
1304                                          * stay unchanged.
1305                                          * The base address is in dwords, thus clear the
1306                                          * highest 2 bits to store.
1307                                          */
1308                                         ip->base_address[k] =
1309                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1310                                 else
1311                                         ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1312                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1313                         }
1314
1315                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1316                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1317                                     hw_id_map[hw_ip] != 0) {
1318                                         DRM_DEBUG("set register base offset for %s\n",
1319                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1320                                         adev->reg_offset[hw_ip][ip->instance_number] =
1321                                                 ip->base_address;
1322                                         /* Instance support is somewhat inconsistent.
1323                                          * SDMA is a good example.  Sienna cichlid has 4 total
1324                                          * SDMA instances, each enumerated separately (HWIDs
1325                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1326                                          * but they are enumerated as multiple instances of the
1327                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1328                                          * example.  On most chips there are multiple instances
1329                                          * with the same HWID.
1330                                          */
1331                                         adev->ip_versions[hw_ip][ip->instance_number] =
1332                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1333                                 }
1334                         }
1335
1336 next_ip:
1337                         if (ihdr->base_addr_64_bit)
1338                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1339                         else
1340                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1341                 }
1342         }
1343
1344         return 0;
1345 }
1346
1347 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1348 {
1349         int vcn_harvest_count = 0;
1350         int umc_harvest_count = 0;
1351
1352         /*
1353          * Harvest table does not fit Navi1x and legacy GPUs,
1354          * so read harvest bit per IP data structure to set
1355          * harvest configuration.
1356          */
1357         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) &&
1358             adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) {
1359                 if ((adev->pdev->device == 0x731E &&
1360                         (adev->pdev->revision == 0xC6 ||
1361                          adev->pdev->revision == 0xC7)) ||
1362                         (adev->pdev->device == 0x7340 &&
1363                          adev->pdev->revision == 0xC9) ||
1364                         (adev->pdev->device == 0x7360 &&
1365                          adev->pdev->revision == 0xC7))
1366                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1367                                 &vcn_harvest_count);
1368         } else {
1369                 amdgpu_discovery_read_from_harvest_table(adev,
1370                                                          &vcn_harvest_count,
1371                                                          &umc_harvest_count);
1372         }
1373
1374         amdgpu_discovery_harvest_config_quirk(adev);
1375
1376         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1377                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1378                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1379         }
1380
1381         if (umc_harvest_count < adev->gmc.num_umc) {
1382                 adev->gmc.num_umc -= umc_harvest_count;
1383         }
1384 }
1385
1386 union gc_info {
1387         struct gc_info_v1_0 v1;
1388         struct gc_info_v1_1 v1_1;
1389         struct gc_info_v1_2 v1_2;
1390         struct gc_info_v2_0 v2;
1391 };
1392
1393 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1394 {
1395         struct binary_header *bhdr;
1396         union gc_info *gc_info;
1397         u16 offset;
1398
1399         if (!adev->mman.discovery_bin) {
1400                 DRM_ERROR("ip discovery uninitialized\n");
1401                 return -EINVAL;
1402         }
1403
1404         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1405         offset = le16_to_cpu(bhdr->table_list[GC].offset);
1406
1407         if (!offset)
1408                 return 0;
1409
1410         gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1411
1412         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1413         case 1:
1414                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1415                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1416                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1417                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1418                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1419                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1420                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1421                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1422                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1423                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1424                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1425                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1426                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1427                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1428                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1429                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1430                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1431                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1432                 if (gc_info->v1.header.version_minor >= 1) {
1433                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1434                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1435                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1436                 }
1437                 if (gc_info->v1.header.version_minor >= 2) {
1438                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1439                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1440                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1441                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1442                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1443                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1444                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1445                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1446                 }
1447                 break;
1448         case 2:
1449                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1450                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1451                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1452                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1453                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1454                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1455                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1456                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1457                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1458                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1459                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1460                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1461                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1462                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1463                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1464                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1465                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1466                 break;
1467         default:
1468                 dev_err(adev->dev,
1469                         "Unhandled GC info table %d.%d\n",
1470                         le16_to_cpu(gc_info->v1.header.version_major),
1471                         le16_to_cpu(gc_info->v1.header.version_minor));
1472                 return -EINVAL;
1473         }
1474         return 0;
1475 }
1476
1477 union mall_info {
1478         struct mall_info_v1_0 v1;
1479 };
1480
1481 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1482 {
1483         struct binary_header *bhdr;
1484         union mall_info *mall_info;
1485         u32 u, mall_size_per_umc, m_s_present, half_use;
1486         u64 mall_size;
1487         u16 offset;
1488
1489         if (!adev->mman.discovery_bin) {
1490                 DRM_ERROR("ip discovery uninitialized\n");
1491                 return -EINVAL;
1492         }
1493
1494         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1495         offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1496
1497         if (!offset)
1498                 return 0;
1499
1500         mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1501
1502         switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1503         case 1:
1504                 mall_size = 0;
1505                 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1506                 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1507                 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1508                 for (u = 0; u < adev->gmc.num_umc; u++) {
1509                         if (m_s_present & (1 << u))
1510                                 mall_size += mall_size_per_umc * 2;
1511                         else if (half_use & (1 << u))
1512                                 mall_size += mall_size_per_umc / 2;
1513                         else
1514                                 mall_size += mall_size_per_umc;
1515                 }
1516                 adev->gmc.mall_size = mall_size;
1517                 break;
1518         default:
1519                 dev_err(adev->dev,
1520                         "Unhandled MALL info table %d.%d\n",
1521                         le16_to_cpu(mall_info->v1.header.version_major),
1522                         le16_to_cpu(mall_info->v1.header.version_minor));
1523                 return -EINVAL;
1524         }
1525         return 0;
1526 }
1527
1528 union vcn_info {
1529         struct vcn_info_v1_0 v1;
1530 };
1531
1532 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1533 {
1534         struct binary_header *bhdr;
1535         union vcn_info *vcn_info;
1536         u16 offset;
1537         int v;
1538
1539         if (!adev->mman.discovery_bin) {
1540                 DRM_ERROR("ip discovery uninitialized\n");
1541                 return -EINVAL;
1542         }
1543
1544         /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1545          * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1546          * but that may change in the future with new GPUs so keep this
1547          * check for defensive purposes.
1548          */
1549         if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1550                 dev_err(adev->dev, "invalid vcn instances\n");
1551                 return -EINVAL;
1552         }
1553
1554         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1555         offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1556
1557         if (!offset)
1558                 return 0;
1559
1560         vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1561
1562         switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1563         case 1:
1564                 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1565                  * so this won't overflow.
1566                  */
1567                 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1568                         adev->vcn.vcn_codec_disable_mask[v] =
1569                                 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1570                 }
1571                 break;
1572         default:
1573                 dev_err(adev->dev,
1574                         "Unhandled VCN info table %d.%d\n",
1575                         le16_to_cpu(vcn_info->v1.header.version_major),
1576                         le16_to_cpu(vcn_info->v1.header.version_minor));
1577                 return -EINVAL;
1578         }
1579         return 0;
1580 }
1581
1582 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1583 {
1584         /* what IP to use for this? */
1585         switch (adev->ip_versions[GC_HWIP][0]) {
1586         case IP_VERSION(9, 0, 1):
1587         case IP_VERSION(9, 1, 0):
1588         case IP_VERSION(9, 2, 1):
1589         case IP_VERSION(9, 2, 2):
1590         case IP_VERSION(9, 3, 0):
1591         case IP_VERSION(9, 4, 0):
1592         case IP_VERSION(9, 4, 1):
1593         case IP_VERSION(9, 4, 2):
1594         case IP_VERSION(9, 4, 3):
1595                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1596                 break;
1597         case IP_VERSION(10, 1, 10):
1598         case IP_VERSION(10, 1, 1):
1599         case IP_VERSION(10, 1, 2):
1600         case IP_VERSION(10, 1, 3):
1601         case IP_VERSION(10, 1, 4):
1602         case IP_VERSION(10, 3, 0):
1603         case IP_VERSION(10, 3, 1):
1604         case IP_VERSION(10, 3, 2):
1605         case IP_VERSION(10, 3, 3):
1606         case IP_VERSION(10, 3, 4):
1607         case IP_VERSION(10, 3, 5):
1608         case IP_VERSION(10, 3, 6):
1609         case IP_VERSION(10, 3, 7):
1610                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1611                 break;
1612         case IP_VERSION(11, 0, 0):
1613         case IP_VERSION(11, 0, 1):
1614         case IP_VERSION(11, 0, 2):
1615         case IP_VERSION(11, 0, 3):
1616         case IP_VERSION(11, 0, 4):
1617                 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1618                 break;
1619         default:
1620                 dev_err(adev->dev,
1621                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1622                         adev->ip_versions[GC_HWIP][0]);
1623                 return -EINVAL;
1624         }
1625         return 0;
1626 }
1627
1628 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1629 {
1630         /* use GC or MMHUB IP version */
1631         switch (adev->ip_versions[GC_HWIP][0]) {
1632         case IP_VERSION(9, 0, 1):
1633         case IP_VERSION(9, 1, 0):
1634         case IP_VERSION(9, 2, 1):
1635         case IP_VERSION(9, 2, 2):
1636         case IP_VERSION(9, 3, 0):
1637         case IP_VERSION(9, 4, 0):
1638         case IP_VERSION(9, 4, 1):
1639         case IP_VERSION(9, 4, 2):
1640         case IP_VERSION(9, 4, 3):
1641                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1642                 break;
1643         case IP_VERSION(10, 1, 10):
1644         case IP_VERSION(10, 1, 1):
1645         case IP_VERSION(10, 1, 2):
1646         case IP_VERSION(10, 1, 3):
1647         case IP_VERSION(10, 1, 4):
1648         case IP_VERSION(10, 3, 0):
1649         case IP_VERSION(10, 3, 1):
1650         case IP_VERSION(10, 3, 2):
1651         case IP_VERSION(10, 3, 3):
1652         case IP_VERSION(10, 3, 4):
1653         case IP_VERSION(10, 3, 5):
1654         case IP_VERSION(10, 3, 6):
1655         case IP_VERSION(10, 3, 7):
1656                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1657                 break;
1658         case IP_VERSION(11, 0, 0):
1659         case IP_VERSION(11, 0, 1):
1660         case IP_VERSION(11, 0, 2):
1661         case IP_VERSION(11, 0, 3):
1662         case IP_VERSION(11, 0, 4):
1663                 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1664                 break;
1665         default:
1666                 dev_err(adev->dev,
1667                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1668                         adev->ip_versions[GC_HWIP][0]);
1669                 return -EINVAL;
1670         }
1671         return 0;
1672 }
1673
1674 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1675 {
1676         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1677         case IP_VERSION(4, 0, 0):
1678         case IP_VERSION(4, 0, 1):
1679         case IP_VERSION(4, 1, 0):
1680         case IP_VERSION(4, 1, 1):
1681         case IP_VERSION(4, 3, 0):
1682                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1683                 break;
1684         case IP_VERSION(4, 2, 0):
1685         case IP_VERSION(4, 2, 1):
1686         case IP_VERSION(4, 4, 0):
1687         case IP_VERSION(4, 4, 2):
1688                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1689                 break;
1690         case IP_VERSION(5, 0, 0):
1691         case IP_VERSION(5, 0, 1):
1692         case IP_VERSION(5, 0, 2):
1693         case IP_VERSION(5, 0, 3):
1694         case IP_VERSION(5, 2, 0):
1695         case IP_VERSION(5, 2, 1):
1696                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1697                 break;
1698         case IP_VERSION(6, 0, 0):
1699         case IP_VERSION(6, 0, 1):
1700         case IP_VERSION(6, 0, 2):
1701                 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
1702                 break;
1703         default:
1704                 dev_err(adev->dev,
1705                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1706                         adev->ip_versions[OSSSYS_HWIP][0]);
1707                 return -EINVAL;
1708         }
1709         return 0;
1710 }
1711
1712 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1713 {
1714         switch (adev->ip_versions[MP0_HWIP][0]) {
1715         case IP_VERSION(9, 0, 0):
1716                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1717                 break;
1718         case IP_VERSION(10, 0, 0):
1719         case IP_VERSION(10, 0, 1):
1720                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1721                 break;
1722         case IP_VERSION(11, 0, 0):
1723         case IP_VERSION(11, 0, 2):
1724         case IP_VERSION(11, 0, 4):
1725         case IP_VERSION(11, 0, 5):
1726         case IP_VERSION(11, 0, 9):
1727         case IP_VERSION(11, 0, 7):
1728         case IP_VERSION(11, 0, 11):
1729         case IP_VERSION(11, 0, 12):
1730         case IP_VERSION(11, 0, 13):
1731         case IP_VERSION(11, 5, 0):
1732                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1733                 break;
1734         case IP_VERSION(11, 0, 8):
1735                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1736                 break;
1737         case IP_VERSION(11, 0, 3):
1738         case IP_VERSION(12, 0, 1):
1739                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1740                 break;
1741         case IP_VERSION(13, 0, 0):
1742         case IP_VERSION(13, 0, 1):
1743         case IP_VERSION(13, 0, 2):
1744         case IP_VERSION(13, 0, 3):
1745         case IP_VERSION(13, 0, 5):
1746         case IP_VERSION(13, 0, 6):
1747         case IP_VERSION(13, 0, 7):
1748         case IP_VERSION(13, 0, 8):
1749         case IP_VERSION(13, 0, 10):
1750         case IP_VERSION(13, 0, 11):
1751                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1752                 break;
1753         case IP_VERSION(13, 0, 4):
1754                 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
1755                 break;
1756         default:
1757                 dev_err(adev->dev,
1758                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1759                         adev->ip_versions[MP0_HWIP][0]);
1760                 return -EINVAL;
1761         }
1762         return 0;
1763 }
1764
1765 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1766 {
1767         switch (adev->ip_versions[MP1_HWIP][0]) {
1768         case IP_VERSION(9, 0, 0):
1769         case IP_VERSION(10, 0, 0):
1770         case IP_VERSION(10, 0, 1):
1771         case IP_VERSION(11, 0, 2):
1772                 if (adev->asic_type == CHIP_ARCTURUS)
1773                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1774                 else
1775                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1776                 break;
1777         case IP_VERSION(11, 0, 0):
1778         case IP_VERSION(11, 0, 5):
1779         case IP_VERSION(11, 0, 9):
1780         case IP_VERSION(11, 0, 7):
1781         case IP_VERSION(11, 0, 8):
1782         case IP_VERSION(11, 0, 11):
1783         case IP_VERSION(11, 0, 12):
1784         case IP_VERSION(11, 0, 13):
1785         case IP_VERSION(11, 5, 0):
1786                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1787                 break;
1788         case IP_VERSION(12, 0, 0):
1789         case IP_VERSION(12, 0, 1):
1790                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1791                 break;
1792         case IP_VERSION(13, 0, 0):
1793         case IP_VERSION(13, 0, 1):
1794         case IP_VERSION(13, 0, 2):
1795         case IP_VERSION(13, 0, 3):
1796         case IP_VERSION(13, 0, 4):
1797         case IP_VERSION(13, 0, 5):
1798         case IP_VERSION(13, 0, 7):
1799         case IP_VERSION(13, 0, 8):
1800         case IP_VERSION(13, 0, 10):
1801         case IP_VERSION(13, 0, 11):
1802                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1803                 break;
1804         default:
1805                 dev_err(adev->dev,
1806                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1807                         adev->ip_versions[MP1_HWIP][0]);
1808                 return -EINVAL;
1809         }
1810         return 0;
1811 }
1812
1813 #if defined(CONFIG_DRM_AMD_DC)
1814 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
1815 {
1816         amdgpu_device_set_sriov_virtual_display(adev);
1817         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1818 }
1819 #endif
1820
1821 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1822 {
1823         if (adev->enable_virtual_display) {
1824                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1825                 return 0;
1826         }
1827
1828         if (!amdgpu_device_has_dc_support(adev))
1829                 return 0;
1830
1831 #if defined(CONFIG_DRM_AMD_DC)
1832         if (adev->ip_versions[DCE_HWIP][0]) {
1833                 switch (adev->ip_versions[DCE_HWIP][0]) {
1834                 case IP_VERSION(1, 0, 0):
1835                 case IP_VERSION(1, 0, 1):
1836                 case IP_VERSION(2, 0, 2):
1837                 case IP_VERSION(2, 0, 0):
1838                 case IP_VERSION(2, 0, 3):
1839                 case IP_VERSION(2, 1, 0):
1840                 case IP_VERSION(3, 0, 0):
1841                 case IP_VERSION(3, 0, 2):
1842                 case IP_VERSION(3, 0, 3):
1843                 case IP_VERSION(3, 0, 1):
1844                 case IP_VERSION(3, 1, 2):
1845                 case IP_VERSION(3, 1, 3):
1846                 case IP_VERSION(3, 1, 4):
1847                 case IP_VERSION(3, 1, 5):
1848                 case IP_VERSION(3, 1, 6):
1849                 case IP_VERSION(3, 2, 0):
1850                 case IP_VERSION(3, 2, 1):
1851                         if (amdgpu_sriov_vf(adev))
1852                                 amdgpu_discovery_set_sriov_display(adev);
1853                         else
1854                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1855                         break;
1856                 default:
1857                         dev_err(adev->dev,
1858                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1859                                 adev->ip_versions[DCE_HWIP][0]);
1860                         return -EINVAL;
1861                 }
1862         } else if (adev->ip_versions[DCI_HWIP][0]) {
1863                 switch (adev->ip_versions[DCI_HWIP][0]) {
1864                 case IP_VERSION(12, 0, 0):
1865                 case IP_VERSION(12, 0, 1):
1866                 case IP_VERSION(12, 1, 0):
1867                         if (amdgpu_sriov_vf(adev))
1868                                 amdgpu_discovery_set_sriov_display(adev);
1869                         else
1870                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1871                         break;
1872                 default:
1873                         dev_err(adev->dev,
1874                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1875                                 adev->ip_versions[DCI_HWIP][0]);
1876                         return -EINVAL;
1877                 }
1878         }
1879 #endif
1880         return 0;
1881 }
1882
1883 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1884 {
1885         switch (adev->ip_versions[GC_HWIP][0]) {
1886         case IP_VERSION(9, 0, 1):
1887         case IP_VERSION(9, 1, 0):
1888         case IP_VERSION(9, 2, 1):
1889         case IP_VERSION(9, 2, 2):
1890         case IP_VERSION(9, 3, 0):
1891         case IP_VERSION(9, 4, 0):
1892         case IP_VERSION(9, 4, 1):
1893         case IP_VERSION(9, 4, 2):
1894                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1895                 break;
1896         case IP_VERSION(10, 1, 10):
1897         case IP_VERSION(10, 1, 2):
1898         case IP_VERSION(10, 1, 1):
1899         case IP_VERSION(10, 1, 3):
1900         case IP_VERSION(10, 1, 4):
1901         case IP_VERSION(10, 3, 0):
1902         case IP_VERSION(10, 3, 2):
1903         case IP_VERSION(10, 3, 1):
1904         case IP_VERSION(10, 3, 4):
1905         case IP_VERSION(10, 3, 5):
1906         case IP_VERSION(10, 3, 6):
1907         case IP_VERSION(10, 3, 3):
1908         case IP_VERSION(10, 3, 7):
1909                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1910                 break;
1911         case IP_VERSION(11, 0, 0):
1912         case IP_VERSION(11, 0, 1):
1913         case IP_VERSION(11, 0, 2):
1914         case IP_VERSION(11, 0, 3):
1915         case IP_VERSION(11, 0, 4):
1916                 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
1917                 break;
1918         default:
1919                 dev_err(adev->dev,
1920                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1921                         adev->ip_versions[GC_HWIP][0]);
1922                 return -EINVAL;
1923         }
1924         return 0;
1925 }
1926
1927 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1928 {
1929         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1930         case IP_VERSION(4, 0, 0):
1931         case IP_VERSION(4, 0, 1):
1932         case IP_VERSION(4, 1, 0):
1933         case IP_VERSION(4, 1, 1):
1934         case IP_VERSION(4, 1, 2):
1935         case IP_VERSION(4, 2, 0):
1936         case IP_VERSION(4, 2, 2):
1937         case IP_VERSION(4, 4, 0):
1938                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1939                 break;
1940         case IP_VERSION(4, 4, 2):
1941                 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
1942                 break;
1943         case IP_VERSION(5, 0, 0):
1944         case IP_VERSION(5, 0, 1):
1945         case IP_VERSION(5, 0, 2):
1946         case IP_VERSION(5, 0, 5):
1947                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1948                 break;
1949         case IP_VERSION(5, 2, 0):
1950         case IP_VERSION(5, 2, 2):
1951         case IP_VERSION(5, 2, 4):
1952         case IP_VERSION(5, 2, 5):
1953         case IP_VERSION(5, 2, 6):
1954         case IP_VERSION(5, 2, 3):
1955         case IP_VERSION(5, 2, 1):
1956         case IP_VERSION(5, 2, 7):
1957                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1958                 break;
1959         case IP_VERSION(6, 0, 0):
1960         case IP_VERSION(6, 0, 1):
1961         case IP_VERSION(6, 0, 2):
1962         case IP_VERSION(6, 0, 3):
1963                 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
1964                 break;
1965         default:
1966                 dev_err(adev->dev,
1967                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1968                         adev->ip_versions[SDMA0_HWIP][0]);
1969                 return -EINVAL;
1970         }
1971         return 0;
1972 }
1973
1974 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1975 {
1976         if (adev->ip_versions[VCE_HWIP][0]) {
1977                 switch (adev->ip_versions[UVD_HWIP][0]) {
1978                 case IP_VERSION(7, 0, 0):
1979                 case IP_VERSION(7, 2, 0):
1980                         /* UVD is not supported on vega20 SR-IOV */
1981                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1982                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1983                         break;
1984                 default:
1985                         dev_err(adev->dev,
1986                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1987                                 adev->ip_versions[UVD_HWIP][0]);
1988                         return -EINVAL;
1989                 }
1990                 switch (adev->ip_versions[VCE_HWIP][0]) {
1991                 case IP_VERSION(4, 0, 0):
1992                 case IP_VERSION(4, 1, 0):
1993                         /* VCE is not supported on vega20 SR-IOV */
1994                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1995                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1996                         break;
1997                 default:
1998                         dev_err(adev->dev,
1999                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2000                                 adev->ip_versions[VCE_HWIP][0]);
2001                         return -EINVAL;
2002                 }
2003         } else {
2004                 switch (adev->ip_versions[UVD_HWIP][0]) {
2005                 case IP_VERSION(1, 0, 0):
2006                 case IP_VERSION(1, 0, 1):
2007                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2008                         break;
2009                 case IP_VERSION(2, 0, 0):
2010                 case IP_VERSION(2, 0, 2):
2011                 case IP_VERSION(2, 2, 0):
2012                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2013                         if (!amdgpu_sriov_vf(adev))
2014                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2015                         break;
2016                 case IP_VERSION(2, 0, 3):
2017                         break;
2018                 case IP_VERSION(2, 5, 0):
2019                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2020                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2021                         break;
2022                 case IP_VERSION(2, 6, 0):
2023                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2024                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2025                         break;
2026                 case IP_VERSION(3, 0, 0):
2027                 case IP_VERSION(3, 0, 16):
2028                 case IP_VERSION(3, 1, 1):
2029                 case IP_VERSION(3, 1, 2):
2030                 case IP_VERSION(3, 0, 2):
2031                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2032                         if (!amdgpu_sriov_vf(adev))
2033                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2034                         break;
2035                 case IP_VERSION(3, 0, 33):
2036                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2037                         break;
2038                 case IP_VERSION(4, 0, 0):
2039                 case IP_VERSION(4, 0, 2):
2040                 case IP_VERSION(4, 0, 4):
2041                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2042                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2043                         break;
2044                 case IP_VERSION(4, 0, 3):
2045                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2046                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2047                         break;
2048                 default:
2049                         dev_err(adev->dev,
2050                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2051                                 adev->ip_versions[UVD_HWIP][0]);
2052                         return -EINVAL;
2053                 }
2054         }
2055         return 0;
2056 }
2057
2058 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2059 {
2060         switch (adev->ip_versions[GC_HWIP][0]) {
2061         case IP_VERSION(10, 1, 10):
2062         case IP_VERSION(10, 1, 1):
2063         case IP_VERSION(10, 1, 2):
2064         case IP_VERSION(10, 1, 3):
2065         case IP_VERSION(10, 1, 4):
2066         case IP_VERSION(10, 3, 0):
2067         case IP_VERSION(10, 3, 1):
2068         case IP_VERSION(10, 3, 2):
2069         case IP_VERSION(10, 3, 3):
2070         case IP_VERSION(10, 3, 4):
2071         case IP_VERSION(10, 3, 5):
2072         case IP_VERSION(10, 3, 6):
2073                 if (amdgpu_mes) {
2074                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
2075                         adev->enable_mes = true;
2076                         if (amdgpu_mes_kiq)
2077                                 adev->enable_mes_kiq = true;
2078                 }
2079                 break;
2080         case IP_VERSION(11, 0, 0):
2081         case IP_VERSION(11, 0, 1):
2082         case IP_VERSION(11, 0, 2):
2083         case IP_VERSION(11, 0, 3):
2084         case IP_VERSION(11, 0, 4):
2085                 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2086                 adev->enable_mes = true;
2087                 adev->enable_mes_kiq = true;
2088                 break;
2089         default:
2090                 break;
2091         }
2092         return 0;
2093 }
2094
2095 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2096 {
2097         switch (adev->ip_versions[GC_HWIP][0]) {
2098         case IP_VERSION(9, 4, 3):
2099                 aqua_vanjaram_init_soc_config(adev);
2100                 break;
2101         default:
2102                 break;
2103         }
2104 }
2105
2106 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2107 {
2108         int r;
2109
2110         switch (adev->asic_type) {
2111         case CHIP_VEGA10:
2112                 vega10_reg_base_init(adev);
2113                 adev->sdma.num_instances = 2;
2114                 adev->gmc.num_umc = 4;
2115                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2116                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2117                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2118                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2119                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2120                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2121                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2122                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2123                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2124                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2125                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2126                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2127                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2128                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2129                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2130                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2131                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2132                 break;
2133         case CHIP_VEGA12:
2134                 vega10_reg_base_init(adev);
2135                 adev->sdma.num_instances = 2;
2136                 adev->gmc.num_umc = 4;
2137                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2138                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2139                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2140                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2141                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2142                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2143                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2144                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2145                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2146                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2147                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2148                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2149                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2150                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2151                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2152                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2153                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2154                 break;
2155         case CHIP_RAVEN:
2156                 vega10_reg_base_init(adev);
2157                 adev->sdma.num_instances = 1;
2158                 adev->vcn.num_vcn_inst = 1;
2159                 adev->gmc.num_umc = 2;
2160                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2161                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2162                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2163                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2164                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2165                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2166                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2167                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2168                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2169                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2170                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2171                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2172                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2173                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2174                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2175                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2176                 } else {
2177                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2178                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2179                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2180                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2181                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2182                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2183                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2184                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2185                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2186                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2187                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2188                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2189                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2190                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2191                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2192                 }
2193                 break;
2194         case CHIP_VEGA20:
2195                 vega20_reg_base_init(adev);
2196                 adev->sdma.num_instances = 2;
2197                 adev->gmc.num_umc = 8;
2198                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2199                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2200                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2201                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2202                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2203                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2204                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2205                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2206                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2207                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2208                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2209                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2210                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2211                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2212                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2213                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2214                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2215                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2216                 break;
2217         case CHIP_ARCTURUS:
2218                 arct_reg_base_init(adev);
2219                 adev->sdma.num_instances = 8;
2220                 adev->vcn.num_vcn_inst = 2;
2221                 adev->gmc.num_umc = 8;
2222                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2223                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2224                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2225                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2226                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2227                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2228                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2229                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2230                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2231                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2232                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2233                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2234                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2235                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2236                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2237                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2238                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2239                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2240                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2241                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2242                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2243                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2244                 break;
2245         case CHIP_ALDEBARAN:
2246                 aldebaran_reg_base_init(adev);
2247                 adev->sdma.num_instances = 5;
2248                 adev->vcn.num_vcn_inst = 2;
2249                 adev->gmc.num_umc = 4;
2250                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2251                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2252                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2253                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2254                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2255                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2256                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2257                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2258                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2259                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2260                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2261                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2262                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2263                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2264                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2265                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2266                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2267                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2268                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2269                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2270                 break;
2271         default:
2272                 r = amdgpu_discovery_reg_base_init(adev);
2273                 if (r)
2274                         return -EINVAL;
2275
2276                 amdgpu_discovery_harvest_ip(adev);
2277                 amdgpu_discovery_get_gfx_info(adev);
2278                 amdgpu_discovery_get_mall_info(adev);
2279                 amdgpu_discovery_get_vcn_info(adev);
2280                 break;
2281         }
2282
2283         amdgpu_discovery_init_soc_config(adev);
2284         amdgpu_discovery_sysfs_init(adev);
2285
2286         switch (adev->ip_versions[GC_HWIP][0]) {
2287         case IP_VERSION(9, 0, 1):
2288         case IP_VERSION(9, 2, 1):
2289         case IP_VERSION(9, 4, 0):
2290         case IP_VERSION(9, 4, 1):
2291         case IP_VERSION(9, 4, 2):
2292         case IP_VERSION(9, 4, 3):
2293                 adev->family = AMDGPU_FAMILY_AI;
2294                 break;
2295         case IP_VERSION(9, 1, 0):
2296         case IP_VERSION(9, 2, 2):
2297         case IP_VERSION(9, 3, 0):
2298                 adev->family = AMDGPU_FAMILY_RV;
2299                 break;
2300         case IP_VERSION(10, 1, 10):
2301         case IP_VERSION(10, 1, 1):
2302         case IP_VERSION(10, 1, 2):
2303         case IP_VERSION(10, 1, 3):
2304         case IP_VERSION(10, 1, 4):
2305         case IP_VERSION(10, 3, 0):
2306         case IP_VERSION(10, 3, 2):
2307         case IP_VERSION(10, 3, 4):
2308         case IP_VERSION(10, 3, 5):
2309                 adev->family = AMDGPU_FAMILY_NV;
2310                 break;
2311         case IP_VERSION(10, 3, 1):
2312                 adev->family = AMDGPU_FAMILY_VGH;
2313                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
2314                 break;
2315         case IP_VERSION(10, 3, 3):
2316                 adev->family = AMDGPU_FAMILY_YC;
2317                 break;
2318         case IP_VERSION(10, 3, 6):
2319                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2320                 break;
2321         case IP_VERSION(10, 3, 7):
2322                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2323                 break;
2324         case IP_VERSION(11, 0, 0):
2325         case IP_VERSION(11, 0, 2):
2326         case IP_VERSION(11, 0, 3):
2327                 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2328                 break;
2329         case IP_VERSION(11, 0, 1):
2330         case IP_VERSION(11, 0, 4):
2331                 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2332                 break;
2333         default:
2334                 return -EINVAL;
2335         }
2336
2337         switch (adev->ip_versions[GC_HWIP][0]) {
2338         case IP_VERSION(9, 1, 0):
2339         case IP_VERSION(9, 2, 2):
2340         case IP_VERSION(9, 3, 0):
2341         case IP_VERSION(10, 1, 3):
2342         case IP_VERSION(10, 1, 4):
2343         case IP_VERSION(10, 3, 1):
2344         case IP_VERSION(10, 3, 3):
2345         case IP_VERSION(10, 3, 6):
2346         case IP_VERSION(10, 3, 7):
2347         case IP_VERSION(11, 0, 1):
2348         case IP_VERSION(11, 0, 4):
2349                 adev->flags |= AMD_IS_APU;
2350                 break;
2351         default:
2352                 break;
2353         }
2354
2355         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
2356                 adev->gmc.xgmi.supported = true;
2357
2358         /* set NBIO version */
2359         switch (adev->ip_versions[NBIO_HWIP][0]) {
2360         case IP_VERSION(6, 1, 0):
2361         case IP_VERSION(6, 2, 0):
2362                 adev->nbio.funcs = &nbio_v6_1_funcs;
2363                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2364                 break;
2365         case IP_VERSION(7, 0, 0):
2366         case IP_VERSION(7, 0, 1):
2367         case IP_VERSION(2, 5, 0):
2368                 adev->nbio.funcs = &nbio_v7_0_funcs;
2369                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2370                 break;
2371         case IP_VERSION(7, 4, 0):
2372         case IP_VERSION(7, 4, 1):
2373         case IP_VERSION(7, 4, 4):
2374                 adev->nbio.funcs = &nbio_v7_4_funcs;
2375                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2376                 break;
2377         case IP_VERSION(7, 9, 0):
2378                 adev->nbio.funcs = &nbio_v7_9_funcs;
2379                 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
2380                 break;
2381         case IP_VERSION(7, 2, 0):
2382         case IP_VERSION(7, 2, 1):
2383         case IP_VERSION(7, 3, 0):
2384         case IP_VERSION(7, 5, 0):
2385         case IP_VERSION(7, 5, 1):
2386                 adev->nbio.funcs = &nbio_v7_2_funcs;
2387                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2388                 break;
2389         case IP_VERSION(2, 1, 1):
2390         case IP_VERSION(2, 3, 0):
2391         case IP_VERSION(2, 3, 1):
2392         case IP_VERSION(2, 3, 2):
2393         case IP_VERSION(3, 3, 0):
2394         case IP_VERSION(3, 3, 1):
2395         case IP_VERSION(3, 3, 2):
2396         case IP_VERSION(3, 3, 3):
2397                 adev->nbio.funcs = &nbio_v2_3_funcs;
2398                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2399                 break;
2400         case IP_VERSION(4, 3, 0):
2401         case IP_VERSION(4, 3, 1):
2402                 if (amdgpu_sriov_vf(adev))
2403                         adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
2404                 else
2405                         adev->nbio.funcs = &nbio_v4_3_funcs;
2406                 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2407                 break;
2408         case IP_VERSION(7, 7, 0):
2409         case IP_VERSION(7, 7, 1):
2410                 adev->nbio.funcs = &nbio_v7_7_funcs;
2411                 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2412                 break;
2413         default:
2414                 break;
2415         }
2416
2417         switch (adev->ip_versions[HDP_HWIP][0]) {
2418         case IP_VERSION(4, 0, 0):
2419         case IP_VERSION(4, 0, 1):
2420         case IP_VERSION(4, 1, 0):
2421         case IP_VERSION(4, 1, 1):
2422         case IP_VERSION(4, 1, 2):
2423         case IP_VERSION(4, 2, 0):
2424         case IP_VERSION(4, 2, 1):
2425         case IP_VERSION(4, 4, 0):
2426         case IP_VERSION(4, 4, 2):
2427                 adev->hdp.funcs = &hdp_v4_0_funcs;
2428                 break;
2429         case IP_VERSION(5, 0, 0):
2430         case IP_VERSION(5, 0, 1):
2431         case IP_VERSION(5, 0, 2):
2432         case IP_VERSION(5, 0, 3):
2433         case IP_VERSION(5, 0, 4):
2434         case IP_VERSION(5, 2, 0):
2435                 adev->hdp.funcs = &hdp_v5_0_funcs;
2436                 break;
2437         case IP_VERSION(5, 2, 1):
2438                 adev->hdp.funcs = &hdp_v5_2_funcs;
2439                 break;
2440         case IP_VERSION(6, 0, 0):
2441         case IP_VERSION(6, 0, 1):
2442                 adev->hdp.funcs = &hdp_v6_0_funcs;
2443                 break;
2444         default:
2445                 break;
2446         }
2447
2448         switch (adev->ip_versions[DF_HWIP][0]) {
2449         case IP_VERSION(3, 6, 0):
2450         case IP_VERSION(3, 6, 1):
2451         case IP_VERSION(3, 6, 2):
2452                 adev->df.funcs = &df_v3_6_funcs;
2453                 break;
2454         case IP_VERSION(2, 1, 0):
2455         case IP_VERSION(2, 1, 1):
2456         case IP_VERSION(2, 5, 0):
2457         case IP_VERSION(3, 5, 1):
2458         case IP_VERSION(3, 5, 2):
2459                 adev->df.funcs = &df_v1_7_funcs;
2460                 break;
2461         case IP_VERSION(4, 3, 0):
2462                 adev->df.funcs = &df_v4_3_funcs;
2463                 break;
2464         default:
2465                 break;
2466         }
2467
2468         switch (adev->ip_versions[SMUIO_HWIP][0]) {
2469         case IP_VERSION(9, 0, 0):
2470         case IP_VERSION(9, 0, 1):
2471         case IP_VERSION(10, 0, 0):
2472         case IP_VERSION(10, 0, 1):
2473         case IP_VERSION(10, 0, 2):
2474                 adev->smuio.funcs = &smuio_v9_0_funcs;
2475                 break;
2476         case IP_VERSION(11, 0, 0):
2477         case IP_VERSION(11, 0, 2):
2478         case IP_VERSION(11, 0, 3):
2479         case IP_VERSION(11, 0, 4):
2480         case IP_VERSION(11, 0, 7):
2481         case IP_VERSION(11, 0, 8):
2482                 adev->smuio.funcs = &smuio_v11_0_funcs;
2483                 break;
2484         case IP_VERSION(11, 0, 6):
2485         case IP_VERSION(11, 0, 10):
2486         case IP_VERSION(11, 0, 11):
2487         case IP_VERSION(11, 5, 0):
2488         case IP_VERSION(13, 0, 1):
2489         case IP_VERSION(13, 0, 9):
2490         case IP_VERSION(13, 0, 10):
2491                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2492                 break;
2493         case IP_VERSION(13, 0, 2):
2494                 adev->smuio.funcs = &smuio_v13_0_funcs;
2495                 break;
2496         case IP_VERSION(13, 0, 3):
2497                 adev->smuio.funcs = &smuio_v13_0_3_funcs;
2498                 break;
2499         case IP_VERSION(13, 0, 6):
2500         case IP_VERSION(13, 0, 8):
2501                 adev->smuio.funcs = &smuio_v13_0_6_funcs;
2502                 break;
2503         default:
2504                 break;
2505         }
2506
2507         switch (adev->ip_versions[LSDMA_HWIP][0]) {
2508         case IP_VERSION(6, 0, 0):
2509         case IP_VERSION(6, 0, 1):
2510         case IP_VERSION(6, 0, 2):
2511         case IP_VERSION(6, 0, 3):
2512                 adev->lsdma.funcs = &lsdma_v6_0_funcs;
2513                 break;
2514         default:
2515                 break;
2516         }
2517
2518         r = amdgpu_discovery_set_common_ip_blocks(adev);
2519         if (r)
2520                 return r;
2521
2522         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2523         if (r)
2524                 return r;
2525
2526         /* For SR-IOV, PSP needs to be initialized before IH */
2527         if (amdgpu_sriov_vf(adev)) {
2528                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2529                 if (r)
2530                         return r;
2531                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2532                 if (r)
2533                         return r;
2534         } else {
2535                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2536                 if (r)
2537                         return r;
2538
2539                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2540                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2541                         if (r)
2542                                 return r;
2543                 }
2544         }
2545
2546         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2547                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2548                 if (r)
2549                         return r;
2550         }
2551
2552         r = amdgpu_discovery_set_display_ip_blocks(adev);
2553         if (r)
2554                 return r;
2555
2556         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2557         if (r)
2558                 return r;
2559
2560         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2561         if (r)
2562                 return r;
2563
2564         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2565              !amdgpu_sriov_vf(adev)) ||
2566             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
2567                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2568                 if (r)
2569                         return r;
2570         }
2571
2572         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2573         if (r)
2574                 return r;
2575
2576         r = amdgpu_discovery_set_mes_ip_blocks(adev);
2577         if (r)
2578                 return r;
2579
2580         return 0;
2581 }
2582