arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/spram.h>
  28 #include <asm/uaccess.h>
  29
  30 static int __cpuinitdata mips_fpu_disabled;
  31
  32 static int __init fpu_disable(char *s)
  33 {
  34         cpu_data[0].options &= ~MIPS_CPU_FPU;
  35         mips_fpu_disabled = 1;
  36
  37         return 1;
  38 }
  39
  40 __setup("nofpu", fpu_disable);
  41
  42 int __cpuinitdata mips_dsp_disabled;
  43
  44 static int __init dsp_disable(char *s)
  45 {
  46         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  47         mips_dsp_disabled = 1;
  48
  49         return 1;
  50 }
  51
  52 __setup("nodsp", dsp_disable);
  53
  54 static inline void check_errata(void)
  55 {
  56         struct cpuinfo_mips *c = &current_cpu_data;
  57
  58         switch (c->cputype) {
  59         case CPU_34K:
  60                 /*
  61                  * Erratum "RPS May Cause Incorrect Instruction Execution"
  62                  * This code only handles VPE0, any SMP/SMTC/RTOS code
  63                  * making use of VPE1 will be responsable for that VPE.
  64                  */
  65                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  66                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  67                 break;
  68         default:
  69                 break;
  70         }
  71 }
  72
  73 void __init check_bugs32(void)
  74 {
  75         check_errata();
  76 }
  77
  78 /*
  79  * Probe whether cpu has config register by trying to play with
  80  * alternate cache bit and see whether it matters.
  81  * It's used by cpu_probe to distinguish between R3000A and R3081.
  82  */
  83 static inline int cpu_has_confreg(void)
  84 {
  85 #ifdef CONFIG_CPU_R3000
  86         extern unsigned long r3k_cache_size(unsigned long);
  87         unsigned long size1, size2;
  88         unsigned long cfg = read_c0_conf();
  89
  90         size1 = r3k_cache_size(ST0_ISC);
  91         write_c0_conf(cfg ^ R30XX_CONF_AC);
  92         size2 = r3k_cache_size(ST0_ISC);
  93         write_c0_conf(cfg);
  94         return size1 != size2;
  95 #else
  96         return 0;
  97 #endif
  98 }
  99
 100 static inline void set_elf_platform(int cpu, const char *plat)
 101 {
 102         if (cpu == 0)
 103                 __elf_platform = plat;
 104 }
 105
 106 /*
 107  * Get the FPU Implementation/Revision.
 108  */
 109 static inline unsigned long cpu_get_fpu_id(void)
 110 {
 111         unsigned long tmp, fpu_id;
 112
 113         tmp = read_c0_status();
 114         __enable_fpu();
 115         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 116         write_c0_status(tmp);
 117         return fpu_id;
 118 }
 119
 120 /*
 121  * Check the CPU has an FPU the official way.
 122  */
 123 static inline int __cpu_has_fpu(void)
 124 {
 125         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 126 }
 127
 128 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 129 {
 130 #ifdef __NEED_VMBITS_PROBE
 131         write_c0_entryhi(0x3fffffffffffe000ULL);
 132         back_to_back_c0_hazard();
 133         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 134 #endif
 135 }
 136
 137 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
 138 {
 139         switch (isa) {
 140         case MIPS_CPU_ISA_M64R2:
 141                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 142         case MIPS_CPU_ISA_M64R1:
 143                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 144         case MIPS_CPU_ISA_V:
 145                 c->isa_level |= MIPS_CPU_ISA_V;
 146         case MIPS_CPU_ISA_IV:
 147                 c->isa_level |= MIPS_CPU_ISA_IV;
 148         case MIPS_CPU_ISA_III:
 149                 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
 150                                 MIPS_CPU_ISA_III;
 151                 break;
 152
 153         case MIPS_CPU_ISA_M32R2:
 154                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 155         case MIPS_CPU_ISA_M32R1:
 156                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 157         case MIPS_CPU_ISA_II:
 158                 c->isa_level |= MIPS_CPU_ISA_II;
 159         case MIPS_CPU_ISA_I:
 160                 c->isa_level |= MIPS_CPU_ISA_I;
 161                 break;
 162         }
 163 }
 164
 165 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 166         "Unsupported ISA type, c0.config0: %d.";
 167
 168 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 169 {
 170         unsigned int config0;
 171         int isa;
 172
 173         config0 = read_c0_config();
 174
 175         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 176                 c->options |= MIPS_CPU_TLB;
 177         isa = (config0 & MIPS_CONF_AT) >> 13;
 178         switch (isa) {
 179         case 0:
 180                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 181                 case 0:
 182                         set_isa(c, MIPS_CPU_ISA_M32R1);
 183                         break;
 184                 case 1:
 185                         set_isa(c, MIPS_CPU_ISA_M32R2);
 186                         break;
 187                 default:
 188                         goto unknown;
 189                 }
 190                 break;
 191         case 2:
 192                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 193                 case 0:
 194                         set_isa(c, MIPS_CPU_ISA_M64R1);
 195                         break;
 196                 case 1:
 197                         set_isa(c, MIPS_CPU_ISA_M64R2);
 198                         break;
 199                 default:
 200                         goto unknown;
 201                 }
 202                 break;
 203         default:
 204                 goto unknown;
 205         }
 206
 207         return config0 & MIPS_CONF_M;
 208
 209 unknown:
 210         panic(unknown_isa, config0);
 211 }
 212
 213 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 214 {
 215         unsigned int config1;
 216
 217         config1 = read_c0_config1();
 218
 219         if (config1 & MIPS_CONF1_MD)
 220                 c->ases |= MIPS_ASE_MDMX;
 221         if (config1 & MIPS_CONF1_WR)
 222                 c->options |= MIPS_CPU_WATCH;
 223         if (config1 & MIPS_CONF1_CA)
 224                 c->ases |= MIPS_ASE_MIPS16;
 225         if (config1 & MIPS_CONF1_EP)
 226                 c->options |= MIPS_CPU_EJTAG;
 227         if (config1 & MIPS_CONF1_FP) {
 228                 c->options |= MIPS_CPU_FPU;
 229                 c->options |= MIPS_CPU_32FPR;
 230         }
 231         if (cpu_has_tlb)
 232                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 233
 234         return config1 & MIPS_CONF_M;
 235 }
 236
 237 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 238 {
 239         unsigned int config2;
 240
 241         config2 = read_c0_config2();
 242
 243         if (config2 & MIPS_CONF2_SL)
 244                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 245
 246         return config2 & MIPS_CONF_M;
 247 }
 248
 249 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 250 {
 251         unsigned int config3;
 252
 253         config3 = read_c0_config3();
 254
 255         if (config3 & MIPS_CONF3_SM) {
 256                 c->ases |= MIPS_ASE_SMARTMIPS;
 257                 c->options |= MIPS_CPU_RIXI;
 258         }
 259         if (config3 & MIPS_CONF3_RXI)
 260                 c->options |= MIPS_CPU_RIXI;
 261         if (config3 & MIPS_CONF3_DSP)
 262                 c->ases |= MIPS_ASE_DSP;
 263         if (config3 & MIPS_CONF3_DSP2P)
 264                 c->ases |= MIPS_ASE_DSP2P;
 265         if (config3 & MIPS_CONF3_VINT)
 266                 c->options |= MIPS_CPU_VINT;
 267         if (config3 & MIPS_CONF3_VEIC)
 268                 c->options |= MIPS_CPU_VEIC;
 269         if (config3 & MIPS_CONF3_MT)
 270                 c->ases |= MIPS_ASE_MIPSMT;
 271         if (config3 & MIPS_CONF3_ULRI)
 272                 c->options |= MIPS_CPU_ULRI;
 273         if (config3 & MIPS_CONF3_ISA)
 274                 c->options |= MIPS_CPU_MICROMIPS;
 275 #ifdef CONFIG_CPU_MICROMIPS
 276         write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
 277 #endif
 278         if (config3 & MIPS_CONF3_VZ)
 279                 c->ases |= MIPS_ASE_VZ;
 280
 281         return config3 & MIPS_CONF_M;
 282 }
 283
 284 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 285 {
 286         unsigned int config4;
 287
 288         config4 = read_c0_config4();
 289
 290         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 291             && cpu_has_tlb)
 292                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 293
 294         c->kscratch_mask = (config4 >> 16) & 0xff;
 295
 296         return config4 & MIPS_CONF_M;
 297 }
 298
 299 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 300 {
 301         int ok;
 302
 303         /* MIPS32 or MIPS64 compliant CPU.  */
 304         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 305                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 306
 307         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 308
 309         ok = decode_config0(c);                 /* Read Config registers.  */
 310         BUG_ON(!ok);                            /* Arch spec violation!  */
 311         if (ok)
 312                 ok = decode_config1(c);
 313         if (ok)
 314                 ok = decode_config2(c);
 315         if (ok)
 316                 ok = decode_config3(c);
 317         if (ok)
 318                 ok = decode_config4(c);
 319
 320         mips_probe_watch_registers(c);
 321
 322         if (cpu_has_mips_r2)
 323                 c->core = read_c0_ebase() & 0x3ff;
 324 }
 325
 326 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 327                 | MIPS_CPU_COUNTER)
 328
 329 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 330 {
 331         switch (c->processor_id & 0xff00) {
 332         case PRID_IMP_R2000:
 333                 c->cputype = CPU_R2000;
 334                 __cpu_name[cpu] = "R2000";
 335                 set_isa(c, MIPS_CPU_ISA_I);
 336                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 337                              MIPS_CPU_NOFPUEX;
 338                 if (__cpu_has_fpu())
 339                         c->options |= MIPS_CPU_FPU;
 340                 c->tlbsize = 64;
 341                 break;
 342         case PRID_IMP_R3000:
 343                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 344                         if (cpu_has_confreg()) {
 345                                 c->cputype = CPU_R3081E;
 346                                 __cpu_name[cpu] = "R3081";
 347                         } else {
 348                                 c->cputype = CPU_R3000A;
 349                                 __cpu_name[cpu] = "R3000A";
 350                         }
 351                 } else {
 352                         c->cputype = CPU_R3000;
 353                         __cpu_name[cpu] = "R3000";
 354                 }
 355                 set_isa(c, MIPS_CPU_ISA_I);
 356                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 357                              MIPS_CPU_NOFPUEX;
 358                 if (__cpu_has_fpu())
 359                         c->options |= MIPS_CPU_FPU;
 360                 c->tlbsize = 64;
 361                 break;
 362         case PRID_IMP_R4000:
 363                 if (read_c0_config() & CONF_SC) {
 364                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 365                                 c->cputype = CPU_R4400PC;
 366                                 __cpu_name[cpu] = "R4400PC";
 367                         } else {
 368                                 c->cputype = CPU_R4000PC;
 369                                 __cpu_name[cpu] = "R4000PC";
 370                         }
 371                 } else {
 372                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 373                                 c->cputype = CPU_R4400SC;
 374                                 __cpu_name[cpu] = "R4400SC";
 375                         } else {
 376                                 c->cputype = CPU_R4000SC;
 377                                 __cpu_name[cpu] = "R4000SC";
 378                         }
 379                 }
 380
 381                 set_isa(c, MIPS_CPU_ISA_III);
 382                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 383                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 384                              MIPS_CPU_LLSC;
 385                 c->tlbsize = 48;
 386                 break;
 387         case PRID_IMP_VR41XX:
 388                 set_isa(c, MIPS_CPU_ISA_III);
 389                 c->options = R4K_OPTS;
 390                 c->tlbsize = 32;
 391                 switch (c->processor_id & 0xf0) {
 392                 case PRID_REV_VR4111:
 393                         c->cputype = CPU_VR4111;
 394                         __cpu_name[cpu] = "NEC VR4111";
 395                         break;
 396                 case PRID_REV_VR4121:
 397                         c->cputype = CPU_VR4121;
 398                         __cpu_name[cpu] = "NEC VR4121";
 399                         break;
 400                 case PRID_REV_VR4122:
 401                         if ((c->processor_id & 0xf) < 0x3) {
 402                                 c->cputype = CPU_VR4122;
 403                                 __cpu_name[cpu] = "NEC VR4122";
 404                         } else {
 405                                 c->cputype = CPU_VR4181A;
 406                                 __cpu_name[cpu] = "NEC VR4181A";
 407                         }
 408                         break;
 409                 case PRID_REV_VR4130:
 410                         if ((c->processor_id & 0xf) < 0x4) {
 411                                 c->cputype = CPU_VR4131;
 412                                 __cpu_name[cpu] = "NEC VR4131";
 413                         } else {
 414                                 c->cputype = CPU_VR4133;
 415                                 c->options |= MIPS_CPU_LLSC;
 416                                 __cpu_name[cpu] = "NEC VR4133";
 417                         }
 418                         break;
 419                 default:
 420                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 421                         c->cputype = CPU_VR41XX;
 422                         __cpu_name[cpu] = "NEC Vr41xx";
 423                         break;
 424                 }
 425                 break;
 426         case PRID_IMP_R4300:
 427                 c->cputype = CPU_R4300;
 428                 __cpu_name[cpu] = "R4300";
 429                 set_isa(c, MIPS_CPU_ISA_III);
 430                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 431                              MIPS_CPU_LLSC;
 432                 c->tlbsize = 32;
 433                 break;
 434         case PRID_IMP_R4600:
 435                 c->cputype = CPU_R4600;
 436                 __cpu_name[cpu] = "R4600";
 437                 set_isa(c, MIPS_CPU_ISA_III);
 438                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 439                              MIPS_CPU_LLSC;
 440                 c->tlbsize = 48;
 441                 break;
 442         #if 0
 443         case PRID_IMP_R4650:
 444                 /*
 445                  * This processor doesn't have an MMU, so it's not
 446                  * "real easy" to run Linux on it. It is left purely
 447                  * for documentation.  Commented out because it shares
 448                  * it's c0_prid id number with the TX3900.
 449                  */
 450                 c->cputype = CPU_R4650;
 451                 __cpu_name[cpu] = "R4650";
 452                 set_isa(c, MIPS_CPU_ISA_III);
 453                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 454                 c->tlbsize = 48;
 455                 break;
 456         #endif
 457         case PRID_IMP_TX39:
 458                 set_isa(c, MIPS_CPU_ISA_I);
 459                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 460
 461                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 462                         c->cputype = CPU_TX3927;
 463                         __cpu_name[cpu] = "TX3927";
 464                         c->tlbsize = 64;
 465                 } else {
 466                         switch (c->processor_id & 0xff) {
 467                         case PRID_REV_TX3912:
 468                                 c->cputype = CPU_TX3912;
 469                                 __cpu_name[cpu] = "TX3912";
 470                                 c->tlbsize = 32;
 471                                 break;
 472                         case PRID_REV_TX3922:
 473                                 c->cputype = CPU_TX3922;
 474                                 __cpu_name[cpu] = "TX3922";
 475                                 c->tlbsize = 64;
 476                                 break;
 477                         }
 478                 }
 479                 break;
 480         case PRID_IMP_R4700:
 481                 c->cputype = CPU_R4700;
 482                 __cpu_name[cpu] = "R4700";
 483                 set_isa(c, MIPS_CPU_ISA_III);
 484                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 485                              MIPS_CPU_LLSC;
 486                 c->tlbsize = 48;
 487                 break;
 488         case PRID_IMP_TX49:
 489                 c->cputype = CPU_TX49XX;
 490                 __cpu_name[cpu] = "R49XX";
 491                 set_isa(c, MIPS_CPU_ISA_III);
 492                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 493                 if (!(c->processor_id & 0x08))
 494                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 495                 c->tlbsize = 48;
 496                 break;
 497         case PRID_IMP_R5000:
 498                 c->cputype = CPU_R5000;
 499                 __cpu_name[cpu] = "R5000";
 500                 set_isa(c, MIPS_CPU_ISA_IV);
 501                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 502                              MIPS_CPU_LLSC;
 503                 c->tlbsize = 48;
 504                 break;
 505         case PRID_IMP_R5432:
 506                 c->cputype = CPU_R5432;
 507                 __cpu_name[cpu] = "R5432";
 508                 set_isa(c, MIPS_CPU_ISA_IV);
 509                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 510                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 511                 c->tlbsize = 48;
 512                 break;
 513         case PRID_IMP_R5500:
 514                 c->cputype = CPU_R5500;
 515                 __cpu_name[cpu] = "R5500";
 516                 set_isa(c, MIPS_CPU_ISA_IV);
 517                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 518                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 519                 c->tlbsize = 48;
 520                 break;
 521         case PRID_IMP_NEVADA:
 522                 c->cputype = CPU_NEVADA;
 523                 __cpu_name[cpu] = "Nevada";
 524                 set_isa(c, MIPS_CPU_ISA_IV);
 525                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 526                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 527                 c->tlbsize = 48;
 528                 break;
 529         case PRID_IMP_R6000:
 530                 c->cputype = CPU_R6000;
 531                 __cpu_name[cpu] = "R6000";
 532                 set_isa(c, MIPS_CPU_ISA_II);
 533                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 534                              MIPS_CPU_LLSC;
 535                 c->tlbsize = 32;
 536                 break;
 537         case PRID_IMP_R6000A:
 538                 c->cputype = CPU_R6000A;
 539                 __cpu_name[cpu] = "R6000A";
 540                 set_isa(c, MIPS_CPU_ISA_II);
 541                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 542                              MIPS_CPU_LLSC;
 543                 c->tlbsize = 32;
 544                 break;
 545         case PRID_IMP_RM7000:
 546                 c->cputype = CPU_RM7000;
 547                 __cpu_name[cpu] = "RM7000";
 548                 set_isa(c, MIPS_CPU_ISA_IV);
 549                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 550                              MIPS_CPU_LLSC;
 551                 /*
 552                  * Undocumented RM7000:  Bit 29 in the info register of
 553                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 554                  * entries.
 555                  *
 556                  * 29      1 =>    64 entry JTLB
 557                  *         0 =>    48 entry JTLB
 558                  */
 559                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 560                 break;
 561         case PRID_IMP_RM9000:
 562                 c->cputype = CPU_RM9000;
 563                 __cpu_name[cpu] = "RM9000";
 564                 set_isa(c, MIPS_CPU_ISA_IV);
 565                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 566                              MIPS_CPU_LLSC;
 567                 /*
 568                  * Bit 29 in the info register of the RM9000
 569                  * indicates if the TLB has 48 or 64 entries.
 570                  *
 571                  * 29      1 =>    64 entry JTLB
 572                  *         0 =>    48 entry JTLB
 573                  */
 574                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 575                 break;
 576         case PRID_IMP_R8000:
 577                 c->cputype = CPU_R8000;
 578                 __cpu_name[cpu] = "RM8000";
 579                 set_isa(c, MIPS_CPU_ISA_IV);
 580                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 581                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 582                              MIPS_CPU_LLSC;
 583                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 584                 break;
 585         case PRID_IMP_R10000:
 586                 c->cputype = CPU_R10000;
 587                 __cpu_name[cpu] = "R10000";
 588                 set_isa(c, MIPS_CPU_ISA_IV);
 589                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 590                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 591                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 592                              MIPS_CPU_LLSC;
 593                 c->tlbsize = 64;
 594                 break;
 595         case PRID_IMP_R12000:
 596                 c->cputype = CPU_R12000;
 597                 __cpu_name[cpu] = "R12000";
 598                 set_isa(c, MIPS_CPU_ISA_IV);
 599                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 600                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 601                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 602                              MIPS_CPU_LLSC;
 603                 c->tlbsize = 64;
 604                 break;
 605         case PRID_IMP_R14000:
 606                 c->cputype = CPU_R14000;
 607                 __cpu_name[cpu] = "R14000";
 608                 set_isa(c, MIPS_CPU_ISA_IV);
 609                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 610                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 611                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 612                              MIPS_CPU_LLSC;
 613                 c->tlbsize = 64;
 614                 break;
 615         case PRID_IMP_LOONGSON2:
 616                 c->cputype = CPU_LOONGSON2;
 617                 __cpu_name[cpu] = "ICT Loongson-2";
 618
 619                 switch (c->processor_id & PRID_REV_MASK) {
 620                 case PRID_REV_LOONGSON2E:
 621                         set_elf_platform(cpu, "loongson2e");
 622                         break;
 623                 case PRID_REV_LOONGSON2F:
 624                         set_elf_platform(cpu, "loongson2f");
 625                         break;
 626                 }
 627
 628                 set_isa(c, MIPS_CPU_ISA_III);
 629                 c->options = R4K_OPTS |
 630                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 631                              MIPS_CPU_32FPR;
 632                 c->tlbsize = 64;
 633                 break;
 634         case PRID_IMP_LOONGSON1:
 635                 decode_configs(c);
 636
 637                 c->cputype = CPU_LOONGSON1;
 638
 639                 switch (c->processor_id & PRID_REV_MASK) {
 640                 case PRID_REV_LOONGSON1B:
 641                         __cpu_name[cpu] = "Loongson 1B";
 642                         break;
 643                 }
 644
 645                 break;
 646         }
 647 }
 648
 649 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 650 {
 651         decode_configs(c);
 652         switch (c->processor_id & 0xff00) {
 653         case PRID_IMP_4KC:
 654                 c->cputype = CPU_4KC;
 655                 __cpu_name[cpu] = "MIPS 4Kc";
 656                 break;
 657         case PRID_IMP_4KEC:
 658         case PRID_IMP_4KECR2:
 659                 c->cputype = CPU_4KEC;
 660                 __cpu_name[cpu] = "MIPS 4KEc";
 661                 break;
 662         case PRID_IMP_4KSC:
 663         case PRID_IMP_4KSD:
 664                 c->cputype = CPU_4KSC;
 665                 __cpu_name[cpu] = "MIPS 4KSc";
 666                 break;
 667         case PRID_IMP_5KC:
 668                 c->cputype = CPU_5KC;
 669                 __cpu_name[cpu] = "MIPS 5Kc";
 670                 break;
 671         case PRID_IMP_5KE:
 672                 c->cputype = CPU_5KE;
 673                 __cpu_name[cpu] = "MIPS 5KE";
 674                 break;
 675         case PRID_IMP_20KC:
 676                 c->cputype = CPU_20KC;
 677                 __cpu_name[cpu] = "MIPS 20Kc";
 678                 break;
 679         case PRID_IMP_24K:
 680                 c->cputype = CPU_24K;
 681                 __cpu_name[cpu] = "MIPS 24Kc";
 682                 break;
 683         case PRID_IMP_24KE:
 684                 c->cputype = CPU_24K;
 685                 __cpu_name[cpu] = "MIPS 24KEc";
 686                 break;
 687         case PRID_IMP_25KF:
 688                 c->cputype = CPU_25KF;
 689                 __cpu_name[cpu] = "MIPS 25Kc";
 690                 break;
 691         case PRID_IMP_34K:
 692                 c->cputype = CPU_34K;
 693                 __cpu_name[cpu] = "MIPS 34Kc";
 694                 break;
 695         case PRID_IMP_74K:
 696                 c->cputype = CPU_74K;
 697                 __cpu_name[cpu] = "MIPS 74Kc";
 698                 break;
 699         case PRID_IMP_M14KC:
 700                 c->cputype = CPU_M14KC;
 701                 __cpu_name[cpu] = "MIPS M14Kc";
 702                 break;
 703         case PRID_IMP_M14KEC:
 704                 c->cputype = CPU_M14KEC;
 705                 __cpu_name[cpu] = "MIPS M14KEc";
 706                 break;
 707         case PRID_IMP_1004K:
 708                 c->cputype = CPU_1004K;
 709                 __cpu_name[cpu] = "MIPS 1004Kc";
 710                 break;
 711         case PRID_IMP_1074K:
 712                 c->cputype = CPU_74K;
 713                 __cpu_name[cpu] = "MIPS 1074Kc";
 714                 break;
 715         }
 716
 717         spram_config();
 718 }
 719
 720 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 721 {
 722         decode_configs(c);
 723         switch (c->processor_id & 0xff00) {
 724         case PRID_IMP_AU1_REV1:
 725         case PRID_IMP_AU1_REV2:
 726                 c->cputype = CPU_ALCHEMY;
 727                 switch ((c->processor_id >> 24) & 0xff) {
 728                 case 0:
 729                         __cpu_name[cpu] = "Au1000";
 730                         break;
 731                 case 1:
 732                         __cpu_name[cpu] = "Au1500";
 733                         break;
 734                 case 2:
 735                         __cpu_name[cpu] = "Au1100";
 736                         break;
 737                 case 3:
 738                         __cpu_name[cpu] = "Au1550";
 739                         break;
 740                 case 4:
 741                         __cpu_name[cpu] = "Au1200";
 742                         if ((c->processor_id & 0xff) == 2)
 743                                 __cpu_name[cpu] = "Au1250";
 744                         break;
 745                 case 5:
 746                         __cpu_name[cpu] = "Au1210";
 747                         break;
 748                 default:
 749                         __cpu_name[cpu] = "Au1xxx";
 750                         break;
 751                 }
 752                 break;
 753         }
 754 }
 755
 756 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 757 {
 758         decode_configs(c);
 759
 760         switch (c->processor_id & 0xff00) {
 761         case PRID_IMP_SB1:
 762                 c->cputype = CPU_SB1;
 763                 __cpu_name[cpu] = "SiByte SB1";
 764                 /* FPU in pass1 is known to have issues. */
 765                 if ((c->processor_id & 0xff) < 0x02)
 766                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 767                 break;
 768         case PRID_IMP_SB1A:
 769                 c->cputype = CPU_SB1A;
 770                 __cpu_name[cpu] = "SiByte SB1A";
 771                 break;
 772         }
 773 }
 774
 775 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 776 {
 777         decode_configs(c);
 778         switch (c->processor_id & 0xff00) {
 779         case PRID_IMP_SR71000:
 780                 c->cputype = CPU_SR71000;
 781                 __cpu_name[cpu] = "Sandcraft SR71000";
 782                 c->scache.ways = 8;
 783                 c->tlbsize = 64;
 784                 break;
 785         }
 786 }
 787
 788 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 789 {
 790         decode_configs(c);
 791         switch (c->processor_id & 0xff00) {
 792         case PRID_IMP_PR4450:
 793                 c->cputype = CPU_PR4450;
 794                 __cpu_name[cpu] = "Philips PR4450";
 795                 set_isa(c, MIPS_CPU_ISA_M32R1);
 796                 break;
 797         }
 798 }
 799
 800 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 801 {
 802         decode_configs(c);
 803         switch (c->processor_id & 0xff00) {
 804         case PRID_IMP_BMIPS32_REV4:
 805         case PRID_IMP_BMIPS32_REV8:
 806                 c->cputype = CPU_BMIPS32;
 807                 __cpu_name[cpu] = "Broadcom BMIPS32";
 808                 set_elf_platform(cpu, "bmips32");
 809                 break;
 810         case PRID_IMP_BMIPS3300:
 811         case PRID_IMP_BMIPS3300_ALT:
 812         case PRID_IMP_BMIPS3300_BUG:
 813                 c->cputype = CPU_BMIPS3300;
 814                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 815                 set_elf_platform(cpu, "bmips3300");
 816                 break;
 817         case PRID_IMP_BMIPS43XX: {
 818                 int rev = c->processor_id & 0xff;
 819
 820                 if (rev >= PRID_REV_BMIPS4380_LO &&
 821                                 rev <= PRID_REV_BMIPS4380_HI) {
 822                         c->cputype = CPU_BMIPS4380;
 823                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 824                         set_elf_platform(cpu, "bmips4380");
 825                 } else {
 826                         c->cputype = CPU_BMIPS4350;
 827                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 828                         set_elf_platform(cpu, "bmips4350");
 829                 }
 830                 break;
 831         }
 832         case PRID_IMP_BMIPS5000:
 833                 c->cputype = CPU_BMIPS5000;
 834                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 835                 set_elf_platform(cpu, "bmips5000");
 836                 c->options |= MIPS_CPU_ULRI;
 837                 break;
 838         }
 839 }
 840
 841 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 842 {
 843         decode_configs(c);
 844         switch (c->processor_id & 0xff00) {
 845         case PRID_IMP_CAVIUM_CN38XX:
 846         case PRID_IMP_CAVIUM_CN31XX:
 847         case PRID_IMP_CAVIUM_CN30XX:
 848                 c->cputype = CPU_CAVIUM_OCTEON;
 849                 __cpu_name[cpu] = "Cavium Octeon";
 850                 goto platform;
 851         case PRID_IMP_CAVIUM_CN58XX:
 852         case PRID_IMP_CAVIUM_CN56XX:
 853         case PRID_IMP_CAVIUM_CN50XX:
 854         case PRID_IMP_CAVIUM_CN52XX:
 855                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 856                 __cpu_name[cpu] = "Cavium Octeon+";
 857 platform:
 858                 set_elf_platform(cpu, "octeon");
 859                 break;
 860         case PRID_IMP_CAVIUM_CN61XX:
 861         case PRID_IMP_CAVIUM_CN63XX:
 862         case PRID_IMP_CAVIUM_CN66XX:
 863         case PRID_IMP_CAVIUM_CN68XX:
 864                 c->cputype = CPU_CAVIUM_OCTEON2;
 865                 __cpu_name[cpu] = "Cavium Octeon II";
 866                 set_elf_platform(cpu, "octeon2");
 867                 break;
 868         default:
 869                 printk(KERN_INFO "Unknown Octeon chip!\n");
 870                 c->cputype = CPU_UNKNOWN;
 871                 break;
 872         }
 873 }
 874
 875 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 876 {
 877         decode_configs(c);
 878         /* JZRISC does not implement the CP0 counter. */
 879         c->options &= ~MIPS_CPU_COUNTER;
 880         switch (c->processor_id & 0xff00) {
 881         case PRID_IMP_JZRISC:
 882                 c->cputype = CPU_JZRISC;
 883                 __cpu_name[cpu] = "Ingenic JZRISC";
 884                 break;
 885         default:
 886                 panic("Unknown Ingenic Processor ID!");
 887                 break;
 888         }
 889 }
 890
 891 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 892 {
 893         decode_configs(c);
 894
 895         if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
 896                 c->cputype = CPU_ALCHEMY;
 897                 __cpu_name[cpu] = "Au1300";
 898                 /* following stuff is not for Alchemy */
 899                 return;
 900         }
 901
 902         c->options = (MIPS_CPU_TLB       |
 903                         MIPS_CPU_4KEX    |
 904                         MIPS_CPU_COUNTER |
 905                         MIPS_CPU_DIVEC   |
 906                         MIPS_CPU_WATCH   |
 907                         MIPS_CPU_EJTAG   |
 908                         MIPS_CPU_LLSC);
 909
 910         switch (c->processor_id & 0xff00) {
 911         case PRID_IMP_NETLOGIC_XLP8XX:
 912         case PRID_IMP_NETLOGIC_XLP3XX:
 913                 c->cputype = CPU_XLP;
 914                 __cpu_name[cpu] = "Netlogic XLP";
 915                 break;
 916
 917         case PRID_IMP_NETLOGIC_XLR732:
 918         case PRID_IMP_NETLOGIC_XLR716:
 919         case PRID_IMP_NETLOGIC_XLR532:
 920         case PRID_IMP_NETLOGIC_XLR308:
 921         case PRID_IMP_NETLOGIC_XLR532C:
 922         case PRID_IMP_NETLOGIC_XLR516C:
 923         case PRID_IMP_NETLOGIC_XLR508C:
 924         case PRID_IMP_NETLOGIC_XLR308C:
 925                 c->cputype = CPU_XLR;
 926                 __cpu_name[cpu] = "Netlogic XLR";
 927                 break;
 928
 929         case PRID_IMP_NETLOGIC_XLS608:
 930         case PRID_IMP_NETLOGIC_XLS408:
 931         case PRID_IMP_NETLOGIC_XLS404:
 932         case PRID_IMP_NETLOGIC_XLS208:
 933         case PRID_IMP_NETLOGIC_XLS204:
 934         case PRID_IMP_NETLOGIC_XLS108:
 935         case PRID_IMP_NETLOGIC_XLS104:
 936         case PRID_IMP_NETLOGIC_XLS616B:
 937         case PRID_IMP_NETLOGIC_XLS608B:
 938         case PRID_IMP_NETLOGIC_XLS416B:
 939         case PRID_IMP_NETLOGIC_XLS412B:
 940         case PRID_IMP_NETLOGIC_XLS408B:
 941         case PRID_IMP_NETLOGIC_XLS404B:
 942                 c->cputype = CPU_XLR;
 943                 __cpu_name[cpu] = "Netlogic XLS";
 944                 break;
 945
 946         default:
 947                 pr_info("Unknown Netlogic chip id [%02x]!\n",
 948                        c->processor_id);
 949                 c->cputype = CPU_XLR;
 950                 break;
 951         }
 952
 953         if (c->cputype == CPU_XLP) {
 954                 set_isa(c, MIPS_CPU_ISA_M64R2);
 955                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
 956                 /* This will be updated again after all threads are woken up */
 957                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
 958         } else {
 959                 set_isa(c, MIPS_CPU_ISA_M64R1);
 960                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
 961         }
 962 }
 963
 964 #ifdef CONFIG_64BIT
 965 /* For use by uaccess.h */
 966 u64 __ua_limit;
 967 EXPORT_SYMBOL(__ua_limit);
 968 #endif
 969
 970 const char *__cpu_name[NR_CPUS];
 971 const char *__elf_platform;
 972
 973 __cpuinit void cpu_probe(void)
 974 {
 975         struct cpuinfo_mips *c = &current_cpu_data;
 976         unsigned int cpu = smp_processor_id();
 977
 978         c->processor_id = PRID_IMP_UNKNOWN;
 979         c->fpu_id       = FPIR_IMP_NONE;
 980         c->cputype      = CPU_UNKNOWN;
 981
 982         c->processor_id = read_c0_prid();
 983         switch (c->processor_id & 0xff0000) {
 984         case PRID_COMP_LEGACY:
 985                 cpu_probe_legacy(c, cpu);
 986                 break;
 987         case PRID_COMP_MIPS:
 988                 cpu_probe_mips(c, cpu);
 989                 break;
 990         case PRID_COMP_ALCHEMY:
 991                 cpu_probe_alchemy(c, cpu);
 992                 break;
 993         case PRID_COMP_SIBYTE:
 994                 cpu_probe_sibyte(c, cpu);
 995                 break;
 996         case PRID_COMP_BROADCOM:
 997                 cpu_probe_broadcom(c, cpu);
 998                 break;
 999         case PRID_COMP_SANDCRAFT:
1000                 cpu_probe_sandcraft(c, cpu);
1001                 break;
1002         case PRID_COMP_NXP:
1003                 cpu_probe_nxp(c, cpu);
1004                 break;
1005         case PRID_COMP_CAVIUM:
1006                 cpu_probe_cavium(c, cpu);
1007                 break;
1008         case PRID_COMP_INGENIC:
1009                 cpu_probe_ingenic(c, cpu);
1010                 break;
1011         case PRID_COMP_NETLOGIC:
1012                 cpu_probe_netlogic(c, cpu);
1013                 break;
1014         }
1015
1016         BUG_ON(!__cpu_name[cpu]);
1017         BUG_ON(c->cputype == CPU_UNKNOWN);
1018
1019         /*
1020          * Platform code can force the cpu type to optimize code
1021          * generation. In that case be sure the cpu type is correctly
1022          * manually setup otherwise it could trigger some nasty bugs.
1023          */
1024         BUG_ON(current_cpu_type() != c->cputype);
1025
1026         if (mips_fpu_disabled)
1027                 c->options &= ~MIPS_CPU_FPU;
1028
1029         if (mips_dsp_disabled)
1030                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1031
1032         if (c->options & MIPS_CPU_FPU) {
1033                 c->fpu_id = cpu_get_fpu_id();
1034
1035                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1036                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1037                         if (c->fpu_id & MIPS_FPIR_3D)
1038                                 c->ases |= MIPS_ASE_MIPS3D;
1039                 }
1040         }
1041
1042         if (cpu_has_mips_r2) {
1043                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1044                 /* R2 has Performance Counter Interrupt indicator */
1045                 c->options |= MIPS_CPU_PCI;
1046         }
1047         else
1048                 c->srsets = 1;
1049
1050         cpu_probe_vmbits(c);
1051
1052 #ifdef CONFIG_64BIT
1053         if (cpu == 0)
1054                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1055 #endif
1056 }
1057
1058 __cpuinit void cpu_report(void)
1059 {
1060         struct cpuinfo_mips *c = &current_cpu_data;
1061
1062         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1063                c->processor_id, cpu_name_string());
1064         if (c->options & MIPS_CPU_FPU)
1065                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1066 }