drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "mmsch_v1_0.h"
  31
  32 #include "vega10/soc15ip.h"
  33 #include "vega10/UVD/uvd_7_0_offset.h"
  34 #include "vega10/UVD/uvd_7_0_sh_mask.h"
  35 #include "vega10/VCE/vce_4_0_offset.h"
  36 #include "vega10/VCE/vce_4_0_default.h"
  37 #include "vega10/VCE/vce_4_0_sh_mask.h"
  38 #include "vega10/NBIF/nbif_6_1_offset.h"
  39 #include "vega10/HDP/hdp_4_0_offset.h"
  40 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  41 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  42
  43 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int uvd_v7_0_start(struct amdgpu_device *adev);
  47 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  48 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  49
  50 /**
  51  * uvd_v7_0_ring_get_rptr - get read pointer
  52  *
  53  * @ring: amdgpu_ring pointer
  54  *
  55  * Returns the current hardware read pointer
  56  */
  57 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
  62 }
  63
  64 /**
  65  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware enc read pointer
  70  */
  71 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         if (ring == &adev->uvd.ring_enc[0])
  76                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
  77         else
  78                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
  79 }
  80
  81 /**
  82  * uvd_v7_0_ring_get_wptr - get write pointer
  83  *
  84  * @ring: amdgpu_ring pointer
  85  *
  86  * Returns the current hardware write pointer
  87  */
  88 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
  89 {
  90         struct amdgpu_device *adev = ring->adev;
  91
  92         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
  93 }
  94
  95 /**
  96  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware enc write pointer
 101  */
 102 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         if (ring->use_doorbell)
 107                 return adev->wb.wb[ring->wptr_offs];
 108
 109         if (ring == &adev->uvd.ring_enc[0])
 110                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
 111         else
 112                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
 113 }
 114
 115 /**
 116  * uvd_v7_0_ring_set_wptr - set write pointer
 117  *
 118  * @ring: amdgpu_ring pointer
 119  *
 120  * Commits the write pointer to the hardware
 121  */
 122 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 123 {
 124         struct amdgpu_device *adev = ring->adev;
 125
 126         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 127 }
 128
 129 /**
 130  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the enc write pointer to the hardware
 135  */
 136 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         if (ring->use_doorbell) {
 141                 /* XXX check if swapping is necessary on BE */
 142                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 143                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 144                 return;
 145         }
 146
 147         if (ring == &adev->uvd.ring_enc[0])
 148                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
 149                         lower_32_bits(ring->wptr));
 150         else
 151                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
 152                         lower_32_bits(ring->wptr));
 153 }
 154
 155 /**
 156  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 157  *
 158  * @ring: the engine to test on
 159  *
 160  */
 161 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 162 {
 163         struct amdgpu_device *adev = ring->adev;
 164         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 165         unsigned i;
 166         int r;
 167
 168         r = amdgpu_ring_alloc(ring, 16);
 169         if (r) {
 170                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 171                           ring->idx, r);
 172                 return r;
 173         }
 174         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 175         amdgpu_ring_commit(ring);
 176
 177         for (i = 0; i < adev->usec_timeout; i++) {
 178                 if (amdgpu_ring_get_rptr(ring) != rptr)
 179                         break;
 180                 DRM_UDELAY(1);
 181         }
 182
 183         if (i < adev->usec_timeout) {
 184                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 185                          ring->idx, i);
 186         } else {
 187                 DRM_ERROR("amdgpu: ring %d test failed\n",
 188                           ring->idx);
 189                 r = -ETIMEDOUT;
 190         }
 191
 192         return r;
 193 }
 194
 195 /**
 196  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 197  *
 198  * @adev: amdgpu_device pointer
 199  * @ring: ring we should submit the msg to
 200  * @handle: session handle to use
 201  * @fence: optional fence to return
 202  *
 203  * Open up a stream for HW test
 204  */
 205 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 206                                        struct dma_fence **fence)
 207 {
 208         const unsigned ib_size_dw = 16;
 209         struct amdgpu_job *job;
 210         struct amdgpu_ib *ib;
 211         struct dma_fence *f = NULL;
 212         uint64_t dummy;
 213         int i, r;
 214
 215         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 216         if (r)
 217                 return r;
 218
 219         ib = &job->ibs[0];
 220         dummy = ib->gpu_addr + 1024;
 221
 222         ib->length_dw = 0;
 223         ib->ptr[ib->length_dw++] = 0x00000018;
 224         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 225         ib->ptr[ib->length_dw++] = handle;
 226         ib->ptr[ib->length_dw++] = 0x00000000;
 227         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 228         ib->ptr[ib->length_dw++] = dummy;
 229
 230         ib->ptr[ib->length_dw++] = 0x00000014;
 231         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 232         ib->ptr[ib->length_dw++] = 0x0000001c;
 233         ib->ptr[ib->length_dw++] = 0x00000000;
 234         ib->ptr[ib->length_dw++] = 0x00000000;
 235
 236         ib->ptr[ib->length_dw++] = 0x00000008;
 237         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 238
 239         for (i = ib->length_dw; i < ib_size_dw; ++i)
 240                 ib->ptr[i] = 0x0;
 241
 242         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 243         job->fence = dma_fence_get(f);
 244         if (r)
 245                 goto err;
 246
 247         amdgpu_job_free(job);
 248         if (fence)
 249                 *fence = dma_fence_get(f);
 250         dma_fence_put(f);
 251         return 0;
 252
 253 err:
 254         amdgpu_job_free(job);
 255         return r;
 256 }
 257
 258 /**
 259  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 260  *
 261  * @adev: amdgpu_device pointer
 262  * @ring: ring we should submit the msg to
 263  * @handle: session handle to use
 264  * @fence: optional fence to return
 265  *
 266  * Close up a stream for HW test or if userspace failed to do so
 267  */
 268 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 269                                  bool direct, struct dma_fence **fence)
 270 {
 271         const unsigned ib_size_dw = 16;
 272         struct amdgpu_job *job;
 273         struct amdgpu_ib *ib;
 274         struct dma_fence *f = NULL;
 275         uint64_t dummy;
 276         int i, r;
 277
 278         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 279         if (r)
 280                 return r;
 281
 282         ib = &job->ibs[0];
 283         dummy = ib->gpu_addr + 1024;
 284
 285         ib->length_dw = 0;
 286         ib->ptr[ib->length_dw++] = 0x00000018;
 287         ib->ptr[ib->length_dw++] = 0x00000001;
 288         ib->ptr[ib->length_dw++] = handle;
 289         ib->ptr[ib->length_dw++] = 0x00000000;
 290         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 291         ib->ptr[ib->length_dw++] = dummy;
 292
 293         ib->ptr[ib->length_dw++] = 0x00000014;
 294         ib->ptr[ib->length_dw++] = 0x00000002;
 295         ib->ptr[ib->length_dw++] = 0x0000001c;
 296         ib->ptr[ib->length_dw++] = 0x00000000;
 297         ib->ptr[ib->length_dw++] = 0x00000000;
 298
 299         ib->ptr[ib->length_dw++] = 0x00000008;
 300         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 301
 302         for (i = ib->length_dw; i < ib_size_dw; ++i)
 303                 ib->ptr[i] = 0x0;
 304
 305         if (direct) {
 306                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 307                 job->fence = dma_fence_get(f);
 308                 if (r)
 309                         goto err;
 310
 311                 amdgpu_job_free(job);
 312         } else {
 313                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 314                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 315                 if (r)
 316                         goto err;
 317         }
 318
 319         if (fence)
 320                 *fence = dma_fence_get(f);
 321         dma_fence_put(f);
 322         return 0;
 323
 324 err:
 325         amdgpu_job_free(job);
 326         return r;
 327 }
 328
 329 /**
 330  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 331  *
 332  * @ring: the engine to test on
 333  *
 334  */
 335 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 336 {
 337         struct dma_fence *fence = NULL;
 338         long r;
 339
 340         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 341         if (r) {
 342                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 343                 goto error;
 344         }
 345
 346         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 347         if (r) {
 348                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 349                 goto error;
 350         }
 351
 352         r = dma_fence_wait_timeout(fence, false, timeout);
 353         if (r == 0) {
 354                 DRM_ERROR("amdgpu: IB test timed out.\n");
 355                 r = -ETIMEDOUT;
 356         } else if (r < 0) {
 357                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 358         } else {
 359                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 360                 r = 0;
 361         }
 362 error:
 363         dma_fence_put(fence);
 364         return r;
 365 }
 366
 367 static int uvd_v7_0_early_init(void *handle)
 368 {
 369         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 370
 371         if (amdgpu_sriov_vf(adev))
 372                 adev->uvd.num_enc_rings = 1;
 373         else
 374                 adev->uvd.num_enc_rings = 2;
 375         uvd_v7_0_set_ring_funcs(adev);
 376         uvd_v7_0_set_enc_ring_funcs(adev);
 377         uvd_v7_0_set_irq_funcs(adev);
 378
 379         return 0;
 380 }
 381
 382 static int uvd_v7_0_sw_init(void *handle)
 383 {
 384         struct amdgpu_ring *ring;
 385         struct amd_sched_rq *rq;
 386         int i, r;
 387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 388
 389         /* UVD TRAP */
 390         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
 391         if (r)
 392                 return r;
 393
 394         /* UVD ENC TRAP */
 395         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 396                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
 397                 if (r)
 398                         return r;
 399         }
 400
 401         r = amdgpu_uvd_sw_init(adev);
 402         if (r)
 403                 return r;
 404
 405         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 406                 const struct common_firmware_header *hdr;
 407                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 408                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 409                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 410                 adev->firmware.fw_size +=
 411                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 412                 DRM_INFO("PSP loading UVD firmware\n");
 413         }
 414
 415         ring = &adev->uvd.ring_enc[0];
 416         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 417         r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
 418                                   rq, amdgpu_sched_jobs);
 419         if (r) {
 420                 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 421                 return r;
 422         }
 423
 424         r = amdgpu_uvd_resume(adev);
 425         if (r)
 426                 return r;
 427         if (!amdgpu_sriov_vf(adev)) {
 428                 ring = &adev->uvd.ring;
 429                 sprintf(ring->name, "uvd");
 430                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 431                 if (r)
 432                         return r;
 433         }
 434
 435
 436         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 437                 ring = &adev->uvd.ring_enc[i];
 438                 sprintf(ring->name, "uvd_enc%d", i);
 439                 if (amdgpu_sriov_vf(adev)) {
 440                         ring->use_doorbell = true;
 441                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 442                 }
 443                 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 444                 if (r)
 445                         return r;
 446         }
 447
 448         r = amdgpu_virt_alloc_mm_table(adev);
 449         if (r)
 450                 return r;
 451
 452         return r;
 453 }
 454
 455 static int uvd_v7_0_sw_fini(void *handle)
 456 {
 457         int i, r;
 458         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 459
 460         amdgpu_virt_free_mm_table(adev);
 461
 462         r = amdgpu_uvd_suspend(adev);
 463         if (r)
 464                 return r;
 465
 466         amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 467
 468         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 469                 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 470
 471         return amdgpu_uvd_sw_fini(adev);
 472 }
 473
 474 /**
 475  * uvd_v7_0_hw_init - start and test UVD block
 476  *
 477  * @adev: amdgpu_device pointer
 478  *
 479  * Initialize the hardware, boot up the VCPU and do some testing
 480  */
 481 static int uvd_v7_0_hw_init(void *handle)
 482 {
 483         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 484         struct amdgpu_ring *ring = &adev->uvd.ring;
 485         uint32_t tmp;
 486         int i, r;
 487
 488         if (amdgpu_sriov_vf(adev))
 489                 r = uvd_v7_0_sriov_start(adev);
 490         else
 491                 r = uvd_v7_0_start(adev);
 492         if (r)
 493                 goto done;
 494
 495         if (!amdgpu_sriov_vf(adev)) {
 496                 ring->ready = true;
 497                 r = amdgpu_ring_test_ring(ring);
 498                 if (r) {
 499                         ring->ready = false;
 500                         goto done;
 501                 }
 502
 503                 r = amdgpu_ring_alloc(ring, 10);
 504                 if (r) {
 505                         DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 506                         goto done;
 507                 }
 508
 509                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 510                         mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 511                 amdgpu_ring_write(ring, tmp);
 512                 amdgpu_ring_write(ring, 0xFFFFF);
 513
 514                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 515                         mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 516                 amdgpu_ring_write(ring, tmp);
 517                 amdgpu_ring_write(ring, 0xFFFFF);
 518
 519                 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
 520                         mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 521                 amdgpu_ring_write(ring, tmp);
 522                 amdgpu_ring_write(ring, 0xFFFFF);
 523
 524                 /* Clear timeout status bits */
 525                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 526                         mmUVD_SEMA_TIMEOUT_STATUS), 0));
 527                 amdgpu_ring_write(ring, 0x8);
 528
 529                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
 530                         mmUVD_SEMA_CNTL), 0));
 531                 amdgpu_ring_write(ring, 3);
 532
 533                 amdgpu_ring_commit(ring);
 534         }
 535
 536         for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 537                 ring = &adev->uvd.ring_enc[i];
 538                 ring->ready = true;
 539                 r = amdgpu_ring_test_ring(ring);
 540                 if (r) {
 541                         ring->ready = false;
 542                         goto done;
 543                 }
 544         }
 545
 546 done:
 547         if (!r)
 548                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 549
 550         return r;
 551 }
 552
 553 /**
 554  * uvd_v7_0_hw_fini - stop the hardware block
 555  *
 556  * @adev: amdgpu_device pointer
 557  *
 558  * Stop the UVD block, mark ring as not ready any more
 559  */
 560 static int uvd_v7_0_hw_fini(void *handle)
 561 {
 562         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 563         struct amdgpu_ring *ring = &adev->uvd.ring;
 564
 565         if (!amdgpu_sriov_vf(adev))
 566                 uvd_v7_0_stop(adev);
 567         else {
 568                 /* full access mode, so don't touch any UVD register */
 569                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 570         }
 571
 572         ring->ready = false;
 573
 574         return 0;
 575 }
 576
 577 static int uvd_v7_0_suspend(void *handle)
 578 {
 579         int r;
 580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 581
 582         r = uvd_v7_0_hw_fini(adev);
 583         if (r)
 584                 return r;
 585
 586         /* Skip this for APU for now */
 587         if (!(adev->flags & AMD_IS_APU))
 588                 r = amdgpu_uvd_suspend(adev);
 589
 590         return r;
 591 }
 592
 593 static int uvd_v7_0_resume(void *handle)
 594 {
 595         int r;
 596         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 597
 598         /* Skip this for APU for now */
 599         if (!(adev->flags & AMD_IS_APU)) {
 600                 r = amdgpu_uvd_resume(adev);
 601                 if (r)
 602                         return r;
 603         }
 604         return uvd_v7_0_hw_init(adev);
 605 }
 606
 607 /**
 608  * uvd_v7_0_mc_resume - memory controller programming
 609  *
 610  * @adev: amdgpu_device pointer
 611  *
 612  * Let the UVD memory controller know it's offsets
 613  */
 614 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 615 {
 616         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 617         uint32_t offset;
 618
 619         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 620                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 621                         lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 622                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 623                         upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 624                 offset = 0;
 625         } else {
 626                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 627                         lower_32_bits(adev->uvd.gpu_addr));
 628                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 629                         upper_32_bits(adev->uvd.gpu_addr));
 630                 offset = size;
 631         }
 632
 633         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 634                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 635         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 636
 637         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 638                         lower_32_bits(adev->uvd.gpu_addr + offset));
 639         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 640                         upper_32_bits(adev->uvd.gpu_addr + offset));
 641         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 642         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 643
 644         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 645                         lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 646         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 647                         upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 648         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 649         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
 650                         AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 651
 652         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 653                         adev->gfx.config.gb_addr_config);
 654         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 655                         adev->gfx.config.gb_addr_config);
 656         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 657                         adev->gfx.config.gb_addr_config);
 658
 659         WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 660 }
 661
 662 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 663                                 struct amdgpu_mm_table *table)
 664 {
 665         uint32_t data = 0, loop;
 666         uint64_t addr = table->gpu_addr;
 667         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 668         uint32_t size;
 669
 670         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 671
 672         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 673         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 674         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 675
 676         /* 2, update vmid of descriptor */
 677         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 678         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 679         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 680         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 681
 682         /* 3, notify mmsch about the size of this descriptor */
 683         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 684
 685         /* 4, set resp to zero */
 686         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 687
 688         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 689         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 690
 691         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 692         loop = 1000;
 693         while ((data & 0x10000002) != 0x10000002) {
 694                 udelay(10);
 695                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 696                 loop--;
 697                 if (!loop)
 698                         break;
 699         }
 700
 701         if (!loop) {
 702                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 703                 return -EBUSY;
 704         }
 705         WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
 706
 707         return 0;
 708 }
 709
 710 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 711 {
 712         struct amdgpu_ring *ring;
 713         uint32_t offset, size, tmp;
 714         uint32_t table_size = 0;
 715         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 716         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 717         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 718         struct mmsch_v1_0_cmd_end end = { {0} };
 719         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 720         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 721
 722         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 723         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 724         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 725         end.cmd_header.command_type = MMSCH_COMMAND__END;
 726
 727         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 728                 header->version = MMSCH_VERSION;
 729                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 730
 731                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 732                         header->uvd_table_offset = header->header_size;
 733                 else
 734                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 735
 736                 init_table += header->uvd_table_offset;
 737
 738                 ring = &adev->uvd.ring;
 739                 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 740
 741                 /* disable clock gating */
 742                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
 743                                                    ~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
 744                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 745                                                    0xFFFFFFFF, 0x00000004);
 746                 /* mc resume*/
 747                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 748                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 749                                                     lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 750                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 751                                                     upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 752                         offset = 0;
 753                 } else {
 754                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 755                                                     lower_32_bits(adev->uvd.gpu_addr));
 756                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 757                                                     upper_32_bits(adev->uvd.gpu_addr));
 758                         offset = size;
 759                 }
 760
 761                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 762                                             AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 763                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
 764
 765                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 766                                             lower_32_bits(adev->uvd.gpu_addr + offset));
 767                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 768                                             upper_32_bits(adev->uvd.gpu_addr + offset));
 769                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 770                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 771
 772                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 773                                             lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 774                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 775                                             upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 776                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 777                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
 778                                             AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 779
 780                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
 781                                             adev->gfx.config.gb_addr_config);
 782                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
 783                                             adev->gfx.config.gb_addr_config);
 784                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
 785                                             adev->gfx.config.gb_addr_config);
 786                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 787                 /* mc resume end*/
 788
 789                 /* disable clock gating */
 790                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
 791                                                    ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 792
 793                 /* disable interupt */
 794                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 795                                                    ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 796
 797                 /* stall UMC and register bus before resetting VCPU */
 798                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 799                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 800                                                    UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 801
 802                 /* put LMI, VCPU, RBC etc... into reset */
 803                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 804                                             (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 805                                                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 806                                                        UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 807                                                        UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 808                                                        UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 809                                                        UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 810                                                        UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 811                                                        UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 812
 813                 /* initialize UVD memory controller */
 814                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
 815                                             (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 816                                                        UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 817                                                        UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 818                                                        UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 819                                                        UVD_LMI_CTRL__REQ_MODE_MASK |
 820                                                        0x00100000L));
 821
 822                 /* disable byte swapping */
 823                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), 0);
 824                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), 0);
 825
 826                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
 827                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
 828                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
 829                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
 830                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
 831                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
 832
 833                 /* take all subblocks out of reset, except VCPU */
 834                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 835                                             UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 836
 837                 /* enable VCPU clock */
 838                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 839                                             UVD_VCPU_CNTL__CLK_EN_MASK);
 840
 841                 /* enable UMC */
 842                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 843                                                    ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 844
 845                 /* boot up the VCPU */
 846                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
 847
 848                 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
 849
 850                 /* enable master interrupt */
 851                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 852                                                    ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 853                                                    (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 854
 855                 /* clear the bit 4 of UVD_STATUS */
 856                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
 857                                                    ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 858
 859                 /* force RBC into idle state */
 860                 size = order_base_2(ring->ring_size);
 861                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 862                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 863                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 864                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 865                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 866                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 867                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
 868
 869                 /* set the write pointer delay */
 870                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
 871
 872                 /* set the wb address */
 873                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
 874                                             (upper_32_bits(ring->gpu_addr) >> 2));
 875
 876                 /* programm the RB_BASE for ring buffer */
 877                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
 878                                             lower_32_bits(ring->gpu_addr));
 879                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
 880                                             upper_32_bits(ring->gpu_addr));
 881
 882                 ring->wptr = 0;
 883                 ring = &adev->uvd.ring_enc[0];
 884                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
 885                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 886                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
 887
 888                 /* add end packet */
 889                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 890                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 891                 header->uvd_table_size = table_size;
 892
 893                 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 894         }
 895         return -EINVAL; /* already initializaed ? */
 896 }
 897
 898 /**
 899  * uvd_v7_0_start - start UVD block
 900  *
 901  * @adev: amdgpu_device pointer
 902  *
 903  * Setup and start the UVD block
 904  */
 905 static int uvd_v7_0_start(struct amdgpu_device *adev)
 906 {
 907         struct amdgpu_ring *ring = &adev->uvd.ring;
 908         uint32_t rb_bufsz, tmp;
 909         uint32_t lmi_swap_cntl;
 910         uint32_t mp_swap_cntl;
 911         int i, j, r;
 912
 913         /* disable DPG */
 914         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
 915                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 916
 917         /* disable byte swapping */
 918         lmi_swap_cntl = 0;
 919         mp_swap_cntl = 0;
 920
 921         uvd_v7_0_mc_resume(adev);
 922
 923         /* disable clock gating */
 924         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
 925                         ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 926
 927         /* disable interupt */
 928         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 929                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 930
 931         /* stall UMC and register bus before resetting VCPU */
 932         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 933                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 934                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 935         mdelay(1);
 936
 937         /* put LMI, VCPU, RBC etc... into reset */
 938         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 939                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 940                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 941                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 942                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 943                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 944                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 945                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 946                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 947         mdelay(5);
 948
 949         /* initialize UVD memory controller */
 950         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
 951                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 952                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 953                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 954                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 955                 UVD_LMI_CTRL__REQ_MODE_MASK |
 956                 0x00100000L);
 957
 958 #ifdef __BIG_ENDIAN
 959         /* swap (8 in 32) RB and IB */
 960         lmi_swap_cntl = 0xa;
 961         mp_swap_cntl = 0;
 962 #endif
 963         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 964         WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 965
 966         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 967         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
 968         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 969         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
 970         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
 971         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
 972
 973         /* take all subblocks out of reset, except VCPU */
 974         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 975                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 976         mdelay(5);
 977
 978         /* enable VCPU clock */
 979         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
 980                         UVD_VCPU_CNTL__CLK_EN_MASK);
 981
 982         /* enable UMC */
 983         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 984                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 985
 986         /* boot up the VCPU */
 987         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
 988         mdelay(10);
 989
 990         for (i = 0; i < 10; ++i) {
 991                 uint32_t status;
 992
 993                 for (j = 0; j < 100; ++j) {
 994                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 995                         if (status & 2)
 996                                 break;
 997                         mdelay(10);
 998                 }
 999                 r = 0;
1000                 if (status & 2)
1001                         break;
1002
1003                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
1004                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1005                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1006                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1007                 mdelay(10);
1008                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1009                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1010                 mdelay(10);
1011                 r = -1;
1012         }
1013
1014         if (r) {
1015                 DRM_ERROR("UVD not responding, giving up!!!\n");
1016                 return r;
1017         }
1018         /* enable master interrupt */
1019         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1020                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1021                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1022
1023         /* clear the bit 4 of UVD_STATUS */
1024         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1025                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1026
1027         /* force RBC into idle state */
1028         rb_bufsz = order_base_2(ring->ring_size);
1029         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1030         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1031         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1032         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1033         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1034         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1035         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1036
1037         /* set the write pointer delay */
1038         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1039
1040         /* set the wb address */
1041         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1042                         (upper_32_bits(ring->gpu_addr) >> 2));
1043
1044         /* programm the RB_BASE for ring buffer */
1045         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1046                         lower_32_bits(ring->gpu_addr));
1047         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1048                         upper_32_bits(ring->gpu_addr));
1049
1050         /* Initialize the ring buffer's read and write pointers */
1051         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1052
1053         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1054         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1055                         lower_32_bits(ring->wptr));
1056
1057         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1058                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1059
1060         ring = &adev->uvd.ring_enc[0];
1061         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1062         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1063         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1064         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1065         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1066
1067         ring = &adev->uvd.ring_enc[1];
1068         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1069         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1070         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1071         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1072         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1073
1074         return 0;
1075 }
1076
1077 /**
1078  * uvd_v7_0_stop - stop UVD block
1079  *
1080  * @adev: amdgpu_device pointer
1081  *
1082  * stop the UVD block
1083  */
1084 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1085 {
1086         /* force RBC into idle state */
1087         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
1088
1089         /* Stall UMC and register bus before resetting VCPU */
1090         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1091                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1092                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1093         mdelay(1);
1094
1095         /* put VCPU into reset */
1096         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
1097                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1098         mdelay(5);
1099
1100         /* disable VCPU clock */
1101         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
1102
1103         /* Unstall UMC and register bus */
1104         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1105                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1106 }
1107
1108 /**
1109  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1110  *
1111  * @ring: amdgpu_ring pointer
1112  * @fence: fence to emit
1113  *
1114  * Write a fence and a trap command to the ring.
1115  */
1116 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1117                                      unsigned flags)
1118 {
1119         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1120
1121         amdgpu_ring_write(ring,
1122                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1123         amdgpu_ring_write(ring, seq);
1124         amdgpu_ring_write(ring,
1125                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1126         amdgpu_ring_write(ring, addr & 0xffffffff);
1127         amdgpu_ring_write(ring,
1128                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1129         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1130         amdgpu_ring_write(ring,
1131                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1132         amdgpu_ring_write(ring, 0);
1133
1134         amdgpu_ring_write(ring,
1135                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1136         amdgpu_ring_write(ring, 0);
1137         amdgpu_ring_write(ring,
1138                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1139         amdgpu_ring_write(ring, 0);
1140         amdgpu_ring_write(ring,
1141                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1142         amdgpu_ring_write(ring, 2);
1143 }
1144
1145 /**
1146  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1147  *
1148  * @ring: amdgpu_ring pointer
1149  * @fence: fence to emit
1150  *
1151  * Write enc a fence and a trap command to the ring.
1152  */
1153 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1154                         u64 seq, unsigned flags)
1155 {
1156         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1157
1158         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1159         amdgpu_ring_write(ring, addr);
1160         amdgpu_ring_write(ring, upper_32_bits(addr));
1161         amdgpu_ring_write(ring, seq);
1162         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1163 }
1164
1165 /**
1166  * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
1167  *
1168  * @ring: amdgpu_ring pointer
1169  *
1170  * Emits an hdp flush.
1171  */
1172 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1173 {
1174         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
1175                 mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
1176         amdgpu_ring_write(ring, 0);
1177 }
1178
1179 /**
1180  * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
1181  *
1182  * @ring: amdgpu_ring pointer
1183  *
1184  * Emits an hdp invalidate.
1185  */
1186 static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1187 {
1188         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
1189         amdgpu_ring_write(ring, 1);
1190 }
1191
1192 /**
1193  * uvd_v7_0_ring_test_ring - register write test
1194  *
1195  * @ring: amdgpu_ring pointer
1196  *
1197  * Test if we can successfully write to the context register
1198  */
1199 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1200 {
1201         struct amdgpu_device *adev = ring->adev;
1202         uint32_t tmp = 0;
1203         unsigned i;
1204         int r;
1205
1206         WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1207         r = amdgpu_ring_alloc(ring, 3);
1208         if (r) {
1209                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1210                           ring->idx, r);
1211                 return r;
1212         }
1213         amdgpu_ring_write(ring,
1214                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1215         amdgpu_ring_write(ring, 0xDEADBEEF);
1216         amdgpu_ring_commit(ring);
1217         for (i = 0; i < adev->usec_timeout; i++) {
1218                 tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
1219                 if (tmp == 0xDEADBEEF)
1220                         break;
1221                 DRM_UDELAY(1);
1222         }
1223
1224         if (i < adev->usec_timeout) {
1225                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1226                          ring->idx, i);
1227         } else {
1228                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1229                           ring->idx, tmp);
1230                 r = -EINVAL;
1231         }
1232         return r;
1233 }
1234
1235 /**
1236  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1237  *
1238  * @ring: amdgpu_ring pointer
1239  * @ib: indirect buffer to execute
1240  *
1241  * Write ring commands to execute the indirect buffer
1242  */
1243 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1244                                   struct amdgpu_ib *ib,
1245                                   unsigned vm_id, bool ctx_switch)
1246 {
1247         amdgpu_ring_write(ring,
1248                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1249         amdgpu_ring_write(ring, vm_id);
1250
1251         amdgpu_ring_write(ring,
1252                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1253         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1254         amdgpu_ring_write(ring,
1255                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1256         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1257         amdgpu_ring_write(ring,
1258                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1259         amdgpu_ring_write(ring, ib->length_dw);
1260 }
1261
1262 /**
1263  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1264  *
1265  * @ring: amdgpu_ring pointer
1266  * @ib: indirect buffer to execute
1267  *
1268  * Write enc ring commands to execute the indirect buffer
1269  */
1270 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1271                 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1272 {
1273         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1274         amdgpu_ring_write(ring, vm_id);
1275         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1276         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1277         amdgpu_ring_write(ring, ib->length_dw);
1278 }
1279
1280 static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
1281                                 uint32_t data0, uint32_t data1)
1282 {
1283         amdgpu_ring_write(ring,
1284                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1285         amdgpu_ring_write(ring, data0);
1286         amdgpu_ring_write(ring,
1287                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1288         amdgpu_ring_write(ring, data1);
1289         amdgpu_ring_write(ring,
1290                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1291         amdgpu_ring_write(ring, 8);
1292 }
1293
1294 static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1295                                 uint32_t data0, uint32_t data1, uint32_t mask)
1296 {
1297         amdgpu_ring_write(ring,
1298                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1299         amdgpu_ring_write(ring, data0);
1300         amdgpu_ring_write(ring,
1301                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1302         amdgpu_ring_write(ring, data1);
1303         amdgpu_ring_write(ring,
1304                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1305         amdgpu_ring_write(ring, mask);
1306         amdgpu_ring_write(ring,
1307                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1308         amdgpu_ring_write(ring, 12);
1309 }
1310
1311 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1312                                         unsigned vm_id, uint64_t pd_addr)
1313 {
1314         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1315         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1316         uint32_t data0, data1, mask;
1317         unsigned eng = ring->vm_inv_eng;
1318
1319         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1320         pd_addr |= AMDGPU_PTE_VALID;
1321
1322         data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
1323         data1 = upper_32_bits(pd_addr);
1324         uvd_v7_0_vm_reg_write(ring, data0, data1);
1325
1326         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1327         data1 = lower_32_bits(pd_addr);
1328         uvd_v7_0_vm_reg_write(ring, data0, data1);
1329
1330         data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1331         data1 = lower_32_bits(pd_addr);
1332         mask = 0xffffffff;
1333         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1334
1335         /* flush TLB */
1336         data0 = (hub->vm_inv_eng0_req + eng) << 2;
1337         data1 = req;
1338         uvd_v7_0_vm_reg_write(ring, data0, data1);
1339
1340         /* wait for flush */
1341         data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1342         data1 = 1 << vm_id;
1343         mask =  1 << vm_id;
1344         uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1345 }
1346
1347 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1348 {
1349         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1350 }
1351
1352 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1353                          unsigned int vm_id, uint64_t pd_addr)
1354 {
1355         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1356         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1357         unsigned eng = ring->vm_inv_eng;
1358
1359         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1360         pd_addr |= AMDGPU_PTE_VALID;
1361
1362         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1363         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
1364         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1365
1366         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1367         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1368         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1369
1370         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1371         amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1372         amdgpu_ring_write(ring, 0xffffffff);
1373         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1374
1375         /* flush TLB */
1376         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1377         amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
1378         amdgpu_ring_write(ring, req);
1379
1380         /* wait for flush */
1381         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1382         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1383         amdgpu_ring_write(ring, 1 << vm_id);
1384         amdgpu_ring_write(ring, 1 << vm_id);
1385 }
1386
1387 #if 0
1388 static bool uvd_v7_0_is_idle(void *handle)
1389 {
1390         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1391
1392         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1393 }
1394
1395 static int uvd_v7_0_wait_for_idle(void *handle)
1396 {
1397         unsigned i;
1398         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1399
1400         for (i = 0; i < adev->usec_timeout; i++) {
1401                 if (uvd_v7_0_is_idle(handle))
1402                         return 0;
1403         }
1404         return -ETIMEDOUT;
1405 }
1406
1407 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1408 static bool uvd_v7_0_check_soft_reset(void *handle)
1409 {
1410         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1411         u32 srbm_soft_reset = 0;
1412         u32 tmp = RREG32(mmSRBM_STATUS);
1413
1414         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1415             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1416             (RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
1417                     AMDGPU_UVD_STATUS_BUSY_MASK))
1418                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1419                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1420
1421         if (srbm_soft_reset) {
1422                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1423                 return true;
1424         } else {
1425                 adev->uvd.srbm_soft_reset = 0;
1426                 return false;
1427         }
1428 }
1429
1430 static int uvd_v7_0_pre_soft_reset(void *handle)
1431 {
1432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1433
1434         if (!adev->uvd.srbm_soft_reset)
1435                 return 0;
1436
1437         uvd_v7_0_stop(adev);
1438         return 0;
1439 }
1440
1441 static int uvd_v7_0_soft_reset(void *handle)
1442 {
1443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444         u32 srbm_soft_reset;
1445
1446         if (!adev->uvd.srbm_soft_reset)
1447                 return 0;
1448         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1449
1450         if (srbm_soft_reset) {
1451                 u32 tmp;
1452
1453                 tmp = RREG32(mmSRBM_SOFT_RESET);
1454                 tmp |= srbm_soft_reset;
1455                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1456                 WREG32(mmSRBM_SOFT_RESET, tmp);
1457                 tmp = RREG32(mmSRBM_SOFT_RESET);
1458
1459                 udelay(50);
1460
1461                 tmp &= ~srbm_soft_reset;
1462                 WREG32(mmSRBM_SOFT_RESET, tmp);
1463                 tmp = RREG32(mmSRBM_SOFT_RESET);
1464
1465                 /* Wait a little for things to settle down */
1466                 udelay(50);
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int uvd_v7_0_post_soft_reset(void *handle)
1473 {
1474         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1475
1476         if (!adev->uvd.srbm_soft_reset)
1477                 return 0;
1478
1479         mdelay(5);
1480
1481         return uvd_v7_0_start(adev);
1482 }
1483 #endif
1484
1485 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1486                                         struct amdgpu_irq_src *source,
1487                                         unsigned type,
1488                                         enum amdgpu_interrupt_state state)
1489 {
1490         // TODO
1491         return 0;
1492 }
1493
1494 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1495                                       struct amdgpu_irq_src *source,
1496                                       struct amdgpu_iv_entry *entry)
1497 {
1498         DRM_DEBUG("IH: UVD TRAP\n");
1499         switch (entry->src_id) {
1500         case 124:
1501                 amdgpu_fence_process(&adev->uvd.ring);
1502                 break;
1503         case 119:
1504                 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1505                 break;
1506         case 120:
1507                 if (!amdgpu_sriov_vf(adev))
1508                         amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1509                 break;
1510         default:
1511                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1512                           entry->src_id, entry->src_data[0]);
1513                 break;
1514         }
1515
1516         return 0;
1517 }
1518
1519 #if 0
1520 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1521 {
1522         uint32_t data, data1, data2, suvd_flags;
1523
1524         data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
1525         data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1526         data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
1527
1528         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1529                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1530
1531         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1532                      UVD_SUVD_CGC_GATE__SIT_MASK |
1533                      UVD_SUVD_CGC_GATE__SMP_MASK |
1534                      UVD_SUVD_CGC_GATE__SCM_MASK |
1535                      UVD_SUVD_CGC_GATE__SDB_MASK;
1536
1537         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1538                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1539                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1540
1541         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1542                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1543                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1544                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1545                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1546                         UVD_CGC_CTRL__SYS_MODE_MASK |
1547                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1548                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1549                         UVD_CGC_CTRL__REGS_MODE_MASK |
1550                         UVD_CGC_CTRL__RBC_MODE_MASK |
1551                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1552                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1553                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1554                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1555                         UVD_CGC_CTRL__MPC_MODE_MASK |
1556                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1557                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1558                         UVD_CGC_CTRL__WCB_MODE_MASK |
1559                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1560                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1561                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1562                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1563         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1564                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1565                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1566                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1567                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1568         data1 |= suvd_flags;
1569
1570         WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
1571         WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
1572         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1573         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
1574 }
1575
1576 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1577 {
1578         uint32_t data, data1, cgc_flags, suvd_flags;
1579
1580         data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
1581         data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1582
1583         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1584                 UVD_CGC_GATE__UDEC_MASK |
1585                 UVD_CGC_GATE__MPEG2_MASK |
1586                 UVD_CGC_GATE__RBC_MASK |
1587                 UVD_CGC_GATE__LMI_MC_MASK |
1588                 UVD_CGC_GATE__IDCT_MASK |
1589                 UVD_CGC_GATE__MPRD_MASK |
1590                 UVD_CGC_GATE__MPC_MASK |
1591                 UVD_CGC_GATE__LBSI_MASK |
1592                 UVD_CGC_GATE__LRBBM_MASK |
1593                 UVD_CGC_GATE__UDEC_RE_MASK |
1594                 UVD_CGC_GATE__UDEC_CM_MASK |
1595                 UVD_CGC_GATE__UDEC_IT_MASK |
1596                 UVD_CGC_GATE__UDEC_DB_MASK |
1597                 UVD_CGC_GATE__UDEC_MP_MASK |
1598                 UVD_CGC_GATE__WCB_MASK |
1599                 UVD_CGC_GATE__VCPU_MASK |
1600                 UVD_CGC_GATE__SCPU_MASK |
1601                 UVD_CGC_GATE__JPEG_MASK |
1602                 UVD_CGC_GATE__JPEG2_MASK;
1603
1604         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1605                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1606                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1607                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1608                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1609
1610         data |= cgc_flags;
1611         data1 |= suvd_flags;
1612
1613         WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
1614         WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1615 }
1616
1617 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1618 {
1619         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1620
1621         if (enable)
1622                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1623                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1624         else
1625                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1626                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1627
1628         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1629 }
1630
1631
1632 static int uvd_v7_0_set_clockgating_state(void *handle,
1633                                           enum amd_clockgating_state state)
1634 {
1635         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1636         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1637
1638         uvd_v7_0_set_bypass_mode(adev, enable);
1639
1640         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1641                 return 0;
1642
1643         if (enable) {
1644                 /* disable HW gating and enable Sw gating */
1645                 uvd_v7_0_set_sw_clock_gating(adev);
1646         } else {
1647                 /* wait for STATUS to clear */
1648                 if (uvd_v7_0_wait_for_idle(handle))
1649                         return -EBUSY;
1650
1651                 /* enable HW gates because UVD is idle */
1652                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int uvd_v7_0_set_powergating_state(void *handle,
1659                                           enum amd_powergating_state state)
1660 {
1661         /* This doesn't actually powergate the UVD block.
1662          * That's done in the dpm code via the SMC.  This
1663          * just re-inits the block as necessary.  The actual
1664          * gating still happens in the dpm code.  We should
1665          * revisit this when there is a cleaner line between
1666          * the smc and the hw blocks
1667          */
1668         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1669
1670         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1671                 return 0;
1672
1673         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1674
1675         if (state == AMD_PG_STATE_GATE) {
1676                 uvd_v7_0_stop(adev);
1677                 return 0;
1678         } else {
1679                 return uvd_v7_0_start(adev);
1680         }
1681 }
1682 #endif
1683
1684 static int uvd_v7_0_set_clockgating_state(void *handle,
1685                                           enum amd_clockgating_state state)
1686 {
1687         /* needed for driver unload*/
1688         return 0;
1689 }
1690
1691 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1692         .name = "uvd_v7_0",
1693         .early_init = uvd_v7_0_early_init,
1694         .late_init = NULL,
1695         .sw_init = uvd_v7_0_sw_init,
1696         .sw_fini = uvd_v7_0_sw_fini,
1697         .hw_init = uvd_v7_0_hw_init,
1698         .hw_fini = uvd_v7_0_hw_fini,
1699         .suspend = uvd_v7_0_suspend,
1700         .resume = uvd_v7_0_resume,
1701         .is_idle = NULL /* uvd_v7_0_is_idle */,
1702         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1703         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1704         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1705         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1706         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1707         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1708         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1709 };
1710
1711 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1712         .type = AMDGPU_RING_TYPE_UVD,
1713         .align_mask = 0xf,
1714         .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
1715         .support_64bit_ptrs = false,
1716         .vmhub = AMDGPU_MMHUB,
1717         .get_rptr = uvd_v7_0_ring_get_rptr,
1718         .get_wptr = uvd_v7_0_ring_get_wptr,
1719         .set_wptr = uvd_v7_0_ring_set_wptr,
1720         .emit_frame_size =
1721                 2 + /* uvd_v7_0_ring_emit_hdp_flush */
1722                 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
1723                 34 + /* uvd_v7_0_ring_emit_vm_flush */
1724                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1725         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1726         .emit_ib = uvd_v7_0_ring_emit_ib,
1727         .emit_fence = uvd_v7_0_ring_emit_fence,
1728         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1729         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1730         .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
1731         .test_ring = uvd_v7_0_ring_test_ring,
1732         .test_ib = amdgpu_uvd_ring_test_ib,
1733         .insert_nop = amdgpu_ring_insert_nop,
1734         .pad_ib = amdgpu_ring_generic_pad_ib,
1735         .begin_use = amdgpu_uvd_ring_begin_use,
1736         .end_use = amdgpu_uvd_ring_end_use,
1737 };
1738
1739 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1740         .type = AMDGPU_RING_TYPE_UVD_ENC,
1741         .align_mask = 0x3f,
1742         .nop = HEVC_ENC_CMD_NO_OP,
1743         .support_64bit_ptrs = false,
1744         .vmhub = AMDGPU_MMHUB,
1745         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1746         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1747         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1748         .emit_frame_size =
1749                 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1750                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1751                 1, /* uvd_v7_0_enc_ring_insert_end */
1752         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1753         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1754         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1755         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1756         .test_ring = uvd_v7_0_enc_ring_test_ring,
1757         .test_ib = uvd_v7_0_enc_ring_test_ib,
1758         .insert_nop = amdgpu_ring_insert_nop,
1759         .insert_end = uvd_v7_0_enc_ring_insert_end,
1760         .pad_ib = amdgpu_ring_generic_pad_ib,
1761         .begin_use = amdgpu_uvd_ring_begin_use,
1762         .end_use = amdgpu_uvd_ring_end_use,
1763 };
1764
1765 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1766 {
1767         adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
1768         DRM_INFO("UVD is enabled in VM mode\n");
1769 }
1770
1771 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1772 {
1773         int i;
1774
1775         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1776                 adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1777
1778         DRM_INFO("UVD ENC is enabled in VM mode\n");
1779 }
1780
1781 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1782         .set = uvd_v7_0_set_interrupt_state,
1783         .process = uvd_v7_0_process_interrupt,
1784 };
1785
1786 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1787 {
1788         adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1789         adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
1790 }
1791
1792 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1793 {
1794                 .type = AMD_IP_BLOCK_TYPE_UVD,
1795                 .major = 7,
1796                 .minor = 0,
1797                 .rev = 0,
1798                 .funcs = &uvd_v7_0_ip_funcs,
1799 };