drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "bif/bif_4_1_d.h"
  50
  51 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  52
  53 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  54                              struct ttm_mem_reg *mem, unsigned num_pages,
  55                              uint64_t offset, unsigned window,
  56                              struct amdgpu_ring *ring,
  57                              uint64_t *addr);
  58
  59 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  60 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  61
  62 /*
  63  * Global memory.
  64  */
  65 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  66 {
  67         return ttm_mem_global_init(ref->object);
  68 }
  69
  70 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  71 {
  72         ttm_mem_global_release(ref->object);
  73 }
  74
  75 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  76 {
  77         struct drm_global_reference *global_ref;
  78         struct amdgpu_ring *ring;
  79         struct amd_sched_rq *rq;
  80         int r;
  81
  82         adev->mman.mem_global_referenced = false;
  83         global_ref = &adev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &amdgpu_ttm_mem_global_init;
  87         global_ref->release = &amdgpu_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 goto error_mem;
  93         }
  94
  95         adev->mman.bo_global_ref.mem_glob =
  96                 adev->mman.mem_global_ref.object;
  97         global_ref = &adev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 goto error_bo;
 106         }
 107
 108         mutex_init(&adev->mman.gtt_window_lock);
 109
 110         ring = adev->mman.buffer_funcs_ring;
 111         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 112         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 113                                   rq, amdgpu_sched_jobs, NULL);
 114         if (r) {
 115                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 116                 goto error_entity;
 117         }
 118
 119         adev->mman.mem_global_referenced = true;
 120
 121         return 0;
 122
 123 error_entity:
 124         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 125 error_bo:
 126         drm_global_item_unref(&adev->mman.mem_global_ref);
 127 error_mem:
 128         return r;
 129 }
 130
 131 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 132 {
 133         if (adev->mman.mem_global_referenced) {
 134                 amd_sched_entity_fini(adev->mman.entity.sched,
 135                                       &adev->mman.entity);
 136                 mutex_destroy(&adev->mman.gtt_window_lock);
 137                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 138                 drm_global_item_unref(&adev->mman.mem_global_ref);
 139                 adev->mman.mem_global_referenced = false;
 140         }
 141 }
 142
 143 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 144 {
 145         return 0;
 146 }
 147
 148 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 149                                 struct ttm_mem_type_manager *man)
 150 {
 151         struct amdgpu_device *adev;
 152
 153         adev = amdgpu_ttm_adev(bdev);
 154
 155         switch (type) {
 156         case TTM_PL_SYSTEM:
 157                 /* System memory */
 158                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 159                 man->available_caching = TTM_PL_MASK_CACHING;
 160                 man->default_caching = TTM_PL_FLAG_CACHED;
 161                 break;
 162         case TTM_PL_TT:
 163                 man->func = &amdgpu_gtt_mgr_func;
 164                 man->gpu_offset = adev->mc.gart_start;
 165                 man->available_caching = TTM_PL_MASK_CACHING;
 166                 man->default_caching = TTM_PL_FLAG_CACHED;
 167                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 168                 break;
 169         case TTM_PL_VRAM:
 170                 /* "On-card" video ram */
 171                 man->func = &amdgpu_vram_mgr_func;
 172                 man->gpu_offset = adev->mc.vram_start;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 174                              TTM_MEMTYPE_FLAG_MAPPABLE;
 175                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 176                 man->default_caching = TTM_PL_FLAG_WC;
 177                 break;
 178         case AMDGPU_PL_GDS:
 179         case AMDGPU_PL_GWS:
 180         case AMDGPU_PL_OA:
 181                 /* On-chip GDS memory*/
 182                 man->func = &ttm_bo_manager_func;
 183                 man->gpu_offset = 0;
 184                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 185                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 186                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 187                 break;
 188         default:
 189                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 190                 return -EINVAL;
 191         }
 192         return 0;
 193 }
 194
 195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 196                                 struct ttm_placement *placement)
 197 {
 198         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 199         struct amdgpu_bo *abo;
 200         static const struct ttm_place placements = {
 201                 .fpfn = 0,
 202                 .lpfn = 0,
 203                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 204         };
 205
 206         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 207                 placement->placement = &placements;
 208                 placement->busy_placement = &placements;
 209                 placement->num_placement = 1;
 210                 placement->num_busy_placement = 1;
 211                 return;
 212         }
 213         abo = ttm_to_amdgpu_bo(bo);
 214         switch (bo->mem.mem_type) {
 215         case TTM_PL_VRAM:
 216                 if (adev->mman.buffer_funcs &&
 217                     adev->mman.buffer_funcs_ring &&
 218                     adev->mman.buffer_funcs_ring->ready == false) {
 219                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 220                 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 221                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 222                         unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 223                         struct drm_mm_node *node = bo->mem.mm_node;
 224                         unsigned long pages_left;
 225
 226                         for (pages_left = bo->mem.num_pages;
 227                              pages_left;
 228                              pages_left -= node->size, node++) {
 229                                 if (node->start < fpfn)
 230                                         break;
 231                         }
 232
 233                         if (!pages_left)
 234                                 goto gtt;
 235
 236                         /* Try evicting to the CPU inaccessible part of VRAM
 237                          * first, but only set GTT as busy placement, so this
 238                          * BO will be evicted to GTT rather than causing other
 239                          * BOs to be evicted from VRAM
 240                          */
 241                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 242                                                          AMDGPU_GEM_DOMAIN_GTT);
 243                         abo->placements[0].fpfn = fpfn;
 244                         abo->placements[0].lpfn = 0;
 245                         abo->placement.busy_placement = &abo->placements[1];
 246                         abo->placement.num_busy_placement = 1;
 247                 } else {
 248 gtt:
 249                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 250                 }
 251                 break;
 252         case TTM_PL_TT:
 253         default:
 254                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 255         }
 256         *placement = abo->placement;
 257 }
 258
 259 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 260 {
 261         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 262
 263         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 264                 return -EPERM;
 265         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 266                                           filp->private_data);
 267 }
 268
 269 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 270                              struct ttm_mem_reg *new_mem)
 271 {
 272         struct ttm_mem_reg *old_mem = &bo->mem;
 273
 274         BUG_ON(old_mem->mm_node != NULL);
 275         *old_mem = *new_mem;
 276         new_mem->mm_node = NULL;
 277 }
 278
 279 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 280                                     struct drm_mm_node *mm_node,
 281                                     struct ttm_mem_reg *mem)
 282 {
 283         uint64_t addr = 0;
 284
 285         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 286                 addr = mm_node->start << PAGE_SHIFT;
 287                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 288         }
 289         return addr;
 290 }
 291
 292 /**
 293  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
 294  *  corresponding to @offset. It also modifies the offset to be
 295  *  within the drm_mm_node returned
 296  */
 297 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 298                                                unsigned long *offset)
 299 {
 300         struct drm_mm_node *mm_node = mem->mm_node;
 301
 302         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 303                 *offset -= (mm_node->size << PAGE_SHIFT);
 304                 ++mm_node;
 305         }
 306         return mm_node;
 307 }
 308
 309 /**
 310  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 311  *
 312  * The function copies @size bytes from {src->mem + src->offset} to
 313  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 314  * move and different for a BO to BO copy.
 315  *
 316  * @f: Returns the last fence if multiple jobs are submitted.
 317  */
 318 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 319                                struct amdgpu_copy_mem *src,
 320                                struct amdgpu_copy_mem *dst,
 321                                uint64_t size,
 322                                struct reservation_object *resv,
 323                                struct dma_fence **f)
 324 {
 325         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 326         struct drm_mm_node *src_mm, *dst_mm;
 327         uint64_t src_node_start, dst_node_start, src_node_size,
 328                  dst_node_size, src_page_offset, dst_page_offset;
 329         struct dma_fence *fence = NULL;
 330         int r = 0;
 331         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 332                                         AMDGPU_GPU_PAGE_SIZE);
 333
 334         if (!ring->ready) {
 335                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 336                 return -EINVAL;
 337         }
 338
 339         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 340         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 341                                              src->offset;
 342         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 343         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 344
 345         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 346         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 347                                              dst->offset;
 348         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 349         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 350
 351         mutex_lock(&adev->mman.gtt_window_lock);
 352
 353         while (size) {
 354                 unsigned long cur_size;
 355                 uint64_t from = src_node_start, to = dst_node_start;
 356                 struct dma_fence *next;
 357
 358                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 359                  * begins at an offset, then adjust the size accordingly
 360                  */
 361                 cur_size = min3(min(src_node_size, dst_node_size), size,
 362                                 GTT_MAX_BYTES);
 363                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 364                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 365                         cur_size -= max(src_page_offset, dst_page_offset);
 366
 367                 /* Map only what needs to be accessed. Map src to window 0 and
 368                  * dst to window 1
 369                  */
 370                 if (src->mem->mem_type == TTM_PL_TT &&
 371                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 372                         r = amdgpu_map_buffer(src->bo, src->mem,
 373                                         PFN_UP(cur_size + src_page_offset),
 374                                         src_node_start, 0, ring,
 375                                         &from);
 376                         if (r)
 377                                 goto error;
 378                         /* Adjust the offset because amdgpu_map_buffer returns
 379                          * start of mapped page
 380                          */
 381                         from += src_page_offset;
 382                 }
 383
 384                 if (dst->mem->mem_type == TTM_PL_TT &&
 385                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 386                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 387                                         PFN_UP(cur_size + dst_page_offset),
 388                                         dst_node_start, 1, ring,
 389                                         &to);
 390                         if (r)
 391                                 goto error;
 392                         to += dst_page_offset;
 393                 }
 394
 395                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 396                                        resv, &next, false, true);
 397                 if (r)
 398                         goto error;
 399
 400                 dma_fence_put(fence);
 401                 fence = next;
 402
 403                 size -= cur_size;
 404                 if (!size)
 405                         break;
 406
 407                 src_node_size -= cur_size;
 408                 if (!src_node_size) {
 409                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 410                                                              src->mem);
 411                         src_node_size = (src_mm->size << PAGE_SHIFT);
 412                 } else {
 413                         src_node_start += cur_size;
 414                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 415                 }
 416                 dst_node_size -= cur_size;
 417                 if (!dst_node_size) {
 418                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 419                                                              dst->mem);
 420                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 421                 } else {
 422                         dst_node_start += cur_size;
 423                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 424                 }
 425         }
 426 error:
 427         mutex_unlock(&adev->mman.gtt_window_lock);
 428         if (f)
 429                 *f = dma_fence_get(fence);
 430         dma_fence_put(fence);
 431         return r;
 432 }
 433
 434
 435 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 436                             bool evict, bool no_wait_gpu,
 437                             struct ttm_mem_reg *new_mem,
 438                             struct ttm_mem_reg *old_mem)
 439 {
 440         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 441         struct amdgpu_copy_mem src, dst;
 442         struct dma_fence *fence = NULL;
 443         int r;
 444
 445         src.bo = bo;
 446         dst.bo = bo;
 447         src.mem = old_mem;
 448         dst.mem = new_mem;
 449         src.offset = 0;
 450         dst.offset = 0;
 451
 452         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 453                                        new_mem->num_pages << PAGE_SHIFT,
 454                                        bo->resv, &fence);
 455         if (r)
 456                 goto error;
 457
 458         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 459         dma_fence_put(fence);
 460         return r;
 461
 462 error:
 463         if (fence)
 464                 dma_fence_wait(fence, false);
 465         dma_fence_put(fence);
 466         return r;
 467 }
 468
 469 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 470                                 bool evict, bool interruptible,
 471                                 bool no_wait_gpu,
 472                                 struct ttm_mem_reg *new_mem)
 473 {
 474         struct amdgpu_device *adev;
 475         struct ttm_mem_reg *old_mem = &bo->mem;
 476         struct ttm_mem_reg tmp_mem;
 477         struct ttm_place placements;
 478         struct ttm_placement placement;
 479         int r;
 480
 481         adev = amdgpu_ttm_adev(bo->bdev);
 482         tmp_mem = *new_mem;
 483         tmp_mem.mm_node = NULL;
 484         placement.num_placement = 1;
 485         placement.placement = &placements;
 486         placement.num_busy_placement = 1;
 487         placement.busy_placement = &placements;
 488         placements.fpfn = 0;
 489         placements.lpfn = 0;
 490         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 491         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 492                              interruptible, no_wait_gpu);
 493         if (unlikely(r)) {
 494                 return r;
 495         }
 496
 497         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 498         if (unlikely(r)) {
 499                 goto out_cleanup;
 500         }
 501
 502         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 503         if (unlikely(r)) {
 504                 goto out_cleanup;
 505         }
 506         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 507         if (unlikely(r)) {
 508                 goto out_cleanup;
 509         }
 510         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 511 out_cleanup:
 512         ttm_bo_mem_put(bo, &tmp_mem);
 513         return r;
 514 }
 515
 516 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 517                                 bool evict, bool interruptible,
 518                                 bool no_wait_gpu,
 519                                 struct ttm_mem_reg *new_mem)
 520 {
 521         struct amdgpu_device *adev;
 522         struct ttm_mem_reg *old_mem = &bo->mem;
 523         struct ttm_mem_reg tmp_mem;
 524         struct ttm_placement placement;
 525         struct ttm_place placements;
 526         int r;
 527
 528         adev = amdgpu_ttm_adev(bo->bdev);
 529         tmp_mem = *new_mem;
 530         tmp_mem.mm_node = NULL;
 531         placement.num_placement = 1;
 532         placement.placement = &placements;
 533         placement.num_busy_placement = 1;
 534         placement.busy_placement = &placements;
 535         placements.fpfn = 0;
 536         placements.lpfn = 0;
 537         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 538         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 539                              interruptible, no_wait_gpu);
 540         if (unlikely(r)) {
 541                 return r;
 542         }
 543         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 544         if (unlikely(r)) {
 545                 goto out_cleanup;
 546         }
 547         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 548         if (unlikely(r)) {
 549                 goto out_cleanup;
 550         }
 551 out_cleanup:
 552         ttm_bo_mem_put(bo, &tmp_mem);
 553         return r;
 554 }
 555
 556 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 557                         bool evict, bool interruptible,
 558                         bool no_wait_gpu,
 559                         struct ttm_mem_reg *new_mem)
 560 {
 561         struct amdgpu_device *adev;
 562         struct amdgpu_bo *abo;
 563         struct ttm_mem_reg *old_mem = &bo->mem;
 564         int r;
 565
 566         /* Can't move a pinned BO */
 567         abo = ttm_to_amdgpu_bo(bo);
 568         if (WARN_ON_ONCE(abo->pin_count > 0))
 569                 return -EINVAL;
 570
 571         adev = amdgpu_ttm_adev(bo->bdev);
 572
 573         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 574                 amdgpu_move_null(bo, new_mem);
 575                 return 0;
 576         }
 577         if ((old_mem->mem_type == TTM_PL_TT &&
 578              new_mem->mem_type == TTM_PL_SYSTEM) ||
 579             (old_mem->mem_type == TTM_PL_SYSTEM &&
 580              new_mem->mem_type == TTM_PL_TT)) {
 581                 /* bind is enough */
 582                 amdgpu_move_null(bo, new_mem);
 583                 return 0;
 584         }
 585         if (adev->mman.buffer_funcs == NULL ||
 586             adev->mman.buffer_funcs_ring == NULL ||
 587             !adev->mman.buffer_funcs_ring->ready) {
 588                 /* use memcpy */
 589                 goto memcpy;
 590         }
 591
 592         if (old_mem->mem_type == TTM_PL_VRAM &&
 593             new_mem->mem_type == TTM_PL_SYSTEM) {
 594                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 595                                         no_wait_gpu, new_mem);
 596         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 597                    new_mem->mem_type == TTM_PL_VRAM) {
 598                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 599                                             no_wait_gpu, new_mem);
 600         } else {
 601                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 602         }
 603
 604         if (r) {
 605 memcpy:
 606                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 607                 if (r) {
 608                         return r;
 609                 }
 610         }
 611
 612         if (bo->type == ttm_bo_type_device &&
 613             new_mem->mem_type == TTM_PL_VRAM &&
 614             old_mem->mem_type != TTM_PL_VRAM) {
 615                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 616                  * accesses the BO after it's moved.
 617                  */
 618                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 619         }
 620
 621         /* update statistics */
 622         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 623         return 0;
 624 }
 625
 626 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 627 {
 628         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 629         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 630
 631         mem->bus.addr = NULL;
 632         mem->bus.offset = 0;
 633         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 634         mem->bus.base = 0;
 635         mem->bus.is_iomem = false;
 636         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 637                 return -EINVAL;
 638         switch (mem->mem_type) {
 639         case TTM_PL_SYSTEM:
 640                 /* system memory */
 641                 return 0;
 642         case TTM_PL_TT:
 643                 break;
 644         case TTM_PL_VRAM:
 645                 mem->bus.offset = mem->start << PAGE_SHIFT;
 646                 /* check if it's visible */
 647                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 648                         return -EINVAL;
 649                 mem->bus.base = adev->mc.aper_base;
 650                 mem->bus.is_iomem = true;
 651                 break;
 652         default:
 653                 return -EINVAL;
 654         }
 655         return 0;
 656 }
 657
 658 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 659 {
 660 }
 661
 662 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 663                                            unsigned long page_offset)
 664 {
 665         struct drm_mm_node *mm;
 666         unsigned long offset = (page_offset << PAGE_SHIFT);
 667
 668         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 669         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 670                 (offset >> PAGE_SHIFT);
 671 }
 672
 673 /*
 674  * TTM backend functions.
 675  */
 676 struct amdgpu_ttm_gup_task_list {
 677         struct list_head        list;
 678         struct task_struct      *task;
 679 };
 680
 681 struct amdgpu_ttm_tt {
 682         struct ttm_dma_tt       ttm;
 683         struct amdgpu_device    *adev;
 684         u64                     offset;
 685         uint64_t                userptr;
 686         struct mm_struct        *usermm;
 687         uint32_t                userflags;
 688         spinlock_t              guptasklock;
 689         struct list_head        guptasks;
 690         atomic_t                mmu_invalidations;
 691         uint32_t                last_set_pages;
 692         struct list_head        list;
 693 };
 694
 695 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 696 {
 697         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 698         unsigned int flags = 0;
 699         unsigned pinned = 0;
 700         int r;
 701
 702         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 703                 flags |= FOLL_WRITE;
 704
 705         down_read(&current->mm->mmap_sem);
 706
 707         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 708                 /* check that we only use anonymous memory
 709                    to prevent problems with writeback */
 710                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 711                 struct vm_area_struct *vma;
 712
 713                 vma = find_vma(gtt->usermm, gtt->userptr);
 714                 if (!vma || vma->vm_file || vma->vm_end < end) {
 715                         up_read(&current->mm->mmap_sem);
 716                         return -EPERM;
 717                 }
 718         }
 719
 720         do {
 721                 unsigned num_pages = ttm->num_pages - pinned;
 722                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 723                 struct page **p = pages + pinned;
 724                 struct amdgpu_ttm_gup_task_list guptask;
 725
 726                 guptask.task = current;
 727                 spin_lock(&gtt->guptasklock);
 728                 list_add(&guptask.list, &gtt->guptasks);
 729                 spin_unlock(&gtt->guptasklock);
 730
 731                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 732
 733                 spin_lock(&gtt->guptasklock);
 734                 list_del(&guptask.list);
 735                 spin_unlock(&gtt->guptasklock);
 736
 737                 if (r < 0)
 738                         goto release_pages;
 739
 740                 pinned += r;
 741
 742         } while (pinned < ttm->num_pages);
 743
 744         up_read(&current->mm->mmap_sem);
 745         return 0;
 746
 747 release_pages:
 748         release_pages(pages, pinned);
 749         up_read(&current->mm->mmap_sem);
 750         return r;
 751 }
 752
 753 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 754 {
 755         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 756         unsigned i;
 757
 758         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 759         for (i = 0; i < ttm->num_pages; ++i) {
 760                 if (ttm->pages[i])
 761                         put_page(ttm->pages[i]);
 762
 763                 ttm->pages[i] = pages ? pages[i] : NULL;
 764         }
 765 }
 766
 767 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 768 {
 769         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 770         unsigned i;
 771
 772         for (i = 0; i < ttm->num_pages; ++i) {
 773                 struct page *page = ttm->pages[i];
 774
 775                 if (!page)
 776                         continue;
 777
 778                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 779                         set_page_dirty(page);
 780
 781                 mark_page_accessed(page);
 782         }
 783 }
 784
 785 /* prepare the sg table with the user pages */
 786 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 787 {
 788         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 789         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 790         unsigned nents;
 791         int r;
 792
 793         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 794         enum dma_data_direction direction = write ?
 795                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 796
 797         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 798                                       ttm->num_pages << PAGE_SHIFT,
 799                                       GFP_KERNEL);
 800         if (r)
 801                 goto release_sg;
 802
 803         r = -ENOMEM;
 804         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 805         if (nents != ttm->sg->nents)
 806                 goto release_sg;
 807
 808         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 809                                          gtt->ttm.dma_address, ttm->num_pages);
 810
 811         return 0;
 812
 813 release_sg:
 814         kfree(ttm->sg);
 815         return r;
 816 }
 817
 818 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 819 {
 820         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 821         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 822
 823         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 824         enum dma_data_direction direction = write ?
 825                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 826
 827         /* double check that we don't free the table twice */
 828         if (!ttm->sg->sgl)
 829                 return;
 830
 831         /* free the sg table and pages again */
 832         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 833
 834         amdgpu_ttm_tt_mark_user_pages(ttm);
 835
 836         sg_free_table(ttm->sg);
 837 }
 838
 839 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 840                                    struct ttm_mem_reg *bo_mem)
 841 {
 842         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 843         uint64_t flags;
 844         int r = 0;
 845
 846         if (gtt->userptr) {
 847                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 848                 if (r) {
 849                         DRM_ERROR("failed to pin userptr\n");
 850                         return r;
 851                 }
 852         }
 853         if (!ttm->num_pages) {
 854                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 855                      ttm->num_pages, bo_mem, ttm);
 856         }
 857
 858         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 859             bo_mem->mem_type == AMDGPU_PL_GWS ||
 860             bo_mem->mem_type == AMDGPU_PL_OA)
 861                 return -EINVAL;
 862
 863         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 864                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 865                 return 0;
 866         }
 867
 868         spin_lock(&gtt->adev->gtt_list_lock);
 869         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 870         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 871         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 872                 ttm->pages, gtt->ttm.dma_address, flags);
 873
 874         if (r) {
 875                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 876                           ttm->num_pages, gtt->offset);
 877                 goto error_gart_bind;
 878         }
 879
 880         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 881 error_gart_bind:
 882         spin_unlock(&gtt->adev->gtt_list_lock);
 883         return r;
 884 }
 885
 886 int amdgpu_ttm_bind(struct ttm_buffer_object *bo)
 887 {
 888         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 889         struct ttm_mem_reg tmp;
 890         struct ttm_placement placement;
 891         struct ttm_place placements;
 892         int r;
 893
 894         if (bo->mem.mem_type != TTM_PL_TT ||
 895             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
 896                 return 0;
 897
 898         tmp = bo->mem;
 899         tmp.mm_node = NULL;
 900         placement.num_placement = 1;
 901         placement.placement = &placements;
 902         placement.num_busy_placement = 1;
 903         placement.busy_placement = &placements;
 904         placements.fpfn = 0;
 905         placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
 906         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
 907                 TTM_PL_FLAG_TT;
 908
 909         r = ttm_bo_mem_space(bo, &placement, &tmp, false, false);
 910         if (unlikely(r))
 911                 return r;
 912
 913         r = ttm_bo_move_ttm(bo, true, false, &tmp);
 914         if (unlikely(r))
 915                 ttm_bo_mem_put(bo, &tmp);
 916         else
 917                 bo->offset = (bo->mem.start << PAGE_SHIFT) +
 918                         bo->bdev->man[bo->mem.mem_type].gpu_offset;
 919
 920         return r;
 921 }
 922
 923 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 924 {
 925         struct amdgpu_ttm_tt *gtt, *tmp;
 926         struct ttm_mem_reg bo_mem;
 927         uint64_t flags;
 928         int r;
 929
 930         bo_mem.mem_type = TTM_PL_TT;
 931         spin_lock(&adev->gtt_list_lock);
 932         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 933                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 934                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 935                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 936                                      flags);
 937                 if (r) {
 938                         spin_unlock(&adev->gtt_list_lock);
 939                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 940                                   gtt->ttm.ttm.num_pages, gtt->offset);
 941                         return r;
 942                 }
 943         }
 944         spin_unlock(&adev->gtt_list_lock);
 945         return 0;
 946 }
 947
 948 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 949 {
 950         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 951         int r;
 952
 953         if (gtt->userptr)
 954                 amdgpu_ttm_tt_unpin_userptr(ttm);
 955
 956         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
 957                 return 0;
 958
 959         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 960         spin_lock(&gtt->adev->gtt_list_lock);
 961         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 962         if (r) {
 963                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 964                           gtt->ttm.ttm.num_pages, gtt->offset);
 965                 goto error_unbind;
 966         }
 967         list_del_init(&gtt->list);
 968 error_unbind:
 969         spin_unlock(&gtt->adev->gtt_list_lock);
 970         return r;
 971 }
 972
 973 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 974 {
 975         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 976
 977         ttm_dma_tt_fini(&gtt->ttm);
 978         kfree(gtt);
 979 }
 980
 981 static struct ttm_backend_func amdgpu_backend_func = {
 982         .bind = &amdgpu_ttm_backend_bind,
 983         .unbind = &amdgpu_ttm_backend_unbind,
 984         .destroy = &amdgpu_ttm_backend_destroy,
 985 };
 986
 987 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 988                                     unsigned long size, uint32_t page_flags,
 989                                     struct page *dummy_read_page)
 990 {
 991         struct amdgpu_device *adev;
 992         struct amdgpu_ttm_tt *gtt;
 993
 994         adev = amdgpu_ttm_adev(bdev);
 995
 996         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 997         if (gtt == NULL) {
 998                 return NULL;
 999         }
1000         gtt->ttm.ttm.func = &amdgpu_backend_func;
1001         gtt->adev = adev;
1002         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
1003                 kfree(gtt);
1004                 return NULL;
1005         }
1006         INIT_LIST_HEAD(&gtt->list);
1007         return &gtt->ttm.ttm;
1008 }
1009
1010 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
1011 {
1012         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1013         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1014         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1015
1016         if (ttm->state != tt_unpopulated)
1017                 return 0;
1018
1019         if (gtt && gtt->userptr) {
1020                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1021                 if (!ttm->sg)
1022                         return -ENOMEM;
1023
1024                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1025                 ttm->state = tt_unbound;
1026                 return 0;
1027         }
1028
1029         if (slave && ttm->sg) {
1030                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1031                                                  gtt->ttm.dma_address, ttm->num_pages);
1032                 ttm->state = tt_unbound;
1033                 return 0;
1034         }
1035
1036 #ifdef CONFIG_SWIOTLB
1037         if (swiotlb_nr_tbl()) {
1038                 return ttm_dma_populate(&gtt->ttm, adev->dev);
1039         }
1040 #endif
1041
1042         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
1043 }
1044
1045 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1046 {
1047         struct amdgpu_device *adev;
1048         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1049         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1050
1051         if (gtt && gtt->userptr) {
1052                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1053                 kfree(ttm->sg);
1054                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1055                 return;
1056         }
1057
1058         if (slave)
1059                 return;
1060
1061         adev = amdgpu_ttm_adev(ttm->bdev);
1062
1063 #ifdef CONFIG_SWIOTLB
1064         if (swiotlb_nr_tbl()) {
1065                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1066                 return;
1067         }
1068 #endif
1069
1070         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1071 }
1072
1073 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1074                               uint32_t flags)
1075 {
1076         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1077
1078         if (gtt == NULL)
1079                 return -EINVAL;
1080
1081         gtt->userptr = addr;
1082         gtt->usermm = current->mm;
1083         gtt->userflags = flags;
1084         spin_lock_init(&gtt->guptasklock);
1085         INIT_LIST_HEAD(&gtt->guptasks);
1086         atomic_set(&gtt->mmu_invalidations, 0);
1087         gtt->last_set_pages = 0;
1088
1089         return 0;
1090 }
1091
1092 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1093 {
1094         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1095
1096         if (gtt == NULL)
1097                 return NULL;
1098
1099         return gtt->usermm;
1100 }
1101
1102 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1103                                   unsigned long end)
1104 {
1105         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1106         struct amdgpu_ttm_gup_task_list *entry;
1107         unsigned long size;
1108
1109         if (gtt == NULL || !gtt->userptr)
1110                 return false;
1111
1112         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1113         if (gtt->userptr > end || gtt->userptr + size <= start)
1114                 return false;
1115
1116         spin_lock(&gtt->guptasklock);
1117         list_for_each_entry(entry, &gtt->guptasks, list) {
1118                 if (entry->task == current) {
1119                         spin_unlock(&gtt->guptasklock);
1120                         return false;
1121                 }
1122         }
1123         spin_unlock(&gtt->guptasklock);
1124
1125         atomic_inc(&gtt->mmu_invalidations);
1126
1127         return true;
1128 }
1129
1130 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1131                                        int *last_invalidated)
1132 {
1133         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1134         int prev_invalidated = *last_invalidated;
1135
1136         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1137         return prev_invalidated != *last_invalidated;
1138 }
1139
1140 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1141 {
1142         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1143
1144         if (gtt == NULL || !gtt->userptr)
1145                 return false;
1146
1147         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1148 }
1149
1150 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1151 {
1152         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1153
1154         if (gtt == NULL)
1155                 return false;
1156
1157         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1158 }
1159
1160 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1161                                  struct ttm_mem_reg *mem)
1162 {
1163         uint64_t flags = 0;
1164
1165         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1166                 flags |= AMDGPU_PTE_VALID;
1167
1168         if (mem && mem->mem_type == TTM_PL_TT) {
1169                 flags |= AMDGPU_PTE_SYSTEM;
1170
1171                 if (ttm->caching_state == tt_cached)
1172                         flags |= AMDGPU_PTE_SNOOPED;
1173         }
1174
1175         flags |= adev->gart.gart_pte_flags;
1176         flags |= AMDGPU_PTE_READABLE;
1177
1178         if (!amdgpu_ttm_tt_is_readonly(ttm))
1179                 flags |= AMDGPU_PTE_WRITEABLE;
1180
1181         return flags;
1182 }
1183
1184 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1185                                             const struct ttm_place *place)
1186 {
1187         unsigned long num_pages = bo->mem.num_pages;
1188         struct drm_mm_node *node = bo->mem.mm_node;
1189
1190         switch (bo->mem.mem_type) {
1191         case TTM_PL_TT:
1192                 return true;
1193
1194         case TTM_PL_VRAM:
1195                 /* Check each drm MM node individually */
1196                 while (num_pages) {
1197                         if (place->fpfn < (node->start + node->size) &&
1198                             !(place->lpfn && place->lpfn <= node->start))
1199                                 return true;
1200
1201                         num_pages -= node->size;
1202                         ++node;
1203                 }
1204                 return false;
1205
1206         default:
1207                 break;
1208         }
1209
1210         return ttm_bo_eviction_valuable(bo, place);
1211 }
1212
1213 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1214                                     unsigned long offset,
1215                                     void *buf, int len, int write)
1216 {
1217         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1218         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1219         struct drm_mm_node *nodes;
1220         uint32_t value = 0;
1221         int ret = 0;
1222         uint64_t pos;
1223         unsigned long flags;
1224
1225         if (bo->mem.mem_type != TTM_PL_VRAM)
1226                 return -EIO;
1227
1228         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1229         pos = (nodes->start << PAGE_SHIFT) + offset;
1230
1231         while (len && pos < adev->mc.mc_vram_size) {
1232                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1233                 uint32_t bytes = 4 - (pos & 3);
1234                 uint32_t shift = (pos & 3) * 8;
1235                 uint32_t mask = 0xffffffff << shift;
1236
1237                 if (len < bytes) {
1238                         mask &= 0xffffffff >> (bytes - len) * 8;
1239                         bytes = len;
1240                 }
1241
1242                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1243                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1244                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1245                 if (!write || mask != 0xffffffff)
1246                         value = RREG32_NO_KIQ(mmMM_DATA);
1247                 if (write) {
1248                         value &= ~mask;
1249                         value |= (*(uint32_t *)buf << shift) & mask;
1250                         WREG32_NO_KIQ(mmMM_DATA, value);
1251                 }
1252                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1253                 if (!write) {
1254                         value = (value & mask) >> shift;
1255                         memcpy(buf, &value, bytes);
1256                 }
1257
1258                 ret += bytes;
1259                 buf = (uint8_t *)buf + bytes;
1260                 pos += bytes;
1261                 len -= bytes;
1262                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1263                         ++nodes;
1264                         pos = (nodes->start << PAGE_SHIFT);
1265                 }
1266         }
1267
1268         return ret;
1269 }
1270
1271 static struct ttm_bo_driver amdgpu_bo_driver = {
1272         .ttm_tt_create = &amdgpu_ttm_tt_create,
1273         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1274         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1275         .invalidate_caches = &amdgpu_invalidate_caches,
1276         .init_mem_type = &amdgpu_init_mem_type,
1277         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1278         .evict_flags = &amdgpu_evict_flags,
1279         .move = &amdgpu_bo_move,
1280         .verify_access = &amdgpu_verify_access,
1281         .move_notify = &amdgpu_bo_move_notify,
1282         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1283         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1284         .io_mem_free = &amdgpu_ttm_io_mem_free,
1285         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1286         .access_memory = &amdgpu_ttm_access_memory
1287 };
1288
1289 int amdgpu_ttm_init(struct amdgpu_device *adev)
1290 {
1291         uint64_t gtt_size;
1292         int r;
1293         u64 vis_vram_limit;
1294
1295         r = amdgpu_ttm_global_init(adev);
1296         if (r) {
1297                 return r;
1298         }
1299         /* No others user of address space so set it to 0 */
1300         r = ttm_bo_device_init(&adev->mman.bdev,
1301                                adev->mman.bo_global_ref.ref.object,
1302                                &amdgpu_bo_driver,
1303                                adev->ddev->anon_inode->i_mapping,
1304                                DRM_FILE_PAGE_OFFSET,
1305                                adev->need_dma32);
1306         if (r) {
1307                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1308                 return r;
1309         }
1310         adev->mman.initialized = true;
1311         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1312                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1313         if (r) {
1314                 DRM_ERROR("Failed initializing VRAM heap.\n");
1315                 return r;
1316         }
1317
1318         /* Reduce size of CPU-visible VRAM if requested */
1319         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1320         if (amdgpu_vis_vram_limit > 0 &&
1321             vis_vram_limit <= adev->mc.visible_vram_size)
1322                 adev->mc.visible_vram_size = vis_vram_limit;
1323
1324         /* Change the size here instead of the init above so only lpfn is affected */
1325         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1326
1327         /*
1328          *The reserved vram for firmware must be pinned to the specified
1329          *place on the VRAM, so reserve it early.
1330          */
1331         r = amdgpu_fw_reserve_vram_init(adev);
1332         if (r) {
1333                 return r;
1334         }
1335
1336         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1337                                     AMDGPU_GEM_DOMAIN_VRAM,
1338                                     &adev->stolen_vga_memory,
1339                                     NULL, NULL);
1340         if (r)
1341                 return r;
1342         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1343                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1344
1345         if (amdgpu_gtt_size == -1)
1346                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1347                                adev->mc.mc_vram_size);
1348         else
1349                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1350         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1351         if (r) {
1352                 DRM_ERROR("Failed initializing GTT heap.\n");
1353                 return r;
1354         }
1355         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1356                  (unsigned)(gtt_size / (1024 * 1024)));
1357
1358         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1359         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1360         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1361         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1362         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1363         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1364         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1365         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1366         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1367         /* GDS Memory */
1368         if (adev->gds.mem.total_size) {
1369                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1370                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1371                 if (r) {
1372                         DRM_ERROR("Failed initializing GDS heap.\n");
1373                         return r;
1374                 }
1375         }
1376
1377         /* GWS */
1378         if (adev->gds.gws.total_size) {
1379                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1380                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1381                 if (r) {
1382                         DRM_ERROR("Failed initializing gws heap.\n");
1383                         return r;
1384                 }
1385         }
1386
1387         /* OA */
1388         if (adev->gds.oa.total_size) {
1389                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1390                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1391                 if (r) {
1392                         DRM_ERROR("Failed initializing oa heap.\n");
1393                         return r;
1394                 }
1395         }
1396
1397         r = amdgpu_ttm_debugfs_init(adev);
1398         if (r) {
1399                 DRM_ERROR("Failed to init debugfs\n");
1400                 return r;
1401         }
1402         return 0;
1403 }
1404
1405 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1406 {
1407         int r;
1408
1409         if (!adev->mman.initialized)
1410                 return;
1411         amdgpu_ttm_debugfs_fini(adev);
1412         if (adev->stolen_vga_memory) {
1413                 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1414                 if (r == 0) {
1415                         amdgpu_bo_unpin(adev->stolen_vga_memory);
1416                         amdgpu_bo_unreserve(adev->stolen_vga_memory);
1417                 }
1418                 amdgpu_bo_unref(&adev->stolen_vga_memory);
1419         }
1420         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1421         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1422         if (adev->gds.mem.total_size)
1423                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1424         if (adev->gds.gws.total_size)
1425                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1426         if (adev->gds.oa.total_size)
1427                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1428         ttm_bo_device_release(&adev->mman.bdev);
1429         amdgpu_gart_fini(adev);
1430         amdgpu_ttm_global_fini(adev);
1431         adev->mman.initialized = false;
1432         DRM_INFO("amdgpu: ttm finalized\n");
1433 }
1434
1435 /* this should only be called at bootup or when userspace
1436  * isn't running */
1437 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1438 {
1439         struct ttm_mem_type_manager *man;
1440
1441         if (!adev->mman.initialized)
1442                 return;
1443
1444         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1445         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1446         man->size = size >> PAGE_SHIFT;
1447 }
1448
1449 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1450 {
1451         struct drm_file *file_priv;
1452         struct amdgpu_device *adev;
1453
1454         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1455                 return -EINVAL;
1456
1457         file_priv = filp->private_data;
1458         adev = file_priv->minor->dev->dev_private;
1459         if (adev == NULL)
1460                 return -EINVAL;
1461
1462         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1463 }
1464
1465 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1466                              struct ttm_mem_reg *mem, unsigned num_pages,
1467                              uint64_t offset, unsigned window,
1468                              struct amdgpu_ring *ring,
1469                              uint64_t *addr)
1470 {
1471         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1472         struct amdgpu_device *adev = ring->adev;
1473         struct ttm_tt *ttm = bo->ttm;
1474         struct amdgpu_job *job;
1475         unsigned num_dw, num_bytes;
1476         dma_addr_t *dma_address;
1477         struct dma_fence *fence;
1478         uint64_t src_addr, dst_addr;
1479         uint64_t flags;
1480         int r;
1481
1482         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1483                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1484
1485         *addr = adev->mc.gart_start;
1486         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1487                 AMDGPU_GPU_PAGE_SIZE;
1488
1489         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1490         while (num_dw & 0x7)
1491                 num_dw++;
1492
1493         num_bytes = num_pages * 8;
1494
1495         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1496         if (r)
1497                 return r;
1498
1499         src_addr = num_dw * 4;
1500         src_addr += job->ibs[0].gpu_addr;
1501
1502         dst_addr = adev->gart.table_addr;
1503         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1504         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1505                                 dst_addr, num_bytes);
1506
1507         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1508         WARN_ON(job->ibs[0].length_dw > num_dw);
1509
1510         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1511         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1512         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1513                             &job->ibs[0].ptr[num_dw]);
1514         if (r)
1515                 goto error_free;
1516
1517         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1518                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1519         if (r)
1520                 goto error_free;
1521
1522         dma_fence_put(fence);
1523
1524         return r;
1525
1526 error_free:
1527         amdgpu_job_free(job);
1528         return r;
1529 }
1530
1531 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1532                        uint64_t dst_offset, uint32_t byte_count,
1533                        struct reservation_object *resv,
1534                        struct dma_fence **fence, bool direct_submit,
1535                        bool vm_needs_flush)
1536 {
1537         struct amdgpu_device *adev = ring->adev;
1538         struct amdgpu_job *job;
1539
1540         uint32_t max_bytes;
1541         unsigned num_loops, num_dw;
1542         unsigned i;
1543         int r;
1544
1545         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1546         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1547         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1548
1549         /* for IB padding */
1550         while (num_dw & 0x7)
1551                 num_dw++;
1552
1553         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1554         if (r)
1555                 return r;
1556
1557         job->vm_needs_flush = vm_needs_flush;
1558         if (resv) {
1559                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1560                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1561                                      false);
1562                 if (r) {
1563                         DRM_ERROR("sync failed (%d).\n", r);
1564                         goto error_free;
1565                 }
1566         }
1567
1568         for (i = 0; i < num_loops; i++) {
1569                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1570
1571                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1572                                         dst_offset, cur_size_in_bytes);
1573
1574                 src_offset += cur_size_in_bytes;
1575                 dst_offset += cur_size_in_bytes;
1576                 byte_count -= cur_size_in_bytes;
1577         }
1578
1579         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1580         WARN_ON(job->ibs[0].length_dw > num_dw);
1581         if (direct_submit) {
1582                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1583                                        NULL, fence);
1584                 job->fence = dma_fence_get(*fence);
1585                 if (r)
1586                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1587                 amdgpu_job_free(job);
1588         } else {
1589                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1590                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1591                 if (r)
1592                         goto error_free;
1593         }
1594
1595         return r;
1596
1597 error_free:
1598         amdgpu_job_free(job);
1599         return r;
1600 }
1601
1602 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1603                        uint64_t src_data,
1604                        struct reservation_object *resv,
1605                        struct dma_fence **fence)
1606 {
1607         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1608         uint32_t max_bytes = 8 *
1609                         adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
1610         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1611
1612         struct drm_mm_node *mm_node;
1613         unsigned long num_pages;
1614         unsigned int num_loops, num_dw;
1615
1616         struct amdgpu_job *job;
1617         int r;
1618
1619         if (!ring->ready) {
1620                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1621                 return -EINVAL;
1622         }
1623
1624         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1625                 r = amdgpu_ttm_bind(&bo->tbo);
1626                 if (r)
1627                         return r;
1628         }
1629
1630         num_pages = bo->tbo.num_pages;
1631         mm_node = bo->tbo.mem.mm_node;
1632         num_loops = 0;
1633         while (num_pages) {
1634                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1635
1636                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1637                 num_pages -= mm_node->size;
1638                 ++mm_node;
1639         }
1640
1641         /* num of dwords for each SDMA_OP_PTEPDE cmd */
1642         num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1643
1644         /* for IB padding */
1645         num_dw += 64;
1646
1647         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1648         if (r)
1649                 return r;
1650
1651         if (resv) {
1652                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1653                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1654                 if (r) {
1655                         DRM_ERROR("sync failed (%d).\n", r);
1656                         goto error_free;
1657                 }
1658         }
1659
1660         num_pages = bo->tbo.num_pages;
1661         mm_node = bo->tbo.mem.mm_node;
1662
1663         while (num_pages) {
1664                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1665                 uint64_t dst_addr;
1666
1667                 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1668
1669                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1670                 while (byte_count) {
1671                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1672
1673                         amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1674                                         dst_addr, 0,
1675                                         cur_size_in_bytes >> 3, 0,
1676                                         src_data);
1677
1678                         dst_addr += cur_size_in_bytes;
1679                         byte_count -= cur_size_in_bytes;
1680                 }
1681
1682                 num_pages -= mm_node->size;
1683                 ++mm_node;
1684         }
1685
1686         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1687         WARN_ON(job->ibs[0].length_dw > num_dw);
1688         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1689                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1690         if (r)
1691                 goto error_free;
1692
1693         return 0;
1694
1695 error_free:
1696         amdgpu_job_free(job);
1697         return r;
1698 }
1699
1700 #if defined(CONFIG_DEBUG_FS)
1701
1702 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1703 {
1704         struct drm_info_node *node = (struct drm_info_node *)m->private;
1705         unsigned ttm_pl = *(int *)node->info_ent->data;
1706         struct drm_device *dev = node->minor->dev;
1707         struct amdgpu_device *adev = dev->dev_private;
1708         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1709         struct drm_printer p = drm_seq_file_printer(m);
1710
1711         man->func->debug(man, &p);
1712         return 0;
1713 }
1714
1715 static int ttm_pl_vram = TTM_PL_VRAM;
1716 static int ttm_pl_tt = TTM_PL_TT;
1717
1718 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1719         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1720         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1721         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1722 #ifdef CONFIG_SWIOTLB
1723         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1724 #endif
1725 };
1726
1727 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1728                                     size_t size, loff_t *pos)
1729 {
1730         struct amdgpu_device *adev = file_inode(f)->i_private;
1731         ssize_t result = 0;
1732         int r;
1733
1734         if (size & 0x3 || *pos & 0x3)
1735                 return -EINVAL;
1736
1737         if (*pos >= adev->mc.mc_vram_size)
1738                 return -ENXIO;
1739
1740         while (size) {
1741                 unsigned long flags;
1742                 uint32_t value;
1743
1744                 if (*pos >= adev->mc.mc_vram_size)
1745                         return result;
1746
1747                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1748                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1749                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1750                 value = RREG32_NO_KIQ(mmMM_DATA);
1751                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1752
1753                 r = put_user(value, (uint32_t *)buf);
1754                 if (r)
1755                         return r;
1756
1757                 result += 4;
1758                 buf += 4;
1759                 *pos += 4;
1760                 size -= 4;
1761         }
1762
1763         return result;
1764 }
1765
1766 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1767                                     size_t size, loff_t *pos)
1768 {
1769         struct amdgpu_device *adev = file_inode(f)->i_private;
1770         ssize_t result = 0;
1771         int r;
1772
1773         if (size & 0x3 || *pos & 0x3)
1774                 return -EINVAL;
1775
1776         if (*pos >= adev->mc.mc_vram_size)
1777                 return -ENXIO;
1778
1779         while (size) {
1780                 unsigned long flags;
1781                 uint32_t value;
1782
1783                 if (*pos >= adev->mc.mc_vram_size)
1784                         return result;
1785
1786                 r = get_user(value, (uint32_t *)buf);
1787                 if (r)
1788                         return r;
1789
1790                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1791                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1792                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1793                 WREG32_NO_KIQ(mmMM_DATA, value);
1794                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1795
1796                 result += 4;
1797                 buf += 4;
1798                 *pos += 4;
1799                 size -= 4;
1800         }
1801
1802         return result;
1803 }
1804
1805 static const struct file_operations amdgpu_ttm_vram_fops = {
1806         .owner = THIS_MODULE,
1807         .read = amdgpu_ttm_vram_read,
1808         .write = amdgpu_ttm_vram_write,
1809         .llseek = default_llseek,
1810 };
1811
1812 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1813
1814 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1815                                    size_t size, loff_t *pos)
1816 {
1817         struct amdgpu_device *adev = file_inode(f)->i_private;
1818         ssize_t result = 0;
1819         int r;
1820
1821         while (size) {
1822                 loff_t p = *pos / PAGE_SIZE;
1823                 unsigned off = *pos & ~PAGE_MASK;
1824                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1825                 struct page *page;
1826                 void *ptr;
1827
1828                 if (p >= adev->gart.num_cpu_pages)
1829                         return result;
1830
1831                 page = adev->gart.pages[p];
1832                 if (page) {
1833                         ptr = kmap(page);
1834                         ptr += off;
1835
1836                         r = copy_to_user(buf, ptr, cur_size);
1837                         kunmap(adev->gart.pages[p]);
1838                 } else
1839                         r = clear_user(buf, cur_size);
1840
1841                 if (r)
1842                         return -EFAULT;
1843
1844                 result += cur_size;
1845                 buf += cur_size;
1846                 *pos += cur_size;
1847                 size -= cur_size;
1848         }
1849
1850         return result;
1851 }
1852
1853 static const struct file_operations amdgpu_ttm_gtt_fops = {
1854         .owner = THIS_MODULE,
1855         .read = amdgpu_ttm_gtt_read,
1856         .llseek = default_llseek
1857 };
1858
1859 #endif
1860
1861 static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
1862                                    size_t size, loff_t *pos)
1863 {
1864         struct amdgpu_device *adev = file_inode(f)->i_private;
1865         int r;
1866         uint64_t phys;
1867         struct iommu_domain *dom;
1868
1869         // always return 8 bytes
1870         if (size != 8)
1871                 return -EINVAL;
1872
1873         // only accept page addresses
1874         if (*pos & 0xFFF)
1875                 return -EINVAL;
1876
1877         dom = iommu_get_domain_for_dev(adev->dev);
1878         if (dom)
1879                 phys = iommu_iova_to_phys(dom, *pos);
1880         else
1881                 phys = *pos;
1882
1883         r = copy_to_user(buf, &phys, 8);
1884         if (r)
1885                 return -EFAULT;
1886
1887         return 8;
1888 }
1889
1890 static const struct file_operations amdgpu_ttm_iova_fops = {
1891         .owner = THIS_MODULE,
1892         .read = amdgpu_iova_to_phys_read,
1893         .llseek = default_llseek
1894 };
1895
1896 static const struct {
1897         char *name;
1898         const struct file_operations *fops;
1899         int domain;
1900 } ttm_debugfs_entries[] = {
1901         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
1902 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1903         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
1904 #endif
1905         { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
1906 };
1907
1908 #endif
1909
1910 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1911 {
1912 #if defined(CONFIG_DEBUG_FS)
1913         unsigned count;
1914
1915         struct drm_minor *minor = adev->ddev->primary;
1916         struct dentry *ent, *root = minor->debugfs_root;
1917
1918         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
1919                 ent = debugfs_create_file(
1920                                 ttm_debugfs_entries[count].name,
1921                                 S_IFREG | S_IRUGO, root,
1922                                 adev,
1923                                 ttm_debugfs_entries[count].fops);
1924                 if (IS_ERR(ent))
1925                         return PTR_ERR(ent);
1926                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
1927                         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1928                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
1929                         i_size_write(ent->d_inode, adev->mc.gart_size);
1930                 adev->mman.debugfs_entries[count] = ent;
1931         }
1932
1933         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1934
1935 #ifdef CONFIG_SWIOTLB
1936         if (!swiotlb_nr_tbl())
1937                 --count;
1938 #endif
1939
1940         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1941 #else
1942         return 0;
1943 #endif
1944 }
1945
1946 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1947 {
1948 #if defined(CONFIG_DEBUG_FS)
1949         unsigned i;
1950
1951         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
1952                 debugfs_remove(adev->mman.debugfs_entries[i]);
1953 #endif
1954 }