drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu_cs.h"
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38 #include "amdgpu_gmc.h"
  39 #include "amdgpu_gem.h"
  40 #include "amdgpu_ras.h"
  41
  42 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  43                                       struct drm_amdgpu_cs_chunk_fence *data,
  44                                       uint32_t *offset)
  45 {
  46         struct drm_gem_object *gobj;
  47         struct amdgpu_bo *bo;
  48         unsigned long size;
  49         int r;
  50
  51         gobj = drm_gem_object_lookup(p->filp, data->handle);
  52         if (gobj == NULL)
  53                 return -EINVAL;
  54
  55         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  56         p->uf_entry.priority = 0;
  57         p->uf_entry.tv.bo = &bo->tbo;
  58         /* One for TTM and one for the CS job */
  59         p->uf_entry.tv.num_shared = 2;
  60
  61         drm_gem_object_put(gobj);
  62
  63         size = amdgpu_bo_size(bo);
  64         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  65                 r = -EINVAL;
  66                 goto error_unref;
  67         }
  68
  69         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  70                 r = -EINVAL;
  71                 goto error_unref;
  72         }
  73
  74         *offset = data->offset;
  75
  76         return 0;
  77
  78 error_unref:
  79         amdgpu_bo_unref(&bo);
  80         return r;
  81 }
  82
  83 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  84                                       struct drm_amdgpu_bo_list_in *data)
  85 {
  86         int r;
  87         struct drm_amdgpu_bo_list_entry *info = NULL;
  88
  89         r = amdgpu_bo_create_list_entry_array(data, &info);
  90         if (r)
  91                 return r;
  92
  93         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  94                                   &p->bo_list);
  95         if (r)
  96                 goto error_free;
  97
  98         kvfree(info);
  99         return 0;
 100
 101 error_free:
 102         kvfree(info);
 103
 104         return r;
 105 }
 106
 107 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 108 {
 109         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 110         struct amdgpu_vm *vm = &fpriv->vm;
 111         uint64_t *chunk_array_user;
 112         uint64_t *chunk_array;
 113         unsigned size, num_ibs = 0;
 114         uint32_t uf_offset = 0;
 115         int i;
 116         int ret;
 117
 118         if (cs->in.num_chunks == 0)
 119                 return 0;
 120
 121         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 122         if (!chunk_array)
 123                 return -ENOMEM;
 124
 125         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 126         if (!p->ctx) {
 127                 ret = -EINVAL;
 128                 goto free_chunk;
 129         }
 130
 131         /* skip guilty context job */
 132         if (atomic_read(&p->ctx->guilty) == 1) {
 133                 ret = -ECANCELED;
 134                 goto free_chunk;
 135         }
 136
 137         /* get chunks */
 138         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 139         if (copy_from_user(chunk_array, chunk_array_user,
 140                            sizeof(uint64_t)*cs->in.num_chunks)) {
 141                 ret = -EFAULT;
 142                 goto free_chunk;
 143         }
 144
 145         p->nchunks = cs->in.num_chunks;
 146         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 147                             GFP_KERNEL);
 148         if (!p->chunks) {
 149                 ret = -ENOMEM;
 150                 goto free_chunk;
 151         }
 152
 153         for (i = 0; i < p->nchunks; i++) {
 154                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 155                 struct drm_amdgpu_cs_chunk user_chunk;
 156                 uint32_t __user *cdata;
 157
 158                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 159                 if (copy_from_user(&user_chunk, chunk_ptr,
 160                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 161                         ret = -EFAULT;
 162                         i--;
 163                         goto free_partial_kdata;
 164                 }
 165                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 166                 p->chunks[i].length_dw = user_chunk.length_dw;
 167
 168                 size = p->chunks[i].length_dw;
 169                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 170
 171                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 172                 if (p->chunks[i].kdata == NULL) {
 173                         ret = -ENOMEM;
 174                         i--;
 175                         goto free_partial_kdata;
 176                 }
 177                 size *= sizeof(uint32_t);
 178                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 179                         ret = -EFAULT;
 180                         goto free_partial_kdata;
 181                 }
 182
 183                 switch (p->chunks[i].chunk_id) {
 184                 case AMDGPU_CHUNK_ID_IB:
 185                         ++num_ibs;
 186                         break;
 187
 188                 case AMDGPU_CHUNK_ID_FENCE:
 189                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 190                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 191                                 ret = -EINVAL;
 192                                 goto free_partial_kdata;
 193                         }
 194
 195                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 196                                                          &uf_offset);
 197                         if (ret)
 198                                 goto free_partial_kdata;
 199
 200                         break;
 201
 202                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 203                         size = sizeof(struct drm_amdgpu_bo_list_in);
 204                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 205                                 ret = -EINVAL;
 206                                 goto free_partial_kdata;
 207                         }
 208
 209                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 210                         if (ret)
 211                                 goto free_partial_kdata;
 212
 213                         break;
 214
 215                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 216                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 218                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 219                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 221                         break;
 222
 223                 default:
 224                         ret = -EINVAL;
 225                         goto free_partial_kdata;
 226                 }
 227         }
 228
 229         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 230         if (ret)
 231                 goto free_all_kdata;
 232
 233         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 234                 ret = -ECANCELED;
 235                 goto free_all_kdata;
 236         }
 237
 238         if (p->uf_entry.tv.bo)
 239                 p->job->uf_addr = uf_offset;
 240         kvfree(chunk_array);
 241
 242         /* Use this opportunity to fill in task info for the vm */
 243         amdgpu_vm_set_task_info(vm);
 244
 245         return 0;
 246
 247 free_all_kdata:
 248         i = p->nchunks - 1;
 249 free_partial_kdata:
 250         for (; i >= 0; i--)
 251                 kvfree(p->chunks[i].kdata);
 252         kvfree(p->chunks);
 253         p->chunks = NULL;
 254         p->nchunks = 0;
 255 free_chunk:
 256         kvfree(chunk_array);
 257
 258         return ret;
 259 }
 260
 261 /* Convert microseconds to bytes. */
 262 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 263 {
 264         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 265                 return 0;
 266
 267         /* Since accum_us is incremented by a million per second, just
 268          * multiply it by the number of MB/s to get the number of bytes.
 269          */
 270         return us << adev->mm_stats.log2_max_MBps;
 271 }
 272
 273 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 274 {
 275         if (!adev->mm_stats.log2_max_MBps)
 276                 return 0;
 277
 278         return bytes >> adev->mm_stats.log2_max_MBps;
 279 }
 280
 281 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 282  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 283  * which means it can go over the threshold once. If that happens, the driver
 284  * will be in debt and no other buffer migrations can be done until that debt
 285  * is repaid.
 286  *
 287  * This approach allows moving a buffer of any size (it's important to allow
 288  * that).
 289  *
 290  * The currency is simply time in microseconds and it increases as the clock
 291  * ticks. The accumulated microseconds (us) are converted to bytes and
 292  * returned.
 293  */
 294 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 295                                               u64 *max_bytes,
 296                                               u64 *max_vis_bytes)
 297 {
 298         s64 time_us, increment_us;
 299         u64 free_vram, total_vram, used_vram;
 300         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 301          * throttling.
 302          *
 303          * It means that in order to get full max MBps, at least 5 IBs per
 304          * second must be submitted and not more than 200ms apart from each
 305          * other.
 306          */
 307         const s64 us_upper_bound = 200000;
 308
 309         if (!adev->mm_stats.log2_max_MBps) {
 310                 *max_bytes = 0;
 311                 *max_vis_bytes = 0;
 312                 return;
 313         }
 314
 315         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 316         used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 317         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 318
 319         spin_lock(&adev->mm_stats.lock);
 320
 321         /* Increase the amount of accumulated us. */
 322         time_us = ktime_to_us(ktime_get());
 323         increment_us = time_us - adev->mm_stats.last_update_us;
 324         adev->mm_stats.last_update_us = time_us;
 325         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 326                                       us_upper_bound);
 327
 328         /* This prevents the short period of low performance when the VRAM
 329          * usage is low and the driver is in debt or doesn't have enough
 330          * accumulated us to fill VRAM quickly.
 331          *
 332          * The situation can occur in these cases:
 333          * - a lot of VRAM is freed by userspace
 334          * - the presence of a big buffer causes a lot of evictions
 335          *   (solution: split buffers into smaller ones)
 336          *
 337          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 338          * accum_us to a positive number.
 339          */
 340         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 341                 s64 min_us;
 342
 343                 /* Be more aggressive on dGPUs. Try to fill a portion of free
 344                  * VRAM now.
 345                  */
 346                 if (!(adev->flags & AMD_IS_APU))
 347                         min_us = bytes_to_us(adev, free_vram / 4);
 348                 else
 349                         min_us = 0; /* Reset accum_us on APUs. */
 350
 351                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 352         }
 353
 354         /* This is set to 0 if the driver is in debt to disallow (optional)
 355          * buffer moves.
 356          */
 357         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 358
 359         /* Do the same for visible VRAM if half of it is free */
 360         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 361                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 362                 u64 used_vis_vram =
 363                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 364
 365                 if (used_vis_vram < total_vis_vram) {
 366                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 367                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 368                                                           increment_us, us_upper_bound);
 369
 370                         if (free_vis_vram >= total_vis_vram / 2)
 371                                 adev->mm_stats.accum_us_vis =
 372                                         max(bytes_to_us(adev, free_vis_vram / 2),
 373                                             adev->mm_stats.accum_us_vis);
 374                 }
 375
 376                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 377         } else {
 378                 *max_vis_bytes = 0;
 379         }
 380
 381         spin_unlock(&adev->mm_stats.lock);
 382 }
 383
 384 /* Report how many bytes have really been moved for the last command
 385  * submission. This can result in a debt that can stop buffer migrations
 386  * temporarily.
 387  */
 388 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 389                                   u64 num_vis_bytes)
 390 {
 391         spin_lock(&adev->mm_stats.lock);
 392         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 393         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 394         spin_unlock(&adev->mm_stats.lock);
 395 }
 396
 397 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 398 {
 399         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 400         struct amdgpu_cs_parser *p = param;
 401         struct ttm_operation_ctx ctx = {
 402                 .interruptible = true,
 403                 .no_wait_gpu = false,
 404                 .resv = bo->tbo.base.resv
 405         };
 406         uint32_t domain;
 407         int r;
 408
 409         if (bo->tbo.pin_count)
 410                 return 0;
 411
 412         /* Don't move this buffer if we have depleted our allowance
 413          * to move it. Don't move anything if the threshold is zero.
 414          */
 415         if (p->bytes_moved < p->bytes_moved_threshold &&
 416             (!bo->tbo.base.dma_buf ||
 417             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 418                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 419                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 420                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 421                          * visible VRAM if we've depleted our allowance to do
 422                          * that.
 423                          */
 424                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 425                                 domain = bo->preferred_domains;
 426                         else
 427                                 domain = bo->allowed_domains;
 428                 } else {
 429                         domain = bo->preferred_domains;
 430                 }
 431         } else {
 432                 domain = bo->allowed_domains;
 433         }
 434
 435 retry:
 436         amdgpu_bo_placement_from_domain(bo, domain);
 437         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 438
 439         p->bytes_moved += ctx.bytes_moved;
 440         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 441             amdgpu_bo_in_cpu_visible_vram(bo))
 442                 p->bytes_moved_vis += ctx.bytes_moved;
 443
 444         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 445                 domain = bo->allowed_domains;
 446                 goto retry;
 447         }
 448
 449         return r;
 450 }
 451
 452 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 453                             struct list_head *validated)
 454 {
 455         struct ttm_operation_ctx ctx = { true, false };
 456         struct amdgpu_bo_list_entry *lobj;
 457         int r;
 458
 459         list_for_each_entry(lobj, validated, tv.head) {
 460                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 461                 struct mm_struct *usermm;
 462
 463                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 464                 if (usermm && usermm != current->mm)
 465                         return -EPERM;
 466
 467                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 468                     lobj->user_invalidated && lobj->user_pages) {
 469                         amdgpu_bo_placement_from_domain(bo,
 470                                                         AMDGPU_GEM_DOMAIN_CPU);
 471                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 472                         if (r)
 473                                 return r;
 474
 475                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 476                                                      lobj->user_pages);
 477                 }
 478
 479                 r = amdgpu_cs_bo_validate(p, bo);
 480                 if (r)
 481                         return r;
 482
 483                 kvfree(lobj->user_pages);
 484                 lobj->user_pages = NULL;
 485         }
 486         return 0;
 487 }
 488
 489 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 490                                 union drm_amdgpu_cs *cs)
 491 {
 492         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 493         struct amdgpu_vm *vm = &fpriv->vm;
 494         struct amdgpu_bo_list_entry *e;
 495         struct list_head duplicates;
 496         struct amdgpu_bo *gds;
 497         struct amdgpu_bo *gws;
 498         struct amdgpu_bo *oa;
 499         int r;
 500
 501         INIT_LIST_HEAD(&p->validated);
 502
 503         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 504         if (cs->in.bo_list_handle) {
 505                 if (p->bo_list)
 506                         return -EINVAL;
 507
 508                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 509                                        &p->bo_list);
 510                 if (r)
 511                         return r;
 512         } else if (!p->bo_list) {
 513                 /* Create a empty bo_list when no handle is provided */
 514                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 515                                           &p->bo_list);
 516                 if (r)
 517                         return r;
 518         }
 519
 520         /* One for TTM and one for the CS job */
 521         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 522                 e->tv.num_shared = 2;
 523
 524         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 525
 526         INIT_LIST_HEAD(&duplicates);
 527         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 528
 529         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 530                 list_add(&p->uf_entry.tv.head, &p->validated);
 531
 532         /* Get userptr backing pages. If pages are updated after registered
 533          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 534          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 535          */
 536         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 537                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 538                 bool userpage_invalidated = false;
 539                 int i;
 540
 541                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 542                                         sizeof(struct page *),
 543                                         GFP_KERNEL | __GFP_ZERO);
 544                 if (!e->user_pages) {
 545                         DRM_ERROR("kvmalloc_array failure\n");
 546                         return -ENOMEM;
 547                 }
 548
 549                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 550                 if (r) {
 551                         kvfree(e->user_pages);
 552                         e->user_pages = NULL;
 553                         goto out_free_user_pages;
 554                 }
 555
 556                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 557                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 558                                 userpage_invalidated = true;
 559                                 break;
 560                         }
 561                 }
 562                 e->user_invalidated = userpage_invalidated;
 563         }
 564
 565         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 566                                    &duplicates);
 567         if (unlikely(r != 0)) {
 568                 if (r != -ERESTARTSYS)
 569                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 570                 goto out_free_user_pages;
 571         }
 572
 573         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 574                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 575
 576                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 577
 578                 if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
 579                         e->chain = dma_fence_chain_alloc();
 580                         if (!e->chain) {
 581                                 r = -ENOMEM;
 582                                 goto error_validate;
 583                         }
 584                 }
 585         }
 586
 587         /* Move fence waiting after getting reservation lock of
 588          * PD root. Then there is no need on a ctx mutex lock.
 589          */
 590         r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);
 591         if (unlikely(r != 0)) {
 592                 if (r != -ERESTARTSYS)
 593                         DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
 594                 goto error_validate;
 595         }
 596
 597         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 598                                           &p->bytes_moved_vis_threshold);
 599         p->bytes_moved = 0;
 600         p->bytes_moved_vis = 0;
 601
 602         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 603                                       amdgpu_cs_bo_validate, p);
 604         if (r) {
 605                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 606                 goto error_validate;
 607         }
 608
 609         r = amdgpu_cs_list_validate(p, &duplicates);
 610         if (r)
 611                 goto error_validate;
 612
 613         r = amdgpu_cs_list_validate(p, &p->validated);
 614         if (r)
 615                 goto error_validate;
 616
 617         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 618                                      p->bytes_moved_vis);
 619
 620         gds = p->bo_list->gds_obj;
 621         gws = p->bo_list->gws_obj;
 622         oa = p->bo_list->oa_obj;
 623
 624         if (gds) {
 625                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 626                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 627         }
 628         if (gws) {
 629                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 630                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 631         }
 632         if (oa) {
 633                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 634                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 635         }
 636
 637         if (!r && p->uf_entry.tv.bo) {
 638                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 639
 640                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 641                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 642         }
 643
 644 error_validate:
 645         if (r) {
 646                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 647                         dma_fence_chain_free(e->chain);
 648                         e->chain = NULL;
 649                 }
 650                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 651         }
 652
 653 out_free_user_pages:
 654         if (r) {
 655                 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 656                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 657
 658                         if (!e->user_pages)
 659                                 continue;
 660                         amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
 661                         kvfree(e->user_pages);
 662                         e->user_pages = NULL;
 663                 }
 664         }
 665         return r;
 666 }
 667
 668 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 669 {
 670         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 671         struct amdgpu_bo_list_entry *e;
 672         int r;
 673
 674         list_for_each_entry(e, &p->validated, tv.head) {
 675                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 676                 struct dma_resv *resv = bo->tbo.base.resv;
 677                 enum amdgpu_sync_mode sync_mode;
 678
 679                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
 680                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
 681                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
 682                                      &fpriv->vm);
 683                 if (r)
 684                         return r;
 685         }
 686         return 0;
 687 }
 688
 689 /**
 690  * amdgpu_cs_parser_fini() - clean parser states
 691  * @parser:     parser structure holding parsing context.
 692  * @error:      error number
 693  * @backoff:    indicator to backoff the reservation
 694  *
 695  * If error is set then unvalidate buffer, otherwise just free memory
 696  * used by parsing context.
 697  **/
 698 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 699                                   bool backoff)
 700 {
 701         unsigned i;
 702
 703         if (error && backoff) {
 704                 struct amdgpu_bo_list_entry *e;
 705
 706                 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
 707                         dma_fence_chain_free(e->chain);
 708                         e->chain = NULL;
 709                 }
 710
 711                 ttm_eu_backoff_reservation(&parser->ticket,
 712                                            &parser->validated);
 713         }
 714
 715         for (i = 0; i < parser->num_post_deps; i++) {
 716                 drm_syncobj_put(parser->post_deps[i].syncobj);
 717                 kfree(parser->post_deps[i].chain);
 718         }
 719         kfree(parser->post_deps);
 720
 721         dma_fence_put(parser->fence);
 722
 723         if (parser->ctx) {
 724                 amdgpu_ctx_put(parser->ctx);
 725         }
 726         if (parser->bo_list)
 727                 amdgpu_bo_list_put(parser->bo_list);
 728
 729         for (i = 0; i < parser->nchunks; i++)
 730                 kvfree(parser->chunks[i].kdata);
 731         kvfree(parser->chunks);
 732         if (parser->job)
 733                 amdgpu_job_free(parser->job);
 734         if (parser->uf_entry.tv.bo) {
 735                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 736
 737                 amdgpu_bo_unref(&uf);
 738         }
 739 }
 740
 741 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 742 {
 743         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 744         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 745         struct amdgpu_device *adev = p->adev;
 746         struct amdgpu_vm *vm = &fpriv->vm;
 747         struct amdgpu_bo_list_entry *e;
 748         struct amdgpu_bo_va *bo_va;
 749         struct amdgpu_bo *bo;
 750         int r;
 751
 752         /* Only for UVD/VCE VM emulation */
 753         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 754                 unsigned i, j;
 755
 756                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 757                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 758                         struct amdgpu_bo_va_mapping *m;
 759                         struct amdgpu_bo *aobj = NULL;
 760                         struct amdgpu_cs_chunk *chunk;
 761                         uint64_t offset, va_start;
 762                         struct amdgpu_ib *ib;
 763                         uint8_t *kptr;
 764
 765                         chunk = &p->chunks[i];
 766                         ib = &p->job->ibs[j];
 767                         chunk_ib = chunk->kdata;
 768
 769                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 770                                 continue;
 771
 772                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 773                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 774                         if (r) {
 775                                 DRM_ERROR("IB va_start is invalid\n");
 776                                 return r;
 777                         }
 778
 779                         if ((va_start + chunk_ib->ib_bytes) >
 780                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 781                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 782                                 return -EINVAL;
 783                         }
 784
 785                         /* the IB should be reserved at this point */
 786                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 787                         if (r) {
 788                                 return r;
 789                         }
 790
 791                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 792                         kptr += va_start - offset;
 793
 794                         if (ring->funcs->parse_cs) {
 795                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 796                                 amdgpu_bo_kunmap(aobj);
 797
 798                                 r = amdgpu_ring_parse_cs(ring, p, p->job, ib);
 799                                 if (r)
 800                                         return r;
 801                         } else {
 802                                 ib->ptr = (uint32_t *)kptr;
 803                                 r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);
 804                                 amdgpu_bo_kunmap(aobj);
 805                                 if (r)
 806                                         return r;
 807                         }
 808
 809                         j++;
 810                 }
 811         }
 812
 813         if (!p->job->vm)
 814                 return amdgpu_cs_sync_rings(p);
 815
 816
 817         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 818         if (r)
 819                 return r;
 820
 821         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 822         if (r)
 823                 return r;
 824
 825         r = amdgpu_sync_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
 826         if (r)
 827                 return r;
 828
 829         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 830                 bo_va = fpriv->csa_va;
 831                 BUG_ON(!bo_va);
 832                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 833                 if (r)
 834                         return r;
 835
 836                 r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);
 837                 if (r)
 838                         return r;
 839         }
 840
 841         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 842                 /* ignore duplicates */
 843                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 844                 if (!bo)
 845                         continue;
 846
 847                 bo_va = e->bo_va;
 848                 if (bo_va == NULL)
 849                         continue;
 850
 851                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 852                 if (r)
 853                         return r;
 854
 855                 r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);
 856                 if (r)
 857                         return r;
 858         }
 859
 860         r = amdgpu_vm_handle_moved(adev, vm);
 861         if (r)
 862                 return r;
 863
 864         r = amdgpu_vm_update_pdes(adev, vm, false);
 865         if (r)
 866                 return r;
 867
 868         r = amdgpu_sync_fence(&p->job->sync, vm->last_update);
 869         if (r)
 870                 return r;
 871
 872         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 873
 874         if (amdgpu_vm_debug) {
 875                 /* Invalidate all BOs to test for userspace bugs */
 876                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 877                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 878
 879                         /* ignore duplicates */
 880                         if (!bo)
 881                                 continue;
 882
 883                         amdgpu_vm_bo_invalidate(adev, bo, false);
 884                 }
 885         }
 886
 887         return amdgpu_cs_sync_rings(p);
 888 }
 889
 890 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 891                              struct amdgpu_cs_parser *parser)
 892 {
 893         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 894         struct amdgpu_vm *vm = &fpriv->vm;
 895         int r, ce_preempt = 0, de_preempt = 0;
 896         struct amdgpu_ring *ring;
 897         int i, j;
 898
 899         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 900                 struct amdgpu_cs_chunk *chunk;
 901                 struct amdgpu_ib *ib;
 902                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 903                 struct drm_sched_entity *entity;
 904
 905                 chunk = &parser->chunks[i];
 906                 ib = &parser->job->ibs[j];
 907                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 908
 909                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 910                         continue;
 911
 912                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 913                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 914                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 915                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 916                                         ce_preempt++;
 917                                 else
 918                                         de_preempt++;
 919                         }
 920
 921                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 922                         if (ce_preempt > 1 || de_preempt > 1)
 923                                 return -EINVAL;
 924                 }
 925
 926                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 927                                           chunk_ib->ip_instance, chunk_ib->ring,
 928                                           &entity);
 929                 if (r)
 930                         return r;
 931
 932                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 933                         parser->job->preamble_status |=
 934                                 AMDGPU_PREAMBLE_IB_PRESENT;
 935
 936                 if (parser->entity && parser->entity != entity)
 937                         return -EINVAL;
 938
 939                 /* Return if there is no run queue associated with this entity.
 940                  * Possibly because of disabled HW IP*/
 941                 if (entity->rq == NULL)
 942                         return -EINVAL;
 943
 944                 parser->entity = entity;
 945
 946                 ring = to_amdgpu_ring(entity->rq->sched);
 947                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 948                                    chunk_ib->ib_bytes : 0,
 949                                    AMDGPU_IB_POOL_DELAYED, ib);
 950                 if (r) {
 951                         DRM_ERROR("Failed to get ib !\n");
 952                         return r;
 953                 }
 954
 955                 ib->gpu_addr = chunk_ib->va_start;
 956                 ib->length_dw = chunk_ib->ib_bytes / 4;
 957                 ib->flags = chunk_ib->flags;
 958
 959                 j++;
 960         }
 961
 962         /* MM engine doesn't support user fences */
 963         ring = to_amdgpu_ring(parser->entity->rq->sched);
 964         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 965                 return -EINVAL;
 966
 967         return 0;
 968 }
 969
 970 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 971                                        struct amdgpu_cs_chunk *chunk)
 972 {
 973         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 974         unsigned num_deps;
 975         int i, r;
 976         struct drm_amdgpu_cs_chunk_dep *deps;
 977
 978         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 979         num_deps = chunk->length_dw * 4 /
 980                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 981
 982         for (i = 0; i < num_deps; ++i) {
 983                 struct amdgpu_ctx *ctx;
 984                 struct drm_sched_entity *entity;
 985                 struct dma_fence *fence;
 986
 987                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 988                 if (ctx == NULL)
 989                         return -EINVAL;
 990
 991                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 992                                           deps[i].ip_instance,
 993                                           deps[i].ring, &entity);
 994                 if (r) {
 995                         amdgpu_ctx_put(ctx);
 996                         return r;
 997                 }
 998
 999                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
1000                 amdgpu_ctx_put(ctx);
1001
1002                 if (IS_ERR(fence))
1003                         return PTR_ERR(fence);
1004                 else if (!fence)
1005                         continue;
1006
1007                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1008                         struct drm_sched_fence *s_fence;
1009                         struct dma_fence *old = fence;
1010
1011                         s_fence = to_drm_sched_fence(fence);
1012                         fence = dma_fence_get(&s_fence->scheduled);
1013                         dma_fence_put(old);
1014                 }
1015
1016                 r = amdgpu_sync_fence(&p->job->sync, fence);
1017                 dma_fence_put(fence);
1018                 if (r)
1019                         return r;
1020         }
1021         return 0;
1022 }
1023
1024 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1025                                                  uint32_t handle, u64 point,
1026                                                  u64 flags)
1027 {
1028         struct dma_fence *fence;
1029         int r;
1030
1031         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1032         if (r) {
1033                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1034                           handle, point, r);
1035                 return r;
1036         }
1037
1038         r = amdgpu_sync_fence(&p->job->sync, fence);
1039         dma_fence_put(fence);
1040
1041         return r;
1042 }
1043
1044 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1045                                             struct amdgpu_cs_chunk *chunk)
1046 {
1047         struct drm_amdgpu_cs_chunk_sem *deps;
1048         unsigned num_deps;
1049         int i, r;
1050
1051         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1052         num_deps = chunk->length_dw * 4 /
1053                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1054         for (i = 0; i < num_deps; ++i) {
1055                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1056                                                           0, 0);
1057                 if (r)
1058                         return r;
1059         }
1060
1061         return 0;
1062 }
1063
1064
1065 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1066                                                      struct amdgpu_cs_chunk *chunk)
1067 {
1068         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1069         unsigned num_deps;
1070         int i, r;
1071
1072         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1073         num_deps = chunk->length_dw * 4 /
1074                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1075         for (i = 0; i < num_deps; ++i) {
1076                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1077                                                           syncobj_deps[i].handle,
1078                                                           syncobj_deps[i].point,
1079                                                           syncobj_deps[i].flags);
1080                 if (r)
1081                         return r;
1082         }
1083
1084         return 0;
1085 }
1086
1087 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1088                                              struct amdgpu_cs_chunk *chunk)
1089 {
1090         struct drm_amdgpu_cs_chunk_sem *deps;
1091         unsigned num_deps;
1092         int i;
1093
1094         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1095         num_deps = chunk->length_dw * 4 /
1096                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1097
1098         if (p->post_deps)
1099                 return -EINVAL;
1100
1101         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1102                                      GFP_KERNEL);
1103         p->num_post_deps = 0;
1104
1105         if (!p->post_deps)
1106                 return -ENOMEM;
1107
1108
1109         for (i = 0; i < num_deps; ++i) {
1110                 p->post_deps[i].syncobj =
1111                         drm_syncobj_find(p->filp, deps[i].handle);
1112                 if (!p->post_deps[i].syncobj)
1113                         return -EINVAL;
1114                 p->post_deps[i].chain = NULL;
1115                 p->post_deps[i].point = 0;
1116                 p->num_post_deps++;
1117         }
1118
1119         return 0;
1120 }
1121
1122
1123 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1124                                                       struct amdgpu_cs_chunk *chunk)
1125 {
1126         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1127         unsigned num_deps;
1128         int i;
1129
1130         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1131         num_deps = chunk->length_dw * 4 /
1132                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1133
1134         if (p->post_deps)
1135                 return -EINVAL;
1136
1137         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1138                                      GFP_KERNEL);
1139         p->num_post_deps = 0;
1140
1141         if (!p->post_deps)
1142                 return -ENOMEM;
1143
1144         for (i = 0; i < num_deps; ++i) {
1145                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1146
1147                 dep->chain = NULL;
1148                 if (syncobj_deps[i].point) {
1149                         dep->chain = dma_fence_chain_alloc();
1150                         if (!dep->chain)
1151                                 return -ENOMEM;
1152                 }
1153
1154                 dep->syncobj = drm_syncobj_find(p->filp,
1155                                                 syncobj_deps[i].handle);
1156                 if (!dep->syncobj) {
1157                         dma_fence_chain_free(dep->chain);
1158                         return -EINVAL;
1159                 }
1160                 dep->point = syncobj_deps[i].point;
1161                 p->num_post_deps++;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1168                                   struct amdgpu_cs_parser *p)
1169 {
1170         int i, r;
1171
1172         for (i = 0; i < p->nchunks; ++i) {
1173                 struct amdgpu_cs_chunk *chunk;
1174
1175                 chunk = &p->chunks[i];
1176
1177                 switch (chunk->chunk_id) {
1178                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1179                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1180                         r = amdgpu_cs_process_fence_dep(p, chunk);
1181                         if (r)
1182                                 return r;
1183                         break;
1184                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1185                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1186                         if (r)
1187                                 return r;
1188                         break;
1189                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1190                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1191                         if (r)
1192                                 return r;
1193                         break;
1194                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1195                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1196                         if (r)
1197                                 return r;
1198                         break;
1199                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1200                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1201                         if (r)
1202                                 return r;
1203                         break;
1204                 }
1205         }
1206
1207         return 0;
1208 }
1209
1210 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1211 {
1212         int i;
1213
1214         for (i = 0; i < p->num_post_deps; ++i) {
1215                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1216                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1217                                               p->post_deps[i].chain,
1218                                               p->fence, p->post_deps[i].point);
1219                         p->post_deps[i].chain = NULL;
1220                 } else {
1221                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1222                                                   p->fence);
1223                 }
1224         }
1225 }
1226
1227 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1228                             union drm_amdgpu_cs *cs)
1229 {
1230         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1231         struct drm_sched_entity *entity = p->entity;
1232         struct amdgpu_bo_list_entry *e;
1233         struct amdgpu_job *job;
1234         uint64_t seq;
1235         int r;
1236
1237         job = p->job;
1238         p->job = NULL;
1239
1240         r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1241         if (r)
1242                 goto error_unlock;
1243
1244         drm_sched_job_arm(&job->base);
1245
1246         /* No memory allocation is allowed while holding the notifier lock.
1247          * The lock is held until amdgpu_cs_submit is finished and fence is
1248          * added to BOs.
1249          */
1250         mutex_lock(&p->adev->notifier_lock);
1251
1252         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1253          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1254          */
1255         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1256                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1257
1258                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1259         }
1260         if (r) {
1261                 r = -EAGAIN;
1262                 goto error_abort;
1263         }
1264
1265         p->fence = dma_fence_get(&job->base.s_fence->finished);
1266
1267         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1268         amdgpu_cs_post_dependencies(p);
1269
1270         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1271             !p->ctx->preamble_presented) {
1272                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1273                 p->ctx->preamble_presented = true;
1274         }
1275
1276         cs->out.handle = seq;
1277         job->uf_sequence = seq;
1278
1279         amdgpu_job_free_resources(job);
1280
1281         trace_amdgpu_cs_ioctl(job);
1282         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1283         drm_sched_entity_push_job(&job->base);
1284
1285         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1286
1287         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1288                 struct dma_resv *resv = e->tv.bo->base.resv;
1289                 struct dma_fence_chain *chain = e->chain;
1290
1291                 if (!chain)
1292                         continue;
1293
1294                 /*
1295                  * Work around dma_resv shortcomings by wrapping up the
1296                  * submission in a dma_fence_chain and add it as exclusive
1297                  * fence.
1298                  */
1299                 dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
1300                                      dma_fence_get(p->fence), 1);
1301
1302                 rcu_assign_pointer(resv->fence_excl, &chain->base);
1303                 e->chain = NULL;
1304         }
1305
1306         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1307         mutex_unlock(&p->adev->notifier_lock);
1308
1309         return 0;
1310
1311 error_abort:
1312         drm_sched_job_cleanup(&job->base);
1313         mutex_unlock(&p->adev->notifier_lock);
1314
1315 error_unlock:
1316         amdgpu_job_free(job);
1317         return r;
1318 }
1319
1320 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1321 {
1322         int i;
1323
1324         if (!trace_amdgpu_cs_enabled())
1325                 return;
1326
1327         for (i = 0; i < parser->job->num_ibs; i++)
1328                 trace_amdgpu_cs(parser, i);
1329 }
1330
1331 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1332 {
1333         struct amdgpu_device *adev = drm_to_adev(dev);
1334         union drm_amdgpu_cs *cs = data;
1335         struct amdgpu_cs_parser parser = {};
1336         bool reserved_buffers = false;
1337         int r;
1338
1339         if (amdgpu_ras_intr_triggered())
1340                 return -EHWPOISON;
1341
1342         if (!adev->accel_working)
1343                 return -EBUSY;
1344
1345         parser.adev = adev;
1346         parser.filp = filp;
1347
1348         r = amdgpu_cs_parser_init(&parser, data);
1349         if (r) {
1350                 if (printk_ratelimit())
1351                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1352                 goto out;
1353         }
1354
1355         r = amdgpu_cs_ib_fill(adev, &parser);
1356         if (r)
1357                 goto out;
1358
1359         r = amdgpu_cs_dependencies(adev, &parser);
1360         if (r) {
1361                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1362                 goto out;
1363         }
1364
1365         r = amdgpu_cs_parser_bos(&parser, data);
1366         if (r) {
1367                 if (r == -ENOMEM)
1368                         DRM_ERROR("Not enough memory for command submission!\n");
1369                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1370                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1371                 goto out;
1372         }
1373
1374         reserved_buffers = true;
1375
1376         trace_amdgpu_cs_ibs(&parser);
1377
1378         r = amdgpu_cs_vm_handling(&parser);
1379         if (r)
1380                 goto out;
1381
1382         r = amdgpu_cs_submit(&parser, cs);
1383 out:
1384         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1385
1386         return r;
1387 }
1388
1389 /**
1390  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1391  *
1392  * @dev: drm device
1393  * @data: data from userspace
1394  * @filp: file private
1395  *
1396  * Wait for the command submission identified by handle to finish.
1397  */
1398 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1399                          struct drm_file *filp)
1400 {
1401         union drm_amdgpu_wait_cs *wait = data;
1402         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1403         struct drm_sched_entity *entity;
1404         struct amdgpu_ctx *ctx;
1405         struct dma_fence *fence;
1406         long r;
1407
1408         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1409         if (ctx == NULL)
1410                 return -EINVAL;
1411
1412         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1413                                   wait->in.ring, &entity);
1414         if (r) {
1415                 amdgpu_ctx_put(ctx);
1416                 return r;
1417         }
1418
1419         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1420         if (IS_ERR(fence))
1421                 r = PTR_ERR(fence);
1422         else if (fence) {
1423                 r = dma_fence_wait_timeout(fence, true, timeout);
1424                 if (r > 0 && fence->error)
1425                         r = fence->error;
1426                 dma_fence_put(fence);
1427         } else
1428                 r = 1;
1429
1430         amdgpu_ctx_put(ctx);
1431         if (r < 0)
1432                 return r;
1433
1434         memset(wait, 0, sizeof(*wait));
1435         wait->out.status = (r == 0);
1436
1437         return 0;
1438 }
1439
1440 /**
1441  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1442  *
1443  * @adev: amdgpu device
1444  * @filp: file private
1445  * @user: drm_amdgpu_fence copied from user space
1446  */
1447 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1448                                              struct drm_file *filp,
1449                                              struct drm_amdgpu_fence *user)
1450 {
1451         struct drm_sched_entity *entity;
1452         struct amdgpu_ctx *ctx;
1453         struct dma_fence *fence;
1454         int r;
1455
1456         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1457         if (ctx == NULL)
1458                 return ERR_PTR(-EINVAL);
1459
1460         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1461                                   user->ring, &entity);
1462         if (r) {
1463                 amdgpu_ctx_put(ctx);
1464                 return ERR_PTR(r);
1465         }
1466
1467         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1468         amdgpu_ctx_put(ctx);
1469
1470         return fence;
1471 }
1472
1473 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1474                                     struct drm_file *filp)
1475 {
1476         struct amdgpu_device *adev = drm_to_adev(dev);
1477         union drm_amdgpu_fence_to_handle *info = data;
1478         struct dma_fence *fence;
1479         struct drm_syncobj *syncobj;
1480         struct sync_file *sync_file;
1481         int fd, r;
1482
1483         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1484         if (IS_ERR(fence))
1485                 return PTR_ERR(fence);
1486
1487         if (!fence)
1488                 fence = dma_fence_get_stub();
1489
1490         switch (info->in.what) {
1491         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1492                 r = drm_syncobj_create(&syncobj, 0, fence);
1493                 dma_fence_put(fence);
1494                 if (r)
1495                         return r;
1496                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1497                 drm_syncobj_put(syncobj);
1498                 return r;
1499
1500         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1501                 r = drm_syncobj_create(&syncobj, 0, fence);
1502                 dma_fence_put(fence);
1503                 if (r)
1504                         return r;
1505                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1506                 drm_syncobj_put(syncobj);
1507                 return r;
1508
1509         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1510                 fd = get_unused_fd_flags(O_CLOEXEC);
1511                 if (fd < 0) {
1512                         dma_fence_put(fence);
1513                         return fd;
1514                 }
1515
1516                 sync_file = sync_file_create(fence);
1517                 dma_fence_put(fence);
1518                 if (!sync_file) {
1519                         put_unused_fd(fd);
1520                         return -ENOMEM;
1521                 }
1522
1523                 fd_install(fd, sync_file->file);
1524                 info->out.handle = fd;
1525                 return 0;
1526
1527         default:
1528                 dma_fence_put(fence);
1529                 return -EINVAL;
1530         }
1531 }
1532
1533 /**
1534  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1535  *
1536  * @adev: amdgpu device
1537  * @filp: file private
1538  * @wait: wait parameters
1539  * @fences: array of drm_amdgpu_fence
1540  */
1541 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1542                                      struct drm_file *filp,
1543                                      union drm_amdgpu_wait_fences *wait,
1544                                      struct drm_amdgpu_fence *fences)
1545 {
1546         uint32_t fence_count = wait->in.fence_count;
1547         unsigned int i;
1548         long r = 1;
1549
1550         for (i = 0; i < fence_count; i++) {
1551                 struct dma_fence *fence;
1552                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1553
1554                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1555                 if (IS_ERR(fence))
1556                         return PTR_ERR(fence);
1557                 else if (!fence)
1558                         continue;
1559
1560                 r = dma_fence_wait_timeout(fence, true, timeout);
1561                 dma_fence_put(fence);
1562                 if (r < 0)
1563                         return r;
1564
1565                 if (r == 0)
1566                         break;
1567
1568                 if (fence->error)
1569                         return fence->error;
1570         }
1571
1572         memset(wait, 0, sizeof(*wait));
1573         wait->out.status = (r > 0);
1574
1575         return 0;
1576 }
1577
1578 /**
1579  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1580  *
1581  * @adev: amdgpu device
1582  * @filp: file private
1583  * @wait: wait parameters
1584  * @fences: array of drm_amdgpu_fence
1585  */
1586 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1587                                     struct drm_file *filp,
1588                                     union drm_amdgpu_wait_fences *wait,
1589                                     struct drm_amdgpu_fence *fences)
1590 {
1591         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1592         uint32_t fence_count = wait->in.fence_count;
1593         uint32_t first = ~0;
1594         struct dma_fence **array;
1595         unsigned int i;
1596         long r;
1597
1598         /* Prepare the fence array */
1599         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1600
1601         if (array == NULL)
1602                 return -ENOMEM;
1603
1604         for (i = 0; i < fence_count; i++) {
1605                 struct dma_fence *fence;
1606
1607                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1608                 if (IS_ERR(fence)) {
1609                         r = PTR_ERR(fence);
1610                         goto err_free_fence_array;
1611                 } else if (fence) {
1612                         array[i] = fence;
1613                 } else { /* NULL, the fence has been already signaled */
1614                         r = 1;
1615                         first = i;
1616                         goto out;
1617                 }
1618         }
1619
1620         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1621                                        &first);
1622         if (r < 0)
1623                 goto err_free_fence_array;
1624
1625 out:
1626         memset(wait, 0, sizeof(*wait));
1627         wait->out.status = (r > 0);
1628         wait->out.first_signaled = first;
1629
1630         if (first < fence_count && array[first])
1631                 r = array[first]->error;
1632         else
1633                 r = 0;
1634
1635 err_free_fence_array:
1636         for (i = 0; i < fence_count; i++)
1637                 dma_fence_put(array[i]);
1638         kfree(array);
1639
1640         return r;
1641 }
1642
1643 /**
1644  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1645  *
1646  * @dev: drm device
1647  * @data: data from userspace
1648  * @filp: file private
1649  */
1650 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1651                                 struct drm_file *filp)
1652 {
1653         struct amdgpu_device *adev = drm_to_adev(dev);
1654         union drm_amdgpu_wait_fences *wait = data;
1655         uint32_t fence_count = wait->in.fence_count;
1656         struct drm_amdgpu_fence *fences_user;
1657         struct drm_amdgpu_fence *fences;
1658         int r;
1659
1660         /* Get the fences from userspace */
1661         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1662                         GFP_KERNEL);
1663         if (fences == NULL)
1664                 return -ENOMEM;
1665
1666         fences_user = u64_to_user_ptr(wait->in.fences);
1667         if (copy_from_user(fences, fences_user,
1668                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1669                 r = -EFAULT;
1670                 goto err_free_fences;
1671         }
1672
1673         if (wait->in.wait_all)
1674                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1675         else
1676                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1677
1678 err_free_fences:
1679         kfree(fences);
1680
1681         return r;
1682 }
1683
1684 /**
1685  * amdgpu_cs_find_mapping - find bo_va for VM address
1686  *
1687  * @parser: command submission parser context
1688  * @addr: VM address
1689  * @bo: resulting BO of the mapping found
1690  * @map: Placeholder to return found BO mapping
1691  *
1692  * Search the buffer objects in the command submission context for a certain
1693  * virtual memory address. Returns allocation structure when found, NULL
1694  * otherwise.
1695  */
1696 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1697                            uint64_t addr, struct amdgpu_bo **bo,
1698                            struct amdgpu_bo_va_mapping **map)
1699 {
1700         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1701         struct ttm_operation_ctx ctx = { false, false };
1702         struct amdgpu_vm *vm = &fpriv->vm;
1703         struct amdgpu_bo_va_mapping *mapping;
1704         int r;
1705
1706         addr /= AMDGPU_GPU_PAGE_SIZE;
1707
1708         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1709         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1710                 return -EINVAL;
1711
1712         *bo = mapping->bo_va->base.bo;
1713         *map = mapping;
1714
1715         /* Double check that the BO is reserved by this CS */
1716         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1717                 return -EINVAL;
1718
1719         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1720                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1721                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1722                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1723                 if (r)
1724                         return r;
1725         }
1726
1727         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1728 }