drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  71 {
  72         if (adev->pm.dpm_enabled) {
  73                 mutex_lock(&adev->pm.mutex);
  74                 if (power_supply_is_system_supplied() > 0)
  75                         adev->pm.ac_power = true;
  76                 else
  77                         adev->pm.ac_power = false;
  78                 if (adev->powerplay.pp_funcs->enable_bapm)
  79                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  80                 mutex_unlock(&adev->pm.mutex);
  81         }
  82 }
  83
  84 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  85                            void *data, uint32_t *size)
  86 {
  87         int ret = 0;
  88
  89         if (!data || !size)
  90                 return -EINVAL;
  91
  92         if (is_support_sw_smu(adev))
  93                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
  94         else {
  95                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  96                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
  97                                                                     sensor, data, size);
  98                 else
  99                         ret = -EINVAL;
 100         }
 101
 102         return ret;
 103 }
 104
 105 /**
 106  * DOC: power_dpm_state
 107  *
 108  * The power_dpm_state file is a legacy interface and is only provided for
 109  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 110  * certain power related parameters.  The file power_dpm_state is used for this.
 111  * It accepts the following arguments:
 112  *
 113  * - battery
 114  *
 115  * - balanced
 116  *
 117  * - performance
 118  *
 119  * battery
 120  *
 121  * On older GPUs, the vbios provided a special power state for battery
 122  * operation.  Selecting battery switched to this state.  This is no
 123  * longer provided on newer GPUs so the option does nothing in that case.
 124  *
 125  * balanced
 126  *
 127  * On older GPUs, the vbios provided a special power state for balanced
 128  * operation.  Selecting balanced switched to this state.  This is no
 129  * longer provided on newer GPUs so the option does nothing in that case.
 130  *
 131  * performance
 132  *
 133  * On older GPUs, the vbios provided a special power state for performance
 134  * operation.  Selecting performance switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  */
 138
 139 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 140                                     struct device_attribute *attr,
 141                                     char *buf)
 142 {
 143         struct drm_device *ddev = dev_get_drvdata(dev);
 144         struct amdgpu_device *adev = ddev->dev_private;
 145         enum amd_pm_state_type pm;
 146
 147         if (adev->smu.ppt_funcs->get_current_power_state)
 148                 pm = amdgpu_smu_get_current_power_state(adev);
 149         else if (adev->powerplay.pp_funcs->get_current_power_state)
 150                 pm = amdgpu_dpm_get_current_power_state(adev);
 151         else
 152                 pm = adev->pm.dpm.user_state;
 153
 154         return snprintf(buf, PAGE_SIZE, "%s\n",
 155                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 156                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 157 }
 158
 159 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 160                                     struct device_attribute *attr,
 161                                     const char *buf,
 162                                     size_t count)
 163 {
 164         struct drm_device *ddev = dev_get_drvdata(dev);
 165         struct amdgpu_device *adev = ddev->dev_private;
 166         enum amd_pm_state_type  state;
 167
 168         if (strncmp("battery", buf, strlen("battery")) == 0)
 169                 state = POWER_STATE_TYPE_BATTERY;
 170         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 171                 state = POWER_STATE_TYPE_BALANCED;
 172         else if (strncmp("performance", buf, strlen("performance")) == 0)
 173                 state = POWER_STATE_TYPE_PERFORMANCE;
 174         else {
 175                 count = -EINVAL;
 176                 goto fail;
 177         }
 178
 179         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 180                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 181         } else {
 182                 mutex_lock(&adev->pm.mutex);
 183                 adev->pm.dpm.user_state = state;
 184                 mutex_unlock(&adev->pm.mutex);
 185
 186                 /* Can't set dpm state when the card is off */
 187                 if (!(adev->flags & AMD_IS_PX) ||
 188                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 189                         amdgpu_pm_compute_clocks(adev);
 190         }
 191 fail:
 192         return count;
 193 }
 194
 195
 196 /**
 197  * DOC: power_dpm_force_performance_level
 198  *
 199  * The amdgpu driver provides a sysfs API for adjusting certain power
 200  * related parameters.  The file power_dpm_force_performance_level is
 201  * used for this.  It accepts the following arguments:
 202  *
 203  * - auto
 204  *
 205  * - low
 206  *
 207  * - high
 208  *
 209  * - manual
 210  *
 211  * - profile_standard
 212  *
 213  * - profile_min_sclk
 214  *
 215  * - profile_min_mclk
 216  *
 217  * - profile_peak
 218  *
 219  * auto
 220  *
 221  * When auto is selected, the driver will attempt to dynamically select
 222  * the optimal power profile for current conditions in the driver.
 223  *
 224  * low
 225  *
 226  * When low is selected, the clocks are forced to the lowest power state.
 227  *
 228  * high
 229  *
 230  * When high is selected, the clocks are forced to the highest power state.
 231  *
 232  * manual
 233  *
 234  * When manual is selected, the user can manually adjust which power states
 235  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 236  * and pp_dpm_pcie files and adjust the power state transition heuristics
 237  * via the pp_power_profile_mode sysfs file.
 238  *
 239  * profile_standard
 240  * profile_min_sclk
 241  * profile_min_mclk
 242  * profile_peak
 243  *
 244  * When the profiling modes are selected, clock and power gating are
 245  * disabled and the clocks are set for different profiling cases. This
 246  * mode is recommended for profiling specific work loads where you do
 247  * not want clock or power gating for clock fluctuation to interfere
 248  * with your results. profile_standard sets the clocks to a fixed clock
 249  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 250  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 251  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 252  *
 253  */
 254
 255 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 256                                                 struct device_attribute *attr,
 257                                                                 char *buf)
 258 {
 259         struct drm_device *ddev = dev_get_drvdata(dev);
 260         struct amdgpu_device *adev = ddev->dev_private;
 261         enum amd_dpm_forced_level level = 0xff;
 262
 263         if  ((adev->flags & AMD_IS_PX) &&
 264              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 265                 return snprintf(buf, PAGE_SIZE, "off\n");
 266
 267         if (is_support_sw_smu(adev))
 268                 level = smu_get_performance_level(&adev->smu);
 269         else if (adev->powerplay.pp_funcs->get_performance_level)
 270                 level = amdgpu_dpm_get_performance_level(adev);
 271         else
 272                 level = adev->pm.dpm.forced_level;
 273
 274         return snprintf(buf, PAGE_SIZE, "%s\n",
 275                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 276                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 277                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 278                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 279                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 280                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 281                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 282                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 283                         "unknown");
 284 }
 285
 286 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 287                                                        struct device_attribute *attr,
 288                                                        const char *buf,
 289                                                        size_t count)
 290 {
 291         struct drm_device *ddev = dev_get_drvdata(dev);
 292         struct amdgpu_device *adev = ddev->dev_private;
 293         enum amd_dpm_forced_level level;
 294         enum amd_dpm_forced_level current_level = 0xff;
 295         int ret = 0;
 296
 297         /* Can't force performance level when the card is off */
 298         if  ((adev->flags & AMD_IS_PX) &&
 299              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 300                 return -EINVAL;
 301
 302         if (is_support_sw_smu(adev))
 303                 current_level = smu_get_performance_level(&adev->smu);
 304         else if (adev->powerplay.pp_funcs->get_performance_level)
 305                 current_level = amdgpu_dpm_get_performance_level(adev);
 306
 307         if (strncmp("low", buf, strlen("low")) == 0) {
 308                 level = AMD_DPM_FORCED_LEVEL_LOW;
 309         } else if (strncmp("high", buf, strlen("high")) == 0) {
 310                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 311         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 312                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 313         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 315         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 317         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 319         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 321         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 323         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 325         }  else {
 326                 count = -EINVAL;
 327                 goto fail;
 328         }
 329
 330         if (current_level == level)
 331                 return count;
 332
 333         if (is_support_sw_smu(adev)) {
 334                 mutex_lock(&adev->pm.mutex);
 335                 if (adev->pm.dpm.thermal_active) {
 336                         count = -EINVAL;
 337                         mutex_unlock(&adev->pm.mutex);
 338                         goto fail;
 339                 }
 340                 ret = smu_force_performance_level(&adev->smu, level);
 341                 if (ret)
 342                         count = -EINVAL;
 343                 else
 344                         adev->pm.dpm.forced_level = level;
 345                 mutex_unlock(&adev->pm.mutex);
 346         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 347                 mutex_lock(&adev->pm.mutex);
 348                 if (adev->pm.dpm.thermal_active) {
 349                         count = -EINVAL;
 350                         mutex_unlock(&adev->pm.mutex);
 351                         goto fail;
 352                 }
 353                 ret = amdgpu_dpm_force_performance_level(adev, level);
 354                 if (ret)
 355                         count = -EINVAL;
 356                 else
 357                         adev->pm.dpm.forced_level = level;
 358                 mutex_unlock(&adev->pm.mutex);
 359         }
 360
 361 fail:
 362         return count;
 363 }
 364
 365 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 366                 struct device_attribute *attr,
 367                 char *buf)
 368 {
 369         struct drm_device *ddev = dev_get_drvdata(dev);
 370         struct amdgpu_device *adev = ddev->dev_private;
 371         struct pp_states_info data;
 372         int i, buf_len, ret;
 373
 374         if (is_support_sw_smu(adev)) {
 375                 ret = smu_get_power_num_states(&adev->smu, &data);
 376                 if (ret)
 377                         return ret;
 378         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 379                 amdgpu_dpm_get_pp_num_states(adev, &data);
 380
 381         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 382         for (i = 0; i < data.nums; i++)
 383                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 384                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 385                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 386                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 387                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 388
 389         return buf_len;
 390 }
 391
 392 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 393                 struct device_attribute *attr,
 394                 char *buf)
 395 {
 396         struct drm_device *ddev = dev_get_drvdata(dev);
 397         struct amdgpu_device *adev = ddev->dev_private;
 398         struct pp_states_info data;
 399         struct smu_context *smu = &adev->smu;
 400         enum amd_pm_state_type pm = 0;
 401         int i = 0, ret = 0;
 402
 403         if (is_support_sw_smu(adev)) {
 404                 pm = smu_get_current_power_state(smu);
 405                 ret = smu_get_power_num_states(smu, &data);
 406                 if (ret)
 407                         return ret;
 408         } else if (adev->powerplay.pp_funcs->get_current_power_state
 409                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 410                 pm = amdgpu_dpm_get_current_power_state(adev);
 411                 amdgpu_dpm_get_pp_num_states(adev, &data);
 412         }
 413
 414         for (i = 0; i < data.nums; i++) {
 415                 if (pm == data.states[i])
 416                         break;
 417         }
 418
 419         if (i == data.nums)
 420                 i = -EINVAL;
 421
 422         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 423 }
 424
 425 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 426                 struct device_attribute *attr,
 427                 char *buf)
 428 {
 429         struct drm_device *ddev = dev_get_drvdata(dev);
 430         struct amdgpu_device *adev = ddev->dev_private;
 431
 432         if (adev->pp_force_state_enabled)
 433                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 434         else
 435                 return snprintf(buf, PAGE_SIZE, "\n");
 436 }
 437
 438 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 439                 struct device_attribute *attr,
 440                 const char *buf,
 441                 size_t count)
 442 {
 443         struct drm_device *ddev = dev_get_drvdata(dev);
 444         struct amdgpu_device *adev = ddev->dev_private;
 445         enum amd_pm_state_type state = 0;
 446         unsigned long idx;
 447         int ret;
 448
 449         if (strlen(buf) == 1)
 450                 adev->pp_force_state_enabled = false;
 451         else if (is_support_sw_smu(adev))
 452                 adev->pp_force_state_enabled = false;
 453         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 454                         adev->powerplay.pp_funcs->get_pp_num_states) {
 455                 struct pp_states_info data;
 456
 457                 ret = kstrtoul(buf, 0, &idx);
 458                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 459                         count = -EINVAL;
 460                         goto fail;
 461                 }
 462                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 463
 464                 amdgpu_dpm_get_pp_num_states(adev, &data);
 465                 state = data.states[idx];
 466                 /* only set user selected power states */
 467                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 468                     state != POWER_STATE_TYPE_DEFAULT) {
 469                         amdgpu_dpm_dispatch_task(adev,
 470                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 471                         adev->pp_force_state_enabled = true;
 472                 }
 473         }
 474 fail:
 475         return count;
 476 }
 477
 478 /**
 479  * DOC: pp_table
 480  *
 481  * The amdgpu driver provides a sysfs API for uploading new powerplay
 482  * tables.  The file pp_table is used for this.  Reading the file
 483  * will dump the current power play table.  Writing to the file
 484  * will attempt to upload a new powerplay table and re-initialize
 485  * powerplay using that new table.
 486  *
 487  */
 488
 489 static ssize_t amdgpu_get_pp_table(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = ddev->dev_private;
 495         char *table = NULL;
 496         int size;
 497
 498         if (is_support_sw_smu(adev)) {
 499                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 500                 if (size < 0)
 501                         return size;
 502         }
 503         else if (adev->powerplay.pp_funcs->get_pp_table)
 504                 size = amdgpu_dpm_get_pp_table(adev, &table);
 505         else
 506                 return 0;
 507
 508         if (size >= PAGE_SIZE)
 509                 size = PAGE_SIZE - 1;
 510
 511         memcpy(buf, table, size);
 512
 513         return size;
 514 }
 515
 516 static ssize_t amdgpu_set_pp_table(struct device *dev,
 517                 struct device_attribute *attr,
 518                 const char *buf,
 519                 size_t count)
 520 {
 521         struct drm_device *ddev = dev_get_drvdata(dev);
 522         struct amdgpu_device *adev = ddev->dev_private;
 523         int ret = 0;
 524
 525         if (is_support_sw_smu(adev)) {
 526                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 527                 if (ret)
 528                         return ret;
 529         } else if (adev->powerplay.pp_funcs->set_pp_table)
 530                 amdgpu_dpm_set_pp_table(adev, buf, count);
 531
 532         return count;
 533 }
 534
 535 /**
 536  * DOC: pp_od_clk_voltage
 537  *
 538  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 539  * in each power level within a power state.  The pp_od_clk_voltage is used for
 540  * this.
 541  *
 542  * < For Vega10 and previous ASICs >
 543  *
 544  * Reading the file will display:
 545  *
 546  * - a list of engine clock levels and voltages labeled OD_SCLK
 547  *
 548  * - a list of memory clock levels and voltages labeled OD_MCLK
 549  *
 550  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 551  *
 552  * To manually adjust these settings, first select manual using
 553  * power_dpm_force_performance_level. Enter a new value for each
 554  * level by writing a string that contains "s/m level clock voltage" to
 555  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 556  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 557  * 810 mV.  When you have edited all of the states as needed, write
 558  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 559  * default power levels, write "r" (reset) to the file to reset them.
 560  *
 561  *
 562  * < For Vega20 >
 563  *
 564  * Reading the file will display:
 565  *
 566  * - minimum and maximum engine clock labeled OD_SCLK
 567  *
 568  * - maximum memory clock labeled OD_MCLK
 569  *
 570  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 571  *   They can be used to calibrate the sclk voltage curve.
 572  *
 573  * - a list of valid ranges for sclk, mclk, and voltage curve points
 574  *   labeled OD_RANGE
 575  *
 576  * To manually adjust these settings:
 577  *
 578  * - First select manual using power_dpm_force_performance_level
 579  *
 580  * - For clock frequency setting, enter a new value by writing a
 581  *   string that contains "s/m index clock" to the file. The index
 582  *   should be 0 if to set minimum clock. And 1 if to set maximum
 583  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 584  *   "m 1 800" will update maximum mclk to be 800Mhz.
 585  *
 586  *   For sclk voltage curve, enter the new values by writing a
 587  *   string that contains "vc point clock voltage" to the file. The
 588  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 589  *   update point1 with clock set as 300Mhz and voltage as
 590  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 591  *   as 1000Mhz and voltage 1000mV.
 592  *
 593  * - When you have edited all of the states as needed, write "c" (commit)
 594  *   to the file to commit your changes
 595  *
 596  * - If you want to reset to the default power levels, write "r" (reset)
 597  *   to the file to reset them
 598  *
 599  */
 600
 601 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 602                 struct device_attribute *attr,
 603                 const char *buf,
 604                 size_t count)
 605 {
 606         struct drm_device *ddev = dev_get_drvdata(dev);
 607         struct amdgpu_device *adev = ddev->dev_private;
 608         int ret;
 609         uint32_t parameter_size = 0;
 610         long parameter[64];
 611         char buf_cpy[128];
 612         char *tmp_str;
 613         char *sub_str;
 614         const char delimiter[3] = {' ', '\n', '\0'};
 615         uint32_t type;
 616
 617         if (count > 127)
 618                 return -EINVAL;
 619
 620         if (*buf == 's')
 621                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 622         else if (*buf == 'm')
 623                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 624         else if(*buf == 'r')
 625                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 626         else if (*buf == 'c')
 627                 type = PP_OD_COMMIT_DPM_TABLE;
 628         else if (!strncmp(buf, "vc", 2))
 629                 type = PP_OD_EDIT_VDDC_CURVE;
 630         else
 631                 return -EINVAL;
 632
 633         memcpy(buf_cpy, buf, count+1);
 634
 635         tmp_str = buf_cpy;
 636
 637         if (type == PP_OD_EDIT_VDDC_CURVE)
 638                 tmp_str++;
 639         while (isspace(*++tmp_str));
 640
 641         while (tmp_str[0]) {
 642                 sub_str = strsep(&tmp_str, delimiter);
 643                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 644                 if (ret)
 645                         return -EINVAL;
 646                 parameter_size++;
 647
 648                 while (isspace(*tmp_str))
 649                         tmp_str++;
 650         }
 651
 652         if (is_support_sw_smu(adev)) {
 653                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 654                                             parameter, parameter_size);
 655
 656                 if (ret)
 657                         return -EINVAL;
 658         } else {
 659                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 660                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 661                                                 parameter, parameter_size);
 662
 663                 if (ret)
 664                         return -EINVAL;
 665
 666                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 667                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 668                                 amdgpu_dpm_dispatch_task(adev,
 669                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 670                                                 NULL);
 671                                 return count;
 672                         } else {
 673                                 return -EINVAL;
 674                         }
 675                 }
 676         }
 677
 678         return count;
 679 }
 680
 681 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 682                 struct device_attribute *attr,
 683                 char *buf)
 684 {
 685         struct drm_device *ddev = dev_get_drvdata(dev);
 686         struct amdgpu_device *adev = ddev->dev_private;
 687         uint32_t size = 0;
 688
 689         if (is_support_sw_smu(adev)) {
 690                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 691                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 692                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 693                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 694                 return size;
 695         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 696                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 697                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 698                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 699                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 700                 return size;
 701         } else {
 702                 return snprintf(buf, PAGE_SIZE, "\n");
 703         }
 704
 705 }
 706
 707 /**
 708  * DOC: ppfeatures
 709  *
 710  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 711  * features to be enabled. The file ppfeatures is used for this. And
 712  * this is only available for Vega10 and later dGPUs.
 713  *
 714  * Reading back the file will show you the followings:
 715  * - Current ppfeature masks
 716  * - List of the all supported powerplay features with their naming,
 717  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 718  *
 719  * To manually enable or disable a specific feature, just set or clear
 720  * the corresponding bit from original ppfeature masks and input the
 721  * new ppfeature masks.
 722  */
 723 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 724                 struct device_attribute *attr,
 725                 const char *buf,
 726                 size_t count)
 727 {
 728         struct drm_device *ddev = dev_get_drvdata(dev);
 729         struct amdgpu_device *adev = ddev->dev_private;
 730         uint64_t featuremask;
 731         int ret;
 732
 733         ret = kstrtou64(buf, 0, &featuremask);
 734         if (ret)
 735                 return -EINVAL;
 736
 737         pr_debug("featuremask = 0x%llx\n", featuremask);
 738
 739         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 740                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 741                 if (ret)
 742                         return -EINVAL;
 743         }
 744
 745         return count;
 746 }
 747
 748 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 749                 struct device_attribute *attr,
 750                 char *buf)
 751 {
 752         struct drm_device *ddev = dev_get_drvdata(dev);
 753         struct amdgpu_device *adev = ddev->dev_private;
 754
 755         if (adev->powerplay.pp_funcs->get_ppfeature_status)
 756                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 757
 758         return snprintf(buf, PAGE_SIZE, "\n");
 759 }
 760
 761 /**
 762  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 763  * pp_dpm_pcie
 764  *
 765  * The amdgpu driver provides a sysfs API for adjusting what power levels
 766  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 767  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 768  * this.
 769  *
 770  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 771  * Vega10 and later ASICs.
 772  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 773  *
 774  * Reading back the files will show you the available power levels within
 775  * the power state and the clock information for those levels.
 776  *
 777  * To manually adjust these states, first select manual using
 778  * power_dpm_force_performance_level.
 779  * Secondly,Enter a new value for each level by inputing a string that
 780  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 781  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 782  *
 783  * NOTE: change to the dcefclk max dpm level is not supported now
 784  */
 785
 786 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 787                 struct device_attribute *attr,
 788                 char *buf)
 789 {
 790         struct drm_device *ddev = dev_get_drvdata(dev);
 791         struct amdgpu_device *adev = ddev->dev_private;
 792
 793         if (is_support_sw_smu(adev))
 794                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 795         else if (adev->powerplay.pp_funcs->print_clock_levels)
 796                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 797         else
 798                 return snprintf(buf, PAGE_SIZE, "\n");
 799 }
 800
 801 /*
 802  * Worst case: 32 bits individually specified, in octal at 12 characters
 803  * per line (+1 for \n).
 804  */
 805 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 806
 807 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 808 {
 809         int ret;
 810         long level;
 811         char *sub_str = NULL;
 812         char *tmp;
 813         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 814         const char delimiter[3] = {' ', '\n', '\0'};
 815         size_t bytes;
 816
 817         *mask = 0;
 818
 819         bytes = min(count, sizeof(buf_cpy) - 1);
 820         memcpy(buf_cpy, buf, bytes);
 821         buf_cpy[bytes] = '\0';
 822         tmp = buf_cpy;
 823         while (tmp[0]) {
 824                 sub_str = strsep(&tmp, delimiter);
 825                 if (strlen(sub_str)) {
 826                         ret = kstrtol(sub_str, 0, &level);
 827                         if (ret)
 828                                 return -EINVAL;
 829                         *mask |= 1 << level;
 830                 } else
 831                         break;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 838                 struct device_attribute *attr,
 839                 const char *buf,
 840                 size_t count)
 841 {
 842         struct drm_device *ddev = dev_get_drvdata(dev);
 843         struct amdgpu_device *adev = ddev->dev_private;
 844         int ret;
 845         uint32_t mask = 0;
 846
 847         ret = amdgpu_read_mask(buf, count, &mask);
 848         if (ret)
 849                 return ret;
 850
 851         if (is_support_sw_smu(adev))
 852                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 853         else if (adev->powerplay.pp_funcs->force_clock_level)
 854                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 855
 856         if (ret)
 857                 return -EINVAL;
 858
 859         return count;
 860 }
 861
 862 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 863                 struct device_attribute *attr,
 864                 char *buf)
 865 {
 866         struct drm_device *ddev = dev_get_drvdata(dev);
 867         struct amdgpu_device *adev = ddev->dev_private;
 868
 869         if (is_support_sw_smu(adev))
 870                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 871         else if (adev->powerplay.pp_funcs->print_clock_levels)
 872                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 873         else
 874                 return snprintf(buf, PAGE_SIZE, "\n");
 875 }
 876
 877 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 878                 struct device_attribute *attr,
 879                 const char *buf,
 880                 size_t count)
 881 {
 882         struct drm_device *ddev = dev_get_drvdata(dev);
 883         struct amdgpu_device *adev = ddev->dev_private;
 884         int ret;
 885         uint32_t mask = 0;
 886
 887         ret = amdgpu_read_mask(buf, count, &mask);
 888         if (ret)
 889                 return ret;
 890
 891         if (is_support_sw_smu(adev))
 892                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 893         else if (adev->powerplay.pp_funcs->force_clock_level)
 894                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 895
 896         if (ret)
 897                 return -EINVAL;
 898
 899         return count;
 900 }
 901
 902 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 903                 struct device_attribute *attr,
 904                 char *buf)
 905 {
 906         struct drm_device *ddev = dev_get_drvdata(dev);
 907         struct amdgpu_device *adev = ddev->dev_private;
 908
 909         if (is_support_sw_smu(adev))
 910                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 911         else if (adev->powerplay.pp_funcs->print_clock_levels)
 912                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 913         else
 914                 return snprintf(buf, PAGE_SIZE, "\n");
 915 }
 916
 917 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 918                 struct device_attribute *attr,
 919                 const char *buf,
 920                 size_t count)
 921 {
 922         struct drm_device *ddev = dev_get_drvdata(dev);
 923         struct amdgpu_device *adev = ddev->dev_private;
 924         int ret;
 925         uint32_t mask = 0;
 926
 927         ret = amdgpu_read_mask(buf, count, &mask);
 928         if (ret)
 929                 return ret;
 930
 931         if (is_support_sw_smu(adev))
 932                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 933         else if (adev->powerplay.pp_funcs->force_clock_level)
 934                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 935
 936         if (ret)
 937                 return -EINVAL;
 938
 939         return count;
 940 }
 941
 942 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 943                 struct device_attribute *attr,
 944                 char *buf)
 945 {
 946         struct drm_device *ddev = dev_get_drvdata(dev);
 947         struct amdgpu_device *adev = ddev->dev_private;
 948
 949         if (is_support_sw_smu(adev))
 950                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
 951         else if (adev->powerplay.pp_funcs->print_clock_levels)
 952                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 953         else
 954                 return snprintf(buf, PAGE_SIZE, "\n");
 955 }
 956
 957 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 958                 struct device_attribute *attr,
 959                 const char *buf,
 960                 size_t count)
 961 {
 962         struct drm_device *ddev = dev_get_drvdata(dev);
 963         struct amdgpu_device *adev = ddev->dev_private;
 964         int ret;
 965         uint32_t mask = 0;
 966
 967         ret = amdgpu_read_mask(buf, count, &mask);
 968         if (ret)
 969                 return ret;
 970
 971         if (is_support_sw_smu(adev))
 972                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
 973         else if (adev->powerplay.pp_funcs->force_clock_level)
 974                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
 975
 976         if (ret)
 977                 return -EINVAL;
 978
 979         return count;
 980 }
 981
 982 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
 983                 struct device_attribute *attr,
 984                 char *buf)
 985 {
 986         struct drm_device *ddev = dev_get_drvdata(dev);
 987         struct amdgpu_device *adev = ddev->dev_private;
 988
 989         if (is_support_sw_smu(adev))
 990                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
 991         else if (adev->powerplay.pp_funcs->print_clock_levels)
 992                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
 993         else
 994                 return snprintf(buf, PAGE_SIZE, "\n");
 995 }
 996
 997 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
 998                 struct device_attribute *attr,
 999                 const char *buf,
1000                 size_t count)
1001 {
1002         struct drm_device *ddev = dev_get_drvdata(dev);
1003         struct amdgpu_device *adev = ddev->dev_private;
1004         int ret;
1005         uint32_t mask = 0;
1006
1007         ret = amdgpu_read_mask(buf, count, &mask);
1008         if (ret)
1009                 return ret;
1010
1011         if (is_support_sw_smu(adev))
1012                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1013         else if (adev->powerplay.pp_funcs->force_clock_level)
1014                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1015
1016         if (ret)
1017                 return -EINVAL;
1018
1019         return count;
1020 }
1021
1022 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1023                 struct device_attribute *attr,
1024                 char *buf)
1025 {
1026         struct drm_device *ddev = dev_get_drvdata(dev);
1027         struct amdgpu_device *adev = ddev->dev_private;
1028
1029         if (is_support_sw_smu(adev))
1030                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1031         else if (adev->powerplay.pp_funcs->print_clock_levels)
1032                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1033         else
1034                 return snprintf(buf, PAGE_SIZE, "\n");
1035 }
1036
1037 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1038                 struct device_attribute *attr,
1039                 const char *buf,
1040                 size_t count)
1041 {
1042         struct drm_device *ddev = dev_get_drvdata(dev);
1043         struct amdgpu_device *adev = ddev->dev_private;
1044         int ret;
1045         uint32_t mask = 0;
1046
1047         ret = amdgpu_read_mask(buf, count, &mask);
1048         if (ret)
1049                 return ret;
1050
1051         if (is_support_sw_smu(adev))
1052                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1053         else if (adev->powerplay.pp_funcs->force_clock_level)
1054                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1055
1056         if (ret)
1057                 return -EINVAL;
1058
1059         return count;
1060 }
1061
1062 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1063                 struct device_attribute *attr,
1064                 char *buf)
1065 {
1066         struct drm_device *ddev = dev_get_drvdata(dev);
1067         struct amdgpu_device *adev = ddev->dev_private;
1068         uint32_t value = 0;
1069
1070         if (is_support_sw_smu(adev))
1071                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1072         else if (adev->powerplay.pp_funcs->get_sclk_od)
1073                 value = amdgpu_dpm_get_sclk_od(adev);
1074
1075         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1076 }
1077
1078 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1079                 struct device_attribute *attr,
1080                 const char *buf,
1081                 size_t count)
1082 {
1083         struct drm_device *ddev = dev_get_drvdata(dev);
1084         struct amdgpu_device *adev = ddev->dev_private;
1085         int ret;
1086         long int value;
1087
1088         ret = kstrtol(buf, 0, &value);
1089
1090         if (ret) {
1091                 count = -EINVAL;
1092                 goto fail;
1093         }
1094
1095         if (is_support_sw_smu(adev)) {
1096                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1097         } else {
1098                 if (adev->powerplay.pp_funcs->set_sclk_od)
1099                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1100
1101                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1102                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1103                 } else {
1104                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1105                         amdgpu_pm_compute_clocks(adev);
1106                 }
1107         }
1108
1109 fail:
1110         return count;
1111 }
1112
1113 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1114                 struct device_attribute *attr,
1115                 char *buf)
1116 {
1117         struct drm_device *ddev = dev_get_drvdata(dev);
1118         struct amdgpu_device *adev = ddev->dev_private;
1119         uint32_t value = 0;
1120
1121         if (is_support_sw_smu(adev))
1122                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1123         else if (adev->powerplay.pp_funcs->get_mclk_od)
1124                 value = amdgpu_dpm_get_mclk_od(adev);
1125
1126         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1127 }
1128
1129 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1130                 struct device_attribute *attr,
1131                 const char *buf,
1132                 size_t count)
1133 {
1134         struct drm_device *ddev = dev_get_drvdata(dev);
1135         struct amdgpu_device *adev = ddev->dev_private;
1136         int ret;
1137         long int value;
1138
1139         ret = kstrtol(buf, 0, &value);
1140
1141         if (ret) {
1142                 count = -EINVAL;
1143                 goto fail;
1144         }
1145
1146         if (is_support_sw_smu(adev)) {
1147                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1148         } else {
1149                 if (adev->powerplay.pp_funcs->set_mclk_od)
1150                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1151
1152                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1153                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1154                 } else {
1155                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1156                         amdgpu_pm_compute_clocks(adev);
1157                 }
1158         }
1159
1160 fail:
1161         return count;
1162 }
1163
1164 /**
1165  * DOC: pp_power_profile_mode
1166  *
1167  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1168  * related to switching between power levels in a power state.  The file
1169  * pp_power_profile_mode is used for this.
1170  *
1171  * Reading this file outputs a list of all of the predefined power profiles
1172  * and the relevant heuristics settings for that profile.
1173  *
1174  * To select a profile or create a custom profile, first select manual using
1175  * power_dpm_force_performance_level.  Writing the number of a predefined
1176  * profile to pp_power_profile_mode will enable those heuristics.  To
1177  * create a custom set of heuristics, write a string of numbers to the file
1178  * starting with the number of the custom profile along with a setting
1179  * for each heuristic parameter.  Due to differences across asic families
1180  * the heuristic parameters vary from family to family.
1181  *
1182  */
1183
1184 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1185                 struct device_attribute *attr,
1186                 char *buf)
1187 {
1188         struct drm_device *ddev = dev_get_drvdata(dev);
1189         struct amdgpu_device *adev = ddev->dev_private;
1190
1191         if (is_support_sw_smu(adev))
1192                 return smu_get_power_profile_mode(&adev->smu, buf);
1193         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1194                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1195
1196         return snprintf(buf, PAGE_SIZE, "\n");
1197 }
1198
1199
1200 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1201                 struct device_attribute *attr,
1202                 const char *buf,
1203                 size_t count)
1204 {
1205         int ret = 0xff;
1206         struct drm_device *ddev = dev_get_drvdata(dev);
1207         struct amdgpu_device *adev = ddev->dev_private;
1208         uint32_t parameter_size = 0;
1209         long parameter[64];
1210         char *sub_str, buf_cpy[128];
1211         char *tmp_str;
1212         uint32_t i = 0;
1213         char tmp[2];
1214         long int profile_mode = 0;
1215         const char delimiter[3] = {' ', '\n', '\0'};
1216
1217         tmp[0] = *(buf);
1218         tmp[1] = '\0';
1219         ret = kstrtol(tmp, 0, &profile_mode);
1220         if (ret)
1221                 goto fail;
1222
1223         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1224                 if (count < 2 || count > 127)
1225                         return -EINVAL;
1226                 while (isspace(*++buf))
1227                         i++;
1228                 memcpy(buf_cpy, buf, count-i);
1229                 tmp_str = buf_cpy;
1230                 while (tmp_str[0]) {
1231                         sub_str = strsep(&tmp_str, delimiter);
1232                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1233                         if (ret) {
1234                                 count = -EINVAL;
1235                                 goto fail;
1236                         }
1237                         parameter_size++;
1238                         while (isspace(*tmp_str))
1239                                 tmp_str++;
1240                 }
1241         }
1242         parameter[parameter_size] = profile_mode;
1243         if (is_support_sw_smu(adev))
1244                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1245         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1246                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1247         if (!ret)
1248                 return count;
1249 fail:
1250         return -EINVAL;
1251 }
1252
1253 /**
1254  * DOC: busy_percent
1255  *
1256  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1257  * is as a percentage.  The file gpu_busy_percent is used for this.
1258  * The SMU firmware computes a percentage of load based on the
1259  * aggregate activity level in the IP cores.
1260  */
1261 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1262                 struct device_attribute *attr,
1263                 char *buf)
1264 {
1265         struct drm_device *ddev = dev_get_drvdata(dev);
1266         struct amdgpu_device *adev = ddev->dev_private;
1267         int r, value, size = sizeof(value);
1268
1269         /* read the IP busy sensor */
1270         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1271                                    (void *)&value, &size);
1272
1273         if (r)
1274                 return r;
1275
1276         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1277 }
1278
1279 /**
1280  * DOC: pcie_bw
1281  *
1282  * The amdgpu driver provides a sysfs API for estimating how much data
1283  * has been received and sent by the GPU in the last second through PCIe.
1284  * The file pcie_bw is used for this.
1285  * The Perf counters count the number of received and sent messages and return
1286  * those values, as well as the maximum payload size of a PCIe packet (mps).
1287  * Note that it is not possible to easily and quickly obtain the size of each
1288  * packet transmitted, so we output the max payload size (mps) to allow for
1289  * quick estimation of the PCIe bandwidth usage
1290  */
1291 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1292                 struct device_attribute *attr,
1293                 char *buf)
1294 {
1295         struct drm_device *ddev = dev_get_drvdata(dev);
1296         struct amdgpu_device *adev = ddev->dev_private;
1297         uint64_t count0, count1;
1298
1299         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1300         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1301                         count0, count1, pcie_get_mps(adev->pdev));
1302 }
1303
1304 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1305 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1306                    amdgpu_get_dpm_forced_performance_level,
1307                    amdgpu_set_dpm_forced_performance_level);
1308 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1309 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1310 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1311                 amdgpu_get_pp_force_state,
1312                 amdgpu_set_pp_force_state);
1313 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1314                 amdgpu_get_pp_table,
1315                 amdgpu_set_pp_table);
1316 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1317                 amdgpu_get_pp_dpm_sclk,
1318                 amdgpu_set_pp_dpm_sclk);
1319 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1320                 amdgpu_get_pp_dpm_mclk,
1321                 amdgpu_set_pp_dpm_mclk);
1322 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1323                 amdgpu_get_pp_dpm_socclk,
1324                 amdgpu_set_pp_dpm_socclk);
1325 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1326                 amdgpu_get_pp_dpm_fclk,
1327                 amdgpu_set_pp_dpm_fclk);
1328 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1329                 amdgpu_get_pp_dpm_dcefclk,
1330                 amdgpu_set_pp_dpm_dcefclk);
1331 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1332                 amdgpu_get_pp_dpm_pcie,
1333                 amdgpu_set_pp_dpm_pcie);
1334 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1335                 amdgpu_get_pp_sclk_od,
1336                 amdgpu_set_pp_sclk_od);
1337 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1338                 amdgpu_get_pp_mclk_od,
1339                 amdgpu_set_pp_mclk_od);
1340 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1341                 amdgpu_get_pp_power_profile_mode,
1342                 amdgpu_set_pp_power_profile_mode);
1343 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1344                 amdgpu_get_pp_od_clk_voltage,
1345                 amdgpu_set_pp_od_clk_voltage);
1346 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1347                 amdgpu_get_busy_percent, NULL);
1348 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1349 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1350                 amdgpu_get_ppfeature_status,
1351                 amdgpu_set_ppfeature_status);
1352
1353 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1354                                       struct device_attribute *attr,
1355                                       char *buf)
1356 {
1357         struct amdgpu_device *adev = dev_get_drvdata(dev);
1358         struct drm_device *ddev = adev->ddev;
1359         int r, temp, size = sizeof(temp);
1360
1361         /* Can't get temperature when the card is off */
1362         if  ((adev->flags & AMD_IS_PX) &&
1363              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1364                 return -EINVAL;
1365
1366         /* get the temperature */
1367         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1368                                    (void *)&temp, &size);
1369         if (r)
1370                 return r;
1371
1372         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1373 }
1374
1375 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1376                                              struct device_attribute *attr,
1377                                              char *buf)
1378 {
1379         struct amdgpu_device *adev = dev_get_drvdata(dev);
1380         int hyst = to_sensor_dev_attr(attr)->index;
1381         int temp;
1382
1383         if (hyst)
1384                 temp = adev->pm.dpm.thermal.min_temp;
1385         else
1386                 temp = adev->pm.dpm.thermal.max_temp;
1387
1388         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1389 }
1390
1391 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1392                                             struct device_attribute *attr,
1393                                             char *buf)
1394 {
1395         struct amdgpu_device *adev = dev_get_drvdata(dev);
1396         u32 pwm_mode = 0;
1397         if (is_support_sw_smu(adev)) {
1398                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1399         } else {
1400                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1401                         return -EINVAL;
1402
1403                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1404         }
1405
1406         return sprintf(buf, "%i\n", pwm_mode);
1407 }
1408
1409 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1410                                             struct device_attribute *attr,
1411                                             const char *buf,
1412                                             size_t count)
1413 {
1414         struct amdgpu_device *adev = dev_get_drvdata(dev);
1415         int err;
1416         int value;
1417
1418         /* Can't adjust fan when the card is off */
1419         if  ((adev->flags & AMD_IS_PX) &&
1420              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1421                 return -EINVAL;
1422
1423         if (is_support_sw_smu(adev)) {
1424                 err = kstrtoint(buf, 10, &value);
1425                 if (err)
1426                         return err;
1427
1428                 smu_set_fan_control_mode(&adev->smu, value);
1429         } else {
1430                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1431                         return -EINVAL;
1432
1433                 err = kstrtoint(buf, 10, &value);
1434                 if (err)
1435                         return err;
1436
1437                 amdgpu_dpm_set_fan_control_mode(adev, value);
1438         }
1439
1440         return count;
1441 }
1442
1443 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1444                                          struct device_attribute *attr,
1445                                          char *buf)
1446 {
1447         return sprintf(buf, "%i\n", 0);
1448 }
1449
1450 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1451                                          struct device_attribute *attr,
1452                                          char *buf)
1453 {
1454         return sprintf(buf, "%i\n", 255);
1455 }
1456
1457 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1458                                      struct device_attribute *attr,
1459                                      const char *buf, size_t count)
1460 {
1461         struct amdgpu_device *adev = dev_get_drvdata(dev);
1462         int err;
1463         u32 value;
1464         u32 pwm_mode;
1465
1466         /* Can't adjust fan when the card is off */
1467         if  ((adev->flags & AMD_IS_PX) &&
1468              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1469                 return -EINVAL;
1470         if (is_support_sw_smu(adev))
1471                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1472         else
1473                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1474         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1475                 pr_info("manual fan speed control should be enabled first\n");
1476                 return -EINVAL;
1477         }
1478
1479         err = kstrtou32(buf, 10, &value);
1480         if (err)
1481                 return err;
1482
1483         value = (value * 100) / 255;
1484
1485         if (is_support_sw_smu(adev)) {
1486                 err = smu_set_fan_speed_percent(&adev->smu, value);
1487                 if (err)
1488                         return err;
1489         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1490                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1491                 if (err)
1492                         return err;
1493         }
1494
1495         return count;
1496 }
1497
1498 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1499                                      struct device_attribute *attr,
1500                                      char *buf)
1501 {
1502         struct amdgpu_device *adev = dev_get_drvdata(dev);
1503         int err;
1504         u32 speed = 0;
1505
1506         /* Can't adjust fan when the card is off */
1507         if  ((adev->flags & AMD_IS_PX) &&
1508              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1509                 return -EINVAL;
1510
1511         if (is_support_sw_smu(adev)) {
1512                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1513                 if (err)
1514                         return err;
1515         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1516                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1517                 if (err)
1518                         return err;
1519         }
1520
1521         speed = (speed * 255) / 100;
1522
1523         return sprintf(buf, "%i\n", speed);
1524 }
1525
1526 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1527                                            struct device_attribute *attr,
1528                                            char *buf)
1529 {
1530         struct amdgpu_device *adev = dev_get_drvdata(dev);
1531         int err;
1532         u32 speed = 0;
1533
1534         /* Can't adjust fan when the card is off */
1535         if  ((adev->flags & AMD_IS_PX) &&
1536              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1537                 return -EINVAL;
1538
1539         if (is_support_sw_smu(adev)) {
1540                 err = smu_get_current_rpm(&adev->smu, &speed);
1541                 if (err)
1542                         return err;
1543         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1544                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1545                 if (err)
1546                         return err;
1547         }
1548
1549         return sprintf(buf, "%i\n", speed);
1550 }
1551
1552 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1553                                          struct device_attribute *attr,
1554                                          char *buf)
1555 {
1556         struct amdgpu_device *adev = dev_get_drvdata(dev);
1557         u32 min_rpm = 0;
1558         u32 size = sizeof(min_rpm);
1559         int r;
1560
1561         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1562                                    (void *)&min_rpm, &size);
1563         if (r)
1564                 return r;
1565
1566         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1567 }
1568
1569 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1570                                          struct device_attribute *attr,
1571                                          char *buf)
1572 {
1573         struct amdgpu_device *adev = dev_get_drvdata(dev);
1574         u32 max_rpm = 0;
1575         u32 size = sizeof(max_rpm);
1576         int r;
1577
1578         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1579                                    (void *)&max_rpm, &size);
1580         if (r)
1581                 return r;
1582
1583         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1584 }
1585
1586 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1587                                            struct device_attribute *attr,
1588                                            char *buf)
1589 {
1590         struct amdgpu_device *adev = dev_get_drvdata(dev);
1591         int err;
1592         u32 rpm = 0;
1593
1594         /* Can't adjust fan when the card is off */
1595         if  ((adev->flags & AMD_IS_PX) &&
1596              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1597                 return -EINVAL;
1598
1599         if (is_support_sw_smu(adev)) {
1600                 err = smu_get_current_rpm(&adev->smu, &rpm);
1601                 if (err)
1602                         return err;
1603         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1604                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1605                 if (err)
1606                         return err;
1607         }
1608
1609         return sprintf(buf, "%i\n", rpm);
1610 }
1611
1612 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1613                                      struct device_attribute *attr,
1614                                      const char *buf, size_t count)
1615 {
1616         struct amdgpu_device *adev = dev_get_drvdata(dev);
1617         int err;
1618         u32 value;
1619         u32 pwm_mode;
1620
1621         if (is_support_sw_smu(adev))
1622                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1623         else
1624                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1625
1626         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1627                 return -ENODATA;
1628
1629         /* Can't adjust fan when the card is off */
1630         if  ((adev->flags & AMD_IS_PX) &&
1631              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1632                 return -EINVAL;
1633
1634         err = kstrtou32(buf, 10, &value);
1635         if (err)
1636                 return err;
1637
1638         if (is_support_sw_smu(adev)) {
1639                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1640                 if (err)
1641                         return err;
1642         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1643                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1644                 if (err)
1645                         return err;
1646         }
1647
1648         return count;
1649 }
1650
1651 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1652                                             struct device_attribute *attr,
1653                                             char *buf)
1654 {
1655         struct amdgpu_device *adev = dev_get_drvdata(dev);
1656         u32 pwm_mode = 0;
1657
1658         if (is_support_sw_smu(adev)) {
1659                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1660         } else {
1661                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1662                         return -EINVAL;
1663
1664                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1665         }
1666         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1667 }
1668
1669 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1670                                             struct device_attribute *attr,
1671                                             const char *buf,
1672                                             size_t count)
1673 {
1674         struct amdgpu_device *adev = dev_get_drvdata(dev);
1675         int err;
1676         int value;
1677         u32 pwm_mode;
1678
1679         /* Can't adjust fan when the card is off */
1680         if  ((adev->flags & AMD_IS_PX) &&
1681              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1682                 return -EINVAL;
1683
1684
1685         err = kstrtoint(buf, 10, &value);
1686         if (err)
1687                 return err;
1688
1689         if (value == 0)
1690                 pwm_mode = AMD_FAN_CTRL_AUTO;
1691         else if (value == 1)
1692                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1693         else
1694                 return -EINVAL;
1695
1696         if (is_support_sw_smu(adev)) {
1697                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1698         } else {
1699                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1700                         return -EINVAL;
1701                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1702         }
1703
1704         return count;
1705 }
1706
1707 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1708                                         struct device_attribute *attr,
1709                                         char *buf)
1710 {
1711         struct amdgpu_device *adev = dev_get_drvdata(dev);
1712         struct drm_device *ddev = adev->ddev;
1713         u32 vddgfx;
1714         int r, size = sizeof(vddgfx);
1715
1716         /* Can't get voltage when the card is off */
1717         if  ((adev->flags & AMD_IS_PX) &&
1718              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1719                 return -EINVAL;
1720
1721         /* get the voltage */
1722         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1723                                    (void *)&vddgfx, &size);
1724         if (r)
1725                 return r;
1726
1727         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1728 }
1729
1730 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1731                                               struct device_attribute *attr,
1732                                               char *buf)
1733 {
1734         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1735 }
1736
1737 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1738                                        struct device_attribute *attr,
1739                                        char *buf)
1740 {
1741         struct amdgpu_device *adev = dev_get_drvdata(dev);
1742         struct drm_device *ddev = adev->ddev;
1743         u32 vddnb;
1744         int r, size = sizeof(vddnb);
1745
1746         /* only APUs have vddnb */
1747         if  (!(adev->flags & AMD_IS_APU))
1748                 return -EINVAL;
1749
1750         /* Can't get voltage when the card is off */
1751         if  ((adev->flags & AMD_IS_PX) &&
1752              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1753                 return -EINVAL;
1754
1755         /* get the voltage */
1756         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1757                                    (void *)&vddnb, &size);
1758         if (r)
1759                 return r;
1760
1761         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1762 }
1763
1764 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1765                                               struct device_attribute *attr,
1766                                               char *buf)
1767 {
1768         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1769 }
1770
1771 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1772                                            struct device_attribute *attr,
1773                                            char *buf)
1774 {
1775         struct amdgpu_device *adev = dev_get_drvdata(dev);
1776         struct drm_device *ddev = adev->ddev;
1777         u32 query = 0;
1778         int r, size = sizeof(u32);
1779         unsigned uw;
1780
1781         /* Can't get power when the card is off */
1782         if  ((adev->flags & AMD_IS_PX) &&
1783              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1784                 return -EINVAL;
1785
1786         /* get the voltage */
1787         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1788                                    (void *)&query, &size);
1789         if (r)
1790                 return r;
1791
1792         /* convert to microwatts */
1793         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1794
1795         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1796 }
1797
1798 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1799                                          struct device_attribute *attr,
1800                                          char *buf)
1801 {
1802         return sprintf(buf, "%i\n", 0);
1803 }
1804
1805 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1806                                          struct device_attribute *attr,
1807                                          char *buf)
1808 {
1809         struct amdgpu_device *adev = dev_get_drvdata(dev);
1810         uint32_t limit = 0;
1811
1812         if (is_support_sw_smu(adev)) {
1813                 smu_get_power_limit(&adev->smu, &limit, true);
1814                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1815         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1816                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1817                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1818         } else {
1819                 return snprintf(buf, PAGE_SIZE, "\n");
1820         }
1821 }
1822
1823 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1824                                          struct device_attribute *attr,
1825                                          char *buf)
1826 {
1827         struct amdgpu_device *adev = dev_get_drvdata(dev);
1828         uint32_t limit = 0;
1829
1830         if (is_support_sw_smu(adev)) {
1831                 smu_get_power_limit(&adev->smu, &limit, false);
1832                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1833         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1834                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1835                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1836         } else {
1837                 return snprintf(buf, PAGE_SIZE, "\n");
1838         }
1839 }
1840
1841
1842 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1843                 struct device_attribute *attr,
1844                 const char *buf,
1845                 size_t count)
1846 {
1847         struct amdgpu_device *adev = dev_get_drvdata(dev);
1848         int err;
1849         u32 value;
1850
1851         err = kstrtou32(buf, 10, &value);
1852         if (err)
1853                 return err;
1854
1855         value = value / 1000000; /* convert to Watt */
1856         if (is_support_sw_smu(adev)) {
1857                 adev->smu.funcs->set_power_limit(&adev->smu, value);
1858         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1859                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1860                 if (err)
1861                         return err;
1862         } else {
1863                 return -EINVAL;
1864         }
1865
1866         return count;
1867 }
1868
1869 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
1870                                       struct device_attribute *attr,
1871                                       char *buf)
1872 {
1873         struct amdgpu_device *adev = dev_get_drvdata(dev);
1874         struct drm_device *ddev = adev->ddev;
1875         uint32_t sclk;
1876         int r, size = sizeof(sclk);
1877
1878         /* Can't get voltage when the card is off */
1879         if  ((adev->flags & AMD_IS_PX) &&
1880              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1881                 return -EINVAL;
1882
1883         /* sanity check PP is enabled */
1884         if (!(adev->powerplay.pp_funcs &&
1885               adev->powerplay.pp_funcs->read_sensor))
1886               return -EINVAL;
1887
1888         /* get the sclk */
1889         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
1890                                    (void *)&sclk, &size);
1891         if (r)
1892                 return r;
1893
1894         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
1895 }
1896
1897 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
1898                                             struct device_attribute *attr,
1899                                             char *buf)
1900 {
1901         return snprintf(buf, PAGE_SIZE, "sclk\n");
1902 }
1903
1904 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
1905                                       struct device_attribute *attr,
1906                                       char *buf)
1907 {
1908         struct amdgpu_device *adev = dev_get_drvdata(dev);
1909         struct drm_device *ddev = adev->ddev;
1910         uint32_t mclk;
1911         int r, size = sizeof(mclk);
1912
1913         /* Can't get voltage when the card is off */
1914         if  ((adev->flags & AMD_IS_PX) &&
1915              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1916                 return -EINVAL;
1917
1918         /* sanity check PP is enabled */
1919         if (!(adev->powerplay.pp_funcs &&
1920               adev->powerplay.pp_funcs->read_sensor))
1921               return -EINVAL;
1922
1923         /* get the sclk */
1924         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
1925                                    (void *)&mclk, &size);
1926         if (r)
1927                 return r;
1928
1929         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
1930 }
1931
1932 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
1933                                             struct device_attribute *attr,
1934                                             char *buf)
1935 {
1936         return snprintf(buf, PAGE_SIZE, "mclk\n");
1937 }
1938
1939 /**
1940  * DOC: hwmon
1941  *
1942  * The amdgpu driver exposes the following sensor interfaces:
1943  *
1944  * - GPU temperature (via the on-die sensor)
1945  *
1946  * - GPU voltage
1947  *
1948  * - Northbridge voltage (APUs only)
1949  *
1950  * - GPU power
1951  *
1952  * - GPU fan
1953  *
1954  * - GPU gfx/compute engine clock
1955  *
1956  * - GPU memory clock (dGPU only)
1957  *
1958  * hwmon interfaces for GPU temperature:
1959  *
1960  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1961  *
1962  * - temp1_crit: temperature critical max value in millidegrees Celsius
1963  *
1964  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1965  *
1966  * hwmon interfaces for GPU voltage:
1967  *
1968  * - in0_input: the voltage on the GPU in millivolts
1969  *
1970  * - in1_input: the voltage on the Northbridge in millivolts
1971  *
1972  * hwmon interfaces for GPU power:
1973  *
1974  * - power1_average: average power used by the GPU in microWatts
1975  *
1976  * - power1_cap_min: minimum cap supported in microWatts
1977  *
1978  * - power1_cap_max: maximum cap supported in microWatts
1979  *
1980  * - power1_cap: selected power cap in microWatts
1981  *
1982  * hwmon interfaces for GPU fan:
1983  *
1984  * - pwm1: pulse width modulation fan level (0-255)
1985  *
1986  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1987  *
1988  * - pwm1_min: pulse width modulation fan control minimum level (0)
1989  *
1990  * - pwm1_max: pulse width modulation fan control maximum level (255)
1991  *
1992  * - fan1_min: an minimum value Unit: revolution/min (RPM)
1993  *
1994  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1995  *
1996  * - fan1_input: fan speed in RPM
1997  *
1998  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1999  *
2000  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2001  *
2002  * hwmon interfaces for GPU clocks:
2003  *
2004  * - freq1_input: the gfx/compute clock in hertz
2005  *
2006  * - freq2_input: the memory clock in hertz
2007  *
2008  * You can use hwmon tools like sensors to view this information on your system.
2009  *
2010  */
2011
2012 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
2013 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2014 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2015 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2016 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2017 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2018 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2019 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2020 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2021 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2022 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2023 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2024 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2025 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2026 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2027 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2028 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2029 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2030 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2031 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2032 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2033 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2034 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2035 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2036
2037 static struct attribute *hwmon_attributes[] = {
2038         &sensor_dev_attr_temp1_input.dev_attr.attr,
2039         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2040         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2041         &sensor_dev_attr_pwm1.dev_attr.attr,
2042         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2043         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2044         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2045         &sensor_dev_attr_fan1_input.dev_attr.attr,
2046         &sensor_dev_attr_fan1_min.dev_attr.attr,
2047         &sensor_dev_attr_fan1_max.dev_attr.attr,
2048         &sensor_dev_attr_fan1_target.dev_attr.attr,
2049         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2050         &sensor_dev_attr_in0_input.dev_attr.attr,
2051         &sensor_dev_attr_in0_label.dev_attr.attr,
2052         &sensor_dev_attr_in1_input.dev_attr.attr,
2053         &sensor_dev_attr_in1_label.dev_attr.attr,
2054         &sensor_dev_attr_power1_average.dev_attr.attr,
2055         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2056         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2057         &sensor_dev_attr_power1_cap.dev_attr.attr,
2058         &sensor_dev_attr_freq1_input.dev_attr.attr,
2059         &sensor_dev_attr_freq1_label.dev_attr.attr,
2060         &sensor_dev_attr_freq2_input.dev_attr.attr,
2061         &sensor_dev_attr_freq2_label.dev_attr.attr,
2062         NULL
2063 };
2064
2065 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2066                                         struct attribute *attr, int index)
2067 {
2068         struct device *dev = kobj_to_dev(kobj);
2069         struct amdgpu_device *adev = dev_get_drvdata(dev);
2070         umode_t effective_mode = attr->mode;
2071
2072         /* Skip fan attributes if fan is not present */
2073         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2074             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2075             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2076             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2077             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2078             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2079             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2080             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2081             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2082                 return 0;
2083
2084         /* Skip fan attributes on APU */
2085         if ((adev->flags & AMD_IS_APU) &&
2086             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2087              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2088              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2089              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2090              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2091              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2092              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2093              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2094              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2095                 return 0;
2096
2097         /* Skip limit attributes if DPM is not enabled */
2098         if (!adev->pm.dpm_enabled &&
2099             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2100              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2101              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2102              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2103              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2104              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2105              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2106              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2107              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2108              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2109              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2110                 return 0;
2111
2112         if (!is_support_sw_smu(adev)) {
2113                 /* mask fan attributes if we have no bindings for this asic to expose */
2114                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2115                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2116                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2117                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2118                         effective_mode &= ~S_IRUGO;
2119
2120                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2121                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2122                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2123                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2124                         effective_mode &= ~S_IWUSR;
2125         }
2126
2127         if ((adev->flags & AMD_IS_APU) &&
2128             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2129              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2130              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2131              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2132                 return 0;
2133
2134         if (!is_support_sw_smu(adev)) {
2135                 /* hide max/min values if we can't both query and manage the fan */
2136                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2137                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2138                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2139                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2140                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2141                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2142                         return 0;
2143
2144                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2145                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2146                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2147                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2148                         return 0;
2149         }
2150
2151         /* only APUs have vddnb */
2152         if (!(adev->flags & AMD_IS_APU) &&
2153             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2154              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2155                 return 0;
2156
2157         /* no mclk on APUs */
2158         if ((adev->flags & AMD_IS_APU) &&
2159             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2160              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2161                 return 0;
2162
2163         return effective_mode;
2164 }
2165
2166 static const struct attribute_group hwmon_attrgroup = {
2167         .attrs = hwmon_attributes,
2168         .is_visible = hwmon_attributes_visible,
2169 };
2170
2171 static const struct attribute_group *hwmon_groups[] = {
2172         &hwmon_attrgroup,
2173         NULL
2174 };
2175
2176 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2177 {
2178         struct amdgpu_device *adev =
2179                 container_of(work, struct amdgpu_device,
2180                              pm.dpm.thermal.work);
2181         /* switch to the thermal state */
2182         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2183         int temp, size = sizeof(temp);
2184
2185         if (!adev->pm.dpm_enabled)
2186                 return;
2187
2188         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2189                                     (void *)&temp, &size)) {
2190                 if (temp < adev->pm.dpm.thermal.min_temp)
2191                         /* switch back the user state */
2192                         dpm_state = adev->pm.dpm.user_state;
2193         } else {
2194                 if (adev->pm.dpm.thermal.high_to_low)
2195                         /* switch back the user state */
2196                         dpm_state = adev->pm.dpm.user_state;
2197         }
2198         mutex_lock(&adev->pm.mutex);
2199         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2200                 adev->pm.dpm.thermal_active = true;
2201         else
2202                 adev->pm.dpm.thermal_active = false;
2203         adev->pm.dpm.state = dpm_state;
2204         mutex_unlock(&adev->pm.mutex);
2205
2206         amdgpu_pm_compute_clocks(adev);
2207 }
2208
2209 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2210                                                      enum amd_pm_state_type dpm_state)
2211 {
2212         int i;
2213         struct amdgpu_ps *ps;
2214         u32 ui_class;
2215         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2216                 true : false;
2217
2218         /* check if the vblank period is too short to adjust the mclk */
2219         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2220                 if (amdgpu_dpm_vblank_too_short(adev))
2221                         single_display = false;
2222         }
2223
2224         /* certain older asics have a separare 3D performance state,
2225          * so try that first if the user selected performance
2226          */
2227         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2228                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2229         /* balanced states don't exist at the moment */
2230         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2231                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2232
2233 restart_search:
2234         /* Pick the best power state based on current conditions */
2235         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2236                 ps = &adev->pm.dpm.ps[i];
2237                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2238                 switch (dpm_state) {
2239                 /* user states */
2240                 case POWER_STATE_TYPE_BATTERY:
2241                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2242                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2243                                         if (single_display)
2244                                                 return ps;
2245                                 } else
2246                                         return ps;
2247                         }
2248                         break;
2249                 case POWER_STATE_TYPE_BALANCED:
2250                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2251                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2252                                         if (single_display)
2253                                                 return ps;
2254                                 } else
2255                                         return ps;
2256                         }
2257                         break;
2258                 case POWER_STATE_TYPE_PERFORMANCE:
2259                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2260                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2261                                         if (single_display)
2262                                                 return ps;
2263                                 } else
2264                                         return ps;
2265                         }
2266                         break;
2267                 /* internal states */
2268                 case POWER_STATE_TYPE_INTERNAL_UVD:
2269                         if (adev->pm.dpm.uvd_ps)
2270                                 return adev->pm.dpm.uvd_ps;
2271                         else
2272                                 break;
2273                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2274                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2275                                 return ps;
2276                         break;
2277                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2278                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2279                                 return ps;
2280                         break;
2281                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2282                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2283                                 return ps;
2284                         break;
2285                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2286                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2287                                 return ps;
2288                         break;
2289                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2290                         return adev->pm.dpm.boot_ps;
2291                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2292                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2293                                 return ps;
2294                         break;
2295                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2296                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2297                                 return ps;
2298                         break;
2299                 case POWER_STATE_TYPE_INTERNAL_ULV:
2300                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2301                                 return ps;
2302                         break;
2303                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2304                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2305                                 return ps;
2306                         break;
2307                 default:
2308                         break;
2309                 }
2310         }
2311         /* use a fallback state if we didn't match */
2312         switch (dpm_state) {
2313         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2314                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2315                 goto restart_search;
2316         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2317         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2318         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2319                 if (adev->pm.dpm.uvd_ps) {
2320                         return adev->pm.dpm.uvd_ps;
2321                 } else {
2322                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2323                         goto restart_search;
2324                 }
2325         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2326                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2327                 goto restart_search;
2328         case POWER_STATE_TYPE_INTERNAL_ACPI:
2329                 dpm_state = POWER_STATE_TYPE_BATTERY;
2330                 goto restart_search;
2331         case POWER_STATE_TYPE_BATTERY:
2332         case POWER_STATE_TYPE_BALANCED:
2333         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2334                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2335                 goto restart_search;
2336         default:
2337                 break;
2338         }
2339
2340         return NULL;
2341 }
2342
2343 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2344 {
2345         struct amdgpu_ps *ps;
2346         enum amd_pm_state_type dpm_state;
2347         int ret;
2348         bool equal = false;
2349
2350         /* if dpm init failed */
2351         if (!adev->pm.dpm_enabled)
2352                 return;
2353
2354         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2355                 /* add other state override checks here */
2356                 if ((!adev->pm.dpm.thermal_active) &&
2357                     (!adev->pm.dpm.uvd_active))
2358                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2359         }
2360         dpm_state = adev->pm.dpm.state;
2361
2362         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2363         if (ps)
2364                 adev->pm.dpm.requested_ps = ps;
2365         else
2366                 return;
2367
2368         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2369                 printk("switching from power state:\n");
2370                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2371                 printk("switching to power state:\n");
2372                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2373         }
2374
2375         /* update whether vce is active */
2376         ps->vce_active = adev->pm.dpm.vce_active;
2377         if (adev->powerplay.pp_funcs->display_configuration_changed)
2378                 amdgpu_dpm_display_configuration_changed(adev);
2379
2380         ret = amdgpu_dpm_pre_set_power_state(adev);
2381         if (ret)
2382                 return;
2383
2384         if (adev->powerplay.pp_funcs->check_state_equal) {
2385                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2386                         equal = false;
2387         }
2388
2389         if (equal)
2390                 return;
2391
2392         amdgpu_dpm_set_power_state(adev);
2393         amdgpu_dpm_post_set_power_state(adev);
2394
2395         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2396         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2397
2398         if (adev->powerplay.pp_funcs->force_performance_level) {
2399                 if (adev->pm.dpm.thermal_active) {
2400                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2401                         /* force low perf level for thermal */
2402                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2403                         /* save the user's level */
2404                         adev->pm.dpm.forced_level = level;
2405                 } else {
2406                         /* otherwise, user selected level */
2407                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2408                 }
2409         }
2410 }
2411
2412 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2413 {
2414         int ret = 0;
2415         if (is_support_sw_smu(adev)) {
2416             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2417             if (ret)
2418                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2419                           enable ? "true" : "false", ret);
2420         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2421                 /* enable/disable UVD */
2422                 mutex_lock(&adev->pm.mutex);
2423                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2424                 mutex_unlock(&adev->pm.mutex);
2425         }
2426         /* enable/disable Low Memory PState for UVD (4k videos) */
2427         if (adev->asic_type == CHIP_STONEY &&
2428                 adev->uvd.decode_image_width >= WIDTH_4K) {
2429                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2430
2431                 if (hwmgr && hwmgr->hwmgr_func &&
2432                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2433                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2434                                                                !enable,
2435                                                                true);
2436         }
2437 }
2438
2439 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2440 {
2441         int ret = 0;
2442         if (is_support_sw_smu(adev)) {
2443             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2444             if (ret)
2445                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2446                           enable ? "true" : "false", ret);
2447         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2448                 /* enable/disable VCE */
2449                 mutex_lock(&adev->pm.mutex);
2450                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2451                 mutex_unlock(&adev->pm.mutex);
2452         }
2453 }
2454
2455 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2456 {
2457         int i;
2458
2459         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2460                 return;
2461
2462         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2463                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2464
2465 }
2466
2467 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2468 {
2469         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2470         int ret;
2471
2472         if (adev->pm.sysfs_initialized)
2473                 return 0;
2474
2475         if (adev->pm.dpm_enabled == 0)
2476                 return 0;
2477
2478         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2479                                                                    DRIVER_NAME, adev,
2480                                                                    hwmon_groups);
2481         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2482                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2483                 dev_err(adev->dev,
2484                         "Unable to register hwmon device: %d\n", ret);
2485                 return ret;
2486         }
2487
2488         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2489         if (ret) {
2490                 DRM_ERROR("failed to create device file for dpm state\n");
2491                 return ret;
2492         }
2493         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2494         if (ret) {
2495                 DRM_ERROR("failed to create device file for dpm state\n");
2496                 return ret;
2497         }
2498
2499
2500         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2501         if (ret) {
2502                 DRM_ERROR("failed to create device file pp_num_states\n");
2503                 return ret;
2504         }
2505         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2506         if (ret) {
2507                 DRM_ERROR("failed to create device file pp_cur_state\n");
2508                 return ret;
2509         }
2510         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2511         if (ret) {
2512                 DRM_ERROR("failed to create device file pp_force_state\n");
2513                 return ret;
2514         }
2515         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2516         if (ret) {
2517                 DRM_ERROR("failed to create device file pp_table\n");
2518                 return ret;
2519         }
2520
2521         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2522         if (ret) {
2523                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2524                 return ret;
2525         }
2526         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2527         if (ret) {
2528                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2529                 return ret;
2530         }
2531         if (adev->asic_type >= CHIP_VEGA10) {
2532                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2533                 if (ret) {
2534                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2535                         return ret;
2536                 }
2537                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2538                 if (ret) {
2539                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2540                         return ret;
2541                 }
2542         }
2543         if (adev->asic_type >= CHIP_VEGA20) {
2544                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2545                 if (ret) {
2546                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2547                         return ret;
2548                 }
2549         }
2550         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2551         if (ret) {
2552                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2553                 return ret;
2554         }
2555         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2556         if (ret) {
2557                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2558                 return ret;
2559         }
2560         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2561         if (ret) {
2562                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2563                 return ret;
2564         }
2565         ret = device_create_file(adev->dev,
2566                         &dev_attr_pp_power_profile_mode);
2567         if (ret) {
2568                 DRM_ERROR("failed to create device file "
2569                                 "pp_power_profile_mode\n");
2570                 return ret;
2571         }
2572         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2573             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2574                 ret = device_create_file(adev->dev,
2575                                 &dev_attr_pp_od_clk_voltage);
2576                 if (ret) {
2577                         DRM_ERROR("failed to create device file "
2578                                         "pp_od_clk_voltage\n");
2579                         return ret;
2580                 }
2581         }
2582         ret = device_create_file(adev->dev,
2583                         &dev_attr_gpu_busy_percent);
2584         if (ret) {
2585                 DRM_ERROR("failed to create device file "
2586                                 "gpu_busy_level\n");
2587                 return ret;
2588         }
2589         /* PCIe Perf counters won't work on APU nodes */
2590         if (!(adev->flags & AMD_IS_APU)) {
2591                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2592                 if (ret) {
2593                         DRM_ERROR("failed to create device file pcie_bw\n");
2594                         return ret;
2595                 }
2596         }
2597         ret = amdgpu_debugfs_pm_init(adev);
2598         if (ret) {
2599                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2600                 return ret;
2601         }
2602
2603         if ((adev->asic_type >= CHIP_VEGA10) &&
2604             !(adev->flags & AMD_IS_APU)) {
2605                 ret = device_create_file(adev->dev,
2606                                 &dev_attr_ppfeatures);
2607                 if (ret) {
2608                         DRM_ERROR("failed to create device file "
2609                                         "ppfeatures\n");
2610                         return ret;
2611                 }
2612         }
2613
2614         adev->pm.sysfs_initialized = true;
2615
2616         return 0;
2617 }
2618
2619 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2620 {
2621         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2622
2623         if (adev->pm.dpm_enabled == 0)
2624                 return;
2625
2626         if (adev->pm.int_hwmon_dev)
2627                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2628         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2629         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2630
2631         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2632         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2633         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2634         device_remove_file(adev->dev, &dev_attr_pp_table);
2635
2636         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2637         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2638         if (adev->asic_type >= CHIP_VEGA10) {
2639                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2640                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2641         }
2642         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2643         if (adev->asic_type >= CHIP_VEGA20)
2644                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2645         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2646         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2647         device_remove_file(adev->dev,
2648                         &dev_attr_pp_power_profile_mode);
2649         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2650             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2651                 device_remove_file(adev->dev,
2652                                 &dev_attr_pp_od_clk_voltage);
2653         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2654         if (!(adev->flags & AMD_IS_APU))
2655                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2656         if ((adev->asic_type >= CHIP_VEGA10) &&
2657             !(adev->flags & AMD_IS_APU))
2658                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2659 }
2660
2661 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2662 {
2663         int i = 0;
2664
2665         if (!adev->pm.dpm_enabled)
2666                 return;
2667
2668         if (adev->mode_info.num_crtc)
2669                 amdgpu_display_bandwidth_update(adev);
2670
2671         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2672                 struct amdgpu_ring *ring = adev->rings[i];
2673                 if (ring && ring->sched.ready)
2674                         amdgpu_fence_wait_empty(ring);
2675         }
2676
2677         if (is_support_sw_smu(adev)) {
2678                 struct smu_context *smu = &adev->smu;
2679                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2680                 mutex_lock(&(smu->mutex));
2681                 smu_handle_task(&adev->smu,
2682                                 smu_dpm->dpm_level,
2683                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2684                 mutex_unlock(&(smu->mutex));
2685         } else {
2686                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2687                         if (!amdgpu_device_has_dc_support(adev)) {
2688                                 mutex_lock(&adev->pm.mutex);
2689                                 amdgpu_dpm_get_active_displays(adev);
2690                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2691                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2692                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2693                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2694                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2695                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2696                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2697                                         adev->powerplay.pp_funcs->display_configuration_change(
2698                                                                         adev->powerplay.pp_handle,
2699                                                                         &adev->pm.pm_display_cfg);
2700                                 mutex_unlock(&adev->pm.mutex);
2701                         }
2702                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2703                 } else {
2704                         mutex_lock(&adev->pm.mutex);
2705                         amdgpu_dpm_get_active_displays(adev);
2706                         amdgpu_dpm_change_power_state_locked(adev);
2707                         mutex_unlock(&adev->pm.mutex);
2708                 }
2709         }
2710 }
2711
2712 /*
2713  * Debugfs info
2714  */
2715 #if defined(CONFIG_DEBUG_FS)
2716
2717 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2718 {
2719         uint32_t value;
2720         uint64_t value64;
2721         uint32_t query = 0;
2722         int size;
2723
2724         /* GPU Clocks */
2725         size = sizeof(value);
2726         seq_printf(m, "GFX Clocks and Power:\n");
2727         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2728                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2729         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2730                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2731         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2732                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2733         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2734                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2735         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2736                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2737         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2738                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2739         size = sizeof(uint32_t);
2740         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2741                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2742         size = sizeof(value);
2743         seq_printf(m, "\n");
2744
2745         /* GPU Temp */
2746         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2747                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2748
2749         /* GPU Load */
2750         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2751                 seq_printf(m, "GPU Load: %u %%\n", value);
2752         seq_printf(m, "\n");
2753
2754         /* SMC feature mask */
2755         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2756                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2757
2758         /* UVD clocks */
2759         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2760                 if (!value) {
2761                         seq_printf(m, "UVD: Disabled\n");
2762                 } else {
2763                         seq_printf(m, "UVD: Enabled\n");
2764                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2765                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2766                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2767                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2768                 }
2769         }
2770         seq_printf(m, "\n");
2771
2772         /* VCE clocks */
2773         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2774                 if (!value) {
2775                         seq_printf(m, "VCE: Disabled\n");
2776                 } else {
2777                         seq_printf(m, "VCE: Enabled\n");
2778                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2779                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2780                 }
2781         }
2782
2783         return 0;
2784 }
2785
2786 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2787 {
2788         int i;
2789
2790         for (i = 0; clocks[i].flag; i++)
2791                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2792                            (flags & clocks[i].flag) ? "On" : "Off");
2793 }
2794
2795 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2796 {
2797         struct drm_info_node *node = (struct drm_info_node *) m->private;
2798         struct drm_device *dev = node->minor->dev;
2799         struct amdgpu_device *adev = dev->dev_private;
2800         struct drm_device *ddev = adev->ddev;
2801         u32 flags = 0;
2802
2803         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2804         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2805         amdgpu_parse_cg_state(m, flags);
2806         seq_printf(m, "\n");
2807
2808         if (!adev->pm.dpm_enabled) {
2809                 seq_printf(m, "dpm not enabled\n");
2810                 return 0;
2811         }
2812         if  ((adev->flags & AMD_IS_PX) &&
2813              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2814                 seq_printf(m, "PX asic powered off\n");
2815         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2816                 mutex_lock(&adev->pm.mutex);
2817                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2818                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2819                 else
2820                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2821                 mutex_unlock(&adev->pm.mutex);
2822         } else {
2823                 return amdgpu_debugfs_pm_info_pp(m, adev);
2824         }
2825
2826         return 0;
2827 }
2828
2829 static const struct drm_info_list amdgpu_pm_info_list[] = {
2830         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2831 };
2832 #endif
2833
2834 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2835 {
2836 #if defined(CONFIG_DEBUG_FS)
2837         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2838 #else
2839         return 0;
2840 #endif
2841 }