drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "dce_virtual.h"
  60 #include "mes_v10_1.h"
  61 #include "mxgpu_nv.h"
  62
  63 static const struct amd_ip_funcs nv_common_ip_funcs;
  64
  65 /*
  66  * Indirect registers accessor
  67  */
  68 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  69 {
  70         unsigned long flags, address, data;
  71         u32 r;
  72         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  73         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  74
  75         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  76         WREG32(address, reg);
  77         (void)RREG32(address);
  78         r = RREG32(data);
  79         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  80         return r;
  81 }
  82
  83 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  84 {
  85         unsigned long flags, address, data;
  86
  87         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  88         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  89
  90         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  91         WREG32(address, reg);
  92         (void)RREG32(address);
  93         WREG32(data, v);
  94         (void)RREG32(data);
  95         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  96 }
  97
  98 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
  99 {
 100         unsigned long flags, address, data;
 101         u32 r;
 102
 103         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 104         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 105
 106         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 107         WREG32(address, (reg));
 108         r = RREG32(data);
 109         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 110         return r;
 111 }
 112
 113 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 114 {
 115         unsigned long flags, address, data;
 116
 117         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 118         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 119
 120         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 121         WREG32(address, (reg));
 122         WREG32(data, (v));
 123         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 124 }
 125
 126 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 127 {
 128         return adev->nbio.funcs->get_memsize(adev);
 129 }
 130
 131 static u32 nv_get_xclk(struct amdgpu_device *adev)
 132 {
 133         return adev->clock.spll.reference_freq;
 134 }
 135
 136
 137 void nv_grbm_select(struct amdgpu_device *adev,
 138                      u32 me, u32 pipe, u32 queue, u32 vmid)
 139 {
 140         u32 grbm_gfx_cntl = 0;
 141         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 142         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 143         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 144         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 145
 146         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 147 }
 148
 149 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 150 {
 151         /* todo */
 152 }
 153
 154 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 155 {
 156         /* todo */
 157         return false;
 158 }
 159
 160 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 161                                   u8 *bios, u32 length_bytes)
 162 {
 163         u32 *dw_ptr;
 164         u32 i, length_dw;
 165
 166         if (bios == NULL)
 167                 return false;
 168         if (length_bytes == 0)
 169                 return false;
 170         /* APU vbios image is part of sbios image */
 171         if (adev->flags & AMD_IS_APU)
 172                 return false;
 173
 174         dw_ptr = (u32 *)bios;
 175         length_dw = ALIGN(length_bytes, 4) / 4;
 176
 177         /* set rom index to 0 */
 178         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 179         /* read out the rom data */
 180         for (i = 0; i < length_dw; i++)
 181                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 182
 183         return true;
 184 }
 185
 186 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 187         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 188         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 189         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 190         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 191         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 192         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 193         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 194         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 195         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 196         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 197         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 198         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 199         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 200         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 201         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 202         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 203         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 204         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 205         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 206 };
 207
 208 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 209                                          u32 sh_num, u32 reg_offset)
 210 {
 211         uint32_t val;
 212
 213         mutex_lock(&adev->grbm_idx_mutex);
 214         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 215                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 216
 217         val = RREG32(reg_offset);
 218
 219         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 220                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 221         mutex_unlock(&adev->grbm_idx_mutex);
 222         return val;
 223 }
 224
 225 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 226                                       bool indexed, u32 se_num,
 227                                       u32 sh_num, u32 reg_offset)
 228 {
 229         if (indexed) {
 230                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 231         } else {
 232                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 233                         return adev->gfx.config.gb_addr_config;
 234                 return RREG32(reg_offset);
 235         }
 236 }
 237
 238 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 239                             u32 sh_num, u32 reg_offset, u32 *value)
 240 {
 241         uint32_t i;
 242         struct soc15_allowed_register_entry  *en;
 243
 244         *value = 0;
 245         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 246                 en = &nv_allowed_read_registers[i];
 247                 if (reg_offset !=
 248                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 249                         continue;
 250
 251                 *value = nv_get_register_value(adev,
 252                                                nv_allowed_read_registers[i].grbm_indexed,
 253                                                se_num, sh_num, reg_offset);
 254                 return 0;
 255         }
 256         return -EINVAL;
 257 }
 258
 259 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 260 {
 261         u32 i;
 262         int ret = 0;
 263
 264         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 265
 266         dev_info(adev->dev, "GPU mode1 reset\n");
 267
 268         /* disable BM */
 269         pci_clear_master(adev->pdev);
 270
 271         pci_save_state(adev->pdev);
 272
 273         ret = psp_gpu_reset(adev);
 274         if (ret)
 275                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 276
 277         pci_restore_state(adev->pdev);
 278
 279         /* wait for asic to come out of reset */
 280         for (i = 0; i < adev->usec_timeout; i++) {
 281                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 282
 283                 if (memsize != 0xffffffff)
 284                         break;
 285                 udelay(1);
 286         }
 287
 288         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 289
 290         return ret;
 291 }
 292
 293 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 294 {
 295         struct smu_context *smu = &adev->smu;
 296
 297         if (smu_baco_is_support(smu))
 298                 return true;
 299         else
 300                 return false;
 301 }
 302
 303 static enum amd_reset_method
 304 nv_asic_reset_method(struct amdgpu_device *adev)
 305 {
 306         struct smu_context *smu = &adev->smu;
 307
 308         if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
 309                 return AMD_RESET_METHOD_BACO;
 310         else
 311                 return AMD_RESET_METHOD_MODE1;
 312 }
 313
 314 static int nv_asic_reset(struct amdgpu_device *adev)
 315 {
 316         int ret = 0;
 317         struct smu_context *smu = &adev->smu;
 318
 319         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 320                 ret = smu_baco_enter(smu);
 321                 if (ret)
 322                         return ret;
 323                 ret = smu_baco_exit(smu);
 324                 if (ret)
 325                         return ret;
 326         } else {
 327                 ret = nv_asic_mode1_reset(adev);
 328         }
 329
 330         return ret;
 331 }
 332
 333 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 334 {
 335         /* todo */
 336         return 0;
 337 }
 338
 339 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 340 {
 341         /* todo */
 342         return 0;
 343 }
 344
 345 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 346 {
 347         if (pci_is_root_bus(adev->pdev->bus))
 348                 return;
 349
 350         if (amdgpu_pcie_gen2 == 0)
 351                 return;
 352
 353         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 354                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 355                 return;
 356
 357         /* todo */
 358 }
 359
 360 static void nv_program_aspm(struct amdgpu_device *adev)
 361 {
 362
 363         if (amdgpu_aspm == 0)
 364                 return;
 365
 366         /* todo */
 367 }
 368
 369 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 370                                         bool enable)
 371 {
 372         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 373         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 374 }
 375
 376 static const struct amdgpu_ip_block_version nv_common_ip_block =
 377 {
 378         .type = AMD_IP_BLOCK_TYPE_COMMON,
 379         .major = 1,
 380         .minor = 0,
 381         .rev = 0,
 382         .funcs = &nv_common_ip_funcs,
 383 };
 384
 385 static int nv_reg_base_init(struct amdgpu_device *adev)
 386 {
 387         int r;
 388
 389         if (amdgpu_discovery) {
 390                 r = amdgpu_discovery_reg_base_init(adev);
 391                 if (r) {
 392                         DRM_WARN("failed to init reg base from ip discovery table, "
 393                                         "fallback to legacy init method\n");
 394                         goto legacy_init;
 395                 }
 396
 397                 return 0;
 398         }
 399
 400 legacy_init:
 401         switch (adev->asic_type) {
 402         case CHIP_NAVI10:
 403                 navi10_reg_base_init(adev);
 404                 break;
 405         case CHIP_NAVI14:
 406                 navi14_reg_base_init(adev);
 407                 break;
 408         case CHIP_NAVI12:
 409                 navi12_reg_base_init(adev);
 410                 break;
 411         case CHIP_SIENNA_CICHLID:
 412                 sienna_cichlid_reg_base_init(adev);
 413                 break;
 414         default:
 415                 return -EINVAL;
 416         }
 417
 418         return 0;
 419 }
 420
 421 int nv_set_ip_blocks(struct amdgpu_device *adev)
 422 {
 423         int r;
 424
 425         adev->nbio.funcs = &nbio_v2_3_funcs;
 426         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 427
 428         if (amdgpu_sriov_vf(adev)) {
 429                 adev->virt.ops = &xgpu_nv_virt_ops;
 430                 /* try send GPU_INIT_DATA request to host */
 431                 amdgpu_virt_request_init_data(adev);
 432         }
 433
 434         /* Set IP register base before any HW register access */
 435         r = nv_reg_base_init(adev);
 436         if (r)
 437                 return r;
 438
 439         switch (adev->asic_type) {
 440         case CHIP_NAVI10:
 441         case CHIP_NAVI14:
 442                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 443                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 444                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 445                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 446                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 447                     !amdgpu_sriov_vf(adev))
 448                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 449                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 450                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 451 #if defined(CONFIG_DRM_AMD_DC)
 452                 else if (amdgpu_device_has_dc_support(adev))
 453                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 454 #endif
 455                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 456                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 457                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 458                     !amdgpu_sriov_vf(adev))
 459                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 460                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 461                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 462                 if (adev->enable_mes)
 463                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 464                 break;
 465         case CHIP_NAVI12:
 466                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 467                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 468                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 469                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 470                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 471                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 472                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 473                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 474 #if defined(CONFIG_DRM_AMD_DC)
 475                 else if (amdgpu_device_has_dc_support(adev))
 476                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 477 #endif
 478                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 479                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 480                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 481                     !amdgpu_sriov_vf(adev))
 482                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 483                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 484                 if (!amdgpu_sriov_vf(adev))
 485                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 486                 break;
 487         case CHIP_SIENNA_CICHLID:
 488                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 489                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 490                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 491                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 492                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 493                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 494                     is_support_sw_smu(adev))
 495                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 496                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 497                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 498                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 499                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 500                 break;
 501         default:
 502                 return -EINVAL;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 509 {
 510         return adev->nbio.funcs->get_rev_id(adev);
 511 }
 512
 513 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 514 {
 515         adev->nbio.funcs->hdp_flush(adev, ring);
 516 }
 517
 518 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 519                                 struct amdgpu_ring *ring)
 520 {
 521         if (!ring || !ring->funcs->emit_wreg) {
 522                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 523         } else {
 524                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 525                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 526         }
 527 }
 528
 529 static bool nv_need_full_reset(struct amdgpu_device *adev)
 530 {
 531         return true;
 532 }
 533
 534 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 535 {
 536         u32 sol_reg;
 537
 538         if (adev->flags & AMD_IS_APU)
 539                 return false;
 540
 541         /* Check sOS sign of life register to confirm sys driver and sOS
 542          * are already been loaded.
 543          */
 544         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 545         if (sol_reg)
 546                 return true;
 547
 548         return false;
 549 }
 550
 551 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 552 {
 553
 554         /* TODO
 555          * dummy implement for pcie_replay_count sysfs interface
 556          * */
 557
 558         return 0;
 559 }
 560
 561 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 562 {
 563         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 564         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 565         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 566         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 567         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 568         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 569         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 570         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 571         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 572         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 573         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 574         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 575         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 576         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 577         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 578         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 579         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 580         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 581         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 582         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 583         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 584         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 585         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 586         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 587         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 588
 589         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 590         adev->doorbell_index.sdma_doorbell_range = 20;
 591 }
 592
 593 static const struct amdgpu_asic_funcs nv_asic_funcs =
 594 {
 595         .read_disabled_bios = &nv_read_disabled_bios,
 596         .read_bios_from_rom = &nv_read_bios_from_rom,
 597         .read_register = &nv_read_register,
 598         .reset = &nv_asic_reset,
 599         .reset_method = &nv_asic_reset_method,
 600         .set_vga_state = &nv_vga_set_state,
 601         .get_xclk = &nv_get_xclk,
 602         .set_uvd_clocks = &nv_set_uvd_clocks,
 603         .set_vce_clocks = &nv_set_vce_clocks,
 604         .get_config_memsize = &nv_get_config_memsize,
 605         .flush_hdp = &nv_flush_hdp,
 606         .invalidate_hdp = &nv_invalidate_hdp,
 607         .init_doorbell_index = &nv_init_doorbell_index,
 608         .need_full_reset = &nv_need_full_reset,
 609         .need_reset_on_init = &nv_need_reset_on_init,
 610         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 611         .supports_baco = &nv_asic_supports_baco,
 612 };
 613
 614 static int nv_common_early_init(void *handle)
 615 {
 616 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 617         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 618
 619         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 620         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 621         adev->smc_rreg = NULL;
 622         adev->smc_wreg = NULL;
 623         adev->pcie_rreg = &nv_pcie_rreg;
 624         adev->pcie_wreg = &nv_pcie_wreg;
 625
 626         /* TODO: will add them during VCN v2 implementation */
 627         adev->uvd_ctx_rreg = NULL;
 628         adev->uvd_ctx_wreg = NULL;
 629
 630         adev->didt_rreg = &nv_didt_rreg;
 631         adev->didt_wreg = &nv_didt_wreg;
 632
 633         adev->asic_funcs = &nv_asic_funcs;
 634
 635         adev->rev_id = nv_get_rev_id(adev);
 636         adev->external_rev_id = 0xff;
 637         switch (adev->asic_type) {
 638         case CHIP_NAVI10:
 639                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 640                         AMD_CG_SUPPORT_GFX_CGCG |
 641                         AMD_CG_SUPPORT_IH_CG |
 642                         AMD_CG_SUPPORT_HDP_MGCG |
 643                         AMD_CG_SUPPORT_HDP_LS |
 644                         AMD_CG_SUPPORT_SDMA_MGCG |
 645                         AMD_CG_SUPPORT_SDMA_LS |
 646                         AMD_CG_SUPPORT_MC_MGCG |
 647                         AMD_CG_SUPPORT_MC_LS |
 648                         AMD_CG_SUPPORT_ATHUB_MGCG |
 649                         AMD_CG_SUPPORT_ATHUB_LS |
 650                         AMD_CG_SUPPORT_VCN_MGCG |
 651                         AMD_CG_SUPPORT_JPEG_MGCG |
 652                         AMD_CG_SUPPORT_BIF_MGCG |
 653                         AMD_CG_SUPPORT_BIF_LS;
 654                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 655                         AMD_PG_SUPPORT_VCN_DPG |
 656                         AMD_PG_SUPPORT_JPEG |
 657                         AMD_PG_SUPPORT_ATHUB;
 658                 adev->external_rev_id = adev->rev_id + 0x1;
 659                 break;
 660         case CHIP_NAVI14:
 661                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 662                         AMD_CG_SUPPORT_GFX_CGCG |
 663                         AMD_CG_SUPPORT_IH_CG |
 664                         AMD_CG_SUPPORT_HDP_MGCG |
 665                         AMD_CG_SUPPORT_HDP_LS |
 666                         AMD_CG_SUPPORT_SDMA_MGCG |
 667                         AMD_CG_SUPPORT_SDMA_LS |
 668                         AMD_CG_SUPPORT_MC_MGCG |
 669                         AMD_CG_SUPPORT_MC_LS |
 670                         AMD_CG_SUPPORT_ATHUB_MGCG |
 671                         AMD_CG_SUPPORT_ATHUB_LS |
 672                         AMD_CG_SUPPORT_VCN_MGCG |
 673                         AMD_CG_SUPPORT_JPEG_MGCG |
 674                         AMD_CG_SUPPORT_BIF_MGCG |
 675                         AMD_CG_SUPPORT_BIF_LS;
 676                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 677                         AMD_PG_SUPPORT_JPEG |
 678                         AMD_PG_SUPPORT_VCN_DPG;
 679                 adev->external_rev_id = adev->rev_id + 20;
 680                 break;
 681         case CHIP_NAVI12:
 682                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 683                         AMD_CG_SUPPORT_GFX_MGLS |
 684                         AMD_CG_SUPPORT_GFX_CGCG |
 685                         AMD_CG_SUPPORT_GFX_CP_LS |
 686                         AMD_CG_SUPPORT_GFX_RLC_LS |
 687                         AMD_CG_SUPPORT_IH_CG |
 688                         AMD_CG_SUPPORT_HDP_MGCG |
 689                         AMD_CG_SUPPORT_HDP_LS |
 690                         AMD_CG_SUPPORT_SDMA_MGCG |
 691                         AMD_CG_SUPPORT_SDMA_LS |
 692                         AMD_CG_SUPPORT_MC_MGCG |
 693                         AMD_CG_SUPPORT_MC_LS |
 694                         AMD_CG_SUPPORT_ATHUB_MGCG |
 695                         AMD_CG_SUPPORT_ATHUB_LS |
 696                         AMD_CG_SUPPORT_VCN_MGCG |
 697                         AMD_CG_SUPPORT_JPEG_MGCG;
 698                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 699                         AMD_PG_SUPPORT_VCN_DPG |
 700                         AMD_PG_SUPPORT_JPEG |
 701                         AMD_PG_SUPPORT_ATHUB;
 702                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 703                  * as a consequence, the rev_id and external_rev_id are wrong.
 704                  * workaround it by hardcoding rev_id to 0 (default value).
 705                  */
 706                 if (amdgpu_sriov_vf(adev))
 707                         adev->rev_id = 0;
 708                 adev->external_rev_id = adev->rev_id + 0xa;
 709                 break;
 710         case CHIP_SIENNA_CICHLID:
 711                 adev->cg_flags = 0;
 712                 adev->pg_flags = 0;
 713                 adev->external_rev_id = adev->rev_id + 0x28;
 714                 break;
 715         default:
 716                 /* FIXME: not supported yet */
 717                 return -EINVAL;
 718         }
 719
 720         if (amdgpu_sriov_vf(adev)) {
 721                 amdgpu_virt_init_setting(adev);
 722                 xgpu_nv_mailbox_set_irq_funcs(adev);
 723         }
 724
 725         return 0;
 726 }
 727
 728 static int nv_common_late_init(void *handle)
 729 {
 730         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 731
 732         if (amdgpu_sriov_vf(adev))
 733                 xgpu_nv_mailbox_get_irq(adev);
 734
 735         return 0;
 736 }
 737
 738 static int nv_common_sw_init(void *handle)
 739 {
 740         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 741
 742         if (amdgpu_sriov_vf(adev))
 743                 xgpu_nv_mailbox_add_irq_id(adev);
 744
 745         return 0;
 746 }
 747
 748 static int nv_common_sw_fini(void *handle)
 749 {
 750         return 0;
 751 }
 752
 753 static int nv_common_hw_init(void *handle)
 754 {
 755         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 756
 757         /* enable pcie gen2/3 link */
 758         nv_pcie_gen3_enable(adev);
 759         /* enable aspm */
 760         nv_program_aspm(adev);
 761         /* setup nbio registers */
 762         adev->nbio.funcs->init_registers(adev);
 763         /* remap HDP registers to a hole in mmio space,
 764          * for the purpose of expose those registers
 765          * to process space
 766          */
 767         if (adev->nbio.funcs->remap_hdp_registers)
 768                 adev->nbio.funcs->remap_hdp_registers(adev);
 769         /* enable the doorbell aperture */
 770         nv_enable_doorbell_aperture(adev, true);
 771
 772         return 0;
 773 }
 774
 775 static int nv_common_hw_fini(void *handle)
 776 {
 777         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 778
 779         /* disable the doorbell aperture */
 780         nv_enable_doorbell_aperture(adev, false);
 781
 782         return 0;
 783 }
 784
 785 static int nv_common_suspend(void *handle)
 786 {
 787         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 788
 789         return nv_common_hw_fini(adev);
 790 }
 791
 792 static int nv_common_resume(void *handle)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 795
 796         return nv_common_hw_init(adev);
 797 }
 798
 799 static bool nv_common_is_idle(void *handle)
 800 {
 801         return true;
 802 }
 803
 804 static int nv_common_wait_for_idle(void *handle)
 805 {
 806         return 0;
 807 }
 808
 809 static int nv_common_soft_reset(void *handle)
 810 {
 811         return 0;
 812 }
 813
 814 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 815                                            bool enable)
 816 {
 817         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 818         uint32_t hdp_mem_pwr_cntl;
 819
 820         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 821                                 AMD_CG_SUPPORT_HDP_DS |
 822                                 AMD_CG_SUPPORT_HDP_SD)))
 823                 return;
 824
 825         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 826         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 827
 828         /* Before doing clock/power mode switch,
 829          * forced on IPH & RC clock */
 830         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 831                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 832         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 833                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 834         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 835
 836         /* HDP 5.0 doesn't support dynamic power mode switch,
 837          * disable clock and power gating before any changing */
 838         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 839                                          IPH_MEM_POWER_CTRL_EN, 0);
 840         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 841                                          IPH_MEM_POWER_LS_EN, 0);
 842         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 843                                          IPH_MEM_POWER_DS_EN, 0);
 844         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 845                                          IPH_MEM_POWER_SD_EN, 0);
 846         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 847                                          RC_MEM_POWER_CTRL_EN, 0);
 848         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 849                                          RC_MEM_POWER_LS_EN, 0);
 850         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 851                                          RC_MEM_POWER_DS_EN, 0);
 852         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 853                                          RC_MEM_POWER_SD_EN, 0);
 854         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 855
 856         /* only one clock gating mode (LS/DS/SD) can be enabled */
 857         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 858                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 859                                                  HDP_MEM_POWER_CTRL,
 860                                                  IPH_MEM_POWER_LS_EN, enable);
 861                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 862                                                  HDP_MEM_POWER_CTRL,
 863                                                  RC_MEM_POWER_LS_EN, enable);
 864         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 865                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 866                                                  HDP_MEM_POWER_CTRL,
 867                                                  IPH_MEM_POWER_DS_EN, enable);
 868                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 869                                                  HDP_MEM_POWER_CTRL,
 870                                                  RC_MEM_POWER_DS_EN, enable);
 871         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 872                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 873                                                  HDP_MEM_POWER_CTRL,
 874                                                  IPH_MEM_POWER_SD_EN, enable);
 875                 /* RC should not use shut down mode, fallback to ds */
 876                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 877                                                  HDP_MEM_POWER_CTRL,
 878                                                  RC_MEM_POWER_DS_EN, enable);
 879         }
 880
 881         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 882
 883         /* restore IPH & RC clock override after clock/power mode changing */
 884         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
 885 }
 886
 887 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
 888                                        bool enable)
 889 {
 890         uint32_t hdp_clk_cntl;
 891
 892         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 893                 return;
 894
 895         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 896
 897         if (enable) {
 898                 hdp_clk_cntl &=
 899                         ~(uint32_t)
 900                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 901                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 902                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 903                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 904                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 905                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
 906         } else {
 907                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 908                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 909                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 910                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 911                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 912                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
 913         }
 914
 915         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 916 }
 917
 918 static int nv_common_set_clockgating_state(void *handle,
 919                                            enum amd_clockgating_state state)
 920 {
 921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 922
 923         if (amdgpu_sriov_vf(adev))
 924                 return 0;
 925
 926         switch (adev->asic_type) {
 927         case CHIP_NAVI10:
 928         case CHIP_NAVI14:
 929         case CHIP_NAVI12:
 930         case CHIP_SIENNA_CICHLID:
 931                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 932                                 state == AMD_CG_STATE_GATE);
 933                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
 934                                 state == AMD_CG_STATE_GATE);
 935                 nv_update_hdp_mem_power_gating(adev,
 936                                    state == AMD_CG_STATE_GATE);
 937                 nv_update_hdp_clock_gating(adev,
 938                                 state == AMD_CG_STATE_GATE);
 939                 break;
 940         default:
 941                 break;
 942         }
 943         return 0;
 944 }
 945
 946 static int nv_common_set_powergating_state(void *handle,
 947                                            enum amd_powergating_state state)
 948 {
 949         /* TODO */
 950         return 0;
 951 }
 952
 953 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
 954 {
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956         uint32_t tmp;
 957
 958         if (amdgpu_sriov_vf(adev))
 959                 *flags = 0;
 960
 961         adev->nbio.funcs->get_clockgating_state(adev, flags);
 962
 963         /* AMD_CG_SUPPORT_HDP_MGCG */
 964         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 965         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 966                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 967                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 968                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 969                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 970                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
 971                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
 972
 973         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
 974         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 975         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
 976                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 977         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
 978                 *flags |= AMD_CG_SUPPORT_HDP_DS;
 979         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
 980                 *flags |= AMD_CG_SUPPORT_HDP_SD;
 981
 982         return;
 983 }
 984
 985 static const struct amd_ip_funcs nv_common_ip_funcs = {
 986         .name = "nv_common",
 987         .early_init = nv_common_early_init,
 988         .late_init = nv_common_late_init,
 989         .sw_init = nv_common_sw_init,
 990         .sw_fini = nv_common_sw_fini,
 991         .hw_init = nv_common_hw_init,
 992         .hw_fini = nv_common_hw_fini,
 993         .suspend = nv_common_suspend,
 994         .resume = nv_common_resume,
 995         .is_idle = nv_common_is_idle,
 996         .wait_for_idle = nv_common_wait_for_idle,
 997         .soft_reset = nv_common_soft_reset,
 998         .set_clockgating_state = nv_common_set_clockgating_state,
 999         .set_powergating_state = nv_common_set_powergating_state,
1000         .get_clockgating_state = nv_common_get_clockgating_state,
1001 };