drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_MES_H__
  25 #define __AMDGPU_MES_H__
  26
  27 #define AMDGPU_MES_MAX_COMPUTE_PIPES        8
  28 #define AMDGPU_MES_MAX_GFX_PIPES            2
  29 #define AMDGPU_MES_MAX_SDMA_PIPES           2
  30
  31 enum amdgpu_mes_priority_level {
  32         AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
  33         AMDGPU_MES_PRIORITY_LEVEL_NORMAL    = 1,
  34         AMDGPU_MES_PRIORITY_LEVEL_MEDIUM    = 2,
  35         AMDGPU_MES_PRIORITY_LEVEL_HIGH      = 3,
  36         AMDGPU_MES_PRIORITY_LEVEL_REALTIME  = 4,
  37         AMDGPU_MES_PRIORITY_NUM_LEVELS
  38 };
  39
  40 struct amdgpu_mes_funcs;
  41
  42 struct amdgpu_mes {
  43         struct amdgpu_device            *adev;
  44
  45         uint32_t                        total_max_queue;
  46         uint32_t                        doorbell_id_offset;
  47         uint32_t                        max_doorbell_slices;
  48
  49         uint64_t                        default_process_quantum;
  50         uint64_t                        default_gang_quantum;
  51
  52         struct amdgpu_ring              ring;
  53
  54         const struct firmware           *fw;
  55
  56         /* mes ucode */
  57         struct amdgpu_bo                *ucode_fw_obj;
  58         uint64_t                        ucode_fw_gpu_addr;
  59         uint32_t                        *ucode_fw_ptr;
  60         uint32_t                        ucode_fw_version;
  61         uint64_t                        uc_start_addr;
  62
  63         /* mes ucode data */
  64         struct amdgpu_bo                *data_fw_obj;
  65         uint64_t                        data_fw_gpu_addr;
  66         uint32_t                        *data_fw_ptr;
  67         uint32_t                        data_fw_version;
  68         uint64_t                        data_start_addr;
  69
  70         /* eop gpu obj */
  71         struct amdgpu_bo                *eop_gpu_obj;
  72         uint64_t                        eop_gpu_addr;
  73
  74         void                            *mqd_backup;
  75
  76         uint32_t                        vmid_mask_gfxhub;
  77         uint32_t                        vmid_mask_mmhub;
  78         uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
  79         uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
  80         uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
  81         uint32_t                        agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
  82         uint32_t                        sch_ctx_offs;
  83         uint64_t                        sch_ctx_gpu_addr;
  84         uint64_t                        *sch_ctx_ptr;
  85
  86         /* ip specific functions */
  87         const struct amdgpu_mes_funcs   *funcs;
  88 };
  89
  90 struct mes_add_queue_input {
  91         uint32_t        process_id;
  92         uint64_t        page_table_base_addr;
  93         uint64_t        process_va_start;
  94         uint64_t        process_va_end;
  95         uint64_t        process_quantum;
  96         uint64_t        process_context_addr;
  97         uint64_t        gang_quantum;
  98         uint64_t        gang_context_addr;
  99         uint32_t        inprocess_gang_priority;
 100         uint32_t        gang_global_priority_level;
 101         uint32_t        doorbell_offset;
 102         uint64_t        mqd_addr;
 103         uint64_t        wptr_addr;
 104         uint32_t        queue_type;
 105         uint32_t        paging;
 106 };
 107
 108 struct mes_remove_queue_input {
 109         uint32_t        doorbell_offset;
 110         uint64_t        gang_context_addr;
 111 };
 112
 113 struct mes_suspend_gang_input {
 114         bool            suspend_all_gangs;
 115         uint64_t        gang_context_addr;
 116         uint64_t        suspend_fence_addr;
 117         uint32_t        suspend_fence_value;
 118 };
 119
 120 struct mes_resume_gang_input {
 121         bool            resume_all_gangs;
 122         uint64_t        gang_context_addr;
 123 };
 124
 125 struct amdgpu_mes_funcs {
 126         int (*add_hw_queue)(struct amdgpu_mes *mes,
 127                             struct mes_add_queue_input *input);
 128
 129         int (*remove_hw_queue)(struct amdgpu_mes *mes,
 130                                struct mes_remove_queue_input *input);
 131
 132         int (*suspend_gang)(struct amdgpu_mes *mes,
 133                             struct mes_suspend_gang_input *input);
 134
 135         int (*resume_gang)(struct amdgpu_mes *mes,
 136                            struct mes_resume_gang_input *input);
 137 };
 138
 139 #endif /* __AMDGPU_MES_H__ */