drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "smuio/smuio_9_0_offset.h"
  45 #include "smuio/smuio_9_0_sh_mask.h"
  46 #include "nbio/nbio_7_0_default.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "vega10_ih.h"
  60 #include "sdma_v4_0.h"
  61 #include "uvd_v7_0.h"
  62 #include "vce_v4_0.h"
  63 #include "vcn_v1_0.h"
  64 #include "dce_virtual.h"
  65 #include "mxgpu_ai.h"
  66 #include "amdgpu_smu.h"
  67
  68 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  69 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  70 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  71 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  72
  73 /* for Vega20 register name change */
  74 #define mmHDP_MEM_POWER_CTRL    0x00d4
  75 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  76 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  77 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  78 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  79 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  80 /*
  81  * Indirect registers accessor
  82  */
  83 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  84 {
  85         unsigned long flags, address, data;
  86         u32 r;
  87         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  88         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  89
  90         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  91         WREG32(address, reg);
  92         (void)RREG32(address);
  93         r = RREG32(data);
  94         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  95         return r;
  96 }
  97
  98 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  99 {
 100         unsigned long flags, address, data;
 101
 102         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 103         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 104
 105         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 106         WREG32(address, reg);
 107         (void)RREG32(address);
 108         WREG32(data, v);
 109         (void)RREG32(data);
 110         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 111 }
 112
 113 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 114 {
 115         unsigned long flags, address, data;
 116         u32 r;
 117
 118         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 119         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 120
 121         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 122         WREG32(address, ((reg) & 0x1ff));
 123         r = RREG32(data);
 124         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 125         return r;
 126 }
 127
 128 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 129 {
 130         unsigned long flags, address, data;
 131
 132         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 133         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 134
 135         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 136         WREG32(address, ((reg) & 0x1ff));
 137         WREG32(data, (v));
 138         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 139 }
 140
 141 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 142 {
 143         unsigned long flags, address, data;
 144         u32 r;
 145
 146         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 147         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 148
 149         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 150         WREG32(address, (reg));
 151         r = RREG32(data);
 152         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 153         return r;
 154 }
 155
 156 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 157 {
 158         unsigned long flags, address, data;
 159
 160         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 161         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 162
 163         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 164         WREG32(address, (reg));
 165         WREG32(data, (v));
 166         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 167 }
 168
 169 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 170 {
 171         unsigned long flags;
 172         u32 r;
 173
 174         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 175         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 176         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 177         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 178         return r;
 179 }
 180
 181 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 182 {
 183         unsigned long flags;
 184
 185         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 186         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 187         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 188         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 189 }
 190
 191 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 192 {
 193         unsigned long flags;
 194         u32 r;
 195
 196         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 197         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 198         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 199         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 200         return r;
 201 }
 202
 203 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 204 {
 205         unsigned long flags;
 206
 207         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 208         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 209         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 210         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 211 }
 212
 213 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 214 {
 215         return adev->nbio_funcs->get_memsize(adev);
 216 }
 217
 218 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 219 {
 220         return adev->clock.spll.reference_freq;
 221 }
 222
 223
 224 void soc15_grbm_select(struct amdgpu_device *adev,
 225                      u32 me, u32 pipe, u32 queue, u32 vmid)
 226 {
 227         u32 grbm_gfx_cntl = 0;
 228         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 229         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 230         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 231         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 232
 233         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 234 }
 235
 236 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 237 {
 238         /* todo */
 239 }
 240
 241 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 242 {
 243         /* todo */
 244         return false;
 245 }
 246
 247 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 248                                      u8 *bios, u32 length_bytes)
 249 {
 250         u32 *dw_ptr;
 251         u32 i, length_dw;
 252
 253         if (bios == NULL)
 254                 return false;
 255         if (length_bytes == 0)
 256                 return false;
 257         /* APU vbios image is part of sbios image */
 258         if (adev->flags & AMD_IS_APU)
 259                 return false;
 260
 261         dw_ptr = (u32 *)bios;
 262         length_dw = ALIGN(length_bytes, 4) / 4;
 263
 264         /* set rom index to 0 */
 265         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 266         /* read out the rom data */
 267         for (i = 0; i < length_dw; i++)
 268                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 269
 270         return true;
 271 }
 272
 273 struct soc15_allowed_register_entry {
 274         uint32_t hwip;
 275         uint32_t inst;
 276         uint32_t seg;
 277         uint32_t reg_offset;
 278         bool grbm_indexed;
 279 };
 280
 281
 282 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 283         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 284         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 285         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 286         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 287         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 288         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 289         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 290         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 291         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 292         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 293         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 294         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 295         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 296         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 297         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 298         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 299         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 300         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 301         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 302 };
 303
 304 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 305                                          u32 sh_num, u32 reg_offset)
 306 {
 307         uint32_t val;
 308
 309         mutex_lock(&adev->grbm_idx_mutex);
 310         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 311                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 312
 313         val = RREG32(reg_offset);
 314
 315         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 316                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 317         mutex_unlock(&adev->grbm_idx_mutex);
 318         return val;
 319 }
 320
 321 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 322                                          bool indexed, u32 se_num,
 323                                          u32 sh_num, u32 reg_offset)
 324 {
 325         if (indexed) {
 326                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 327         } else {
 328                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 329                         return adev->gfx.config.gb_addr_config;
 330                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 331                         return adev->gfx.config.db_debug2;
 332                 return RREG32(reg_offset);
 333         }
 334 }
 335
 336 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 337                             u32 sh_num, u32 reg_offset, u32 *value)
 338 {
 339         uint32_t i;
 340         struct soc15_allowed_register_entry  *en;
 341
 342         *value = 0;
 343         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 344                 en = &soc15_allowed_read_registers[i];
 345                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 346                                         + en->reg_offset))
 347                         continue;
 348
 349                 *value = soc15_get_register_value(adev,
 350                                                   soc15_allowed_read_registers[i].grbm_indexed,
 351                                                   se_num, sh_num, reg_offset);
 352                 return 0;
 353         }
 354         return -EINVAL;
 355 }
 356
 357
 358 /**
 359  * soc15_program_register_sequence - program an array of registers.
 360  *
 361  * @adev: amdgpu_device pointer
 362  * @regs: pointer to the register array
 363  * @array_size: size of the register array
 364  *
 365  * Programs an array or registers with and and or masks.
 366  * This is a helper for setting golden registers.
 367  */
 368
 369 void soc15_program_register_sequence(struct amdgpu_device *adev,
 370                                              const struct soc15_reg_golden *regs,
 371                                              const u32 array_size)
 372 {
 373         const struct soc15_reg_golden *entry;
 374         u32 tmp, reg;
 375         int i;
 376
 377         for (i = 0; i < array_size; ++i) {
 378                 entry = &regs[i];
 379                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 380
 381                 if (entry->and_mask == 0xffffffff) {
 382                         tmp = entry->or_mask;
 383                 } else {
 384                         tmp = RREG32(reg);
 385                         tmp &= ~(entry->and_mask);
 386                         tmp |= entry->or_mask;
 387                 }
 388                 WREG32(reg, tmp);
 389         }
 390
 391 }
 392
 393 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 394 {
 395         u32 i;
 396
 397         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 398
 399         dev_info(adev->dev, "GPU mode1 reset\n");
 400
 401         /* disable BM */
 402         pci_clear_master(adev->pdev);
 403
 404         pci_save_state(adev->pdev);
 405
 406         psp_gpu_reset(adev);
 407
 408         pci_restore_state(adev->pdev);
 409
 410         /* wait for asic to come out of reset */
 411         for (i = 0; i < adev->usec_timeout; i++) {
 412                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 413
 414                 if (memsize != 0xffffffff)
 415                         break;
 416                 udelay(1);
 417         }
 418
 419         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 420
 421         return 0;
 422 }
 423
 424 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
 425 {
 426         void *pp_handle = adev->powerplay.pp_handle;
 427         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 428
 429         if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
 430                 *cap = false;
 431                 return -ENOENT;
 432         }
 433
 434         return pp_funcs->get_asic_baco_capability(pp_handle, cap);
 435 }
 436
 437 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 438 {
 439         void *pp_handle = adev->powerplay.pp_handle;
 440         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 441
 442         if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
 443                 return -ENOENT;
 444
 445         /* enter BACO state */
 446         if (pp_funcs->set_asic_baco_state(pp_handle, 1))
 447                 return -EIO;
 448
 449         /* exit BACO state */
 450         if (pp_funcs->set_asic_baco_state(pp_handle, 0))
 451                 return -EIO;
 452
 453         dev_info(adev->dev, "GPU BACO reset\n");
 454
 455         return 0;
 456 }
 457
 458 static int soc15_asic_reset(struct amdgpu_device *adev)
 459 {
 460         int ret;
 461         bool baco_reset;
 462
 463         switch (adev->asic_type) {
 464         case CHIP_VEGA10:
 465         case CHIP_VEGA12:
 466                 soc15_asic_get_baco_capability(adev, &baco_reset);
 467                 break;
 468         default:
 469                 baco_reset = false;
 470                 break;
 471         }
 472
 473         if (baco_reset)
 474                 ret = soc15_asic_baco_reset(adev);
 475         else
 476                 ret = soc15_asic_mode1_reset(adev);
 477
 478         return ret;
 479 }
 480
 481 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 482                         u32 cntl_reg, u32 status_reg)
 483 {
 484         return 0;
 485 }*/
 486
 487 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 488 {
 489         /*int r;
 490
 491         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 492         if (r)
 493                 return r;
 494
 495         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 496         */
 497         return 0;
 498 }
 499
 500 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 501 {
 502         /* todo */
 503
 504         return 0;
 505 }
 506
 507 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 508 {
 509         if (pci_is_root_bus(adev->pdev->bus))
 510                 return;
 511
 512         if (amdgpu_pcie_gen2 == 0)
 513                 return;
 514
 515         if (adev->flags & AMD_IS_APU)
 516                 return;
 517
 518         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 519                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 520                 return;
 521
 522         /* todo */
 523 }
 524
 525 static void soc15_program_aspm(struct amdgpu_device *adev)
 526 {
 527
 528         if (amdgpu_aspm == 0)
 529                 return;
 530
 531         /* todo */
 532 }
 533
 534 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 535                                            bool enable)
 536 {
 537         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 538         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 539 }
 540
 541 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 542 {
 543         .type = AMD_IP_BLOCK_TYPE_COMMON,
 544         .major = 2,
 545         .minor = 0,
 546         .rev = 0,
 547         .funcs = &soc15_common_ip_funcs,
 548 };
 549
 550 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 551 {
 552         return adev->nbio_funcs->get_rev_id(adev);
 553 }
 554
 555 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 556 {
 557         /* Set IP register base before any HW register access */
 558         switch (adev->asic_type) {
 559         case CHIP_VEGA10:
 560         case CHIP_VEGA12:
 561         case CHIP_RAVEN:
 562                 vega10_reg_base_init(adev);
 563                 break;
 564         case CHIP_VEGA20:
 565                 vega20_reg_base_init(adev);
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         if (adev->asic_type == CHIP_VEGA20)
 572                 adev->gmc.xgmi.supported = true;
 573
 574         if (adev->flags & AMD_IS_APU)
 575                 adev->nbio_funcs = &nbio_v7_0_funcs;
 576         else if (adev->asic_type == CHIP_VEGA20)
 577                 adev->nbio_funcs = &nbio_v7_4_funcs;
 578         else
 579                 adev->nbio_funcs = &nbio_v6_1_funcs;
 580
 581         if (adev->asic_type == CHIP_VEGA20)
 582                 adev->df_funcs = &df_v3_6_funcs;
 583         else
 584                 adev->df_funcs = &df_v1_7_funcs;
 585
 586         adev->rev_id = soc15_get_rev_id(adev);
 587         adev->nbio_funcs->detect_hw_virt(adev);
 588
 589         if (amdgpu_sriov_vf(adev))
 590                 adev->virt.ops = &xgpu_ai_virt_ops;
 591
 592         switch (adev->asic_type) {
 593         case CHIP_VEGA10:
 594         case CHIP_VEGA12:
 595         case CHIP_VEGA20:
 596                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 597                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 598                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 599                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 600                         if (adev->asic_type == CHIP_VEGA20)
 601                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 602                         else
 603                                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 604                 }
 605                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 606                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 607                 if (!amdgpu_sriov_vf(adev)) {
 608                         if (is_support_sw_smu(adev))
 609                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 610                         else
 611                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 612                 }
 613                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 614                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 615 #if defined(CONFIG_DRM_AMD_DC)
 616                 else if (amdgpu_device_has_dc_support(adev))
 617                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 618 #else
 619 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 620 #endif
 621                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 622                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 623                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 624                 }
 625                 break;
 626         case CHIP_RAVEN:
 627                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 628                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 629                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 630                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 631                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 632                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 633                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 634                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 635                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 636                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 637 #if defined(CONFIG_DRM_AMD_DC)
 638                 else if (amdgpu_device_has_dc_support(adev))
 639                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 640 #else
 641 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 642 #endif
 643                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 644                 break;
 645         default:
 646                 return -EINVAL;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 653 {
 654         adev->nbio_funcs->hdp_flush(adev, ring);
 655 }
 656
 657 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 658                                  struct amdgpu_ring *ring)
 659 {
 660         if (!ring || !ring->funcs->emit_wreg)
 661                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 662         else
 663                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 664                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 665 }
 666
 667 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 668 {
 669         /* change this when we implement soft reset */
 670         return true;
 671 }
 672 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 673                                  uint64_t *count1)
 674 {
 675         uint32_t perfctr = 0;
 676         uint64_t cnt0_of, cnt1_of;
 677         int tmp;
 678
 679         /* This reports 0 on APUs, so return to avoid writing/reading registers
 680          * that may or may not be different from their GPU counterparts
 681          */
 682          if (adev->flags & AMD_IS_APU)
 683                  return;
 684
 685         /* Set the 2 events that we wish to watch, defined above */
 686         /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
 687         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 688         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 689
 690         /* Write to enable desired perf counters */
 691         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 692         /* Zero out and enable the perf counters
 693          * Write 0x5:
 694          * Bit 0 = Start all counters(1)
 695          * Bit 2 = Global counter reset enable(1)
 696          */
 697         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 698
 699         msleep(1000);
 700
 701         /* Load the shadow and disable the perf counters
 702          * Write 0x2:
 703          * Bit 0 = Stop counters(0)
 704          * Bit 1 = Load the shadow counters(1)
 705          */
 706         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 707
 708         /* Read register values to get any >32bit overflow */
 709         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 710         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 711         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 712
 713         /* Get the values and add the overflow */
 714         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 715         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 716 }
 717
 718 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 719 {
 720         u32 sol_reg;
 721
 722         if (adev->flags & AMD_IS_APU)
 723                 return false;
 724
 725         /* Check sOS sign of life register to confirm sys driver and sOS
 726          * are already been loaded.
 727          */
 728         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 729         if (sol_reg)
 730                 return true;
 731
 732         return false;
 733 }
 734
 735 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 736 {
 737         .read_disabled_bios = &soc15_read_disabled_bios,
 738         .read_bios_from_rom = &soc15_read_bios_from_rom,
 739         .read_register = &soc15_read_register,
 740         .reset = &soc15_asic_reset,
 741         .set_vga_state = &soc15_vga_set_state,
 742         .get_xclk = &soc15_get_xclk,
 743         .set_uvd_clocks = &soc15_set_uvd_clocks,
 744         .set_vce_clocks = &soc15_set_vce_clocks,
 745         .get_config_memsize = &soc15_get_config_memsize,
 746         .flush_hdp = &soc15_flush_hdp,
 747         .invalidate_hdp = &soc15_invalidate_hdp,
 748         .need_full_reset = &soc15_need_full_reset,
 749         .init_doorbell_index = &vega10_doorbell_index_init,
 750         .get_pcie_usage = &soc15_get_pcie_usage,
 751         .need_reset_on_init = &soc15_need_reset_on_init,
 752 };
 753
 754 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 755 {
 756         .read_disabled_bios = &soc15_read_disabled_bios,
 757         .read_bios_from_rom = &soc15_read_bios_from_rom,
 758         .read_register = &soc15_read_register,
 759         .reset = &soc15_asic_reset,
 760         .set_vga_state = &soc15_vga_set_state,
 761         .get_xclk = &soc15_get_xclk,
 762         .set_uvd_clocks = &soc15_set_uvd_clocks,
 763         .set_vce_clocks = &soc15_set_vce_clocks,
 764         .get_config_memsize = &soc15_get_config_memsize,
 765         .flush_hdp = &soc15_flush_hdp,
 766         .invalidate_hdp = &soc15_invalidate_hdp,
 767         .need_full_reset = &soc15_need_full_reset,
 768         .init_doorbell_index = &vega20_doorbell_index_init,
 769         .get_pcie_usage = &soc15_get_pcie_usage,
 770         .need_reset_on_init = &soc15_need_reset_on_init,
 771 };
 772
 773 static int soc15_common_early_init(void *handle)
 774 {
 775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 776
 777         adev->smc_rreg = NULL;
 778         adev->smc_wreg = NULL;
 779         adev->pcie_rreg = &soc15_pcie_rreg;
 780         adev->pcie_wreg = &soc15_pcie_wreg;
 781         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 782         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 783         adev->didt_rreg = &soc15_didt_rreg;
 784         adev->didt_wreg = &soc15_didt_wreg;
 785         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 786         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 787         adev->se_cac_rreg = &soc15_se_cac_rreg;
 788         adev->se_cac_wreg = &soc15_se_cac_wreg;
 789
 790
 791         adev->external_rev_id = 0xFF;
 792         switch (adev->asic_type) {
 793         case CHIP_VEGA10:
 794                 adev->asic_funcs = &soc15_asic_funcs;
 795                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 796                         AMD_CG_SUPPORT_GFX_MGLS |
 797                         AMD_CG_SUPPORT_GFX_RLC_LS |
 798                         AMD_CG_SUPPORT_GFX_CP_LS |
 799                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 800                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 801                         AMD_CG_SUPPORT_GFX_CGCG |
 802                         AMD_CG_SUPPORT_GFX_CGLS |
 803                         AMD_CG_SUPPORT_BIF_MGCG |
 804                         AMD_CG_SUPPORT_BIF_LS |
 805                         AMD_CG_SUPPORT_HDP_LS |
 806                         AMD_CG_SUPPORT_DRM_MGCG |
 807                         AMD_CG_SUPPORT_DRM_LS |
 808                         AMD_CG_SUPPORT_ROM_MGCG |
 809                         AMD_CG_SUPPORT_DF_MGCG |
 810                         AMD_CG_SUPPORT_SDMA_MGCG |
 811                         AMD_CG_SUPPORT_SDMA_LS |
 812                         AMD_CG_SUPPORT_MC_MGCG |
 813                         AMD_CG_SUPPORT_MC_LS;
 814                 adev->pg_flags = 0;
 815                 adev->external_rev_id = 0x1;
 816                 break;
 817         case CHIP_VEGA12:
 818                 adev->asic_funcs = &soc15_asic_funcs;
 819                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 820                         AMD_CG_SUPPORT_GFX_MGLS |
 821                         AMD_CG_SUPPORT_GFX_CGCG |
 822                         AMD_CG_SUPPORT_GFX_CGLS |
 823                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 824                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 825                         AMD_CG_SUPPORT_GFX_CP_LS |
 826                         AMD_CG_SUPPORT_MC_LS |
 827                         AMD_CG_SUPPORT_MC_MGCG |
 828                         AMD_CG_SUPPORT_SDMA_MGCG |
 829                         AMD_CG_SUPPORT_SDMA_LS |
 830                         AMD_CG_SUPPORT_BIF_MGCG |
 831                         AMD_CG_SUPPORT_BIF_LS |
 832                         AMD_CG_SUPPORT_HDP_MGCG |
 833                         AMD_CG_SUPPORT_HDP_LS |
 834                         AMD_CG_SUPPORT_ROM_MGCG |
 835                         AMD_CG_SUPPORT_VCE_MGCG |
 836                         AMD_CG_SUPPORT_UVD_MGCG;
 837                 adev->pg_flags = 0;
 838                 adev->external_rev_id = adev->rev_id + 0x14;
 839                 break;
 840         case CHIP_VEGA20:
 841                 adev->asic_funcs = &vega20_asic_funcs;
 842                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 843                         AMD_CG_SUPPORT_GFX_MGLS |
 844                         AMD_CG_SUPPORT_GFX_CGCG |
 845                         AMD_CG_SUPPORT_GFX_CGLS |
 846                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 847                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 848                         AMD_CG_SUPPORT_GFX_CP_LS |
 849                         AMD_CG_SUPPORT_MC_LS |
 850                         AMD_CG_SUPPORT_MC_MGCG |
 851                         AMD_CG_SUPPORT_SDMA_MGCG |
 852                         AMD_CG_SUPPORT_SDMA_LS |
 853                         AMD_CG_SUPPORT_BIF_MGCG |
 854                         AMD_CG_SUPPORT_BIF_LS |
 855                         AMD_CG_SUPPORT_HDP_MGCG |
 856                         AMD_CG_SUPPORT_HDP_LS |
 857                         AMD_CG_SUPPORT_ROM_MGCG |
 858                         AMD_CG_SUPPORT_VCE_MGCG |
 859                         AMD_CG_SUPPORT_UVD_MGCG;
 860                 adev->pg_flags = 0;
 861                 adev->external_rev_id = adev->rev_id + 0x28;
 862                 break;
 863         case CHIP_RAVEN:
 864                 adev->asic_funcs = &soc15_asic_funcs;
 865                 if (adev->rev_id >= 0x8)
 866                         adev->external_rev_id = adev->rev_id + 0x79;
 867                 else if (adev->pdev->device == 0x15d8)
 868                         adev->external_rev_id = adev->rev_id + 0x41;
 869                 else if (adev->rev_id == 1)
 870                         adev->external_rev_id = adev->rev_id + 0x20;
 871                 else
 872                         adev->external_rev_id = adev->rev_id + 0x01;
 873
 874                 if (adev->rev_id >= 0x8) {
 875                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 876                                 AMD_CG_SUPPORT_GFX_MGLS |
 877                                 AMD_CG_SUPPORT_GFX_CP_LS |
 878                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 879                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 880                                 AMD_CG_SUPPORT_GFX_CGCG |
 881                                 AMD_CG_SUPPORT_GFX_CGLS |
 882                                 AMD_CG_SUPPORT_BIF_LS |
 883                                 AMD_CG_SUPPORT_HDP_LS |
 884                                 AMD_CG_SUPPORT_ROM_MGCG |
 885                                 AMD_CG_SUPPORT_MC_MGCG |
 886                                 AMD_CG_SUPPORT_MC_LS |
 887                                 AMD_CG_SUPPORT_SDMA_MGCG |
 888                                 AMD_CG_SUPPORT_SDMA_LS |
 889                                 AMD_CG_SUPPORT_VCN_MGCG;
 890
 891                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 892                 } else if (adev->pdev->device == 0x15d8) {
 893                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
 894                                 AMD_CG_SUPPORT_GFX_CP_LS |
 895                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 896                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 897                                 AMD_CG_SUPPORT_GFX_CGCG |
 898                                 AMD_CG_SUPPORT_GFX_CGLS |
 899                                 AMD_CG_SUPPORT_BIF_LS |
 900                                 AMD_CG_SUPPORT_HDP_LS |
 901                                 AMD_CG_SUPPORT_ROM_MGCG |
 902                                 AMD_CG_SUPPORT_MC_MGCG |
 903                                 AMD_CG_SUPPORT_MC_LS |
 904                                 AMD_CG_SUPPORT_SDMA_MGCG |
 905                                 AMD_CG_SUPPORT_SDMA_LS;
 906
 907                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 908                                 AMD_PG_SUPPORT_MMHUB |
 909                                 AMD_PG_SUPPORT_VCN |
 910                                 AMD_PG_SUPPORT_VCN_DPG;
 911                 } else {
 912                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 913                                 AMD_CG_SUPPORT_GFX_MGLS |
 914                                 AMD_CG_SUPPORT_GFX_RLC_LS |
 915                                 AMD_CG_SUPPORT_GFX_CP_LS |
 916                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 917                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 918                                 AMD_CG_SUPPORT_GFX_CGCG |
 919                                 AMD_CG_SUPPORT_GFX_CGLS |
 920                                 AMD_CG_SUPPORT_BIF_MGCG |
 921                                 AMD_CG_SUPPORT_BIF_LS |
 922                                 AMD_CG_SUPPORT_HDP_MGCG |
 923                                 AMD_CG_SUPPORT_HDP_LS |
 924                                 AMD_CG_SUPPORT_DRM_MGCG |
 925                                 AMD_CG_SUPPORT_DRM_LS |
 926                                 AMD_CG_SUPPORT_ROM_MGCG |
 927                                 AMD_CG_SUPPORT_MC_MGCG |
 928                                 AMD_CG_SUPPORT_MC_LS |
 929                                 AMD_CG_SUPPORT_SDMA_MGCG |
 930                                 AMD_CG_SUPPORT_SDMA_LS |
 931                                 AMD_CG_SUPPORT_VCN_MGCG;
 932
 933                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 934                 }
 935
 936                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 937                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 938                                 AMD_PG_SUPPORT_CP |
 939                                 AMD_PG_SUPPORT_RLC_SMU_HS;
 940                 break;
 941         default:
 942                 /* FIXME: not supported yet */
 943                 return -EINVAL;
 944         }
 945
 946         if (amdgpu_sriov_vf(adev)) {
 947                 amdgpu_virt_init_setting(adev);
 948                 xgpu_ai_mailbox_set_irq_funcs(adev);
 949         }
 950
 951         return 0;
 952 }
 953
 954 static int soc15_common_late_init(void *handle)
 955 {
 956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 957
 958         if (amdgpu_sriov_vf(adev))
 959                 xgpu_ai_mailbox_get_irq(adev);
 960
 961         return 0;
 962 }
 963
 964 static int soc15_common_sw_init(void *handle)
 965 {
 966         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 967
 968         if (amdgpu_sriov_vf(adev))
 969                 xgpu_ai_mailbox_add_irq_id(adev);
 970
 971         return 0;
 972 }
 973
 974 static int soc15_common_sw_fini(void *handle)
 975 {
 976         return 0;
 977 }
 978
 979 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
 980 {
 981         int i;
 982         struct amdgpu_ring *ring;
 983
 984         for (i = 0; i < adev->sdma.num_instances; i++) {
 985                 ring = &adev->sdma.instance[i].ring;
 986                 adev->nbio_funcs->sdma_doorbell_range(adev, i,
 987                         ring->use_doorbell, ring->doorbell_index,
 988                         adev->doorbell_index.sdma_doorbell_range);
 989         }
 990
 991         adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
 992                                                 adev->irq.ih.doorbell_index);
 993 }
 994
 995 static int soc15_common_hw_init(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998
 999         /* enable pcie gen2/3 link */
1000         soc15_pcie_gen3_enable(adev);
1001         /* enable aspm */
1002         soc15_program_aspm(adev);
1003         /* setup nbio registers */
1004         adev->nbio_funcs->init_registers(adev);
1005         /* enable the doorbell aperture */
1006         soc15_enable_doorbell_aperture(adev, true);
1007         /* HW doorbell routing policy: doorbell writing not
1008          * in SDMA/IH/MM/ACV range will be routed to CP. So
1009          * we need to init SDMA/IH/MM/ACV doorbell range prior
1010          * to CP ip block init and ring test.
1011          */
1012         soc15_doorbell_range_init(adev);
1013
1014         return 0;
1015 }
1016
1017 static int soc15_common_hw_fini(void *handle)
1018 {
1019         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1020
1021         /* disable the doorbell aperture */
1022         soc15_enable_doorbell_aperture(adev, false);
1023         if (amdgpu_sriov_vf(adev))
1024                 xgpu_ai_mailbox_put_irq(adev);
1025
1026         return 0;
1027 }
1028
1029 static int soc15_common_suspend(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032
1033         return soc15_common_hw_fini(adev);
1034 }
1035
1036 static int soc15_common_resume(void *handle)
1037 {
1038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039
1040         return soc15_common_hw_init(adev);
1041 }
1042
1043 static bool soc15_common_is_idle(void *handle)
1044 {
1045         return true;
1046 }
1047
1048 static int soc15_common_wait_for_idle(void *handle)
1049 {
1050         return 0;
1051 }
1052
1053 static int soc15_common_soft_reset(void *handle)
1054 {
1055         return 0;
1056 }
1057
1058 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1059 {
1060         uint32_t def, data;
1061
1062         if (adev->asic_type == CHIP_VEGA20) {
1063                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1064
1065                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1066                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1067                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1068                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1069                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1070                 else
1071                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1072                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1073                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1074                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1075
1076                 if (def != data)
1077                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1078         } else {
1079                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1080
1081                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1082                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1083                 else
1084                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1085
1086                 if (def != data)
1087                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1088         }
1089 }
1090
1091 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1092 {
1093         uint32_t def, data;
1094
1095         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1096
1097         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1098                 data &= ~(0x01000000 |
1099                           0x02000000 |
1100                           0x04000000 |
1101                           0x08000000 |
1102                           0x10000000 |
1103                           0x20000000 |
1104                           0x40000000 |
1105                           0x80000000);
1106         else
1107                 data |= (0x01000000 |
1108                          0x02000000 |
1109                          0x04000000 |
1110                          0x08000000 |
1111                          0x10000000 |
1112                          0x20000000 |
1113                          0x40000000 |
1114                          0x80000000);
1115
1116         if (def != data)
1117                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1118 }
1119
1120 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1121 {
1122         uint32_t def, data;
1123
1124         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1125
1126         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1127                 data |= 1;
1128         else
1129                 data &= ~1;
1130
1131         if (def != data)
1132                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1133 }
1134
1135 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1136                                                        bool enable)
1137 {
1138         uint32_t def, data;
1139
1140         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1141
1142         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1143                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1144                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1145         else
1146                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1147                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1148
1149         if (def != data)
1150                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1151 }
1152
1153 static int soc15_common_set_clockgating_state(void *handle,
1154                                             enum amd_clockgating_state state)
1155 {
1156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1157
1158         if (amdgpu_sriov_vf(adev))
1159                 return 0;
1160
1161         switch (adev->asic_type) {
1162         case CHIP_VEGA10:
1163         case CHIP_VEGA12:
1164         case CHIP_VEGA20:
1165                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1166                                 state == AMD_CG_STATE_GATE ? true : false);
1167                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1168                                 state == AMD_CG_STATE_GATE ? true : false);
1169                 soc15_update_hdp_light_sleep(adev,
1170                                 state == AMD_CG_STATE_GATE ? true : false);
1171                 soc15_update_drm_clock_gating(adev,
1172                                 state == AMD_CG_STATE_GATE ? true : false);
1173                 soc15_update_drm_light_sleep(adev,
1174                                 state == AMD_CG_STATE_GATE ? true : false);
1175                 soc15_update_rom_medium_grain_clock_gating(adev,
1176                                 state == AMD_CG_STATE_GATE ? true : false);
1177                 adev->df_funcs->update_medium_grain_clock_gating(adev,
1178                                 state == AMD_CG_STATE_GATE ? true : false);
1179                 break;
1180         case CHIP_RAVEN:
1181                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1182                                 state == AMD_CG_STATE_GATE ? true : false);
1183                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1184                                 state == AMD_CG_STATE_GATE ? true : false);
1185                 soc15_update_hdp_light_sleep(adev,
1186                                 state == AMD_CG_STATE_GATE ? true : false);
1187                 soc15_update_drm_clock_gating(adev,
1188                                 state == AMD_CG_STATE_GATE ? true : false);
1189                 soc15_update_drm_light_sleep(adev,
1190                                 state == AMD_CG_STATE_GATE ? true : false);
1191                 soc15_update_rom_medium_grain_clock_gating(adev,
1192                                 state == AMD_CG_STATE_GATE ? true : false);
1193                 break;
1194         default:
1195                 break;
1196         }
1197         return 0;
1198 }
1199
1200 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1201 {
1202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203         int data;
1204
1205         if (amdgpu_sriov_vf(adev))
1206                 *flags = 0;
1207
1208         adev->nbio_funcs->get_clockgating_state(adev, flags);
1209
1210         /* AMD_CG_SUPPORT_HDP_LS */
1211         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1212         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1213                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1214
1215         /* AMD_CG_SUPPORT_DRM_MGCG */
1216         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1217         if (!(data & 0x01000000))
1218                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1219
1220         /* AMD_CG_SUPPORT_DRM_LS */
1221         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1222         if (data & 0x1)
1223                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1224
1225         /* AMD_CG_SUPPORT_ROM_MGCG */
1226         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1227         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1228                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1229
1230         adev->df_funcs->get_clockgating_state(adev, flags);
1231 }
1232
1233 static int soc15_common_set_powergating_state(void *handle,
1234                                             enum amd_powergating_state state)
1235 {
1236         /* todo */
1237         return 0;
1238 }
1239
1240 const struct amd_ip_funcs soc15_common_ip_funcs = {
1241         .name = "soc15_common",
1242         .early_init = soc15_common_early_init,
1243         .late_init = soc15_common_late_init,
1244         .sw_init = soc15_common_sw_init,
1245         .sw_fini = soc15_common_sw_fini,
1246         .hw_init = soc15_common_hw_init,
1247         .hw_fini = soc15_common_hw_fini,
1248         .suspend = soc15_common_suspend,
1249         .resume = soc15_common_resume,
1250         .is_idle = soc15_common_is_idle,
1251         .wait_for_idle = soc15_common_wait_for_idle,
1252         .soft_reset = soc15_common_soft_reset,
1253         .set_clockgating_state = soc15_common_set_clockgating_state,
1254         .set_powergating_state = soc15_common_set_powergating_state,
1255         .get_clockgating_state= soc15_common_get_clockgating_state,
1256 };