drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  */
   5
   6 #include <drm/drm_fourcc.h>
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/soc/mediatek/mtk-cmdq.h>
  14
  15 #include "mtk_disp_drv.h"
  16 #include "mtk_drm_drv.h"
  17 #include "mtk_mdp_rdma.h"
  18
  19 #define MDP_RDMA_EN                     0x000
  20 #define FLD_ROT_ENABLE                          BIT(0)
  21 #define MDP_RDMA_RESET                  0x008
  22 #define MDP_RDMA_CON                    0x020
  23 #define FLD_OUTPUT_10B                          BIT(5)
  24 #define FLD_SIMPLE_MODE                         BIT(4)
  25 #define MDP_RDMA_GMCIF_CON              0x028
  26 #define FLD_COMMAND_DIV                         BIT(0)
  27 #define FLD_EXT_PREULTRA_EN                     BIT(3)
  28 #define FLD_RD_REQ_TYPE                         GENMASK(7, 4)
  29 #define VAL_RD_REQ_TYPE_BURST_8_ACCESS          7
  30 #define FLD_ULTRA_EN                            GENMASK(13, 12)
  31 #define VAL_ULTRA_EN_ENABLE                     1
  32 #define FLD_PRE_ULTRA_EN                        GENMASK(17, 16)
  33 #define VAL_PRE_ULTRA_EN_ENABLE                 1
  34 #define FLD_EXT_ULTRA_EN                        BIT(18)
  35 #define MDP_RDMA_SRC_CON                0x030
  36 #define FLD_OUTPUT_ARGB                         BIT(25)
  37 #define FLD_BIT_NUMBER                          GENMASK(19, 18)
  38 #define FLD_SWAP                                BIT(14)
  39 #define FLD_UNIFORM_CONFIG                      BIT(17)
  40 #define RDMA_INPUT_10BIT                        BIT(18)
  41 #define FLD_SRC_FORMAT                          GENMASK(3, 0)
  42 #define MDP_RDMA_COMP_CON               0x038
  43 #define FLD_AFBC_EN                             BIT(22)
  44 #define FLD_AFBC_YUV_TRANSFORM                  BIT(21)
  45 #define FLD_UFBDC_EN                            BIT(12)
  46 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE   0x060
  47 #define FLD_MF_BKGD_WB                          GENMASK(22, 0)
  48 #define MDP_RDMA_MF_SRC_SIZE            0x070
  49 #define FLD_MF_SRC_H                            GENMASK(30, 16)
  50 #define FLD_MF_SRC_W                            GENMASK(14, 0)
  51 #define MDP_RDMA_MF_CLIP_SIZE           0x078
  52 #define FLD_MF_CLIP_H                           GENMASK(30, 16)
  53 #define FLD_MF_CLIP_W                           GENMASK(14, 0)
  54 #define MDP_RDMA_SRC_OFFSET_0           0x118
  55 #define FLD_SRC_OFFSET_0                        GENMASK(31, 0)
  56 #define MDP_RDMA_TRANSFORM_0            0x200
  57 #define FLD_INT_MATRIX_SEL                      GENMASK(27, 23)
  58 #define FLD_TRANS_EN                            BIT(16)
  59 #define MDP_RDMA_SRC_BASE_0             0xf00
  60 #define FLD_SRC_BASE_0                          GENMASK(31, 0)
  61
  62 #define RDMA_CSC_FULL709_TO_RGB                 5
  63 #define RDMA_CSC_BT601_TO_RGB                   6
  64
  65 static const u32 formats[] = {
  66         DRM_FORMAT_XRGB8888,
  67         DRM_FORMAT_ARGB8888,
  68         DRM_FORMAT_BGRX8888,
  69         DRM_FORMAT_BGRA8888,
  70         DRM_FORMAT_ABGR8888,
  71         DRM_FORMAT_XBGR8888,
  72         DRM_FORMAT_RGB888,
  73         DRM_FORMAT_BGR888,
  74         DRM_FORMAT_RGB565,
  75         DRM_FORMAT_UYVY,
  76         DRM_FORMAT_YUYV,
  77 };
  78
  79 enum rdma_format {
  80         RDMA_INPUT_FORMAT_RGB565 = 0,
  81         RDMA_INPUT_FORMAT_RGB888 = 1,
  82         RDMA_INPUT_FORMAT_RGBA8888 = 2,
  83         RDMA_INPUT_FORMAT_ARGB8888 = 3,
  84         RDMA_INPUT_FORMAT_UYVY = 4,
  85         RDMA_INPUT_FORMAT_YUY2 = 5,
  86         RDMA_INPUT_FORMAT_Y8 = 7,
  87         RDMA_INPUT_FORMAT_YV12 = 8,
  88         RDMA_INPUT_FORMAT_UYVY_3PL = 9,
  89         RDMA_INPUT_FORMAT_NV12 = 12,
  90         RDMA_INPUT_FORMAT_UYVY_2PL = 13,
  91         RDMA_INPUT_FORMAT_Y410 = 14
  92 };
  93
  94 struct mtk_mdp_rdma {
  95         void __iomem            *regs;
  96         struct clk              *clk;
  97         struct cmdq_client_reg  cmdq_reg;
  98 };
  99
 100 static unsigned int rdma_fmt_convert(unsigned int fmt)
 101 {
 102         switch (fmt) {
 103         default:
 104         case DRM_FORMAT_RGB565:
 105                 return RDMA_INPUT_FORMAT_RGB565;
 106         case DRM_FORMAT_BGR565:
 107                 return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
 108         case DRM_FORMAT_RGB888:
 109                 return RDMA_INPUT_FORMAT_RGB888;
 110         case DRM_FORMAT_BGR888:
 111                 return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
 112         case DRM_FORMAT_RGBX8888:
 113         case DRM_FORMAT_RGBA8888:
 114                 return RDMA_INPUT_FORMAT_ARGB8888;
 115         case DRM_FORMAT_BGRX8888:
 116         case DRM_FORMAT_BGRA8888:
 117                 return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
 118         case DRM_FORMAT_XRGB8888:
 119         case DRM_FORMAT_ARGB8888:
 120                 return RDMA_INPUT_FORMAT_RGBA8888;
 121         case DRM_FORMAT_XBGR8888:
 122         case DRM_FORMAT_ABGR8888:
 123                 return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
 124         case DRM_FORMAT_ABGR2101010:
 125                 return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
 126         case DRM_FORMAT_ARGB2101010:
 127                 return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
 128         case DRM_FORMAT_RGBA1010102:
 129                 return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
 130         case DRM_FORMAT_BGRA1010102:
 131                 return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
 132         case DRM_FORMAT_UYVY:
 133                 return RDMA_INPUT_FORMAT_UYVY;
 134         case DRM_FORMAT_YUYV:
 135                 return RDMA_INPUT_FORMAT_YUY2;
 136         }
 137 }
 138
 139 static unsigned int rdma_color_convert(unsigned int color_encoding)
 140 {
 141         switch (color_encoding) {
 142         default:
 143         case DRM_COLOR_YCBCR_BT709:
 144                 return RDMA_CSC_FULL709_TO_RGB;
 145         case DRM_COLOR_YCBCR_BT601:
 146                 return RDMA_CSC_BT601_TO_RGB;
 147         }
 148 }
 149
 150 static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 151 {
 152         struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
 153
 154         mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
 155                            VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
 156                            FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
 157                            priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
 158                            FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
 159                            FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
 160 }
 161
 162 void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 163 {
 164         struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
 165
 166         mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
 167                            priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
 168 }
 169
 170 void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
 171 {
 172         struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
 173
 174         mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
 175                            priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
 176         mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
 177         mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
 178 }
 179
 180 void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
 181                          struct cmdq_pkt *cmdq_pkt)
 182 {
 183         struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
 184         const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
 185         bool csc_enable = fmt_info->is_yuv ? true : false;
 186         unsigned int src_pitch_y = cfg->pitch;
 187         unsigned int offset_y = 0;
 188
 189         mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
 190
 191         mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
 192                            MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
 193         mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
 194                            MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
 195
 196         if (!csc_enable && fmt_info->has_alpha)
 197                 mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
 198                                    priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
 199         else
 200                 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
 201                                    MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
 202
 203         mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
 204                            MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
 205
 206         mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
 207                            MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
 208
 209         mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
 210                            FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
 211         mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
 212                            MDP_RDMA_CON, FLD_OUTPUT_10B);
 213         mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
 214                            MDP_RDMA_CON, FLD_SIMPLE_MODE);
 215         if (csc_enable)
 216                 mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,
 217                                    &priv->cmdq_reg, priv->regs, MDP_RDMA_TRANSFORM_0,
 218                                    FLD_INT_MATRIX_SEL);
 219         mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
 220                            MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
 221
 222         offset_y  = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
 223
 224         mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
 225                            MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
 226         mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
 227                            MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
 228         mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
 229                            MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
 230         mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
 231                            MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
 232         mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
 233                            MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
 234 }
 235
 236 const u32 *mtk_mdp_rdma_get_formats(struct device *dev)
 237 {
 238         return formats;
 239 }
 240
 241 size_t mtk_mdp_rdma_get_num_formats(struct device *dev)
 242 {
 243         return ARRAY_SIZE(formats);
 244 }
 245
 246 int mtk_mdp_rdma_clk_enable(struct device *dev)
 247 {
 248         struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
 249
 250         clk_prepare_enable(rdma->clk);
 251         return 0;
 252 }
 253
 254 void mtk_mdp_rdma_clk_disable(struct device *dev)
 255 {
 256         struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
 257
 258         clk_disable_unprepare(rdma->clk);
 259 }
 260
 261 static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
 262                              void *data)
 263 {
 264         return 0;
 265 }
 266
 267 static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
 268                                 void *data)
 269 {
 270 }
 271
 272 static const struct component_ops mtk_mdp_rdma_component_ops = {
 273         .bind   = mtk_mdp_rdma_bind,
 274         .unbind = mtk_mdp_rdma_unbind,
 275 };
 276
 277 static int mtk_mdp_rdma_probe(struct platform_device *pdev)
 278 {
 279         struct device *dev = &pdev->dev;
 280         struct resource *res;
 281         struct mtk_mdp_rdma *priv;
 282         int ret = 0;
 283
 284         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 285         if (!priv)
 286                 return -ENOMEM;
 287
 288         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 289         priv->regs = devm_ioremap_resource(dev, res);
 290         if (IS_ERR(priv->regs)) {
 291                 dev_err(dev, "failed to ioremap rdma\n");
 292                 return PTR_ERR(priv->regs);
 293         }
 294
 295         priv->clk = devm_clk_get(dev, NULL);
 296         if (IS_ERR(priv->clk)) {
 297                 dev_err(dev, "failed to get rdma clk\n");
 298                 return PTR_ERR(priv->clk);
 299         }
 300
 301 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 302         ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 303         if (ret)
 304                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 305 #endif
 306         platform_set_drvdata(pdev, priv);
 307
 308         pm_runtime_enable(dev);
 309
 310         ret = component_add(dev, &mtk_mdp_rdma_component_ops);
 311         if (ret != 0) {
 312                 pm_runtime_disable(dev);
 313                 dev_err(dev, "Failed to add component: %d\n", ret);
 314         }
 315         return ret;
 316 }
 317
 318 static int mtk_mdp_rdma_remove(struct platform_device *pdev)
 319 {
 320         component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
 321         pm_runtime_disable(&pdev->dev);
 322         return 0;
 323 }
 324
 325 static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
 326         { .compatible = "mediatek,mt8195-vdo1-rdma", },
 327         {},
 328 };
 329 MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
 330
 331 struct platform_driver mtk_mdp_rdma_driver = {
 332         .probe = mtk_mdp_rdma_probe,
 333         .remove = mtk_mdp_rdma_remove,
 334         .driver = {
 335                 .name = "mediatek-mdp-rdma",
 336                 .owner = THIS_MODULE,
 337                 .of_match_table = mtk_mdp_rdma_driver_dt_match,
 338         },
 339 };