drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  *
 369  * @dc: Display Core control structure
 370  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 371  * @planes_count: planes count to update
 372  * @stream: stream state
 373  * @stream_update: stream update
 374  * @array_of_surface_update: dc surface update pointer
 375  *
 376  */
 377 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 378                                                     int update_type,
 379                                                     int planes_count,
 380                                                     struct dc_stream_state *stream,
 381                                                     struct dc_stream_update *stream_update,
 382                                                     struct dc_surface_update *array_of_surface_update)
 383 {
 384         reverse_planes_order(array_of_surface_update, planes_count);
 385
 386         /*
 387          * Previous frame finished and HW is ready for optimization.
 388          */
 389         if (update_type == UPDATE_TYPE_FAST)
 390                 dc_post_update_surfaces_to_stream(dc);
 391
 392         return dc_update_planes_and_stream(dc,
 393                                            array_of_surface_update,
 394                                            planes_count,
 395                                            stream,
 396                                            stream_update);
 397 }
 398
 399 /**
 400  * dm_pflip_high_irq() - Handle pageflip interrupt
 401  * @interrupt_params: ignored
 402  *
 403  * Handles the pageflip interrupt by notifying all interested parties
 404  * that the pageflip has been completed.
 405  */
 406 static void dm_pflip_high_irq(void *interrupt_params)
 407 {
 408         struct amdgpu_crtc *amdgpu_crtc;
 409         struct common_irq_params *irq_params = interrupt_params;
 410         struct amdgpu_device *adev = irq_params->adev;
 411         unsigned long flags;
 412         struct drm_pending_vblank_event *e;
 413         u32 vpos, hpos, v_blank_start, v_blank_end;
 414         bool vrr_active;
 415
 416         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 417
 418         /* IRQ could occur when in initial stage */
 419         /* TODO work and BO cleanup */
 420         if (amdgpu_crtc == NULL) {
 421                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 422                 return;
 423         }
 424
 425         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 426
 427         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 428                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 429                                                  amdgpu_crtc->pflip_status,
 430                                                  AMDGPU_FLIP_SUBMITTED,
 431                                                  amdgpu_crtc->crtc_id,
 432                                                  amdgpu_crtc);
 433                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 434                 return;
 435         }
 436
 437         /* page flip completed. */
 438         e = amdgpu_crtc->event;
 439         amdgpu_crtc->event = NULL;
 440
 441         WARN_ON(!e);
 442
 443         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 444
 445         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 446         if (!vrr_active ||
 447             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 448                                       &v_blank_end, &hpos, &vpos) ||
 449             (vpos < v_blank_start)) {
 450                 /* Update to correct count and vblank timestamp if racing with
 451                  * vblank irq. This also updates to the correct vblank timestamp
 452                  * even in VRR mode, as scanout is past the front-porch atm.
 453                  */
 454                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 455
 456                 /* Wake up userspace by sending the pageflip event with proper
 457                  * count and timestamp of vblank of flip completion.
 458                  */
 459                 if (e) {
 460                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 461
 462                         /* Event sent, so done with vblank for this flip */
 463                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 464                 }
 465         } else if (e) {
 466                 /* VRR active and inside front-porch: vblank count and
 467                  * timestamp for pageflip event will only be up to date after
 468                  * drm_crtc_handle_vblank() has been executed from late vblank
 469                  * irq handler after start of back-porch (vline 0). We queue the
 470                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 471                  * updated timestamp and count, once it runs after us.
 472                  *
 473                  * We need to open-code this instead of using the helper
 474                  * drm_crtc_arm_vblank_event(), as that helper would
 475                  * call drm_crtc_accurate_vblank_count(), which we must
 476                  * not call in VRR mode while we are in front-porch!
 477                  */
 478
 479                 /* sequence will be replaced by real count during send-out. */
 480                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 481                 e->pipe = amdgpu_crtc->crtc_id;
 482
 483                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 484                 e = NULL;
 485         }
 486
 487         /* Keep track of vblank of this flip for flip throttling. We use the
 488          * cooked hw counter, as that one incremented at start of this vblank
 489          * of pageflip completion, so last_flip_vblank is the forbidden count
 490          * for queueing new pageflips if vsync + VRR is enabled.
 491          */
 492         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 493                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 494
 495         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 496         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 497
 498         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 499                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 500                      vrr_active, (int) !e);
 501 }
 502
 503 static void dm_vupdate_high_irq(void *interrupt_params)
 504 {
 505         struct common_irq_params *irq_params = interrupt_params;
 506         struct amdgpu_device *adev = irq_params->adev;
 507         struct amdgpu_crtc *acrtc;
 508         struct drm_device *drm_dev;
 509         struct drm_vblank_crtc *vblank;
 510         ktime_t frame_duration_ns, previous_timestamp;
 511         unsigned long flags;
 512         int vrr_active;
 513
 514         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 515
 516         if (acrtc) {
 517                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 518                 drm_dev = acrtc->base.dev;
 519                 vblank = &drm_dev->vblank[acrtc->base.index];
 520                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 521                 frame_duration_ns = vblank->time - previous_timestamp;
 522
 523                 if (frame_duration_ns > 0) {
 524                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 525                                                 frame_duration_ns,
 526                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 527                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 528                 }
 529
 530                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 531                               acrtc->crtc_id,
 532                               vrr_active);
 533
 534                 /* Core vblank handling is done here after end of front-porch in
 535                  * vrr mode, as vblank timestamping will give valid results
 536                  * while now done after front-porch. This will also deliver
 537                  * page-flip completion events that have been queued to us
 538                  * if a pageflip happened inside front-porch.
 539                  */
 540                 if (vrr_active) {
 541                         amdgpu_dm_crtc_handle_vblank(acrtc);
 542
 543                         /* BTR processing for pre-DCE12 ASICs */
 544                         if (acrtc->dm_irq_params.stream &&
 545                             adev->family < AMDGPU_FAMILY_AI) {
 546                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 547                                 mod_freesync_handle_v_update(
 548                                     adev->dm.freesync_module,
 549                                     acrtc->dm_irq_params.stream,
 550                                     &acrtc->dm_irq_params.vrr_params);
 551
 552                                 dc_stream_adjust_vmin_vmax(
 553                                     adev->dm.dc,
 554                                     acrtc->dm_irq_params.stream,
 555                                     &acrtc->dm_irq_params.vrr_params.adjust);
 556                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 557                         }
 558                 }
 559         }
 560 }
 561
 562 /**
 563  * dm_crtc_high_irq() - Handles CRTC interrupt
 564  * @interrupt_params: used for determining the CRTC instance
 565  *
 566  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 567  * event handler.
 568  */
 569 static void dm_crtc_high_irq(void *interrupt_params)
 570 {
 571         struct common_irq_params *irq_params = interrupt_params;
 572         struct amdgpu_device *adev = irq_params->adev;
 573         struct amdgpu_crtc *acrtc;
 574         unsigned long flags;
 575         int vrr_active;
 576
 577         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 578         if (!acrtc)
 579                 return;
 580
 581         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 582
 583         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 584                       vrr_active, acrtc->dm_irq_params.active_planes);
 585
 586         /**
 587          * Core vblank handling at start of front-porch is only possible
 588          * in non-vrr mode, as only there vblank timestamping will give
 589          * valid results while done in front-porch. Otherwise defer it
 590          * to dm_vupdate_high_irq after end of front-porch.
 591          */
 592         if (!vrr_active)
 593                 amdgpu_dm_crtc_handle_vblank(acrtc);
 594
 595         /**
 596          * Following stuff must happen at start of vblank, for crc
 597          * computation and below-the-range btr support in vrr mode.
 598          */
 599         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 600
 601         /* BTR updates need to happen before VUPDATE on Vega and above. */
 602         if (adev->family < AMDGPU_FAMILY_AI)
 603                 return;
 604
 605         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 606
 607         if (acrtc->dm_irq_params.stream &&
 608             acrtc->dm_irq_params.vrr_params.supported &&
 609             acrtc->dm_irq_params.freesync_config.state ==
 610                     VRR_STATE_ACTIVE_VARIABLE) {
 611                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 612                                              acrtc->dm_irq_params.stream,
 613                                              &acrtc->dm_irq_params.vrr_params);
 614
 615                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 616                                            &acrtc->dm_irq_params.vrr_params.adjust);
 617         }
 618
 619         /*
 620          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 621          * In that case, pageflip completion interrupts won't fire and pageflip
 622          * completion events won't get delivered. Prevent this by sending
 623          * pending pageflip events from here if a flip is still pending.
 624          *
 625          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 626          * avoid race conditions between flip programming and completion,
 627          * which could cause too early flip completion events.
 628          */
 629         if (adev->family >= AMDGPU_FAMILY_RV &&
 630             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 631             acrtc->dm_irq_params.active_planes == 0) {
 632                 if (acrtc->event) {
 633                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 634                         acrtc->event = NULL;
 635                         drm_crtc_vblank_put(&acrtc->base);
 636                 }
 637                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 638         }
 639
 640         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 641 }
 642
 643 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 644 /**
 645  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 646  * DCN generation ASICs
 647  * @interrupt_params: interrupt parameters
 648  *
 649  * Used to set crc window/read out crc value at vertical line 0 position
 650  */
 651 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 652 {
 653         struct common_irq_params *irq_params = interrupt_params;
 654         struct amdgpu_device *adev = irq_params->adev;
 655         struct amdgpu_crtc *acrtc;
 656
 657         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 658
 659         if (!acrtc)
 660                 return;
 661
 662         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 663 }
 664 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 665
 666 /**
 667  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 668  * @adev: amdgpu_device pointer
 669  * @notify: dmub notification structure
 670  *
 671  * Dmub AUX or SET_CONFIG command completion processing callback
 672  * Copies dmub notification to DM which is to be read by AUX command.
 673  * issuing thread and also signals the event to wake up the thread.
 674  */
 675 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 676                                         struct dmub_notification *notify)
 677 {
 678         if (adev->dm.dmub_notify)
 679                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 680         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 681                 complete(&adev->dm.dmub_aux_transfer_done);
 682 }
 683
 684 /**
 685  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 686  * @adev: amdgpu_device pointer
 687  * @notify: dmub notification structure
 688  *
 689  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 690  * ink index and calls helper to do the processing.
 691  */
 692 static void dmub_hpd_callback(struct amdgpu_device *adev,
 693                               struct dmub_notification *notify)
 694 {
 695         struct amdgpu_dm_connector *aconnector;
 696         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 697         struct drm_connector *connector;
 698         struct drm_connector_list_iter iter;
 699         struct dc_link *link;
 700         u8 link_index = 0;
 701         struct drm_device *dev;
 702
 703         if (adev == NULL)
 704                 return;
 705
 706         if (notify == NULL) {
 707                 DRM_ERROR("DMUB HPD callback notification was NULL");
 708                 return;
 709         }
 710
 711         if (notify->link_index > adev->dm.dc->link_count) {
 712                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 713                 return;
 714         }
 715
 716         link_index = notify->link_index;
 717         link = adev->dm.dc->links[link_index];
 718         dev = adev->dm.ddev;
 719
 720         drm_connector_list_iter_begin(dev, &iter);
 721         drm_for_each_connector_iter(connector, &iter) {
 722                 aconnector = to_amdgpu_dm_connector(connector);
 723                 if (link && aconnector->dc_link == link) {
 724                         if (notify->type == DMUB_NOTIFICATION_HPD)
 725                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 726                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 727                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 728                         else
 729                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 730                                                 notify->type, link_index);
 731
 732                         hpd_aconnector = aconnector;
 733                         break;
 734                 }
 735         }
 736         drm_connector_list_iter_end(&iter);
 737
 738         if (hpd_aconnector) {
 739                 if (notify->type == DMUB_NOTIFICATION_HPD)
 740                         handle_hpd_irq_helper(hpd_aconnector);
 741                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 742                         handle_hpd_rx_irq(hpd_aconnector);
 743         }
 744 }
 745
 746 /**
 747  * register_dmub_notify_callback - Sets callback for DMUB notify
 748  * @adev: amdgpu_device pointer
 749  * @type: Type of dmub notification
 750  * @callback: Dmub interrupt callback function
 751  * @dmub_int_thread_offload: offload indicator
 752  *
 753  * API to register a dmub callback handler for a dmub notification
 754  * Also sets indicator whether callback processing to be offloaded.
 755  * to dmub interrupt handling thread
 756  * Return: true if successfully registered, false if there is existing registration
 757  */
 758 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 759                                           enum dmub_notification_type type,
 760                                           dmub_notify_interrupt_callback_t callback,
 761                                           bool dmub_int_thread_offload)
 762 {
 763         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 764                 adev->dm.dmub_callback[type] = callback;
 765                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 766         } else
 767                 return false;
 768
 769         return true;
 770 }
 771
 772 static void dm_handle_hpd_work(struct work_struct *work)
 773 {
 774         struct dmub_hpd_work *dmub_hpd_wrk;
 775
 776         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 777
 778         if (!dmub_hpd_wrk->dmub_notify) {
 779                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 780                 return;
 781         }
 782
 783         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 784                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 785                 dmub_hpd_wrk->dmub_notify);
 786         }
 787
 788         kfree(dmub_hpd_wrk->dmub_notify);
 789         kfree(dmub_hpd_wrk);
 790
 791 }
 792
 793 #define DMUB_TRACE_MAX_READ 64
 794 /**
 795  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 796  * @interrupt_params: used for determining the Outbox instance
 797  *
 798  * Handles the Outbox Interrupt
 799  * event handler.
 800  */
 801 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 802 {
 803         struct dmub_notification notify;
 804         struct common_irq_params *irq_params = interrupt_params;
 805         struct amdgpu_device *adev = irq_params->adev;
 806         struct amdgpu_display_manager *dm = &adev->dm;
 807         struct dmcub_trace_buf_entry entry = { 0 };
 808         u32 count = 0;
 809         struct dmub_hpd_work *dmub_hpd_wrk;
 810         struct dc_link *plink = NULL;
 811
 812         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 813                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 814
 815                 do {
 816                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 817                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 818                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 819                                 continue;
 820                         }
 821                         if (!dm->dmub_callback[notify.type]) {
 822                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 823                                 continue;
 824                         }
 825                         if (dm->dmub_thread_offload[notify.type] == true) {
 826                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 827                                 if (!dmub_hpd_wrk) {
 828                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 829                                         return;
 830                                 }
 831                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 832                                                                     GFP_ATOMIC);
 833                                 if (!dmub_hpd_wrk->dmub_notify) {
 834                                         kfree(dmub_hpd_wrk);
 835                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 836                                         return;
 837                                 }
 838                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 839                                 dmub_hpd_wrk->adev = adev;
 840                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 841                                         plink = adev->dm.dc->links[notify.link_index];
 842                                         if (plink) {
 843                                                 plink->hpd_status =
 844                                                         notify.hpd_status == DP_HPD_PLUG;
 845                                         }
 846                                 }
 847                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 848                         } else {
 849                                 dm->dmub_callback[notify.type](adev, &notify);
 850                         }
 851                 } while (notify.pending_notification);
 852         }
 853
 854
 855         do {
 856                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 857                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 858                                                         entry.param0, entry.param1);
 859
 860                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 861                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 862                 } else
 863                         break;
 864
 865                 count++;
 866
 867         } while (count <= DMUB_TRACE_MAX_READ);
 868
 869         if (count > DMUB_TRACE_MAX_READ)
 870                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 871 }
 872
 873 static int dm_set_clockgating_state(void *handle,
 874                   enum amd_clockgating_state state)
 875 {
 876         return 0;
 877 }
 878
 879 static int dm_set_powergating_state(void *handle,
 880                   enum amd_powergating_state state)
 881 {
 882         return 0;
 883 }
 884
 885 /* Prototypes of private functions */
 886 static int dm_early_init(void* handle);
 887
 888 /* Allocate memory for FBC compressed data  */
 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 890 {
 891         struct drm_device *dev = connector->dev;
 892         struct amdgpu_device *adev = drm_to_adev(dev);
 893         struct dm_compressor_info *compressor = &adev->dm.compressor;
 894         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 895         struct drm_display_mode *mode;
 896         unsigned long max_size = 0;
 897
 898         if (adev->dm.dc->fbc_compressor == NULL)
 899                 return;
 900
 901         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 902                 return;
 903
 904         if (compressor->bo_ptr)
 905                 return;
 906
 907
 908         list_for_each_entry(mode, &connector->modes, head) {
 909                 if (max_size < mode->htotal * mode->vtotal)
 910                         max_size = mode->htotal * mode->vtotal;
 911         }
 912
 913         if (max_size) {
 914                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 915                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 916                             &compressor->gpu_addr, &compressor->cpu_addr);
 917
 918                 if (r)
 919                         DRM_ERROR("DM: Failed to initialize FBC\n");
 920                 else {
 921                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 922                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 923                 }
 924
 925         }
 926
 927 }
 928
 929 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 930                                           int pipe, bool *enabled,
 931                                           unsigned char *buf, int max_bytes)
 932 {
 933         struct drm_device *dev = dev_get_drvdata(kdev);
 934         struct amdgpu_device *adev = drm_to_adev(dev);
 935         struct drm_connector *connector;
 936         struct drm_connector_list_iter conn_iter;
 937         struct amdgpu_dm_connector *aconnector;
 938         int ret = 0;
 939
 940         *enabled = false;
 941
 942         mutex_lock(&adev->dm.audio_lock);
 943
 944         drm_connector_list_iter_begin(dev, &conn_iter);
 945         drm_for_each_connector_iter(connector, &conn_iter) {
 946                 aconnector = to_amdgpu_dm_connector(connector);
 947                 if (aconnector->audio_inst != port)
 948                         continue;
 949
 950                 *enabled = true;
 951                 ret = drm_eld_size(connector->eld);
 952                 memcpy(buf, connector->eld, min(max_bytes, ret));
 953
 954                 break;
 955         }
 956         drm_connector_list_iter_end(&conn_iter);
 957
 958         mutex_unlock(&adev->dm.audio_lock);
 959
 960         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 961
 962         return ret;
 963 }
 964
 965 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 966         .get_eld = amdgpu_dm_audio_component_get_eld,
 967 };
 968
 969 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 970                                        struct device *hda_kdev, void *data)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_audio_component *acomp = data;
 975
 976         acomp->ops = &amdgpu_dm_audio_component_ops;
 977         acomp->dev = kdev;
 978         adev->dm.audio_component = acomp;
 979
 980         return 0;
 981 }
 982
 983 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 984                                           struct device *hda_kdev, void *data)
 985 {
 986         struct drm_device *dev = dev_get_drvdata(kdev);
 987         struct amdgpu_device *adev = drm_to_adev(dev);
 988         struct drm_audio_component *acomp = data;
 989
 990         acomp->ops = NULL;
 991         acomp->dev = NULL;
 992         adev->dm.audio_component = NULL;
 993 }
 994
 995 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 996         .bind   = amdgpu_dm_audio_component_bind,
 997         .unbind = amdgpu_dm_audio_component_unbind,
 998 };
 999
1000 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1001 {
1002         int i, ret;
1003
1004         if (!amdgpu_audio)
1005                 return 0;
1006
1007         adev->mode_info.audio.enabled = true;
1008
1009         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1010
1011         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1012                 adev->mode_info.audio.pin[i].channels = -1;
1013                 adev->mode_info.audio.pin[i].rate = -1;
1014                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1015                 adev->mode_info.audio.pin[i].status_bits = 0;
1016                 adev->mode_info.audio.pin[i].category_code = 0;
1017                 adev->mode_info.audio.pin[i].connected = false;
1018                 adev->mode_info.audio.pin[i].id =
1019                         adev->dm.dc->res_pool->audios[i]->inst;
1020                 adev->mode_info.audio.pin[i].offset = 0;
1021         }
1022
1023         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1024         if (ret < 0)
1025                 return ret;
1026
1027         adev->dm.audio_registered = true;
1028
1029         return 0;
1030 }
1031
1032 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1033 {
1034         if (!amdgpu_audio)
1035                 return;
1036
1037         if (!adev->mode_info.audio.enabled)
1038                 return;
1039
1040         if (adev->dm.audio_registered) {
1041                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1042                 adev->dm.audio_registered = false;
1043         }
1044
1045         /* TODO: Disable audio? */
1046
1047         adev->mode_info.audio.enabled = false;
1048 }
1049
1050 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1051 {
1052         struct drm_audio_component *acomp = adev->dm.audio_component;
1053
1054         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1055                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1056
1057                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1058                                                  pin, -1);
1059         }
1060 }
1061
1062 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1063 {
1064         const struct dmcub_firmware_header_v1_0 *hdr;
1065         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1066         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1067         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1068         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1069         struct abm *abm = adev->dm.dc->res_pool->abm;
1070         struct dmub_srv_hw_params hw_params;
1071         enum dmub_status status;
1072         const unsigned char *fw_inst_const, *fw_bss_data;
1073         u32 i, fw_inst_const_size, fw_bss_data_size;
1074         bool has_hw_support;
1075
1076         if (!dmub_srv)
1077                 /* DMUB isn't supported on the ASIC. */
1078                 return 0;
1079
1080         if (!fb_info) {
1081                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1082                 return -EINVAL;
1083         }
1084
1085         if (!dmub_fw) {
1086                 /* Firmware required for DMUB support. */
1087                 DRM_ERROR("No firmware provided for DMUB.\n");
1088                 return -EINVAL;
1089         }
1090
1091         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1092         if (status != DMUB_STATUS_OK) {
1093                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1094                 return -EINVAL;
1095         }
1096
1097         if (!has_hw_support) {
1098                 DRM_INFO("DMUB unsupported on ASIC\n");
1099                 return 0;
1100         }
1101
1102         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1103         status = dmub_srv_hw_reset(dmub_srv);
1104         if (status != DMUB_STATUS_OK)
1105                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1106
1107         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1108
1109         fw_inst_const = dmub_fw->data +
1110                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1111                         PSP_HEADER_BYTES;
1112
1113         fw_bss_data = dmub_fw->data +
1114                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1115                       le32_to_cpu(hdr->inst_const_bytes);
1116
1117         /* Copy firmware and bios info into FB memory. */
1118         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1119                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1120
1121         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1122
1123         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1124          * amdgpu_ucode_init_single_fw will load dmub firmware
1125          * fw_inst_const part to cw0; otherwise, the firmware back door load
1126          * will be done by dm_dmub_hw_init
1127          */
1128         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1129                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1130                                 fw_inst_const_size);
1131         }
1132
1133         if (fw_bss_data_size)
1134                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1135                        fw_bss_data, fw_bss_data_size);
1136
1137         /* Copy firmware bios info into FB memory. */
1138         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1139                adev->bios_size);
1140
1141         /* Reset regions that need to be reset. */
1142         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1143         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1144
1145         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1146                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1147
1148         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1149                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1150
1151         /* Initialize hardware. */
1152         memset(&hw_params, 0, sizeof(hw_params));
1153         hw_params.fb_base = adev->gmc.fb_start;
1154         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1155
1156         /* backdoor load firmware and trigger dmub running */
1157         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1158                 hw_params.load_inst_const = true;
1159
1160         if (dmcu)
1161                 hw_params.psp_version = dmcu->psp_version;
1162
1163         for (i = 0; i < fb_info->num_fb; ++i)
1164                 hw_params.fb[i] = &fb_info->fb[i];
1165
1166         switch (adev->ip_versions[DCE_HWIP][0]) {
1167         case IP_VERSION(3, 1, 3):
1168         case IP_VERSION(3, 1, 4):
1169                 hw_params.dpia_supported = true;
1170                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1177         if (status != DMUB_STATUS_OK) {
1178                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1179                 return -EINVAL;
1180         }
1181
1182         /* Wait for firmware load to finish. */
1183         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1184         if (status != DMUB_STATUS_OK)
1185                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1186
1187         /* Init DMCU and ABM if available. */
1188         if (dmcu && abm) {
1189                 dmcu->funcs->dmcu_init(dmcu);
1190                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1191         }
1192
1193         if (!adev->dm.dc->ctx->dmub_srv)
1194                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1195         if (!adev->dm.dc->ctx->dmub_srv) {
1196                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1197                 return -ENOMEM;
1198         }
1199
1200         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1201                  adev->dm.dmcub_fw_version);
1202
1203         return 0;
1204 }
1205
1206 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1207 {
1208         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1209         enum dmub_status status;
1210         bool init;
1211
1212         if (!dmub_srv) {
1213                 /* DMUB isn't supported on the ASIC. */
1214                 return;
1215         }
1216
1217         status = dmub_srv_is_hw_init(dmub_srv, &init);
1218         if (status != DMUB_STATUS_OK)
1219                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1220
1221         if (status == DMUB_STATUS_OK && init) {
1222                 /* Wait for firmware load to finish. */
1223                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1224                 if (status != DMUB_STATUS_OK)
1225                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1226         } else {
1227                 /* Perform the full hardware initialization. */
1228                 dm_dmub_hw_init(adev);
1229         }
1230 }
1231
1232 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1233 {
1234         u64 pt_base;
1235         u32 logical_addr_low;
1236         u32 logical_addr_high;
1237         u32 agp_base, agp_bot, agp_top;
1238         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1239
1240         memset(pa_config, 0, sizeof(*pa_config));
1241
1242         agp_base = 0;
1243         agp_bot = adev->gmc.agp_start >> 24;
1244         agp_top = adev->gmc.agp_end >> 24;
1245
1246         /* AGP aperture is disabled */
1247         if (agp_bot == agp_top) {
1248                 logical_addr_low = adev->gmc.fb_start >> 18;
1249                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1250                         /*
1251                          * Raven2 has a HW issue that it is unable to use the vram which
1252                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1253                          * workaround that increase system aperture high address (add 1)
1254                          * to get rid of the VM fault and hardware hang.
1255                          */
1256                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1257                 else
1258                         logical_addr_high = adev->gmc.fb_end >> 18;
1259         } else {
1260                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1261                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1262                         /*
1263                          * Raven2 has a HW issue that it is unable to use the vram which
1264                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265                          * workaround that increase system aperture high address (add 1)
1266                          * to get rid of the VM fault and hardware hang.
1267                          */
1268                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1269                 else
1270                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1271         }
1272
1273         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1274
1275         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1276         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1277         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1278         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1279         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1280         page_table_base.low_part = lower_32_bits(pt_base);
1281
1282         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1283         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1284
1285         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1286         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1287         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1288
1289         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1290         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1291         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1292
1293         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1294         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1295         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1296
1297         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1298
1299 }
1300
1301 static void force_connector_state(
1302         struct amdgpu_dm_connector *aconnector,
1303         enum drm_connector_force force_state)
1304 {
1305         struct drm_connector *connector = &aconnector->base;
1306
1307         mutex_lock(&connector->dev->mode_config.mutex);
1308         aconnector->base.force = force_state;
1309         mutex_unlock(&connector->dev->mode_config.mutex);
1310
1311         mutex_lock(&aconnector->hpd_lock);
1312         drm_kms_helper_connector_hotplug_event(connector);
1313         mutex_unlock(&aconnector->hpd_lock);
1314 }
1315
1316 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1317 {
1318         struct hpd_rx_irq_offload_work *offload_work;
1319         struct amdgpu_dm_connector *aconnector;
1320         struct dc_link *dc_link;
1321         struct amdgpu_device *adev;
1322         enum dc_connection_type new_connection_type = dc_connection_none;
1323         unsigned long flags;
1324         union test_response test_response;
1325
1326         memset(&test_response, 0, sizeof(test_response));
1327
1328         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1329         aconnector = offload_work->offload_wq->aconnector;
1330
1331         if (!aconnector) {
1332                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1333                 goto skip;
1334         }
1335
1336         adev = drm_to_adev(aconnector->base.dev);
1337         dc_link = aconnector->dc_link;
1338
1339         mutex_lock(&aconnector->hpd_lock);
1340         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1341                 DRM_ERROR("KMS: Failed to detect connector\n");
1342         mutex_unlock(&aconnector->hpd_lock);
1343
1344         if (new_connection_type == dc_connection_none)
1345                 goto skip;
1346
1347         if (amdgpu_in_reset(adev))
1348                 goto skip;
1349
1350         mutex_lock(&adev->dm.dc_lock);
1351         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1352                 dc_link_dp_handle_automated_test(dc_link);
1353
1354                 if (aconnector->timing_changed) {
1355                         /* force connector disconnect and reconnect */
1356                         force_connector_state(aconnector, DRM_FORCE_OFF);
1357                         msleep(100);
1358                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1359                 }
1360
1361                 test_response.bits.ACK = 1;
1362
1363                 core_link_write_dpcd(
1364                 dc_link,
1365                 DP_TEST_RESPONSE,
1366                 &test_response.raw,
1367                 sizeof(test_response));
1368         }
1369         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1370                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1371                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1372                 /* offload_work->data is from handle_hpd_rx_irq->
1373                  * schedule_hpd_rx_offload_work.this is defer handle
1374                  * for hpd short pulse. upon here, link status may be
1375                  * changed, need get latest link status from dpcd
1376                  * registers. if link status is good, skip run link
1377                  * training again.
1378                  */
1379                 union hpd_irq_data irq_data;
1380
1381                 memset(&irq_data, 0, sizeof(irq_data));
1382
1383                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1384                  * request be added to work queue if link lost at end of dc_link_
1385                  * dp_handle_link_loss
1386                  */
1387                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1388                 offload_work->offload_wq->is_handling_link_loss = false;
1389                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1390
1391                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1392                         dc_link_check_link_loss_status(dc_link, &irq_data))
1393                         dc_link_dp_handle_link_loss(dc_link);
1394         }
1395         mutex_unlock(&adev->dm.dc_lock);
1396
1397 skip:
1398         kfree(offload_work);
1399
1400 }
1401
1402 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1403 {
1404         int max_caps = dc->caps.max_links;
1405         int i = 0;
1406         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1407
1408         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1409
1410         if (!hpd_rx_offload_wq)
1411                 return NULL;
1412
1413
1414         for (i = 0; i < max_caps; i++) {
1415                 hpd_rx_offload_wq[i].wq =
1416                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1417
1418                 if (hpd_rx_offload_wq[i].wq == NULL) {
1419                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1420                         goto out_err;
1421                 }
1422
1423                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1424         }
1425
1426         return hpd_rx_offload_wq;
1427
1428 out_err:
1429         for (i = 0; i < max_caps; i++) {
1430                 if (hpd_rx_offload_wq[i].wq)
1431                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1432         }
1433         kfree(hpd_rx_offload_wq);
1434         return NULL;
1435 }
1436
1437 struct amdgpu_stutter_quirk {
1438         u16 chip_vendor;
1439         u16 chip_device;
1440         u16 subsys_vendor;
1441         u16 subsys_device;
1442         u8 revision;
1443 };
1444
1445 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1446         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1447         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1448         { 0, 0, 0, 0, 0 },
1449 };
1450
1451 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1452 {
1453         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1454
1455         while (p && p->chip_device != 0) {
1456                 if (pdev->vendor == p->chip_vendor &&
1457                     pdev->device == p->chip_device &&
1458                     pdev->subsystem_vendor == p->subsys_vendor &&
1459                     pdev->subsystem_device == p->subsys_device &&
1460                     pdev->revision == p->revision) {
1461                         return true;
1462                 }
1463                 ++p;
1464         }
1465         return false;
1466 }
1467
1468 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1469         {
1470                 .matches = {
1471                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1472                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1473                 },
1474         },
1475         {
1476                 .matches = {
1477                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1478                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1479                 },
1480         },
1481         {
1482                 .matches = {
1483                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1484                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1485                 },
1486         },
1487         {
1488                 .matches = {
1489                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1490                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1491                 },
1492         },
1493         {
1494                 .matches = {
1495                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1497                 },
1498         },
1499         {
1500                 .matches = {
1501                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1503                 },
1504         },
1505         {
1506                 .matches = {
1507                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1509                 },
1510         },
1511         {
1512                 .matches = {
1513                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1515                 },
1516         },
1517         {
1518                 .matches = {
1519                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1521                 },
1522         },
1523         {}
1524         /* TODO: refactor this from a fixed table to a dynamic option */
1525 };
1526
1527 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1528 {
1529         const struct dmi_system_id *dmi_id;
1530
1531         dm->aux_hpd_discon_quirk = false;
1532
1533         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1534         if (dmi_id) {
1535                 dm->aux_hpd_discon_quirk = true;
1536                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1537         }
1538 }
1539
1540 static int amdgpu_dm_init(struct amdgpu_device *adev)
1541 {
1542         struct dc_init_data init_data;
1543         struct dc_callback_init init_params;
1544         int r;
1545
1546         adev->dm.ddev = adev_to_drm(adev);
1547         adev->dm.adev = adev;
1548
1549         /* Zero all the fields */
1550         memset(&init_data, 0, sizeof(init_data));
1551         memset(&init_params, 0, sizeof(init_params));
1552
1553         mutex_init(&adev->dm.dpia_aux_lock);
1554         mutex_init(&adev->dm.dc_lock);
1555         mutex_init(&adev->dm.audio_lock);
1556
1557         if(amdgpu_dm_irq_init(adev)) {
1558                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1559                 goto error;
1560         }
1561
1562         init_data.asic_id.chip_family = adev->family;
1563
1564         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1565         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1566         init_data.asic_id.chip_id = adev->pdev->device;
1567
1568         init_data.asic_id.vram_width = adev->gmc.vram_width;
1569         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1570         init_data.asic_id.atombios_base_address =
1571                 adev->mode_info.atom_context->bios;
1572
1573         init_data.driver = adev;
1574
1575         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1576
1577         if (!adev->dm.cgs_device) {
1578                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1579                 goto error;
1580         }
1581
1582         init_data.cgs_device = adev->dm.cgs_device;
1583
1584         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1585
1586         switch (adev->ip_versions[DCE_HWIP][0]) {
1587         case IP_VERSION(2, 1, 0):
1588                 switch (adev->dm.dmcub_fw_version) {
1589                 case 0: /* development */
1590                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1591                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1592                         init_data.flags.disable_dmcu = false;
1593                         break;
1594                 default:
1595                         init_data.flags.disable_dmcu = true;
1596                 }
1597                 break;
1598         case IP_VERSION(2, 0, 3):
1599                 init_data.flags.disable_dmcu = true;
1600                 break;
1601         default:
1602                 break;
1603         }
1604
1605         switch (adev->asic_type) {
1606         case CHIP_CARRIZO:
1607         case CHIP_STONEY:
1608                 init_data.flags.gpu_vm_support = true;
1609                 break;
1610         default:
1611                 switch (adev->ip_versions[DCE_HWIP][0]) {
1612                 case IP_VERSION(1, 0, 0):
1613                 case IP_VERSION(1, 0, 1):
1614                         /* enable S/G on PCO and RV2 */
1615                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1616                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1617                                 init_data.flags.gpu_vm_support = true;
1618                         break;
1619                 case IP_VERSION(2, 1, 0):
1620                 case IP_VERSION(3, 0, 1):
1621                 case IP_VERSION(3, 1, 2):
1622                 case IP_VERSION(3, 1, 3):
1623                 case IP_VERSION(3, 1, 4):
1624                 case IP_VERSION(3, 1, 5):
1625                 case IP_VERSION(3, 1, 6):
1626                         init_data.flags.gpu_vm_support = true;
1627                         break;
1628                 default:
1629                         break;
1630                 }
1631                 break;
1632         }
1633         if (init_data.flags.gpu_vm_support &&
1634             (amdgpu_sg_display == 0))
1635                 init_data.flags.gpu_vm_support = false;
1636
1637         if (init_data.flags.gpu_vm_support)
1638                 adev->mode_info.gpu_vm_support = true;
1639
1640         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1641                 init_data.flags.fbc_support = true;
1642
1643         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1644                 init_data.flags.multi_mon_pp_mclk_switch = true;
1645
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1647                 init_data.flags.disable_fractional_pwm = true;
1648
1649         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1650                 init_data.flags.edp_no_power_sequencing = true;
1651
1652         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1653                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1655                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1656
1657         init_data.flags.seamless_boot_edp_requested = false;
1658
1659         if (check_seamless_boot_capability(adev)) {
1660                 init_data.flags.seamless_boot_edp_requested = true;
1661                 init_data.flags.allow_seamless_boot_optimization = true;
1662                 DRM_INFO("Seamless boot condition check passed\n");
1663         }
1664
1665         init_data.flags.enable_mipi_converter_optimization = true;
1666
1667         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1668         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1669
1670         INIT_LIST_HEAD(&adev->dm.da_list);
1671
1672         retrieve_dmi_info(&adev->dm);
1673
1674         /* Display Core create. */
1675         adev->dm.dc = dc_create(&init_data);
1676
1677         if (adev->dm.dc) {
1678                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1679                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1680         } else {
1681                 DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER,
1682                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1683                 goto error;
1684         }
1685
1686         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1687                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1688                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1689         }
1690
1691         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1692                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1693         if (dm_should_disable_stutter(adev->pdev))
1694                 adev->dm.dc->debug.disable_stutter = true;
1695
1696         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1697                 adev->dm.dc->debug.disable_stutter = true;
1698
1699         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1700                 adev->dm.dc->debug.disable_dsc = true;
1701         }
1702
1703         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1704                 adev->dm.dc->debug.disable_clock_gate = true;
1705
1706         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1707                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1708
1709         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1710
1711         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1712         adev->dm.dc->debug.ignore_cable_id = true;
1713
1714         /* TODO: There is a new drm mst change where the freedom of
1715          * vc_next_start_slot update is revoked/moved into drm, instead of in
1716          * driver. This forces us to make sure to get vc_next_start_slot updated
1717          * in drm function each time without considering if mst_state is active
1718          * or not. Otherwise, next time hotplug will give wrong start_slot
1719          * number. We are implementing a temporary solution to even notify drm
1720          * mst deallocation when link is no longer of MST type when uncommitting
1721          * the stream so we will have more time to work on a proper solution.
1722          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1723          * should notify drm to do a complete "reset" of its states and stop
1724          * calling further drm mst functions when link is no longer of an MST
1725          * type. This could happen when we unplug an MST hubs/displays. When
1726          * uncommit stream comes later after unplug, we should just reset
1727          * hardware states only.
1728          */
1729         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1730
1731         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1732                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1733
1734         r = dm_dmub_hw_init(adev);
1735         if (r) {
1736                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1737                 goto error;
1738         }
1739
1740         dc_hardware_init(adev->dm.dc);
1741
1742         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1743         if (!adev->dm.hpd_rx_offload_wq) {
1744                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1745                 goto error;
1746         }
1747
1748         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1749                 struct dc_phy_addr_space_config pa_config;
1750
1751                 mmhub_read_system_context(adev, &pa_config);
1752
1753                 // Call the DC init_memory func
1754                 dc_setup_system_context(adev->dm.dc, &pa_config);
1755         }
1756
1757         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1758         if (!adev->dm.freesync_module) {
1759                 DRM_ERROR(
1760                 "amdgpu: failed to initialize freesync_module.\n");
1761         } else
1762                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1763                                 adev->dm.freesync_module);
1764
1765         amdgpu_dm_init_color_mod();
1766
1767         if (adev->dm.dc->caps.max_links > 0) {
1768                 adev->dm.vblank_control_workqueue =
1769                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1770                 if (!adev->dm.vblank_control_workqueue)
1771                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1772         }
1773
1774         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1775                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1776
1777                 if (!adev->dm.hdcp_workqueue)
1778                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1779                 else
1780                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1781
1782                 dc_init_callbacks(adev->dm.dc, &init_params);
1783         }
1784         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1785                 init_completion(&adev->dm.dmub_aux_transfer_done);
1786                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1787                 if (!adev->dm.dmub_notify) {
1788                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1789                         goto error;
1790                 }
1791
1792                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1793                 if (!adev->dm.delayed_hpd_wq) {
1794                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1795                         goto error;
1796                 }
1797
1798                 amdgpu_dm_outbox_init(adev);
1799                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1800                         dmub_aux_setconfig_callback, false)) {
1801                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1802                         goto error;
1803                 }
1804                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1805                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1806                         goto error;
1807                 }
1808                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1809                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1810                         goto error;
1811                 }
1812         }
1813
1814         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1815          * It is expected that DMUB will resend any pending notifications at this point, for
1816          * example HPD from DPIA.
1817          */
1818         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1819                 dc_enable_dmub_outbox(adev->dm.dc);
1820
1821         if (amdgpu_dm_initialize_drm_device(adev)) {
1822                 DRM_ERROR(
1823                 "amdgpu: failed to initialize sw for display support.\n");
1824                 goto error;
1825         }
1826
1827         /* create fake encoders for MST */
1828         dm_dp_create_fake_mst_encoders(adev);
1829
1830         /* TODO: Add_display_info? */
1831
1832         /* TODO use dynamic cursor width */
1833         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1834         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1835
1836         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1837                 DRM_ERROR(
1838                 "amdgpu: failed to initialize sw for display support.\n");
1839                 goto error;
1840         }
1841
1842 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1843         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1844         if (!adev->dm.secure_display_ctxs)
1845                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1846 #endif
1847
1848         DRM_DEBUG_DRIVER("KMS initialized.\n");
1849
1850         return 0;
1851 error:
1852         amdgpu_dm_fini(adev);
1853
1854         return -EINVAL;
1855 }
1856
1857 static int amdgpu_dm_early_fini(void *handle)
1858 {
1859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1860
1861         amdgpu_dm_audio_fini(adev);
1862
1863         return 0;
1864 }
1865
1866 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1867 {
1868         int i;
1869
1870         if (adev->dm.vblank_control_workqueue) {
1871                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1872                 adev->dm.vblank_control_workqueue = NULL;
1873         }
1874
1875         amdgpu_dm_destroy_drm_device(&adev->dm);
1876
1877 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1878         if (adev->dm.secure_display_ctxs) {
1879                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1880                         if (adev->dm.secure_display_ctxs[i].crtc) {
1881                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1882                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1883                         }
1884                 }
1885                 kfree(adev->dm.secure_display_ctxs);
1886                 adev->dm.secure_display_ctxs = NULL;
1887         }
1888 #endif
1889         if (adev->dm.hdcp_workqueue) {
1890                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1891                 adev->dm.hdcp_workqueue = NULL;
1892         }
1893
1894         if (adev->dm.dc)
1895                 dc_deinit_callbacks(adev->dm.dc);
1896
1897         if (adev->dm.dc)
1898                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1899
1900         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1901                 kfree(adev->dm.dmub_notify);
1902                 adev->dm.dmub_notify = NULL;
1903                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1904                 adev->dm.delayed_hpd_wq = NULL;
1905         }
1906
1907         if (adev->dm.dmub_bo)
1908                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1909                                       &adev->dm.dmub_bo_gpu_addr,
1910                                       &adev->dm.dmub_bo_cpu_addr);
1911
1912         if (adev->dm.hpd_rx_offload_wq) {
1913                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1914                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1915                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1916                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1917                         }
1918                 }
1919
1920                 kfree(adev->dm.hpd_rx_offload_wq);
1921                 adev->dm.hpd_rx_offload_wq = NULL;
1922         }
1923
1924         /* DC Destroy TODO: Replace destroy DAL */
1925         if (adev->dm.dc)
1926                 dc_destroy(&adev->dm.dc);
1927         /*
1928          * TODO: pageflip, vlank interrupt
1929          *
1930          * amdgpu_dm_irq_fini(adev);
1931          */
1932
1933         if (adev->dm.cgs_device) {
1934                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1935                 adev->dm.cgs_device = NULL;
1936         }
1937         if (adev->dm.freesync_module) {
1938                 mod_freesync_destroy(adev->dm.freesync_module);
1939                 adev->dm.freesync_module = NULL;
1940         }
1941
1942         mutex_destroy(&adev->dm.audio_lock);
1943         mutex_destroy(&adev->dm.dc_lock);
1944         mutex_destroy(&adev->dm.dpia_aux_lock);
1945
1946         return;
1947 }
1948
1949 static int load_dmcu_fw(struct amdgpu_device *adev)
1950 {
1951         const char *fw_name_dmcu = NULL;
1952         int r;
1953         const struct dmcu_firmware_header_v1_0 *hdr;
1954
1955         switch(adev->asic_type) {
1956 #if defined(CONFIG_DRM_AMD_DC_SI)
1957         case CHIP_TAHITI:
1958         case CHIP_PITCAIRN:
1959         case CHIP_VERDE:
1960         case CHIP_OLAND:
1961 #endif
1962         case CHIP_BONAIRE:
1963         case CHIP_HAWAII:
1964         case CHIP_KAVERI:
1965         case CHIP_KABINI:
1966         case CHIP_MULLINS:
1967         case CHIP_TONGA:
1968         case CHIP_FIJI:
1969         case CHIP_CARRIZO:
1970         case CHIP_STONEY:
1971         case CHIP_POLARIS11:
1972         case CHIP_POLARIS10:
1973         case CHIP_POLARIS12:
1974         case CHIP_VEGAM:
1975         case CHIP_VEGA10:
1976         case CHIP_VEGA12:
1977         case CHIP_VEGA20:
1978                 return 0;
1979         case CHIP_NAVI12:
1980                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1981                 break;
1982         case CHIP_RAVEN:
1983                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1984                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1985                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1986                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1987                 else
1988                         return 0;
1989                 break;
1990         default:
1991                 switch (adev->ip_versions[DCE_HWIP][0]) {
1992                 case IP_VERSION(2, 0, 2):
1993                 case IP_VERSION(2, 0, 3):
1994                 case IP_VERSION(2, 0, 0):
1995                 case IP_VERSION(2, 1, 0):
1996                 case IP_VERSION(3, 0, 0):
1997                 case IP_VERSION(3, 0, 2):
1998                 case IP_VERSION(3, 0, 3):
1999                 case IP_VERSION(3, 0, 1):
2000                 case IP_VERSION(3, 1, 2):
2001                 case IP_VERSION(3, 1, 3):
2002                 case IP_VERSION(3, 1, 4):
2003                 case IP_VERSION(3, 1, 5):
2004                 case IP_VERSION(3, 1, 6):
2005                 case IP_VERSION(3, 2, 0):
2006                 case IP_VERSION(3, 2, 1):
2007                         return 0;
2008                 default:
2009                         break;
2010                 }
2011                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2012                 return -EINVAL;
2013         }
2014
2015         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2016                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2017                 return 0;
2018         }
2019
2020         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2021         if (r == -ENODEV) {
2022                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2023                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2024                 adev->dm.fw_dmcu = NULL;
2025                 return 0;
2026         }
2027         if (r) {
2028                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2029                         fw_name_dmcu);
2030                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2031                 return r;
2032         }
2033
2034         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2035         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2037         adev->firmware.fw_size +=
2038                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2039
2040         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2041         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2042         adev->firmware.fw_size +=
2043                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2044
2045         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2046
2047         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2048
2049         return 0;
2050 }
2051
2052 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2053 {
2054         struct amdgpu_device *adev = ctx;
2055
2056         return dm_read_reg(adev->dm.dc->ctx, address);
2057 }
2058
2059 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2060                                      uint32_t value)
2061 {
2062         struct amdgpu_device *adev = ctx;
2063
2064         return dm_write_reg(adev->dm.dc->ctx, address, value);
2065 }
2066
2067 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2068 {
2069         struct dmub_srv_create_params create_params;
2070         struct dmub_srv_region_params region_params;
2071         struct dmub_srv_region_info region_info;
2072         struct dmub_srv_fb_params fb_params;
2073         struct dmub_srv_fb_info *fb_info;
2074         struct dmub_srv *dmub_srv;
2075         const struct dmcub_firmware_header_v1_0 *hdr;
2076         enum dmub_asic dmub_asic;
2077         enum dmub_status status;
2078         int r;
2079
2080         switch (adev->ip_versions[DCE_HWIP][0]) {
2081         case IP_VERSION(2, 1, 0):
2082                 dmub_asic = DMUB_ASIC_DCN21;
2083                 break;
2084         case IP_VERSION(3, 0, 0):
2085                 dmub_asic = DMUB_ASIC_DCN30;
2086                 break;
2087         case IP_VERSION(3, 0, 1):
2088                 dmub_asic = DMUB_ASIC_DCN301;
2089                 break;
2090         case IP_VERSION(3, 0, 2):
2091                 dmub_asic = DMUB_ASIC_DCN302;
2092                 break;
2093         case IP_VERSION(3, 0, 3):
2094                 dmub_asic = DMUB_ASIC_DCN303;
2095                 break;
2096         case IP_VERSION(3, 1, 2):
2097         case IP_VERSION(3, 1, 3):
2098                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2099                 break;
2100         case IP_VERSION(3, 1, 4):
2101                 dmub_asic = DMUB_ASIC_DCN314;
2102                 break;
2103         case IP_VERSION(3, 1, 5):
2104                 dmub_asic = DMUB_ASIC_DCN315;
2105                 break;
2106         case IP_VERSION(3, 1, 6):
2107                 dmub_asic = DMUB_ASIC_DCN316;
2108                 break;
2109         case IP_VERSION(3, 2, 0):
2110                 dmub_asic = DMUB_ASIC_DCN32;
2111                 break;
2112         case IP_VERSION(3, 2, 1):
2113                 dmub_asic = DMUB_ASIC_DCN321;
2114                 break;
2115         default:
2116                 /* ASIC doesn't support DMUB. */
2117                 return 0;
2118         }
2119
2120         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2121         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2122
2123         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2124                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2125                         AMDGPU_UCODE_ID_DMCUB;
2126                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2127                         adev->dm.dmub_fw;
2128                 adev->firmware.fw_size +=
2129                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2130
2131                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2132                          adev->dm.dmcub_fw_version);
2133         }
2134
2135
2136         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2137         dmub_srv = adev->dm.dmub_srv;
2138
2139         if (!dmub_srv) {
2140                 DRM_ERROR("Failed to allocate DMUB service!\n");
2141                 return -ENOMEM;
2142         }
2143
2144         memset(&create_params, 0, sizeof(create_params));
2145         create_params.user_ctx = adev;
2146         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2147         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2148         create_params.asic = dmub_asic;
2149
2150         /* Create the DMUB service. */
2151         status = dmub_srv_create(dmub_srv, &create_params);
2152         if (status != DMUB_STATUS_OK) {
2153                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2154                 return -EINVAL;
2155         }
2156
2157         /* Calculate the size of all the regions for the DMUB service. */
2158         memset(&region_params, 0, sizeof(region_params));
2159
2160         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2161                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2162         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2163         region_params.vbios_size = adev->bios_size;
2164         region_params.fw_bss_data = region_params.bss_data_size ?
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2168         region_params.fw_inst_const =
2169                 adev->dm.dmub_fw->data +
2170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2171                 PSP_HEADER_BYTES;
2172
2173         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2174                                            &region_info);
2175
2176         if (status != DMUB_STATUS_OK) {
2177                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2178                 return -EINVAL;
2179         }
2180
2181         /*
2182          * Allocate a framebuffer based on the total size of all the regions.
2183          * TODO: Move this into GART.
2184          */
2185         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2186                                     AMDGPU_GEM_DOMAIN_VRAM |
2187                                     AMDGPU_GEM_DOMAIN_GTT,
2188                                     &adev->dm.dmub_bo,
2189                                     &adev->dm.dmub_bo_gpu_addr,
2190                                     &adev->dm.dmub_bo_cpu_addr);
2191         if (r)
2192                 return r;
2193
2194         /* Rebase the regions on the framebuffer address. */
2195         memset(&fb_params, 0, sizeof(fb_params));
2196         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2197         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2198         fb_params.region_info = &region_info;
2199
2200         adev->dm.dmub_fb_info =
2201                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2202         fb_info = adev->dm.dmub_fb_info;
2203
2204         if (!fb_info) {
2205                 DRM_ERROR(
2206                         "Failed to allocate framebuffer info for DMUB service!\n");
2207                 return -ENOMEM;
2208         }
2209
2210         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2211         if (status != DMUB_STATUS_OK) {
2212                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2213                 return -EINVAL;
2214         }
2215
2216         return 0;
2217 }
2218
2219 static int dm_sw_init(void *handle)
2220 {
2221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2222         int r;
2223
2224         r = dm_dmub_sw_init(adev);
2225         if (r)
2226                 return r;
2227
2228         return load_dmcu_fw(adev);
2229 }
2230
2231 static int dm_sw_fini(void *handle)
2232 {
2233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2234
2235         kfree(adev->dm.dmub_fb_info);
2236         adev->dm.dmub_fb_info = NULL;
2237
2238         if (adev->dm.dmub_srv) {
2239                 dmub_srv_destroy(adev->dm.dmub_srv);
2240                 adev->dm.dmub_srv = NULL;
2241         }
2242
2243         amdgpu_ucode_release(&adev->dm.dmub_fw);
2244         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2245
2246         return 0;
2247 }
2248
2249 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2250 {
2251         struct amdgpu_dm_connector *aconnector;
2252         struct drm_connector *connector;
2253         struct drm_connector_list_iter iter;
2254         int ret = 0;
2255
2256         drm_connector_list_iter_begin(dev, &iter);
2257         drm_for_each_connector_iter(connector, &iter) {
2258                 aconnector = to_amdgpu_dm_connector(connector);
2259                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2260                     aconnector->mst_mgr.aux) {
2261                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2262                                          aconnector,
2263                                          aconnector->base.base.id);
2264
2265                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2266                         if (ret < 0) {
2267                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2268                                 aconnector->dc_link->type =
2269                                         dc_connection_single;
2270                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2271                                                                      aconnector->dc_link);
2272                                 break;
2273                         }
2274                 }
2275         }
2276         drm_connector_list_iter_end(&iter);
2277
2278         return ret;
2279 }
2280
2281 static int dm_late_init(void *handle)
2282 {
2283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2284
2285         struct dmcu_iram_parameters params;
2286         unsigned int linear_lut[16];
2287         int i;
2288         struct dmcu *dmcu = NULL;
2289
2290         dmcu = adev->dm.dc->res_pool->dmcu;
2291
2292         for (i = 0; i < 16; i++)
2293                 linear_lut[i] = 0xFFFF * i / 15;
2294
2295         params.set = 0;
2296         params.backlight_ramping_override = false;
2297         params.backlight_ramping_start = 0xCCCC;
2298         params.backlight_ramping_reduction = 0xCCCCCCCC;
2299         params.backlight_lut_array_size = 16;
2300         params.backlight_lut_array = linear_lut;
2301
2302         /* Min backlight level after ABM reduction,  Don't allow below 1%
2303          * 0xFFFF x 0.01 = 0x28F
2304          */
2305         params.min_abm_backlight = 0x28F;
2306         /* In the case where abm is implemented on dmcub,
2307          * dmcu object will be null.
2308          * ABM 2.4 and up are implemented on dmcub.
2309          */
2310         if (dmcu) {
2311                 if (!dmcu_load_iram(dmcu, params))
2312                         return -EINVAL;
2313         } else if (adev->dm.dc->ctx->dmub_srv) {
2314                 struct dc_link *edp_links[MAX_NUM_EDP];
2315                 int edp_num;
2316
2317                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2318                 for (i = 0; i < edp_num; i++) {
2319                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2320                                 return -EINVAL;
2321                 }
2322         }
2323
2324         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2325 }
2326
2327 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2328 {
2329         struct amdgpu_dm_connector *aconnector;
2330         struct drm_connector *connector;
2331         struct drm_connector_list_iter iter;
2332         struct drm_dp_mst_topology_mgr *mgr;
2333         int ret;
2334         bool need_hotplug = false;
2335
2336         drm_connector_list_iter_begin(dev, &iter);
2337         drm_for_each_connector_iter(connector, &iter) {
2338                 aconnector = to_amdgpu_dm_connector(connector);
2339                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2340                     aconnector->mst_root)
2341                         continue;
2342
2343                 mgr = &aconnector->mst_mgr;
2344
2345                 if (suspend) {
2346                         drm_dp_mst_topology_mgr_suspend(mgr);
2347                 } else {
2348                         /* if extended timeout is supported in hardware,
2349                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2350                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2351                          */
2352                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2353                         if (!dp_is_lttpr_present(aconnector->dc_link))
2354                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2355
2356                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2357                         if (ret < 0) {
2358                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2359                                         aconnector->dc_link);
2360                                 need_hotplug = true;
2361                         }
2362                 }
2363         }
2364         drm_connector_list_iter_end(&iter);
2365
2366         if (need_hotplug)
2367                 drm_kms_helper_hotplug_event(dev);
2368 }
2369
2370 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2371 {
2372         int ret = 0;
2373
2374         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2375          * on window driver dc implementation.
2376          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2377          * should be passed to smu during boot up and resume from s3.
2378          * boot up: dc calculate dcn watermark clock settings within dc_create,
2379          * dcn20_resource_construct
2380          * then call pplib functions below to pass the settings to smu:
2381          * smu_set_watermarks_for_clock_ranges
2382          * smu_set_watermarks_table
2383          * navi10_set_watermarks_table
2384          * smu_write_watermarks_table
2385          *
2386          * For Renoir, clock settings of dcn watermark are also fixed values.
2387          * dc has implemented different flow for window driver:
2388          * dc_hardware_init / dc_set_power_state
2389          * dcn10_init_hw
2390          * notify_wm_ranges
2391          * set_wm_ranges
2392          * -- Linux
2393          * smu_set_watermarks_for_clock_ranges
2394          * renoir_set_watermarks_table
2395          * smu_write_watermarks_table
2396          *
2397          * For Linux,
2398          * dc_hardware_init -> amdgpu_dm_init
2399          * dc_set_power_state --> dm_resume
2400          *
2401          * therefore, this function apply to navi10/12/14 but not Renoir
2402          * *
2403          */
2404         switch (adev->ip_versions[DCE_HWIP][0]) {
2405         case IP_VERSION(2, 0, 2):
2406         case IP_VERSION(2, 0, 0):
2407                 break;
2408         default:
2409                 return 0;
2410         }
2411
2412         ret = amdgpu_dpm_write_watermarks_table(adev);
2413         if (ret) {
2414                 DRM_ERROR("Failed to update WMTABLE!\n");
2415                 return ret;
2416         }
2417
2418         return 0;
2419 }
2420
2421 /**
2422  * dm_hw_init() - Initialize DC device
2423  * @handle: The base driver device containing the amdgpu_dm device.
2424  *
2425  * Initialize the &struct amdgpu_display_manager device. This involves calling
2426  * the initializers of each DM component, then populating the struct with them.
2427  *
2428  * Although the function implies hardware initialization, both hardware and
2429  * software are initialized here. Splitting them out to their relevant init
2430  * hooks is a future TODO item.
2431  *
2432  * Some notable things that are initialized here:
2433  *
2434  * - Display Core, both software and hardware
2435  * - DC modules that we need (freesync and color management)
2436  * - DRM software states
2437  * - Interrupt sources and handlers
2438  * - Vblank support
2439  * - Debug FS entries, if enabled
2440  */
2441 static int dm_hw_init(void *handle)
2442 {
2443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2444         /* Create DAL display manager */
2445         amdgpu_dm_init(adev);
2446         amdgpu_dm_hpd_init(adev);
2447
2448         return 0;
2449 }
2450
2451 /**
2452  * dm_hw_fini() - Teardown DC device
2453  * @handle: The base driver device containing the amdgpu_dm device.
2454  *
2455  * Teardown components within &struct amdgpu_display_manager that require
2456  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2457  * were loaded. Also flush IRQ workqueues and disable them.
2458  */
2459 static int dm_hw_fini(void *handle)
2460 {
2461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2462
2463         amdgpu_dm_hpd_fini(adev);
2464
2465         amdgpu_dm_irq_fini(adev);
2466         amdgpu_dm_fini(adev);
2467         return 0;
2468 }
2469
2470
2471 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2472                                  struct dc_state *state, bool enable)
2473 {
2474         enum dc_irq_source irq_source;
2475         struct amdgpu_crtc *acrtc;
2476         int rc = -EBUSY;
2477         int i = 0;
2478
2479         for (i = 0; i < state->stream_count; i++) {
2480                 acrtc = get_crtc_by_otg_inst(
2481                                 adev, state->stream_status[i].primary_otg_inst);
2482
2483                 if (acrtc && state->stream_status[i].plane_count != 0) {
2484                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2485                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2486                         if (rc)
2487                                 DRM_WARN("Failed to %s pflip interrupts\n",
2488                                          enable ? "enable" : "disable");
2489
2490                         if (enable) {
2491                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2492                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2493                         } else
2494                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2495
2496                         if (rc)
2497                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2498
2499                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2500                         /* During gpu-reset we disable and then enable vblank irq, so
2501                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2502                          */
2503                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2504                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2505                 }
2506         }
2507
2508 }
2509
2510 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2511 {
2512         struct dc_state *context = NULL;
2513         enum dc_status res = DC_ERROR_UNEXPECTED;
2514         int i;
2515         struct dc_stream_state *del_streams[MAX_PIPES];
2516         int del_streams_count = 0;
2517
2518         memset(del_streams, 0, sizeof(del_streams));
2519
2520         context = dc_create_state(dc);
2521         if (context == NULL)
2522                 goto context_alloc_fail;
2523
2524         dc_resource_state_copy_construct_current(dc, context);
2525
2526         /* First remove from context all streams */
2527         for (i = 0; i < context->stream_count; i++) {
2528                 struct dc_stream_state *stream = context->streams[i];
2529
2530                 del_streams[del_streams_count++] = stream;
2531         }
2532
2533         /* Remove all planes for removed streams and then remove the streams */
2534         for (i = 0; i < del_streams_count; i++) {
2535                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2536                         res = DC_FAIL_DETACH_SURFACES;
2537                         goto fail;
2538                 }
2539
2540                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2541                 if (res != DC_OK)
2542                         goto fail;
2543         }
2544
2545         res = dc_commit_streams(dc, context->streams, context->stream_count);
2546
2547 fail:
2548         dc_release_state(context);
2549
2550 context_alloc_fail:
2551         return res;
2552 }
2553
2554 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2555 {
2556         int i;
2557
2558         if (dm->hpd_rx_offload_wq) {
2559                 for (i = 0; i < dm->dc->caps.max_links; i++)
2560                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2561         }
2562 }
2563
2564 static int dm_suspend(void *handle)
2565 {
2566         struct amdgpu_device *adev = handle;
2567         struct amdgpu_display_manager *dm = &adev->dm;
2568         int ret = 0;
2569
2570         if (amdgpu_in_reset(adev)) {
2571                 mutex_lock(&dm->dc_lock);
2572
2573                 dc_allow_idle_optimizations(adev->dm.dc, false);
2574
2575                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2576
2577                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2578
2579                 amdgpu_dm_commit_zero_streams(dm->dc);
2580
2581                 amdgpu_dm_irq_suspend(adev);
2582
2583                 hpd_rx_irq_work_suspend(dm);
2584
2585                 return ret;
2586         }
2587
2588         WARN_ON(adev->dm.cached_state);
2589         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2590
2591         s3_handle_mst(adev_to_drm(adev), true);
2592
2593         amdgpu_dm_irq_suspend(adev);
2594
2595         hpd_rx_irq_work_suspend(dm);
2596
2597         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2598
2599         return 0;
2600 }
2601
2602 struct amdgpu_dm_connector *
2603 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2604                                              struct drm_crtc *crtc)
2605 {
2606         u32 i;
2607         struct drm_connector_state *new_con_state;
2608         struct drm_connector *connector;
2609         struct drm_crtc *crtc_from_state;
2610
2611         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2612                 crtc_from_state = new_con_state->crtc;
2613
2614                 if (crtc_from_state == crtc)
2615                         return to_amdgpu_dm_connector(connector);
2616         }
2617
2618         return NULL;
2619 }
2620
2621 static void emulated_link_detect(struct dc_link *link)
2622 {
2623         struct dc_sink_init_data sink_init_data = { 0 };
2624         struct display_sink_capability sink_caps = { 0 };
2625         enum dc_edid_status edid_status;
2626         struct dc_context *dc_ctx = link->ctx;
2627         struct dc_sink *sink = NULL;
2628         struct dc_sink *prev_sink = NULL;
2629
2630         link->type = dc_connection_none;
2631         prev_sink = link->local_sink;
2632
2633         if (prev_sink)
2634                 dc_sink_release(prev_sink);
2635
2636         switch (link->connector_signal) {
2637         case SIGNAL_TYPE_HDMI_TYPE_A: {
2638                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2639                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2640                 break;
2641         }
2642
2643         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2644                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2645                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2646                 break;
2647         }
2648
2649         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2650                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2651                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2652                 break;
2653         }
2654
2655         case SIGNAL_TYPE_LVDS: {
2656                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2657                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2658                 break;
2659         }
2660
2661         case SIGNAL_TYPE_EDP: {
2662                 sink_caps.transaction_type =
2663                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2664                 sink_caps.signal = SIGNAL_TYPE_EDP;
2665                 break;
2666         }
2667
2668         case SIGNAL_TYPE_DISPLAY_PORT: {
2669                 sink_caps.transaction_type =
2670                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2671                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2672                 break;
2673         }
2674
2675         default:
2676                 DC_ERROR("Invalid connector type! signal:%d\n",
2677                         link->connector_signal);
2678                 return;
2679         }
2680
2681         sink_init_data.link = link;
2682         sink_init_data.sink_signal = sink_caps.signal;
2683
2684         sink = dc_sink_create(&sink_init_data);
2685         if (!sink) {
2686                 DC_ERROR("Failed to create sink!\n");
2687                 return;
2688         }
2689
2690         /* dc_sink_create returns a new reference */
2691         link->local_sink = sink;
2692
2693         edid_status = dm_helpers_read_local_edid(
2694                         link->ctx,
2695                         link,
2696                         sink);
2697
2698         if (edid_status != EDID_OK)
2699                 DC_ERROR("Failed to read EDID");
2700
2701 }
2702
2703 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2704                                      struct amdgpu_display_manager *dm)
2705 {
2706         struct {
2707                 struct dc_surface_update surface_updates[MAX_SURFACES];
2708                 struct dc_plane_info plane_infos[MAX_SURFACES];
2709                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2710                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2711                 struct dc_stream_update stream_update;
2712         } * bundle;
2713         int k, m;
2714
2715         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2716
2717         if (!bundle) {
2718                 dm_error("Failed to allocate update bundle\n");
2719                 goto cleanup;
2720         }
2721
2722         for (k = 0; k < dc_state->stream_count; k++) {
2723                 bundle->stream_update.stream = dc_state->streams[k];
2724
2725                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2726                         bundle->surface_updates[m].surface =
2727                                 dc_state->stream_status->plane_states[m];
2728                         bundle->surface_updates[m].surface->force_full_update =
2729                                 true;
2730                 }
2731
2732                 update_planes_and_stream_adapter(dm->dc,
2733                                          UPDATE_TYPE_FULL,
2734                                          dc_state->stream_status->plane_count,
2735                                          dc_state->streams[k],
2736                                          &bundle->stream_update,
2737                                          bundle->surface_updates);
2738         }
2739
2740 cleanup:
2741         kfree(bundle);
2742
2743         return;
2744 }
2745
2746 static int dm_resume(void *handle)
2747 {
2748         struct amdgpu_device *adev = handle;
2749         struct drm_device *ddev = adev_to_drm(adev);
2750         struct amdgpu_display_manager *dm = &adev->dm;
2751         struct amdgpu_dm_connector *aconnector;
2752         struct drm_connector *connector;
2753         struct drm_connector_list_iter iter;
2754         struct drm_crtc *crtc;
2755         struct drm_crtc_state *new_crtc_state;
2756         struct dm_crtc_state *dm_new_crtc_state;
2757         struct drm_plane *plane;
2758         struct drm_plane_state *new_plane_state;
2759         struct dm_plane_state *dm_new_plane_state;
2760         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2761         enum dc_connection_type new_connection_type = dc_connection_none;
2762         struct dc_state *dc_state;
2763         int i, r, j;
2764
2765         if (amdgpu_in_reset(adev)) {
2766                 dc_state = dm->cached_dc_state;
2767
2768                 /*
2769                  * The dc->current_state is backed up into dm->cached_dc_state
2770                  * before we commit 0 streams.
2771                  *
2772                  * DC will clear link encoder assignments on the real state
2773                  * but the changes won't propagate over to the copy we made
2774                  * before the 0 streams commit.
2775                  *
2776                  * DC expects that link encoder assignments are *not* valid
2777                  * when committing a state, so as a workaround we can copy
2778                  * off of the current state.
2779                  *
2780                  * We lose the previous assignments, but we had already
2781                  * commit 0 streams anyway.
2782                  */
2783                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2784
2785                 r = dm_dmub_hw_init(adev);
2786                 if (r)
2787                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2788
2789                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2790                 dc_resume(dm->dc);
2791
2792                 amdgpu_dm_irq_resume_early(adev);
2793
2794                 for (i = 0; i < dc_state->stream_count; i++) {
2795                         dc_state->streams[i]->mode_changed = true;
2796                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2797                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2798                                         = 0xffffffff;
2799                         }
2800                 }
2801
2802                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2803                         amdgpu_dm_outbox_init(adev);
2804                         dc_enable_dmub_outbox(adev->dm.dc);
2805                 }
2806
2807                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2808
2809                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2810
2811                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2812
2813                 dc_release_state(dm->cached_dc_state);
2814                 dm->cached_dc_state = NULL;
2815
2816                 amdgpu_dm_irq_resume_late(adev);
2817
2818                 mutex_unlock(&dm->dc_lock);
2819
2820                 return 0;
2821         }
2822         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2823         dc_release_state(dm_state->context);
2824         dm_state->context = dc_create_state(dm->dc);
2825         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2826         dc_resource_state_construct(dm->dc, dm_state->context);
2827
2828         /* Before powering on DC we need to re-initialize DMUB. */
2829         dm_dmub_hw_resume(adev);
2830
2831         /* Re-enable outbox interrupts for DPIA. */
2832         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2833                 amdgpu_dm_outbox_init(adev);
2834                 dc_enable_dmub_outbox(adev->dm.dc);
2835         }
2836
2837         /* power on hardware */
2838         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2839
2840         /* program HPD filter */
2841         dc_resume(dm->dc);
2842
2843         /*
2844          * early enable HPD Rx IRQ, should be done before set mode as short
2845          * pulse interrupts are used for MST
2846          */
2847         amdgpu_dm_irq_resume_early(adev);
2848
2849         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2850         s3_handle_mst(ddev, false);
2851
2852         /* Do detection*/
2853         drm_connector_list_iter_begin(ddev, &iter);
2854         drm_for_each_connector_iter(connector, &iter) {
2855                 aconnector = to_amdgpu_dm_connector(connector);
2856
2857                 if (!aconnector->dc_link)
2858                         continue;
2859
2860                 /*
2861                  * this is the case when traversing through already created
2862                  * MST connectors, should be skipped
2863                  */
2864                 if (aconnector && aconnector->mst_root)
2865                         continue;
2866
2867                 mutex_lock(&aconnector->hpd_lock);
2868                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2869                         DRM_ERROR("KMS: Failed to detect connector\n");
2870
2871                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2872                         emulated_link_detect(aconnector->dc_link);
2873                 } else {
2874                         mutex_lock(&dm->dc_lock);
2875                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2876                         mutex_unlock(&dm->dc_lock);
2877                 }
2878
2879                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2880                         aconnector->fake_enable = false;
2881
2882                 if (aconnector->dc_sink)
2883                         dc_sink_release(aconnector->dc_sink);
2884                 aconnector->dc_sink = NULL;
2885                 amdgpu_dm_update_connector_after_detect(aconnector);
2886                 mutex_unlock(&aconnector->hpd_lock);
2887         }
2888         drm_connector_list_iter_end(&iter);
2889
2890         /* Force mode set in atomic commit */
2891         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2892                 new_crtc_state->active_changed = true;
2893
2894         /*
2895          * atomic_check is expected to create the dc states. We need to release
2896          * them here, since they were duplicated as part of the suspend
2897          * procedure.
2898          */
2899         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2900                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2901                 if (dm_new_crtc_state->stream) {
2902                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2903                         dc_stream_release(dm_new_crtc_state->stream);
2904                         dm_new_crtc_state->stream = NULL;
2905                 }
2906         }
2907
2908         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2909                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2910                 if (dm_new_plane_state->dc_state) {
2911                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2912                         dc_plane_state_release(dm_new_plane_state->dc_state);
2913                         dm_new_plane_state->dc_state = NULL;
2914                 }
2915         }
2916
2917         drm_atomic_helper_resume(ddev, dm->cached_state);
2918
2919         dm->cached_state = NULL;
2920
2921         amdgpu_dm_irq_resume_late(adev);
2922
2923         amdgpu_dm_smu_write_watermarks_table(adev);
2924
2925         return 0;
2926 }
2927
2928 /**
2929  * DOC: DM Lifecycle
2930  *
2931  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2932  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2933  * the base driver's device list to be initialized and torn down accordingly.
2934  *
2935  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2936  */
2937
2938 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2939         .name = "dm",
2940         .early_init = dm_early_init,
2941         .late_init = dm_late_init,
2942         .sw_init = dm_sw_init,
2943         .sw_fini = dm_sw_fini,
2944         .early_fini = amdgpu_dm_early_fini,
2945         .hw_init = dm_hw_init,
2946         .hw_fini = dm_hw_fini,
2947         .suspend = dm_suspend,
2948         .resume = dm_resume,
2949         .is_idle = dm_is_idle,
2950         .wait_for_idle = dm_wait_for_idle,
2951         .check_soft_reset = dm_check_soft_reset,
2952         .soft_reset = dm_soft_reset,
2953         .set_clockgating_state = dm_set_clockgating_state,
2954         .set_powergating_state = dm_set_powergating_state,
2955 };
2956
2957 const struct amdgpu_ip_block_version dm_ip_block =
2958 {
2959         .type = AMD_IP_BLOCK_TYPE_DCE,
2960         .major = 1,
2961         .minor = 0,
2962         .rev = 0,
2963         .funcs = &amdgpu_dm_funcs,
2964 };
2965
2966
2967 /**
2968  * DOC: atomic
2969  *
2970  * *WIP*
2971  */
2972
2973 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2974         .fb_create = amdgpu_display_user_framebuffer_create,
2975         .get_format_info = amdgpu_dm_plane_get_format_info,
2976         .atomic_check = amdgpu_dm_atomic_check,
2977         .atomic_commit = drm_atomic_helper_commit,
2978 };
2979
2980 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2981         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2982         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2983 };
2984
2985 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2986 {
2987         struct amdgpu_dm_backlight_caps *caps;
2988         struct drm_connector *conn_base;
2989         struct amdgpu_device *adev;
2990         struct drm_luminance_range_info *luminance_range;
2991
2992         if (aconnector->bl_idx == -1 ||
2993             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2994                 return;
2995
2996         conn_base = &aconnector->base;
2997         adev = drm_to_adev(conn_base->dev);
2998
2999         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3000         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3001         caps->aux_support = false;
3002
3003         if (caps->ext_caps->bits.oled == 1 /*||
3004             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3005             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3006                 caps->aux_support = true;
3007
3008         if (amdgpu_backlight == 0)
3009                 caps->aux_support = false;
3010         else if (amdgpu_backlight == 1)
3011                 caps->aux_support = true;
3012
3013         luminance_range = &conn_base->display_info.luminance_range;
3014
3015         if (luminance_range->max_luminance) {
3016                 caps->aux_min_input_signal = luminance_range->min_luminance;
3017                 caps->aux_max_input_signal = luminance_range->max_luminance;
3018         } else {
3019                 caps->aux_min_input_signal = 0;
3020                 caps->aux_max_input_signal = 512;
3021         }
3022 }
3023
3024 void amdgpu_dm_update_connector_after_detect(
3025                 struct amdgpu_dm_connector *aconnector)
3026 {
3027         struct drm_connector *connector = &aconnector->base;
3028         struct drm_device *dev = connector->dev;
3029         struct dc_sink *sink;
3030
3031         /* MST handled by drm_mst framework */
3032         if (aconnector->mst_mgr.mst_state == true)
3033                 return;
3034
3035         sink = aconnector->dc_link->local_sink;
3036         if (sink)
3037                 dc_sink_retain(sink);
3038
3039         /*
3040          * Edid mgmt connector gets first update only in mode_valid hook and then
3041          * the connector sink is set to either fake or physical sink depends on link status.
3042          * Skip if already done during boot.
3043          */
3044         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3045                         && aconnector->dc_em_sink) {
3046
3047                 /*
3048                  * For S3 resume with headless use eml_sink to fake stream
3049                  * because on resume connector->sink is set to NULL
3050                  */
3051                 mutex_lock(&dev->mode_config.mutex);
3052
3053                 if (sink) {
3054                         if (aconnector->dc_sink) {
3055                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3056                                 /*
3057                                  * retain and release below are used to
3058                                  * bump up refcount for sink because the link doesn't point
3059                                  * to it anymore after disconnect, so on next crtc to connector
3060                                  * reshuffle by UMD we will get into unwanted dc_sink release
3061                                  */
3062                                 dc_sink_release(aconnector->dc_sink);
3063                         }
3064                         aconnector->dc_sink = sink;
3065                         dc_sink_retain(aconnector->dc_sink);
3066                         amdgpu_dm_update_freesync_caps(connector,
3067                                         aconnector->edid);
3068                 } else {
3069                         amdgpu_dm_update_freesync_caps(connector, NULL);
3070                         if (!aconnector->dc_sink) {
3071                                 aconnector->dc_sink = aconnector->dc_em_sink;
3072                                 dc_sink_retain(aconnector->dc_sink);
3073                         }
3074                 }
3075
3076                 mutex_unlock(&dev->mode_config.mutex);
3077
3078                 if (sink)
3079                         dc_sink_release(sink);
3080                 return;
3081         }
3082
3083         /*
3084          * TODO: temporary guard to look for proper fix
3085          * if this sink is MST sink, we should not do anything
3086          */
3087         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3088                 dc_sink_release(sink);
3089                 return;
3090         }
3091
3092         if (aconnector->dc_sink == sink) {
3093                 /*
3094                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3095                  * Do nothing!!
3096                  */
3097                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3098                                 aconnector->connector_id);
3099                 if (sink)
3100                         dc_sink_release(sink);
3101                 return;
3102         }
3103
3104         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3105                 aconnector->connector_id, aconnector->dc_sink, sink);
3106
3107         mutex_lock(&dev->mode_config.mutex);
3108
3109         /*
3110          * 1. Update status of the drm connector
3111          * 2. Send an event and let userspace tell us what to do
3112          */
3113         if (sink) {
3114                 /*
3115                  * TODO: check if we still need the S3 mode update workaround.
3116                  * If yes, put it here.
3117                  */
3118                 if (aconnector->dc_sink) {
3119                         amdgpu_dm_update_freesync_caps(connector, NULL);
3120                         dc_sink_release(aconnector->dc_sink);
3121                 }
3122
3123                 aconnector->dc_sink = sink;
3124                 dc_sink_retain(aconnector->dc_sink);
3125                 if (sink->dc_edid.length == 0) {
3126                         aconnector->edid = NULL;
3127                         if (aconnector->dc_link->aux_mode) {
3128                                 drm_dp_cec_unset_edid(
3129                                         &aconnector->dm_dp_aux.aux);
3130                         }
3131                 } else {
3132                         aconnector->edid =
3133                                 (struct edid *)sink->dc_edid.raw_edid;
3134
3135                         if (aconnector->dc_link->aux_mode)
3136                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3137                                                     aconnector->edid);
3138                 }
3139
3140                 if (!aconnector->timing_requested) {
3141                         aconnector->timing_requested =
3142                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3143                         if (!aconnector->timing_requested)
3144                                 dm_error("failed to create aconnector->requested_timing\n");
3145                 }
3146
3147                 drm_connector_update_edid_property(connector, aconnector->edid);
3148                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3149                 update_connector_ext_caps(aconnector);
3150         } else {
3151                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3152                 amdgpu_dm_update_freesync_caps(connector, NULL);
3153                 drm_connector_update_edid_property(connector, NULL);
3154                 aconnector->num_modes = 0;
3155                 dc_sink_release(aconnector->dc_sink);
3156                 aconnector->dc_sink = NULL;
3157                 aconnector->edid = NULL;
3158                 kfree(aconnector->timing_requested);
3159                 aconnector->timing_requested = NULL;
3160                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3161                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3162                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3163         }
3164
3165         mutex_unlock(&dev->mode_config.mutex);
3166
3167         update_subconnector_property(aconnector);
3168
3169         if (sink)
3170                 dc_sink_release(sink);
3171 }
3172
3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3174 {
3175         struct drm_connector *connector = &aconnector->base;
3176         struct drm_device *dev = connector->dev;
3177         enum dc_connection_type new_connection_type = dc_connection_none;
3178         struct amdgpu_device *adev = drm_to_adev(dev);
3179         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3180         bool ret = false;
3181
3182         if (adev->dm.disable_hpd_irq)
3183                 return;
3184
3185         /*
3186          * In case of failure or MST no need to update connector status or notify the OS
3187          * since (for MST case) MST does this in its own context.
3188          */
3189         mutex_lock(&aconnector->hpd_lock);
3190
3191         if (adev->dm.hdcp_workqueue) {
3192                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3193                 dm_con_state->update_hdcp = true;
3194         }
3195         if (aconnector->fake_enable)
3196                 aconnector->fake_enable = false;
3197
3198         aconnector->timing_changed = false;
3199
3200         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3201                 DRM_ERROR("KMS: Failed to detect connector\n");
3202
3203         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3204                 emulated_link_detect(aconnector->dc_link);
3205
3206                 drm_modeset_lock_all(dev);
3207                 dm_restore_drm_connector_state(dev, connector);
3208                 drm_modeset_unlock_all(dev);
3209
3210                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211                         drm_kms_helper_connector_hotplug_event(connector);
3212         } else {
3213                 mutex_lock(&adev->dm.dc_lock);
3214                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3215                 mutex_unlock(&adev->dm.dc_lock);
3216                 if (ret) {
3217                         amdgpu_dm_update_connector_after_detect(aconnector);
3218
3219                         drm_modeset_lock_all(dev);
3220                         dm_restore_drm_connector_state(dev, connector);
3221                         drm_modeset_unlock_all(dev);
3222
3223                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3224                                 drm_kms_helper_connector_hotplug_event(connector);
3225                 }
3226         }
3227         mutex_unlock(&aconnector->hpd_lock);
3228
3229 }
3230
3231 static void handle_hpd_irq(void *param)
3232 {
3233         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3234
3235         handle_hpd_irq_helper(aconnector);
3236
3237 }
3238
3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3240 {
3241         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3242         u8 dret;
3243         bool new_irq_handled = false;
3244         int dpcd_addr;
3245         int dpcd_bytes_to_read;
3246
3247         const int max_process_count = 30;
3248         int process_count = 0;
3249
3250         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3251
3252         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3253                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3254                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3255                 dpcd_addr = DP_SINK_COUNT;
3256         } else {
3257                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3258                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3259                 dpcd_addr = DP_SINK_COUNT_ESI;
3260         }
3261
3262         dret = drm_dp_dpcd_read(
3263                 &aconnector->dm_dp_aux.aux,
3264                 dpcd_addr,
3265                 esi,
3266                 dpcd_bytes_to_read);
3267
3268         while (dret == dpcd_bytes_to_read &&
3269                 process_count < max_process_count) {
3270                 u8 retry;
3271                 dret = 0;
3272
3273                 process_count++;
3274
3275                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3276                 /* handle HPD short pulse irq */
3277                 if (aconnector->mst_mgr.mst_state)
3278                         drm_dp_mst_hpd_irq(
3279                                 &aconnector->mst_mgr,
3280                                 esi,
3281                                 &new_irq_handled);
3282
3283                 if (new_irq_handled) {
3284                         /* ACK at DPCD to notify down stream */
3285                         const int ack_dpcd_bytes_to_write =
3286                                 dpcd_bytes_to_read - 1;
3287
3288                         for (retry = 0; retry < 3; retry++) {
3289                                 u8 wret;
3290
3291                                 wret = drm_dp_dpcd_write(
3292                                         &aconnector->dm_dp_aux.aux,
3293                                         dpcd_addr + 1,
3294                                         &esi[1],
3295                                         ack_dpcd_bytes_to_write);
3296                                 if (wret == ack_dpcd_bytes_to_write)
3297                                         break;
3298                         }
3299
3300                         /* check if there is new irq to be handled */
3301                         dret = drm_dp_dpcd_read(
3302                                 &aconnector->dm_dp_aux.aux,
3303                                 dpcd_addr,
3304                                 esi,
3305                                 dpcd_bytes_to_read);
3306
3307                         new_irq_handled = false;
3308                 } else {
3309                         break;
3310                 }
3311         }
3312
3313         if (process_count == max_process_count)
3314                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3315 }
3316
3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3318                                                         union hpd_irq_data hpd_irq_data)
3319 {
3320         struct hpd_rx_irq_offload_work *offload_work =
3321                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3322
3323         if (!offload_work) {
3324                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3325                 return;
3326         }
3327
3328         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3329         offload_work->data = hpd_irq_data;
3330         offload_work->offload_wq = offload_wq;
3331
3332         queue_work(offload_wq->wq, &offload_work->work);
3333         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3334 }
3335
3336 static void handle_hpd_rx_irq(void *param)
3337 {
3338         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3339         struct drm_connector *connector = &aconnector->base;
3340         struct drm_device *dev = connector->dev;
3341         struct dc_link *dc_link = aconnector->dc_link;
3342         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3343         bool result = false;
3344         enum dc_connection_type new_connection_type = dc_connection_none;
3345         struct amdgpu_device *adev = drm_to_adev(dev);
3346         union hpd_irq_data hpd_irq_data;
3347         bool link_loss = false;
3348         bool has_left_work = false;
3349         int idx = dc_link->link_index;
3350         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3351
3352         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3353
3354         if (adev->dm.disable_hpd_irq)
3355                 return;
3356
3357         /*
3358          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3359          * conflict, after implement i2c helper, this mutex should be
3360          * retired.
3361          */
3362         mutex_lock(&aconnector->hpd_lock);
3363
3364         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3365                                                 &link_loss, true, &has_left_work);
3366
3367         if (!has_left_work)
3368                 goto out;
3369
3370         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3371                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3372                 goto out;
3373         }
3374
3375         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3376                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3377                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3378                         dm_handle_mst_sideband_msg(aconnector);
3379                         goto out;
3380                 }
3381
3382                 if (link_loss) {
3383                         bool skip = false;
3384
3385                         spin_lock(&offload_wq->offload_lock);
3386                         skip = offload_wq->is_handling_link_loss;
3387
3388                         if (!skip)
3389                                 offload_wq->is_handling_link_loss = true;
3390
3391                         spin_unlock(&offload_wq->offload_lock);
3392
3393                         if (!skip)
3394                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3395
3396                         goto out;
3397                 }
3398         }
3399
3400 out:
3401         if (result && !is_mst_root_connector) {
3402                 /* Downstream Port status changed. */
3403                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3404                         DRM_ERROR("KMS: Failed to detect connector\n");
3405
3406                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3407                         emulated_link_detect(dc_link);
3408
3409                         if (aconnector->fake_enable)
3410                                 aconnector->fake_enable = false;
3411
3412                         amdgpu_dm_update_connector_after_detect(aconnector);
3413
3414
3415                         drm_modeset_lock_all(dev);
3416                         dm_restore_drm_connector_state(dev, connector);
3417                         drm_modeset_unlock_all(dev);
3418
3419                         drm_kms_helper_connector_hotplug_event(connector);
3420                 } else {
3421                         bool ret = false;
3422
3423                         mutex_lock(&adev->dm.dc_lock);
3424                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3425                         mutex_unlock(&adev->dm.dc_lock);
3426
3427                         if (ret) {
3428                                 if (aconnector->fake_enable)
3429                                         aconnector->fake_enable = false;
3430
3431                                 amdgpu_dm_update_connector_after_detect(aconnector);
3432
3433                                 drm_modeset_lock_all(dev);
3434                                 dm_restore_drm_connector_state(dev, connector);
3435                                 drm_modeset_unlock_all(dev);
3436
3437                                 drm_kms_helper_connector_hotplug_event(connector);
3438                         }
3439                 }
3440         }
3441         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3442                 if (adev->dm.hdcp_workqueue)
3443                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3444         }
3445
3446         if (dc_link->type != dc_connection_mst_branch)
3447                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3448
3449         mutex_unlock(&aconnector->hpd_lock);
3450 }
3451
3452 static void register_hpd_handlers(struct amdgpu_device *adev)
3453 {
3454         struct drm_device *dev = adev_to_drm(adev);
3455         struct drm_connector *connector;
3456         struct amdgpu_dm_connector *aconnector;
3457         const struct dc_link *dc_link;
3458         struct dc_interrupt_params int_params = {0};
3459
3460         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3461         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3462
3463         list_for_each_entry(connector,
3464                         &dev->mode_config.connector_list, head) {
3465
3466                 aconnector = to_amdgpu_dm_connector(connector);
3467                 dc_link = aconnector->dc_link;
3468
3469                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3470                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3471                         int_params.irq_source = dc_link->irq_source_hpd;
3472
3473                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3474                                         handle_hpd_irq,
3475                                         (void *) aconnector);
3476                 }
3477
3478                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3479
3480                         /* Also register for DP short pulse (hpd_rx). */
3481                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3482                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3483
3484                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485                                         handle_hpd_rx_irq,
3486                                         (void *) aconnector);
3487
3488                         if (adev->dm.hpd_rx_offload_wq)
3489                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3490                                         aconnector;
3491                 }
3492         }
3493 }
3494
3495 #if defined(CONFIG_DRM_AMD_DC_SI)
3496 /* Register IRQ sources and initialize IRQ callbacks */
3497 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3498 {
3499         struct dc *dc = adev->dm.dc;
3500         struct common_irq_params *c_irq_params;
3501         struct dc_interrupt_params int_params = {0};
3502         int r;
3503         int i;
3504         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3505
3506         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3507         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3508
3509         /*
3510          * Actions of amdgpu_irq_add_id():
3511          * 1. Register a set() function with base driver.
3512          *    Base driver will call set() function to enable/disable an
3513          *    interrupt in DC hardware.
3514          * 2. Register amdgpu_dm_irq_handler().
3515          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3516          *    coming from DC hardware.
3517          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3518          *    for acknowledging and handling. */
3519
3520         /* Use VBLANK interrupt */
3521         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3522                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3523                 if (r) {
3524                         DRM_ERROR("Failed to add crtc irq id!\n");
3525                         return r;
3526                 }
3527
3528                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3529                 int_params.irq_source =
3530                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3531
3532                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3533
3534                 c_irq_params->adev = adev;
3535                 c_irq_params->irq_src = int_params.irq_source;
3536
3537                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3538                                 dm_crtc_high_irq, c_irq_params);
3539         }
3540
3541         /* Use GRPH_PFLIP interrupt */
3542         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3543                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3544                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3545                 if (r) {
3546                         DRM_ERROR("Failed to add page flip irq id!\n");
3547                         return r;
3548                 }
3549
3550                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3551                 int_params.irq_source =
3552                         dc_interrupt_to_irq_source(dc, i, 0);
3553
3554                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3555
3556                 c_irq_params->adev = adev;
3557                 c_irq_params->irq_src = int_params.irq_source;
3558
3559                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3560                                 dm_pflip_high_irq, c_irq_params);
3561
3562         }
3563
3564         /* HPD */
3565         r = amdgpu_irq_add_id(adev, client_id,
3566                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3567         if (r) {
3568                 DRM_ERROR("Failed to add hpd irq id!\n");
3569                 return r;
3570         }
3571
3572         register_hpd_handlers(adev);
3573
3574         return 0;
3575 }
3576 #endif
3577
3578 /* Register IRQ sources and initialize IRQ callbacks */
3579 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3580 {
3581         struct dc *dc = adev->dm.dc;
3582         struct common_irq_params *c_irq_params;
3583         struct dc_interrupt_params int_params = {0};
3584         int r;
3585         int i;
3586         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3587
3588         if (adev->family >= AMDGPU_FAMILY_AI)
3589                 client_id = SOC15_IH_CLIENTID_DCE;
3590
3591         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3592         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3593
3594         /*
3595          * Actions of amdgpu_irq_add_id():
3596          * 1. Register a set() function with base driver.
3597          *    Base driver will call set() function to enable/disable an
3598          *    interrupt in DC hardware.
3599          * 2. Register amdgpu_dm_irq_handler().
3600          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3601          *    coming from DC hardware.
3602          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3603          *    for acknowledging and handling. */
3604
3605         /* Use VBLANK interrupt */
3606         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3607                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3608                 if (r) {
3609                         DRM_ERROR("Failed to add crtc irq id!\n");
3610                         return r;
3611                 }
3612
3613                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3614                 int_params.irq_source =
3615                         dc_interrupt_to_irq_source(dc, i, 0);
3616
3617                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3618
3619                 c_irq_params->adev = adev;
3620                 c_irq_params->irq_src = int_params.irq_source;
3621
3622                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3623                                 dm_crtc_high_irq, c_irq_params);
3624         }
3625
3626         /* Use VUPDATE interrupt */
3627         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3628                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3629                 if (r) {
3630                         DRM_ERROR("Failed to add vupdate irq id!\n");
3631                         return r;
3632                 }
3633
3634                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3635                 int_params.irq_source =
3636                         dc_interrupt_to_irq_source(dc, i, 0);
3637
3638                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3639
3640                 c_irq_params->adev = adev;
3641                 c_irq_params->irq_src = int_params.irq_source;
3642
3643                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3644                                 dm_vupdate_high_irq, c_irq_params);
3645         }
3646
3647         /* Use GRPH_PFLIP interrupt */
3648         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3649                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3650                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3651                 if (r) {
3652                         DRM_ERROR("Failed to add page flip irq id!\n");
3653                         return r;
3654                 }
3655
3656                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657                 int_params.irq_source =
3658                         dc_interrupt_to_irq_source(dc, i, 0);
3659
3660                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3661
3662                 c_irq_params->adev = adev;
3663                 c_irq_params->irq_src = int_params.irq_source;
3664
3665                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666                                 dm_pflip_high_irq, c_irq_params);
3667
3668         }
3669
3670         /* HPD */
3671         r = amdgpu_irq_add_id(adev, client_id,
3672                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3673         if (r) {
3674                 DRM_ERROR("Failed to add hpd irq id!\n");
3675                 return r;
3676         }
3677
3678         register_hpd_handlers(adev);
3679
3680         return 0;
3681 }
3682
3683 /* Register IRQ sources and initialize IRQ callbacks */
3684 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3685 {
3686         struct dc *dc = adev->dm.dc;
3687         struct common_irq_params *c_irq_params;
3688         struct dc_interrupt_params int_params = {0};
3689         int r;
3690         int i;
3691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3692         static const unsigned int vrtl_int_srcid[] = {
3693                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3694                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3695                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3696                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3697                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3698                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3699         };
3700 #endif
3701
3702         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3703         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3704
3705         /*
3706          * Actions of amdgpu_irq_add_id():
3707          * 1. Register a set() function with base driver.
3708          *    Base driver will call set() function to enable/disable an
3709          *    interrupt in DC hardware.
3710          * 2. Register amdgpu_dm_irq_handler().
3711          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3712          *    coming from DC hardware.
3713          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3714          *    for acknowledging and handling.
3715          */
3716
3717         /* Use VSTARTUP interrupt */
3718         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3719                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3720                         i++) {
3721                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3722
3723                 if (r) {
3724                         DRM_ERROR("Failed to add crtc irq id!\n");
3725                         return r;
3726                 }
3727
3728                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3729                 int_params.irq_source =
3730                         dc_interrupt_to_irq_source(dc, i, 0);
3731
3732                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3733
3734                 c_irq_params->adev = adev;
3735                 c_irq_params->irq_src = int_params.irq_source;
3736
3737                 amdgpu_dm_irq_register_interrupt(
3738                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3739         }
3740
3741         /* Use otg vertical line interrupt */
3742 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3743         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3744                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3745                                 vrtl_int_srcid[i], &adev->vline0_irq);
3746
3747                 if (r) {
3748                         DRM_ERROR("Failed to add vline0 irq id!\n");
3749                         return r;
3750                 }
3751
3752                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3753                 int_params.irq_source =
3754                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3755
3756                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3757                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3758                         break;
3759                 }
3760
3761                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3762                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3763
3764                 c_irq_params->adev = adev;
3765                 c_irq_params->irq_src = int_params.irq_source;
3766
3767                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3768                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3769         }
3770 #endif
3771
3772         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3773          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3774          * to trigger at end of each vblank, regardless of state of the lock,
3775          * matching DCE behaviour.
3776          */
3777         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3778              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3779              i++) {
3780                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3781
3782                 if (r) {
3783                         DRM_ERROR("Failed to add vupdate irq id!\n");
3784                         return r;
3785                 }
3786
3787                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3788                 int_params.irq_source =
3789                         dc_interrupt_to_irq_source(dc, i, 0);
3790
3791                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3792
3793                 c_irq_params->adev = adev;
3794                 c_irq_params->irq_src = int_params.irq_source;
3795
3796                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797                                 dm_vupdate_high_irq, c_irq_params);
3798         }
3799
3800         /* Use GRPH_PFLIP interrupt */
3801         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3802                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3803                         i++) {
3804                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3805                 if (r) {
3806                         DRM_ERROR("Failed to add page flip irq id!\n");
3807                         return r;
3808                 }
3809
3810                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3811                 int_params.irq_source =
3812                         dc_interrupt_to_irq_source(dc, i, 0);
3813
3814                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3815
3816                 c_irq_params->adev = adev;
3817                 c_irq_params->irq_src = int_params.irq_source;
3818
3819                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3820                                 dm_pflip_high_irq, c_irq_params);
3821
3822         }
3823
3824         /* HPD */
3825         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3826                         &adev->hpd_irq);
3827         if (r) {
3828                 DRM_ERROR("Failed to add hpd irq id!\n");
3829                 return r;
3830         }
3831
3832         register_hpd_handlers(adev);
3833
3834         return 0;
3835 }
3836 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3837 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3838 {
3839         struct dc *dc = adev->dm.dc;
3840         struct common_irq_params *c_irq_params;
3841         struct dc_interrupt_params int_params = {0};
3842         int r, i;
3843
3844         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3845         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3846
3847         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3848                         &adev->dmub_outbox_irq);
3849         if (r) {
3850                 DRM_ERROR("Failed to add outbox irq id!\n");
3851                 return r;
3852         }
3853
3854         if (dc->ctx->dmub_srv) {
3855                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3856                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3857                 int_params.irq_source =
3858                 dc_interrupt_to_irq_source(dc, i, 0);
3859
3860                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3861
3862                 c_irq_params->adev = adev;
3863                 c_irq_params->irq_src = int_params.irq_source;
3864
3865                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3866                                 dm_dmub_outbox1_low_irq, c_irq_params);
3867         }
3868
3869         return 0;
3870 }
3871
3872 /*
3873  * Acquires the lock for the atomic state object and returns
3874  * the new atomic state.
3875  *
3876  * This should only be called during atomic check.
3877  */
3878 int dm_atomic_get_state(struct drm_atomic_state *state,
3879                         struct dm_atomic_state **dm_state)
3880 {
3881         struct drm_device *dev = state->dev;
3882         struct amdgpu_device *adev = drm_to_adev(dev);
3883         struct amdgpu_display_manager *dm = &adev->dm;
3884         struct drm_private_state *priv_state;
3885
3886         if (*dm_state)
3887                 return 0;
3888
3889         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3890         if (IS_ERR(priv_state))
3891                 return PTR_ERR(priv_state);
3892
3893         *dm_state = to_dm_atomic_state(priv_state);
3894
3895         return 0;
3896 }
3897
3898 static struct dm_atomic_state *
3899 dm_atomic_get_new_state(struct drm_atomic_state *state)
3900 {
3901         struct drm_device *dev = state->dev;
3902         struct amdgpu_device *adev = drm_to_adev(dev);
3903         struct amdgpu_display_manager *dm = &adev->dm;
3904         struct drm_private_obj *obj;
3905         struct drm_private_state *new_obj_state;
3906         int i;
3907
3908         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3909                 if (obj->funcs == dm->atomic_obj.funcs)
3910                         return to_dm_atomic_state(new_obj_state);
3911         }
3912
3913         return NULL;
3914 }
3915
3916 static struct drm_private_state *
3917 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3918 {
3919         struct dm_atomic_state *old_state, *new_state;
3920
3921         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3922         if (!new_state)
3923                 return NULL;
3924
3925         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3926
3927         old_state = to_dm_atomic_state(obj->state);
3928
3929         if (old_state && old_state->context)
3930                 new_state->context = dc_copy_state(old_state->context);
3931
3932         if (!new_state->context) {
3933                 kfree(new_state);
3934                 return NULL;
3935         }
3936
3937         return &new_state->base;
3938 }
3939
3940 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3941                                     struct drm_private_state *state)
3942 {
3943         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3944
3945         if (dm_state && dm_state->context)
3946                 dc_release_state(dm_state->context);
3947
3948         kfree(dm_state);
3949 }
3950
3951 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3952         .atomic_duplicate_state = dm_atomic_duplicate_state,
3953         .atomic_destroy_state = dm_atomic_destroy_state,
3954 };
3955
3956 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3957 {
3958         struct dm_atomic_state *state;
3959         int r;
3960
3961         adev->mode_info.mode_config_initialized = true;
3962
3963         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3964         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3965
3966         adev_to_drm(adev)->mode_config.max_width = 16384;
3967         adev_to_drm(adev)->mode_config.max_height = 16384;
3968
3969         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3970         if (adev->asic_type == CHIP_HAWAII)
3971                 /* disable prefer shadow for now due to hibernation issues */
3972                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3973         else
3974                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3975         /* indicates support for immediate flip */
3976         adev_to_drm(adev)->mode_config.async_page_flip = true;
3977
3978         state = kzalloc(sizeof(*state), GFP_KERNEL);
3979         if (!state)
3980                 return -ENOMEM;
3981
3982         state->context = dc_create_state(adev->dm.dc);
3983         if (!state->context) {
3984                 kfree(state);
3985                 return -ENOMEM;
3986         }
3987
3988         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3989
3990         drm_atomic_private_obj_init(adev_to_drm(adev),
3991                                     &adev->dm.atomic_obj,
3992                                     &state->base,
3993                                     &dm_atomic_state_funcs);
3994
3995         r = amdgpu_display_modeset_create_props(adev);
3996         if (r) {
3997                 dc_release_state(state->context);
3998                 kfree(state);
3999                 return r;
4000         }
4001
4002         r = amdgpu_dm_audio_init(adev);
4003         if (r) {
4004                 dc_release_state(state->context);
4005                 kfree(state);
4006                 return r;
4007         }
4008
4009         return 0;
4010 }
4011
4012 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4013 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4014 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4015
4016 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4017                                             int bl_idx)
4018 {
4019 #if defined(CONFIG_ACPI)
4020         struct amdgpu_dm_backlight_caps caps;
4021
4022         memset(&caps, 0, sizeof(caps));
4023
4024         if (dm->backlight_caps[bl_idx].caps_valid)
4025                 return;
4026
4027         amdgpu_acpi_get_backlight_caps(&caps);
4028         if (caps.caps_valid) {
4029                 dm->backlight_caps[bl_idx].caps_valid = true;
4030                 if (caps.aux_support)
4031                         return;
4032                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4033                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4034         } else {
4035                 dm->backlight_caps[bl_idx].min_input_signal =
4036                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4037                 dm->backlight_caps[bl_idx].max_input_signal =
4038                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4039         }
4040 #else
4041         if (dm->backlight_caps[bl_idx].aux_support)
4042                 return;
4043
4044         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4045         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4046 #endif
4047 }
4048
4049 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4050                                 unsigned *min, unsigned *max)
4051 {
4052         if (!caps)
4053                 return 0;
4054
4055         if (caps->aux_support) {
4056                 // Firmware limits are in nits, DC API wants millinits.
4057                 *max = 1000 * caps->aux_max_input_signal;
4058                 *min = 1000 * caps->aux_min_input_signal;
4059         } else {
4060                 // Firmware limits are 8-bit, PWM control is 16-bit.
4061                 *max = 0x101 * caps->max_input_signal;
4062                 *min = 0x101 * caps->min_input_signal;
4063         }
4064         return 1;
4065 }
4066
4067 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4068                                         uint32_t brightness)
4069 {
4070         unsigned min, max;
4071
4072         if (!get_brightness_range(caps, &min, &max))
4073                 return brightness;
4074
4075         // Rescale 0..255 to min..max
4076         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4077                                        AMDGPU_MAX_BL_LEVEL);
4078 }
4079
4080 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4081                                       uint32_t brightness)
4082 {
4083         unsigned min, max;
4084
4085         if (!get_brightness_range(caps, &min, &max))
4086                 return brightness;
4087
4088         if (brightness < min)
4089                 return 0;
4090         // Rescale min..max to 0..255
4091         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4092                                  max - min);
4093 }
4094
4095 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4096                                          int bl_idx,
4097                                          u32 user_brightness)
4098 {
4099         struct amdgpu_dm_backlight_caps caps;
4100         struct dc_link *link;
4101         u32 brightness;
4102         bool rc;
4103
4104         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4105         caps = dm->backlight_caps[bl_idx];
4106
4107         dm->brightness[bl_idx] = user_brightness;
4108         /* update scratch register */
4109         if (bl_idx == 0)
4110                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4111         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4112         link = (struct dc_link *)dm->backlight_link[bl_idx];
4113
4114         /* Change brightness based on AUX property */
4115         if (caps.aux_support) {
4116                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4117                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4118                 if (!rc)
4119                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4120         } else {
4121                 rc = dc_link_set_backlight_level(link, brightness, 0);
4122                 if (!rc)
4123                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4124         }
4125
4126         if (rc)
4127                 dm->actual_brightness[bl_idx] = user_brightness;
4128 }
4129
4130 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4131 {
4132         struct amdgpu_display_manager *dm = bl_get_data(bd);
4133         int i;
4134
4135         for (i = 0; i < dm->num_of_edps; i++) {
4136                 if (bd == dm->backlight_dev[i])
4137                         break;
4138         }
4139         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4140                 i = 0;
4141         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4142
4143         return 0;
4144 }
4145
4146 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4147                                          int bl_idx)
4148 {
4149         struct amdgpu_dm_backlight_caps caps;
4150         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4151
4152         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4153         caps = dm->backlight_caps[bl_idx];
4154
4155         if (caps.aux_support) {
4156                 u32 avg, peak;
4157                 bool rc;
4158
4159                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4160                 if (!rc)
4161                         return dm->brightness[bl_idx];
4162                 return convert_brightness_to_user(&caps, avg);
4163         } else {
4164                 int ret = dc_link_get_backlight_level(link);
4165
4166                 if (ret == DC_ERROR_UNEXPECTED)
4167                         return dm->brightness[bl_idx];
4168                 return convert_brightness_to_user(&caps, ret);
4169         }
4170 }
4171
4172 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4173 {
4174         struct amdgpu_display_manager *dm = bl_get_data(bd);
4175         int i;
4176
4177         for (i = 0; i < dm->num_of_edps; i++) {
4178                 if (bd == dm->backlight_dev[i])
4179                         break;
4180         }
4181         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4182                 i = 0;
4183         return amdgpu_dm_backlight_get_level(dm, i);
4184 }
4185
4186 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4187         .options = BL_CORE_SUSPENDRESUME,
4188         .get_brightness = amdgpu_dm_backlight_get_brightness,
4189         .update_status  = amdgpu_dm_backlight_update_status,
4190 };
4191
4192 static void
4193 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4194 {
4195         struct drm_device *drm = aconnector->base.dev;
4196         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4197         struct backlight_properties props = { 0 };
4198         char bl_name[16];
4199
4200         if (aconnector->bl_idx == -1)
4201                 return;
4202
4203         if (!acpi_video_backlight_use_native()) {
4204                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4205                 /* Try registering an ACPI video backlight device instead. */
4206                 acpi_video_register_backlight();
4207                 return;
4208         }
4209
4210         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4211         props.brightness = AMDGPU_MAX_BL_LEVEL;
4212         props.type = BACKLIGHT_RAW;
4213
4214         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4215                  drm->primary->index + aconnector->bl_idx);
4216
4217         dm->backlight_dev[aconnector->bl_idx] =
4218                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4219                                           &amdgpu_dm_backlight_ops, &props);
4220
4221         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4222                 DRM_ERROR("DM: Backlight registration failed!\n");
4223                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4224         } else
4225                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4226 }
4227
4228 static int initialize_plane(struct amdgpu_display_manager *dm,
4229                             struct amdgpu_mode_info *mode_info, int plane_id,
4230                             enum drm_plane_type plane_type,
4231                             const struct dc_plane_cap *plane_cap)
4232 {
4233         struct drm_plane *plane;
4234         unsigned long possible_crtcs;
4235         int ret = 0;
4236
4237         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4238         if (!plane) {
4239                 DRM_ERROR("KMS: Failed to allocate plane\n");
4240                 return -ENOMEM;
4241         }
4242         plane->type = plane_type;
4243
4244         /*
4245          * HACK: IGT tests expect that the primary plane for a CRTC
4246          * can only have one possible CRTC. Only expose support for
4247          * any CRTC if they're not going to be used as a primary plane
4248          * for a CRTC - like overlay or underlay planes.
4249          */
4250         possible_crtcs = 1 << plane_id;
4251         if (plane_id >= dm->dc->caps.max_streams)
4252                 possible_crtcs = 0xff;
4253
4254         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4255
4256         if (ret) {
4257                 DRM_ERROR("KMS: Failed to initialize plane\n");
4258                 kfree(plane);
4259                 return ret;
4260         }
4261
4262         if (mode_info)
4263                 mode_info->planes[plane_id] = plane;
4264
4265         return ret;
4266 }
4267
4268
4269 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4270                                    struct amdgpu_dm_connector *aconnector)
4271 {
4272         struct dc_link *link = aconnector->dc_link;
4273         int bl_idx = dm->num_of_edps;
4274
4275         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4276             link->type == dc_connection_none)
4277                 return;
4278
4279         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4280                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4281                 return;
4282         }
4283
4284         aconnector->bl_idx = bl_idx;
4285
4286         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4287         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4288         dm->backlight_link[bl_idx] = link;
4289         dm->num_of_edps++;
4290
4291         update_connector_ext_caps(aconnector);
4292 }
4293
4294 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4295
4296 /*
4297  * In this architecture, the association
4298  * connector -> encoder -> crtc
4299  * id not really requried. The crtc and connector will hold the
4300  * display_index as an abstraction to use with DAL component
4301  *
4302  * Returns 0 on success
4303  */
4304 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4305 {
4306         struct amdgpu_display_manager *dm = &adev->dm;
4307         s32 i;
4308         struct amdgpu_dm_connector *aconnector = NULL;
4309         struct amdgpu_encoder *aencoder = NULL;
4310         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4311         u32 link_cnt;
4312         s32 primary_planes;
4313         enum dc_connection_type new_connection_type = dc_connection_none;
4314         const struct dc_plane_cap *plane;
4315         bool psr_feature_enabled = false;
4316         int max_overlay = dm->dc->caps.max_slave_planes;
4317
4318         dm->display_indexes_num = dm->dc->caps.max_streams;
4319         /* Update the actual used number of crtc */
4320         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4321
4322         amdgpu_dm_set_irq_funcs(adev);
4323
4324         link_cnt = dm->dc->caps.max_links;
4325         if (amdgpu_dm_mode_config_init(dm->adev)) {
4326                 DRM_ERROR("DM: Failed to initialize mode config\n");
4327                 return -EINVAL;
4328         }
4329
4330         /* There is one primary plane per CRTC */
4331         primary_planes = dm->dc->caps.max_streams;
4332         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4333
4334         /*
4335          * Initialize primary planes, implicit planes for legacy IOCTLS.
4336          * Order is reversed to match iteration order in atomic check.
4337          */
4338         for (i = (primary_planes - 1); i >= 0; i--) {
4339                 plane = &dm->dc->caps.planes[i];
4340
4341                 if (initialize_plane(dm, mode_info, i,
4342                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4343                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4344                         goto fail;
4345                 }
4346         }
4347
4348         /*
4349          * Initialize overlay planes, index starting after primary planes.
4350          * These planes have a higher DRM index than the primary planes since
4351          * they should be considered as having a higher z-order.
4352          * Order is reversed to match iteration order in atomic check.
4353          *
4354          * Only support DCN for now, and only expose one so we don't encourage
4355          * userspace to use up all the pipes.
4356          */
4357         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4358                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4359
4360                 /* Do not create overlay if MPO disabled */
4361                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4362                         break;
4363
4364                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4365                         continue;
4366
4367                 if (!plane->pixel_format_support.argb8888)
4368                         continue;
4369
4370                 if (max_overlay-- == 0)
4371                         break;
4372
4373                 if (initialize_plane(dm, NULL, primary_planes + i,
4374                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4375                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4376                         goto fail;
4377                 }
4378         }
4379
4380         for (i = 0; i < dm->dc->caps.max_streams; i++)
4381                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4382                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4383                         goto fail;
4384                 }
4385
4386         /* Use Outbox interrupt */
4387         switch (adev->ip_versions[DCE_HWIP][0]) {
4388         case IP_VERSION(3, 0, 0):
4389         case IP_VERSION(3, 1, 2):
4390         case IP_VERSION(3, 1, 3):
4391         case IP_VERSION(3, 1, 4):
4392         case IP_VERSION(3, 1, 5):
4393         case IP_VERSION(3, 1, 6):
4394         case IP_VERSION(3, 2, 0):
4395         case IP_VERSION(3, 2, 1):
4396         case IP_VERSION(2, 1, 0):
4397                 if (register_outbox_irq_handlers(dm->adev)) {
4398                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4399                         goto fail;
4400                 }
4401                 break;
4402         default:
4403                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4404                               adev->ip_versions[DCE_HWIP][0]);
4405         }
4406
4407         /* Determine whether to enable PSR support by default. */
4408         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4409                 switch (adev->ip_versions[DCE_HWIP][0]) {
4410                 case IP_VERSION(3, 1, 2):
4411                 case IP_VERSION(3, 1, 3):
4412                 case IP_VERSION(3, 1, 4):
4413                 case IP_VERSION(3, 1, 5):
4414                 case IP_VERSION(3, 1, 6):
4415                 case IP_VERSION(3, 2, 0):
4416                 case IP_VERSION(3, 2, 1):
4417                         psr_feature_enabled = true;
4418                         break;
4419                 default:
4420                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4421                         break;
4422                 }
4423         }
4424
4425         /* loops over all connectors on the board */
4426         for (i = 0; i < link_cnt; i++) {
4427                 struct dc_link *link = NULL;
4428
4429                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4430                         DRM_ERROR(
4431                                 "KMS: Cannot support more than %d display indexes\n",
4432                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4433                         continue;
4434                 }
4435
4436                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4437                 if (!aconnector)
4438                         goto fail;
4439
4440                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4441                 if (!aencoder)
4442                         goto fail;
4443
4444                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4445                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4446                         goto fail;
4447                 }
4448
4449                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4450                         DRM_ERROR("KMS: Failed to initialize connector\n");
4451                         goto fail;
4452                 }
4453
4454                 link = dc_get_link_at_index(dm->dc, i);
4455
4456                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4457                         DRM_ERROR("KMS: Failed to detect connector\n");
4458
4459                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4460                         emulated_link_detect(link);
4461                         amdgpu_dm_update_connector_after_detect(aconnector);
4462                 } else {
4463                         bool ret = false;
4464
4465                         mutex_lock(&dm->dc_lock);
4466                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4467                         mutex_unlock(&dm->dc_lock);
4468
4469                         if (ret) {
4470                                 amdgpu_dm_update_connector_after_detect(aconnector);
4471                                 setup_backlight_device(dm, aconnector);
4472
4473                                 if (psr_feature_enabled)
4474                                         amdgpu_dm_set_psr_caps(link);
4475
4476                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4477                                  * PSR is also supported.
4478                                  */
4479                                 if (link->psr_settings.psr_feature_enabled)
4480                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4481                         }
4482                 }
4483                 amdgpu_set_panel_orientation(&aconnector->base);
4484         }
4485
4486         /* If we didn't find a panel, notify the acpi video detection */
4487         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4488                 acpi_video_report_nolcd();
4489
4490         /* Software is initialized. Now we can register interrupt handlers. */
4491         switch (adev->asic_type) {
4492 #if defined(CONFIG_DRM_AMD_DC_SI)
4493         case CHIP_TAHITI:
4494         case CHIP_PITCAIRN:
4495         case CHIP_VERDE:
4496         case CHIP_OLAND:
4497                 if (dce60_register_irq_handlers(dm->adev)) {
4498                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4499                         goto fail;
4500                 }
4501                 break;
4502 #endif
4503         case CHIP_BONAIRE:
4504         case CHIP_HAWAII:
4505         case CHIP_KAVERI:
4506         case CHIP_KABINI:
4507         case CHIP_MULLINS:
4508         case CHIP_TONGA:
4509         case CHIP_FIJI:
4510         case CHIP_CARRIZO:
4511         case CHIP_STONEY:
4512         case CHIP_POLARIS11:
4513         case CHIP_POLARIS10:
4514         case CHIP_POLARIS12:
4515         case CHIP_VEGAM:
4516         case CHIP_VEGA10:
4517         case CHIP_VEGA12:
4518         case CHIP_VEGA20:
4519                 if (dce110_register_irq_handlers(dm->adev)) {
4520                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4521                         goto fail;
4522                 }
4523                 break;
4524         default:
4525                 switch (adev->ip_versions[DCE_HWIP][0]) {
4526                 case IP_VERSION(1, 0, 0):
4527                 case IP_VERSION(1, 0, 1):
4528                 case IP_VERSION(2, 0, 2):
4529                 case IP_VERSION(2, 0, 3):
4530                 case IP_VERSION(2, 0, 0):
4531                 case IP_VERSION(2, 1, 0):
4532                 case IP_VERSION(3, 0, 0):
4533                 case IP_VERSION(3, 0, 2):
4534                 case IP_VERSION(3, 0, 3):
4535                 case IP_VERSION(3, 0, 1):
4536                 case IP_VERSION(3, 1, 2):
4537                 case IP_VERSION(3, 1, 3):
4538                 case IP_VERSION(3, 1, 4):
4539                 case IP_VERSION(3, 1, 5):
4540                 case IP_VERSION(3, 1, 6):
4541                 case IP_VERSION(3, 2, 0):
4542                 case IP_VERSION(3, 2, 1):
4543                         if (dcn10_register_irq_handlers(dm->adev)) {
4544                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4545                                 goto fail;
4546                         }
4547                         break;
4548                 default:
4549                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4550                                         adev->ip_versions[DCE_HWIP][0]);
4551                         goto fail;
4552                 }
4553                 break;
4554         }
4555
4556         return 0;
4557 fail:
4558         kfree(aencoder);
4559         kfree(aconnector);
4560
4561         return -EINVAL;
4562 }
4563
4564 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4565 {
4566         drm_atomic_private_obj_fini(&dm->atomic_obj);
4567         return;
4568 }
4569
4570 /******************************************************************************
4571  * amdgpu_display_funcs functions
4572  *****************************************************************************/
4573
4574 /*
4575  * dm_bandwidth_update - program display watermarks
4576  *
4577  * @adev: amdgpu_device pointer
4578  *
4579  * Calculate and program the display watermarks and line buffer allocation.
4580  */
4581 static void dm_bandwidth_update(struct amdgpu_device *adev)
4582 {
4583         /* TODO: implement later */
4584 }
4585
4586 static const struct amdgpu_display_funcs dm_display_funcs = {
4587         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4588         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4589         .backlight_set_level = NULL, /* never called for DC */
4590         .backlight_get_level = NULL, /* never called for DC */
4591         .hpd_sense = NULL,/* called unconditionally */
4592         .hpd_set_polarity = NULL, /* called unconditionally */
4593         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4594         .page_flip_get_scanoutpos =
4595                 dm_crtc_get_scanoutpos,/* called unconditionally */
4596         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4597         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4598 };
4599
4600 #if defined(CONFIG_DEBUG_KERNEL_DC)
4601
4602 static ssize_t s3_debug_store(struct device *device,
4603                               struct device_attribute *attr,
4604                               const char *buf,
4605                               size_t count)
4606 {
4607         int ret;
4608         int s3_state;
4609         struct drm_device *drm_dev = dev_get_drvdata(device);
4610         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4611
4612         ret = kstrtoint(buf, 0, &s3_state);
4613
4614         if (ret == 0) {
4615                 if (s3_state) {
4616                         dm_resume(adev);
4617                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4618                 } else
4619                         dm_suspend(adev);
4620         }
4621
4622         return ret == 0 ? count : 0;
4623 }
4624
4625 DEVICE_ATTR_WO(s3_debug);
4626
4627 #endif
4628
4629 static int dm_init_microcode(struct amdgpu_device *adev)
4630 {
4631         char *fw_name_dmub;
4632         int r;
4633
4634         switch (adev->ip_versions[DCE_HWIP][0]) {
4635         case IP_VERSION(2, 1, 0):
4636                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4637                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4638                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4639                 break;
4640         case IP_VERSION(3, 0, 0):
4641                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4642                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4643                 else
4644                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4645                 break;
4646         case IP_VERSION(3, 0, 1):
4647                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4648                 break;
4649         case IP_VERSION(3, 0, 2):
4650                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4651                 break;
4652         case IP_VERSION(3, 0, 3):
4653                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4654                 break;
4655         case IP_VERSION(3, 1, 2):
4656         case IP_VERSION(3, 1, 3):
4657                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4658                 break;
4659         case IP_VERSION(3, 1, 4):
4660                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4661                 break;
4662         case IP_VERSION(3, 1, 5):
4663                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4664                 break;
4665         case IP_VERSION(3, 1, 6):
4666                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4667                 break;
4668         case IP_VERSION(3, 2, 0):
4669                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4670                 break;
4671         case IP_VERSION(3, 2, 1):
4672                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4673                 break;
4674         default:
4675                 /* ASIC doesn't support DMUB. */
4676                 return 0;
4677         }
4678         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4679         if (r)
4680                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4681         return r;
4682 }
4683
4684 static int dm_early_init(void *handle)
4685 {
4686         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4687         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4688         struct atom_context *ctx = mode_info->atom_context;
4689         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4690         u16 data_offset;
4691
4692         /* if there is no object header, skip DM */
4693         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4694                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4695                 dev_info(adev->dev, "No object header, skipping DM\n");
4696                 return -ENOENT;
4697         }
4698
4699         switch (adev->asic_type) {
4700 #if defined(CONFIG_DRM_AMD_DC_SI)
4701         case CHIP_TAHITI:
4702         case CHIP_PITCAIRN:
4703         case CHIP_VERDE:
4704                 adev->mode_info.num_crtc = 6;
4705                 adev->mode_info.num_hpd = 6;
4706                 adev->mode_info.num_dig = 6;
4707                 break;
4708         case CHIP_OLAND:
4709                 adev->mode_info.num_crtc = 2;
4710                 adev->mode_info.num_hpd = 2;
4711                 adev->mode_info.num_dig = 2;
4712                 break;
4713 #endif
4714         case CHIP_BONAIRE:
4715         case CHIP_HAWAII:
4716                 adev->mode_info.num_crtc = 6;
4717                 adev->mode_info.num_hpd = 6;
4718                 adev->mode_info.num_dig = 6;
4719                 break;
4720         case CHIP_KAVERI:
4721                 adev->mode_info.num_crtc = 4;
4722                 adev->mode_info.num_hpd = 6;
4723                 adev->mode_info.num_dig = 7;
4724                 break;
4725         case CHIP_KABINI:
4726         case CHIP_MULLINS:
4727                 adev->mode_info.num_crtc = 2;
4728                 adev->mode_info.num_hpd = 6;
4729                 adev->mode_info.num_dig = 6;
4730                 break;
4731         case CHIP_FIJI:
4732         case CHIP_TONGA:
4733                 adev->mode_info.num_crtc = 6;
4734                 adev->mode_info.num_hpd = 6;
4735                 adev->mode_info.num_dig = 7;
4736                 break;
4737         case CHIP_CARRIZO:
4738                 adev->mode_info.num_crtc = 3;
4739                 adev->mode_info.num_hpd = 6;
4740                 adev->mode_info.num_dig = 9;
4741                 break;
4742         case CHIP_STONEY:
4743                 adev->mode_info.num_crtc = 2;
4744                 adev->mode_info.num_hpd = 6;
4745                 adev->mode_info.num_dig = 9;
4746                 break;
4747         case CHIP_POLARIS11:
4748         case CHIP_POLARIS12:
4749                 adev->mode_info.num_crtc = 5;
4750                 adev->mode_info.num_hpd = 5;
4751                 adev->mode_info.num_dig = 5;
4752                 break;
4753         case CHIP_POLARIS10:
4754         case CHIP_VEGAM:
4755                 adev->mode_info.num_crtc = 6;
4756                 adev->mode_info.num_hpd = 6;
4757                 adev->mode_info.num_dig = 6;
4758                 break;
4759         case CHIP_VEGA10:
4760         case CHIP_VEGA12:
4761         case CHIP_VEGA20:
4762                 adev->mode_info.num_crtc = 6;
4763                 adev->mode_info.num_hpd = 6;
4764                 adev->mode_info.num_dig = 6;
4765                 break;
4766         default:
4767
4768                 switch (adev->ip_versions[DCE_HWIP][0]) {
4769                 case IP_VERSION(2, 0, 2):
4770                 case IP_VERSION(3, 0, 0):
4771                         adev->mode_info.num_crtc = 6;
4772                         adev->mode_info.num_hpd = 6;
4773                         adev->mode_info.num_dig = 6;
4774                         break;
4775                 case IP_VERSION(2, 0, 0):
4776                 case IP_VERSION(3, 0, 2):
4777                         adev->mode_info.num_crtc = 5;
4778                         adev->mode_info.num_hpd = 5;
4779                         adev->mode_info.num_dig = 5;
4780                         break;
4781                 case IP_VERSION(2, 0, 3):
4782                 case IP_VERSION(3, 0, 3):
4783                         adev->mode_info.num_crtc = 2;
4784                         adev->mode_info.num_hpd = 2;
4785                         adev->mode_info.num_dig = 2;
4786                         break;
4787                 case IP_VERSION(1, 0, 0):
4788                 case IP_VERSION(1, 0, 1):
4789                 case IP_VERSION(3, 0, 1):
4790                 case IP_VERSION(2, 1, 0):
4791                 case IP_VERSION(3, 1, 2):
4792                 case IP_VERSION(3, 1, 3):
4793                 case IP_VERSION(3, 1, 4):
4794                 case IP_VERSION(3, 1, 5):
4795                 case IP_VERSION(3, 1, 6):
4796                 case IP_VERSION(3, 2, 0):
4797                 case IP_VERSION(3, 2, 1):
4798                         adev->mode_info.num_crtc = 4;
4799                         adev->mode_info.num_hpd = 4;
4800                         adev->mode_info.num_dig = 4;
4801                         break;
4802                 default:
4803                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4804                                         adev->ip_versions[DCE_HWIP][0]);
4805                         return -EINVAL;
4806                 }
4807                 break;
4808         }
4809
4810         if (adev->mode_info.funcs == NULL)
4811                 adev->mode_info.funcs = &dm_display_funcs;
4812
4813         /*
4814          * Note: Do NOT change adev->audio_endpt_rreg and
4815          * adev->audio_endpt_wreg because they are initialised in
4816          * amdgpu_device_init()
4817          */
4818 #if defined(CONFIG_DEBUG_KERNEL_DC)
4819         device_create_file(
4820                 adev_to_drm(adev)->dev,
4821                 &dev_attr_s3_debug);
4822 #endif
4823         adev->dc_enabled = true;
4824
4825         return dm_init_microcode(adev);
4826 }
4827
4828 static bool modereset_required(struct drm_crtc_state *crtc_state)
4829 {
4830         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4831 }
4832
4833 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4834 {
4835         drm_encoder_cleanup(encoder);
4836         kfree(encoder);
4837 }
4838
4839 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4840         .destroy = amdgpu_dm_encoder_destroy,
4841 };
4842
4843 static int
4844 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4845                             const enum surface_pixel_format format,
4846                             enum dc_color_space *color_space)
4847 {
4848         bool full_range;
4849
4850         *color_space = COLOR_SPACE_SRGB;
4851
4852         /* DRM color properties only affect non-RGB formats. */
4853         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4854                 return 0;
4855
4856         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4857
4858         switch (plane_state->color_encoding) {
4859         case DRM_COLOR_YCBCR_BT601:
4860                 if (full_range)
4861                         *color_space = COLOR_SPACE_YCBCR601;
4862                 else
4863                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4864                 break;
4865
4866         case DRM_COLOR_YCBCR_BT709:
4867                 if (full_range)
4868                         *color_space = COLOR_SPACE_YCBCR709;
4869                 else
4870                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4871                 break;
4872
4873         case DRM_COLOR_YCBCR_BT2020:
4874                 if (full_range)
4875                         *color_space = COLOR_SPACE_2020_YCBCR;
4876                 else
4877                         return -EINVAL;
4878                 break;
4879
4880         default:
4881                 return -EINVAL;
4882         }
4883
4884         return 0;
4885 }
4886
4887 static int
4888 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4889                             const struct drm_plane_state *plane_state,
4890                             const u64 tiling_flags,
4891                             struct dc_plane_info *plane_info,
4892                             struct dc_plane_address *address,
4893                             bool tmz_surface,
4894                             bool force_disable_dcc)
4895 {
4896         const struct drm_framebuffer *fb = plane_state->fb;
4897         const struct amdgpu_framebuffer *afb =
4898                 to_amdgpu_framebuffer(plane_state->fb);
4899         int ret;
4900
4901         memset(plane_info, 0, sizeof(*plane_info));
4902
4903         switch (fb->format->format) {
4904         case DRM_FORMAT_C8:
4905                 plane_info->format =
4906                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4907                 break;
4908         case DRM_FORMAT_RGB565:
4909                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4910                 break;
4911         case DRM_FORMAT_XRGB8888:
4912         case DRM_FORMAT_ARGB8888:
4913                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4914                 break;
4915         case DRM_FORMAT_XRGB2101010:
4916         case DRM_FORMAT_ARGB2101010:
4917                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4918                 break;
4919         case DRM_FORMAT_XBGR2101010:
4920         case DRM_FORMAT_ABGR2101010:
4921                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4922                 break;
4923         case DRM_FORMAT_XBGR8888:
4924         case DRM_FORMAT_ABGR8888:
4925                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4926                 break;
4927         case DRM_FORMAT_NV21:
4928                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4929                 break;
4930         case DRM_FORMAT_NV12:
4931                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4932                 break;
4933         case DRM_FORMAT_P010:
4934                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4935                 break;
4936         case DRM_FORMAT_XRGB16161616F:
4937         case DRM_FORMAT_ARGB16161616F:
4938                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4939                 break;
4940         case DRM_FORMAT_XBGR16161616F:
4941         case DRM_FORMAT_ABGR16161616F:
4942                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4943                 break;
4944         case DRM_FORMAT_XRGB16161616:
4945         case DRM_FORMAT_ARGB16161616:
4946                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4947                 break;
4948         case DRM_FORMAT_XBGR16161616:
4949         case DRM_FORMAT_ABGR16161616:
4950                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4951                 break;
4952         default:
4953                 DRM_ERROR(
4954                         "Unsupported screen format %p4cc\n",
4955                         &fb->format->format);
4956                 return -EINVAL;
4957         }
4958
4959         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4960         case DRM_MODE_ROTATE_0:
4961                 plane_info->rotation = ROTATION_ANGLE_0;
4962                 break;
4963         case DRM_MODE_ROTATE_90:
4964                 plane_info->rotation = ROTATION_ANGLE_90;
4965                 break;
4966         case DRM_MODE_ROTATE_180:
4967                 plane_info->rotation = ROTATION_ANGLE_180;
4968                 break;
4969         case DRM_MODE_ROTATE_270:
4970                 plane_info->rotation = ROTATION_ANGLE_270;
4971                 break;
4972         default:
4973                 plane_info->rotation = ROTATION_ANGLE_0;
4974                 break;
4975         }
4976
4977
4978         plane_info->visible = true;
4979         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4980
4981         plane_info->layer_index = plane_state->normalized_zpos;
4982
4983         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4984                                           &plane_info->color_space);
4985         if (ret)
4986                 return ret;
4987
4988         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4989                                            plane_info->rotation, tiling_flags,
4990                                            &plane_info->tiling_info,
4991                                            &plane_info->plane_size,
4992                                            &plane_info->dcc, address,
4993                                            tmz_surface, force_disable_dcc);
4994         if (ret)
4995                 return ret;
4996
4997         amdgpu_dm_plane_fill_blending_from_plane_state(
4998                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4999                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5000
5001         return 0;
5002 }
5003
5004 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5005                                     struct dc_plane_state *dc_plane_state,
5006                                     struct drm_plane_state *plane_state,
5007                                     struct drm_crtc_state *crtc_state)
5008 {
5009         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5010         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5011         struct dc_scaling_info scaling_info;
5012         struct dc_plane_info plane_info;
5013         int ret;
5014         bool force_disable_dcc = false;
5015
5016         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5017         if (ret)
5018                 return ret;
5019
5020         dc_plane_state->src_rect = scaling_info.src_rect;
5021         dc_plane_state->dst_rect = scaling_info.dst_rect;
5022         dc_plane_state->clip_rect = scaling_info.clip_rect;
5023         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5024
5025         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5026         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5027                                           afb->tiling_flags,
5028                                           &plane_info,
5029                                           &dc_plane_state->address,
5030                                           afb->tmz_surface,
5031                                           force_disable_dcc);
5032         if (ret)
5033                 return ret;
5034
5035         dc_plane_state->format = plane_info.format;
5036         dc_plane_state->color_space = plane_info.color_space;
5037         dc_plane_state->format = plane_info.format;
5038         dc_plane_state->plane_size = plane_info.plane_size;
5039         dc_plane_state->rotation = plane_info.rotation;
5040         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5041         dc_plane_state->stereo_format = plane_info.stereo_format;
5042         dc_plane_state->tiling_info = plane_info.tiling_info;
5043         dc_plane_state->visible = plane_info.visible;
5044         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5045         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5046         dc_plane_state->global_alpha = plane_info.global_alpha;
5047         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5048         dc_plane_state->dcc = plane_info.dcc;
5049         dc_plane_state->layer_index = plane_info.layer_index;
5050         dc_plane_state->flip_int_enabled = true;
5051
5052         /*
5053          * Always set input transfer function, since plane state is refreshed
5054          * every time.
5055          */
5056         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5057         if (ret)
5058                 return ret;
5059
5060         return 0;
5061 }
5062
5063 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5064                                       struct rect *dirty_rect, int32_t x,
5065                                       s32 y, s32 width, s32 height,
5066                                       int *i, bool ffu)
5067 {
5068         if (*i > DC_MAX_DIRTY_RECTS)
5069                 return;
5070
5071         if (*i == DC_MAX_DIRTY_RECTS)
5072                 goto out;
5073
5074         dirty_rect->x = x;
5075         dirty_rect->y = y;
5076         dirty_rect->width = width;
5077         dirty_rect->height = height;
5078
5079         if (ffu)
5080                 drm_dbg(plane->dev,
5081                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5082                         plane->base.id, width, height);
5083         else
5084                 drm_dbg(plane->dev,
5085                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5086                         plane->base.id, x, y, width, height);
5087
5088 out:
5089         (*i)++;
5090 }
5091
5092 /**
5093  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5094  *
5095  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5096  *         remote fb
5097  * @old_plane_state: Old state of @plane
5098  * @new_plane_state: New state of @plane
5099  * @crtc_state: New state of CRTC connected to the @plane
5100  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5101  * @dirty_regions_changed: dirty regions changed
5102  *
5103  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5104  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5105  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5106  * amdgpu_dm's.
5107  *
5108  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5109  * plane with regions that require flushing to the eDP remote buffer. In
5110  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5111  * implicitly provide damage clips without any client support via the plane
5112  * bounds.
5113  */
5114 static void fill_dc_dirty_rects(struct drm_plane *plane,
5115                                 struct drm_plane_state *old_plane_state,
5116                                 struct drm_plane_state *new_plane_state,
5117                                 struct drm_crtc_state *crtc_state,
5118                                 struct dc_flip_addrs *flip_addrs,
5119                                 bool *dirty_regions_changed)
5120 {
5121         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5122         struct rect *dirty_rects = flip_addrs->dirty_rects;
5123         u32 num_clips;
5124         struct drm_mode_rect *clips;
5125         bool bb_changed;
5126         bool fb_changed;
5127         u32 i = 0;
5128         *dirty_regions_changed = false;
5129
5130         /*
5131          * Cursor plane has it's own dirty rect update interface. See
5132          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5133          */
5134         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5135                 return;
5136
5137         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5138         clips = drm_plane_get_damage_clips(new_plane_state);
5139
5140         if (!dm_crtc_state->mpo_requested) {
5141                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5142                         goto ffu;
5143
5144                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5145                         fill_dc_dirty_rect(new_plane_state->plane,
5146                                            &dirty_rects[flip_addrs->dirty_rect_count],
5147                                            clips->x1, clips->y1,
5148                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5149                                            &flip_addrs->dirty_rect_count,
5150                                            false);
5151                 return;
5152         }
5153
5154         /*
5155          * MPO is requested. Add entire plane bounding box to dirty rects if
5156          * flipped to or damaged.
5157          *
5158          * If plane is moved or resized, also add old bounding box to dirty
5159          * rects.
5160          */
5161         fb_changed = old_plane_state->fb->base.id !=
5162                      new_plane_state->fb->base.id;
5163         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5164                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5165                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5166                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5167
5168         drm_dbg(plane->dev,
5169                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5170                 new_plane_state->plane->base.id,
5171                 bb_changed, fb_changed, num_clips);
5172
5173         *dirty_regions_changed = bb_changed;
5174
5175         if (bb_changed) {
5176                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5177                                    new_plane_state->crtc_x,
5178                                    new_plane_state->crtc_y,
5179                                    new_plane_state->crtc_w,
5180                                    new_plane_state->crtc_h, &i, false);
5181
5182                 /* Add old plane bounding-box if plane is moved or resized */
5183                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5184                                    old_plane_state->crtc_x,
5185                                    old_plane_state->crtc_y,
5186                                    old_plane_state->crtc_w,
5187                                    old_plane_state->crtc_h, &i, false);
5188         }
5189
5190         if (num_clips) {
5191                 for (; i < num_clips; clips++)
5192                         fill_dc_dirty_rect(new_plane_state->plane,
5193                                            &dirty_rects[i], clips->x1,
5194                                            clips->y1, clips->x2 - clips->x1,
5195                                            clips->y2 - clips->y1, &i, false);
5196         } else if (fb_changed && !bb_changed) {
5197                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5198                                    new_plane_state->crtc_x,
5199                                    new_plane_state->crtc_y,
5200                                    new_plane_state->crtc_w,
5201                                    new_plane_state->crtc_h, &i, false);
5202         }
5203
5204         if (i > DC_MAX_DIRTY_RECTS)
5205                 goto ffu;
5206
5207         flip_addrs->dirty_rect_count = i;
5208         return;
5209
5210 ffu:
5211         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5212                            dm_crtc_state->base.mode.crtc_hdisplay,
5213                            dm_crtc_state->base.mode.crtc_vdisplay,
5214                            &flip_addrs->dirty_rect_count, true);
5215 }
5216
5217 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5218                                            const struct dm_connector_state *dm_state,
5219                                            struct dc_stream_state *stream)
5220 {
5221         enum amdgpu_rmx_type rmx_type;
5222
5223         struct rect src = { 0 }; /* viewport in composition space*/
5224         struct rect dst = { 0 }; /* stream addressable area */
5225
5226         /* no mode. nothing to be done */
5227         if (!mode)
5228                 return;
5229
5230         /* Full screen scaling by default */
5231         src.width = mode->hdisplay;
5232         src.height = mode->vdisplay;
5233         dst.width = stream->timing.h_addressable;
5234         dst.height = stream->timing.v_addressable;
5235
5236         if (dm_state) {
5237                 rmx_type = dm_state->scaling;
5238                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5239                         if (src.width * dst.height <
5240                                         src.height * dst.width) {
5241                                 /* height needs less upscaling/more downscaling */
5242                                 dst.width = src.width *
5243                                                 dst.height / src.height;
5244                         } else {
5245                                 /* width needs less upscaling/more downscaling */
5246                                 dst.height = src.height *
5247                                                 dst.width / src.width;
5248                         }
5249                 } else if (rmx_type == RMX_CENTER) {
5250                         dst = src;
5251                 }
5252
5253                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5254                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5255
5256                 if (dm_state->underscan_enable) {
5257                         dst.x += dm_state->underscan_hborder / 2;
5258                         dst.y += dm_state->underscan_vborder / 2;
5259                         dst.width -= dm_state->underscan_hborder;
5260                         dst.height -= dm_state->underscan_vborder;
5261                 }
5262         }
5263
5264         stream->src = src;
5265         stream->dst = dst;
5266
5267         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5268                       dst.x, dst.y, dst.width, dst.height);
5269
5270 }
5271
5272 static enum dc_color_depth
5273 convert_color_depth_from_display_info(const struct drm_connector *connector,
5274                                       bool is_y420, int requested_bpc)
5275 {
5276         u8 bpc;
5277
5278         if (is_y420) {
5279                 bpc = 8;
5280
5281                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5282                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5283                         bpc = 16;
5284                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5285                         bpc = 12;
5286                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5287                         bpc = 10;
5288         } else {
5289                 bpc = (uint8_t)connector->display_info.bpc;
5290                 /* Assume 8 bpc by default if no bpc is specified. */
5291                 bpc = bpc ? bpc : 8;
5292         }
5293
5294         if (requested_bpc > 0) {
5295                 /*
5296                  * Cap display bpc based on the user requested value.
5297                  *
5298                  * The value for state->max_bpc may not correctly updated
5299                  * depending on when the connector gets added to the state
5300                  * or if this was called outside of atomic check, so it
5301                  * can't be used directly.
5302                  */
5303                 bpc = min_t(u8, bpc, requested_bpc);
5304
5305                 /* Round down to the nearest even number. */
5306                 bpc = bpc - (bpc & 1);
5307         }
5308
5309         switch (bpc) {
5310         case 0:
5311                 /*
5312                  * Temporary Work around, DRM doesn't parse color depth for
5313                  * EDID revision before 1.4
5314                  * TODO: Fix edid parsing
5315                  */
5316                 return COLOR_DEPTH_888;
5317         case 6:
5318                 return COLOR_DEPTH_666;
5319         case 8:
5320                 return COLOR_DEPTH_888;
5321         case 10:
5322                 return COLOR_DEPTH_101010;
5323         case 12:
5324                 return COLOR_DEPTH_121212;
5325         case 14:
5326                 return COLOR_DEPTH_141414;
5327         case 16:
5328                 return COLOR_DEPTH_161616;
5329         default:
5330                 return COLOR_DEPTH_UNDEFINED;
5331         }
5332 }
5333
5334 static enum dc_aspect_ratio
5335 get_aspect_ratio(const struct drm_display_mode *mode_in)
5336 {
5337         /* 1-1 mapping, since both enums follow the HDMI spec. */
5338         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5339 }
5340
5341 static enum dc_color_space
5342 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5343                        const struct drm_connector_state *connector_state)
5344 {
5345         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5346
5347         switch (connector_state->colorspace) {
5348         case DRM_MODE_COLORIMETRY_BT601_YCC:
5349                 if (dc_crtc_timing->flags.Y_ONLY)
5350                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5351                 else
5352                         color_space = COLOR_SPACE_YCBCR601;
5353                 break;
5354         case DRM_MODE_COLORIMETRY_BT709_YCC:
5355                 if (dc_crtc_timing->flags.Y_ONLY)
5356                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5357                 else
5358                         color_space = COLOR_SPACE_YCBCR709;
5359                 break;
5360         case DRM_MODE_COLORIMETRY_OPRGB:
5361                 color_space = COLOR_SPACE_ADOBERGB;
5362                 break;
5363         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5364         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5365                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5366                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5367                 else
5368                         color_space = COLOR_SPACE_2020_YCBCR;
5369                 break;
5370         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5371         default:
5372                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5373                         color_space = COLOR_SPACE_SRGB;
5374                 /*
5375                  * 27030khz is the separation point between HDTV and SDTV
5376                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5377                  * respectively
5378                  */
5379                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5380                         if (dc_crtc_timing->flags.Y_ONLY)
5381                                 color_space =
5382                                         COLOR_SPACE_YCBCR709_LIMITED;
5383                         else
5384                                 color_space = COLOR_SPACE_YCBCR709;
5385                 } else {
5386                         if (dc_crtc_timing->flags.Y_ONLY)
5387                                 color_space =
5388                                         COLOR_SPACE_YCBCR601_LIMITED;
5389                         else
5390                                 color_space = COLOR_SPACE_YCBCR601;
5391                 }
5392                 break;
5393         }
5394
5395         return color_space;
5396 }
5397
5398 static bool adjust_colour_depth_from_display_info(
5399         struct dc_crtc_timing *timing_out,
5400         const struct drm_display_info *info)
5401 {
5402         enum dc_color_depth depth = timing_out->display_color_depth;
5403         int normalized_clk;
5404         do {
5405                 normalized_clk = timing_out->pix_clk_100hz / 10;
5406                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5407                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5408                         normalized_clk /= 2;
5409                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5410                 switch (depth) {
5411                 case COLOR_DEPTH_888:
5412                         break;
5413                 case COLOR_DEPTH_101010:
5414                         normalized_clk = (normalized_clk * 30) / 24;
5415                         break;
5416                 case COLOR_DEPTH_121212:
5417                         normalized_clk = (normalized_clk * 36) / 24;
5418                         break;
5419                 case COLOR_DEPTH_161616:
5420                         normalized_clk = (normalized_clk * 48) / 24;
5421                         break;
5422                 default:
5423                         /* The above depths are the only ones valid for HDMI. */
5424                         return false;
5425                 }
5426                 if (normalized_clk <= info->max_tmds_clock) {
5427                         timing_out->display_color_depth = depth;
5428                         return true;
5429                 }
5430         } while (--depth > COLOR_DEPTH_666);
5431         return false;
5432 }
5433
5434 static void fill_stream_properties_from_drm_display_mode(
5435         struct dc_stream_state *stream,
5436         const struct drm_display_mode *mode_in,
5437         const struct drm_connector *connector,
5438         const struct drm_connector_state *connector_state,
5439         const struct dc_stream_state *old_stream,
5440         int requested_bpc)
5441 {
5442         struct dc_crtc_timing *timing_out = &stream->timing;
5443         const struct drm_display_info *info = &connector->display_info;
5444         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5445         struct hdmi_vendor_infoframe hv_frame;
5446         struct hdmi_avi_infoframe avi_frame;
5447
5448         memset(&hv_frame, 0, sizeof(hv_frame));
5449         memset(&avi_frame, 0, sizeof(avi_frame));
5450
5451         timing_out->h_border_left = 0;
5452         timing_out->h_border_right = 0;
5453         timing_out->v_border_top = 0;
5454         timing_out->v_border_bottom = 0;
5455         /* TODO: un-hardcode */
5456         if (drm_mode_is_420_only(info, mode_in)
5457                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5458                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5459         else if (drm_mode_is_420_also(info, mode_in)
5460                         && aconnector->force_yuv420_output)
5461                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5462         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5463                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5464                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5465         else
5466                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5467
5468         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5469         timing_out->display_color_depth = convert_color_depth_from_display_info(
5470                 connector,
5471                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5472                 requested_bpc);
5473         timing_out->scan_type = SCANNING_TYPE_NODATA;
5474         timing_out->hdmi_vic = 0;
5475
5476         if (old_stream) {
5477                 timing_out->vic = old_stream->timing.vic;
5478                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5479                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5480         } else {
5481                 timing_out->vic = drm_match_cea_mode(mode_in);
5482                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5483                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5484                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5485                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5486         }
5487
5488         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5489                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5490                 timing_out->vic = avi_frame.video_code;
5491                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5492                 timing_out->hdmi_vic = hv_frame.vic;
5493         }
5494
5495         if (is_freesync_video_mode(mode_in, aconnector)) {
5496                 timing_out->h_addressable = mode_in->hdisplay;
5497                 timing_out->h_total = mode_in->htotal;
5498                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5499                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5500                 timing_out->v_total = mode_in->vtotal;
5501                 timing_out->v_addressable = mode_in->vdisplay;
5502                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5503                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5504                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5505         } else {
5506                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5507                 timing_out->h_total = mode_in->crtc_htotal;
5508                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5509                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5510                 timing_out->v_total = mode_in->crtc_vtotal;
5511                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5512                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5513                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5514                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5515         }
5516
5517         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5518
5519         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5520         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5521         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5522                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5523                     drm_mode_is_420_also(info, mode_in) &&
5524                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5525                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5526                         adjust_colour_depth_from_display_info(timing_out, info);
5527                 }
5528         }
5529
5530         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5531 }
5532
5533 static void fill_audio_info(struct audio_info *audio_info,
5534                             const struct drm_connector *drm_connector,
5535                             const struct dc_sink *dc_sink)
5536 {
5537         int i = 0;
5538         int cea_revision = 0;
5539         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5540
5541         audio_info->manufacture_id = edid_caps->manufacturer_id;
5542         audio_info->product_id = edid_caps->product_id;
5543
5544         cea_revision = drm_connector->display_info.cea_rev;
5545
5546         strscpy(audio_info->display_name,
5547                 edid_caps->display_name,
5548                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5549
5550         if (cea_revision >= 3) {
5551                 audio_info->mode_count = edid_caps->audio_mode_count;
5552
5553                 for (i = 0; i < audio_info->mode_count; ++i) {
5554                         audio_info->modes[i].format_code =
5555                                         (enum audio_format_code)
5556                                         (edid_caps->audio_modes[i].format_code);
5557                         audio_info->modes[i].channel_count =
5558                                         edid_caps->audio_modes[i].channel_count;
5559                         audio_info->modes[i].sample_rates.all =
5560                                         edid_caps->audio_modes[i].sample_rate;
5561                         audio_info->modes[i].sample_size =
5562                                         edid_caps->audio_modes[i].sample_size;
5563                 }
5564         }
5565
5566         audio_info->flags.all = edid_caps->speaker_flags;
5567
5568         /* TODO: We only check for the progressive mode, check for interlace mode too */
5569         if (drm_connector->latency_present[0]) {
5570                 audio_info->video_latency = drm_connector->video_latency[0];
5571                 audio_info->audio_latency = drm_connector->audio_latency[0];
5572         }
5573
5574         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5575
5576 }
5577
5578 static void
5579 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5580                                       struct drm_display_mode *dst_mode)
5581 {
5582         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5583         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5584         dst_mode->crtc_clock = src_mode->crtc_clock;
5585         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5586         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5587         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5588         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5589         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5590         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5591         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5592         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5593         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5594         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5595         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5596 }
5597
5598 static void
5599 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5600                                         const struct drm_display_mode *native_mode,
5601                                         bool scale_enabled)
5602 {
5603         if (scale_enabled) {
5604                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5605         } else if (native_mode->clock == drm_mode->clock &&
5606                         native_mode->htotal == drm_mode->htotal &&
5607                         native_mode->vtotal == drm_mode->vtotal) {
5608                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5609         } else {
5610                 /* no scaling nor amdgpu inserted, no need to patch */
5611         }
5612 }
5613
5614 static struct dc_sink *
5615 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5616 {
5617         struct dc_sink_init_data sink_init_data = { 0 };
5618         struct dc_sink *sink = NULL;
5619         sink_init_data.link = aconnector->dc_link;
5620         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5621
5622         sink = dc_sink_create(&sink_init_data);
5623         if (!sink) {
5624                 DRM_ERROR("Failed to create sink!\n");
5625                 return NULL;
5626         }
5627         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5628
5629         return sink;
5630 }
5631
5632 static void set_multisync_trigger_params(
5633                 struct dc_stream_state *stream)
5634 {
5635         struct dc_stream_state *master = NULL;
5636
5637         if (stream->triggered_crtc_reset.enabled) {
5638                 master = stream->triggered_crtc_reset.event_source;
5639                 stream->triggered_crtc_reset.event =
5640                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5641                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5642                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5643         }
5644 }
5645
5646 static void set_master_stream(struct dc_stream_state *stream_set[],
5647                               int stream_count)
5648 {
5649         int j, highest_rfr = 0, master_stream = 0;
5650
5651         for (j = 0;  j < stream_count; j++) {
5652                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5653                         int refresh_rate = 0;
5654
5655                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5656                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5657                         if (refresh_rate > highest_rfr) {
5658                                 highest_rfr = refresh_rate;
5659                                 master_stream = j;
5660                         }
5661                 }
5662         }
5663         for (j = 0;  j < stream_count; j++) {
5664                 if (stream_set[j])
5665                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5666         }
5667 }
5668
5669 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5670 {
5671         int i = 0;
5672         struct dc_stream_state *stream;
5673
5674         if (context->stream_count < 2)
5675                 return;
5676         for (i = 0; i < context->stream_count ; i++) {
5677                 if (!context->streams[i])
5678                         continue;
5679                 /*
5680                  * TODO: add a function to read AMD VSDB bits and set
5681                  * crtc_sync_master.multi_sync_enabled flag
5682                  * For now it's set to false
5683                  */
5684         }
5685
5686         set_master_stream(context->streams, context->stream_count);
5687
5688         for (i = 0; i < context->stream_count ; i++) {
5689                 stream = context->streams[i];
5690
5691                 if (!stream)
5692                         continue;
5693
5694                 set_multisync_trigger_params(stream);
5695         }
5696 }
5697
5698 /**
5699  * DOC: FreeSync Video
5700  *
5701  * When a userspace application wants to play a video, the content follows a
5702  * standard format definition that usually specifies the FPS for that format.
5703  * The below list illustrates some video format and the expected FPS,
5704  * respectively:
5705  *
5706  * - TV/NTSC (23.976 FPS)
5707  * - Cinema (24 FPS)
5708  * - TV/PAL (25 FPS)
5709  * - TV/NTSC (29.97 FPS)
5710  * - TV/NTSC (30 FPS)
5711  * - Cinema HFR (48 FPS)
5712  * - TV/PAL (50 FPS)
5713  * - Commonly used (60 FPS)
5714  * - Multiples of 24 (48,72,96 FPS)
5715  *
5716  * The list of standards video format is not huge and can be added to the
5717  * connector modeset list beforehand. With that, userspace can leverage
5718  * FreeSync to extends the front porch in order to attain the target refresh
5719  * rate. Such a switch will happen seamlessly, without screen blanking or
5720  * reprogramming of the output in any other way. If the userspace requests a
5721  * modesetting change compatible with FreeSync modes that only differ in the
5722  * refresh rate, DC will skip the full update and avoid blink during the
5723  * transition. For example, the video player can change the modesetting from
5724  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5725  * causing any display blink. This same concept can be applied to a mode
5726  * setting change.
5727  */
5728 static struct drm_display_mode *
5729 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5730                 bool use_probed_modes)
5731 {
5732         struct drm_display_mode *m, *m_pref = NULL;
5733         u16 current_refresh, highest_refresh;
5734         struct list_head *list_head = use_probed_modes ?
5735                 &aconnector->base.probed_modes :
5736                 &aconnector->base.modes;
5737
5738         if (aconnector->freesync_vid_base.clock != 0)
5739                 return &aconnector->freesync_vid_base;
5740
5741         /* Find the preferred mode */
5742         list_for_each_entry (m, list_head, head) {
5743                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5744                         m_pref = m;
5745                         break;
5746                 }
5747         }
5748
5749         if (!m_pref) {
5750                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5751                 m_pref = list_first_entry_or_null(
5752                                 &aconnector->base.modes, struct drm_display_mode, head);
5753                 if (!m_pref) {
5754                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5755                         return NULL;
5756                 }
5757         }
5758
5759         highest_refresh = drm_mode_vrefresh(m_pref);
5760
5761         /*
5762          * Find the mode with highest refresh rate with same resolution.
5763          * For some monitors, preferred mode is not the mode with highest
5764          * supported refresh rate.
5765          */
5766         list_for_each_entry (m, list_head, head) {
5767                 current_refresh  = drm_mode_vrefresh(m);
5768
5769                 if (m->hdisplay == m_pref->hdisplay &&
5770                     m->vdisplay == m_pref->vdisplay &&
5771                     highest_refresh < current_refresh) {
5772                         highest_refresh = current_refresh;
5773                         m_pref = m;
5774                 }
5775         }
5776
5777         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5778         return m_pref;
5779 }
5780
5781 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5782                 struct amdgpu_dm_connector *aconnector)
5783 {
5784         struct drm_display_mode *high_mode;
5785         int timing_diff;
5786
5787         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5788         if (!high_mode || !mode)
5789                 return false;
5790
5791         timing_diff = high_mode->vtotal - mode->vtotal;
5792
5793         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5794             high_mode->hdisplay != mode->hdisplay ||
5795             high_mode->vdisplay != mode->vdisplay ||
5796             high_mode->hsync_start != mode->hsync_start ||
5797             high_mode->hsync_end != mode->hsync_end ||
5798             high_mode->htotal != mode->htotal ||
5799             high_mode->hskew != mode->hskew ||
5800             high_mode->vscan != mode->vscan ||
5801             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5802             high_mode->vsync_end - mode->vsync_end != timing_diff)
5803                 return false;
5804         else
5805                 return true;
5806 }
5807
5808 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5809                             struct dc_sink *sink, struct dc_stream_state *stream,
5810                             struct dsc_dec_dpcd_caps *dsc_caps)
5811 {
5812         stream->timing.flags.DSC = 0;
5813         dsc_caps->is_dsc_supported = false;
5814
5815         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5816             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5817                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5818                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5819                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5820                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5821                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5822                                 dsc_caps);
5823         }
5824 }
5825
5826
5827 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5828                                     struct dc_sink *sink, struct dc_stream_state *stream,
5829                                     struct dsc_dec_dpcd_caps *dsc_caps,
5830                                     uint32_t max_dsc_target_bpp_limit_override)
5831 {
5832         const struct dc_link_settings *verified_link_cap = NULL;
5833         u32 link_bw_in_kbps;
5834         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5835         struct dc *dc = sink->ctx->dc;
5836         struct dc_dsc_bw_range bw_range = {0};
5837         struct dc_dsc_config dsc_cfg = {0};
5838         struct dc_dsc_config_options dsc_options = {0};
5839
5840         dc_dsc_get_default_config_option(dc, &dsc_options);
5841         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5842
5843         verified_link_cap = dc_link_get_link_cap(stream->link);
5844         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5845         edp_min_bpp_x16 = 8 * 16;
5846         edp_max_bpp_x16 = 8 * 16;
5847
5848         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5849                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5850
5851         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5852                 edp_min_bpp_x16 = edp_max_bpp_x16;
5853
5854         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5855                                 dc->debug.dsc_min_slice_height_override,
5856                                 edp_min_bpp_x16, edp_max_bpp_x16,
5857                                 dsc_caps,
5858                                 &stream->timing,
5859                                 &bw_range)) {
5860
5861                 if (bw_range.max_kbps < link_bw_in_kbps) {
5862                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5863                                         dsc_caps,
5864                                         &dsc_options,
5865                                         0,
5866                                         &stream->timing,
5867                                         &dsc_cfg)) {
5868                                 stream->timing.dsc_cfg = dsc_cfg;
5869                                 stream->timing.flags.DSC = 1;
5870                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5871                         }
5872                         return;
5873                 }
5874         }
5875
5876         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5877                                 dsc_caps,
5878                                 &dsc_options,
5879                                 link_bw_in_kbps,
5880                                 &stream->timing,
5881                                 &dsc_cfg)) {
5882                 stream->timing.dsc_cfg = dsc_cfg;
5883                 stream->timing.flags.DSC = 1;
5884         }
5885 }
5886
5887
5888 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5889                                         struct dc_sink *sink, struct dc_stream_state *stream,
5890                                         struct dsc_dec_dpcd_caps *dsc_caps)
5891 {
5892         struct drm_connector *drm_connector = &aconnector->base;
5893         u32 link_bandwidth_kbps;
5894         struct dc *dc = sink->ctx->dc;
5895         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5896         u32 dsc_max_supported_bw_in_kbps;
5897         u32 max_dsc_target_bpp_limit_override =
5898                 drm_connector->display_info.max_dsc_bpp;
5899         struct dc_dsc_config_options dsc_options = {0};
5900
5901         dc_dsc_get_default_config_option(dc, &dsc_options);
5902         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5903
5904         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5905                                                         dc_link_get_link_cap(aconnector->dc_link));
5906
5907         /* Set DSC policy according to dsc_clock_en */
5908         dc_dsc_policy_set_enable_dsc_when_not_needed(
5909                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5910
5911         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5912             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5913             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5914
5915                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5916
5917         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5918                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5919                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5920                                                 dsc_caps,
5921                                                 &dsc_options,
5922                                                 link_bandwidth_kbps,
5923                                                 &stream->timing,
5924                                                 &stream->timing.dsc_cfg)) {
5925                                 stream->timing.flags.DSC = 1;
5926                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5927                         }
5928                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5929                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5930                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5931                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5932
5933                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5934                                         max_supported_bw_in_kbps > 0 &&
5935                                         dsc_max_supported_bw_in_kbps > 0)
5936                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5937                                                 dsc_caps,
5938                                                 &dsc_options,
5939                                                 dsc_max_supported_bw_in_kbps,
5940                                                 &stream->timing,
5941                                                 &stream->timing.dsc_cfg)) {
5942                                         stream->timing.flags.DSC = 1;
5943                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5944                                                                          __func__, drm_connector->name);
5945                                 }
5946                 }
5947         }
5948
5949         /* Overwrite the stream flag if DSC is enabled through debugfs */
5950         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5951                 stream->timing.flags.DSC = 1;
5952
5953         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5954                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5955
5956         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5957                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5958
5959         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5960                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5961 }
5962
5963 static struct dc_stream_state *
5964 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5965                        const struct drm_display_mode *drm_mode,
5966                        const struct dm_connector_state *dm_state,
5967                        const struct dc_stream_state *old_stream,
5968                        int requested_bpc)
5969 {
5970         struct drm_display_mode *preferred_mode = NULL;
5971         struct drm_connector *drm_connector;
5972         const struct drm_connector_state *con_state = &dm_state->base;
5973         struct dc_stream_state *stream = NULL;
5974         struct drm_display_mode mode;
5975         struct drm_display_mode saved_mode;
5976         struct drm_display_mode *freesync_mode = NULL;
5977         bool native_mode_found = false;
5978         bool recalculate_timing = false;
5979         bool scale = dm_state->scaling != RMX_OFF;
5980         int mode_refresh;
5981         int preferred_refresh = 0;
5982         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5983         struct dsc_dec_dpcd_caps dsc_caps;
5984
5985         struct dc_sink *sink = NULL;
5986
5987         drm_mode_init(&mode, drm_mode);
5988         memset(&saved_mode, 0, sizeof(saved_mode));
5989
5990         if (aconnector == NULL) {
5991                 DRM_ERROR("aconnector is NULL!\n");
5992                 return stream;
5993         }
5994
5995         drm_connector = &aconnector->base;
5996
5997         if (!aconnector->dc_sink) {
5998                 sink = create_fake_sink(aconnector);
5999                 if (!sink)
6000                         return stream;
6001         } else {
6002                 sink = aconnector->dc_sink;
6003                 dc_sink_retain(sink);
6004         }
6005
6006         stream = dc_create_stream_for_sink(sink);
6007
6008         if (stream == NULL) {
6009                 DRM_ERROR("Failed to create stream for sink!\n");
6010                 goto finish;
6011         }
6012
6013         stream->dm_stream_context = aconnector;
6014
6015         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6016                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6017
6018         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6019                 /* Search for preferred mode */
6020                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6021                         native_mode_found = true;
6022                         break;
6023                 }
6024         }
6025         if (!native_mode_found)
6026                 preferred_mode = list_first_entry_or_null(
6027                                 &aconnector->base.modes,
6028                                 struct drm_display_mode,
6029                                 head);
6030
6031         mode_refresh = drm_mode_vrefresh(&mode);
6032
6033         if (preferred_mode == NULL) {
6034                 /*
6035                  * This may not be an error, the use case is when we have no
6036                  * usermode calls to reset and set mode upon hotplug. In this
6037                  * case, we call set mode ourselves to restore the previous mode
6038                  * and the modelist may not be filled in in time.
6039                  */
6040                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6041         } else {
6042                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6043                 if (recalculate_timing) {
6044                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6045                         drm_mode_copy(&saved_mode, &mode);
6046                         drm_mode_copy(&mode, freesync_mode);
6047                 } else {
6048                         decide_crtc_timing_for_drm_display_mode(
6049                                         &mode, preferred_mode, scale);
6050
6051                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6052                 }
6053         }
6054
6055         if (recalculate_timing)
6056                 drm_mode_set_crtcinfo(&saved_mode, 0);
6057         else
6058                 drm_mode_set_crtcinfo(&mode, 0);
6059
6060         /*
6061         * If scaling is enabled and refresh rate didn't change
6062         * we copy the vic and polarities of the old timings
6063         */
6064         if (!scale || mode_refresh != preferred_refresh)
6065                 fill_stream_properties_from_drm_display_mode(
6066                         stream, &mode, &aconnector->base, con_state, NULL,
6067                         requested_bpc);
6068         else
6069                 fill_stream_properties_from_drm_display_mode(
6070                         stream, &mode, &aconnector->base, con_state, old_stream,
6071                         requested_bpc);
6072
6073         if (aconnector->timing_changed) {
6074                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6075                                 __func__,
6076                                 stream->timing.display_color_depth,
6077                                 aconnector->timing_requested->display_color_depth);
6078                 stream->timing = *aconnector->timing_requested;
6079         }
6080
6081         /* SST DSC determination policy */
6082         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6083         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6084                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6085
6086         update_stream_scaling_settings(&mode, dm_state, stream);
6087
6088         fill_audio_info(
6089                 &stream->audio_info,
6090                 drm_connector,
6091                 sink);
6092
6093         update_stream_signal(stream, sink);
6094
6095         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6096                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6097
6098         if (stream->link->psr_settings.psr_feature_enabled) {
6099                 //
6100                 // should decide stream support vsc sdp colorimetry capability
6101                 // before building vsc info packet
6102                 //
6103                 stream->use_vsc_sdp_for_colorimetry = false;
6104                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6105                         stream->use_vsc_sdp_for_colorimetry =
6106                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6107                 } else {
6108                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6109                                 stream->use_vsc_sdp_for_colorimetry = true;
6110                 }
6111                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6112                         tf = TRANSFER_FUNC_GAMMA_22;
6113                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6114                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6115
6116         }
6117 finish:
6118         dc_sink_release(sink);
6119
6120         return stream;
6121 }
6122
6123 static enum drm_connector_status
6124 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6125 {
6126         bool connected;
6127         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6128
6129         /*
6130          * Notes:
6131          * 1. This interface is NOT called in context of HPD irq.
6132          * 2. This interface *is called* in context of user-mode ioctl. Which
6133          * makes it a bad place for *any* MST-related activity.
6134          */
6135
6136         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6137             !aconnector->fake_enable)
6138                 connected = (aconnector->dc_sink != NULL);
6139         else
6140                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6141                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6142
6143         update_subconnector_property(aconnector);
6144
6145         return (connected ? connector_status_connected :
6146                         connector_status_disconnected);
6147 }
6148
6149 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6150                                             struct drm_connector_state *connector_state,
6151                                             struct drm_property *property,
6152                                             uint64_t val)
6153 {
6154         struct drm_device *dev = connector->dev;
6155         struct amdgpu_device *adev = drm_to_adev(dev);
6156         struct dm_connector_state *dm_old_state =
6157                 to_dm_connector_state(connector->state);
6158         struct dm_connector_state *dm_new_state =
6159                 to_dm_connector_state(connector_state);
6160
6161         int ret = -EINVAL;
6162
6163         if (property == dev->mode_config.scaling_mode_property) {
6164                 enum amdgpu_rmx_type rmx_type;
6165
6166                 switch (val) {
6167                 case DRM_MODE_SCALE_CENTER:
6168                         rmx_type = RMX_CENTER;
6169                         break;
6170                 case DRM_MODE_SCALE_ASPECT:
6171                         rmx_type = RMX_ASPECT;
6172                         break;
6173                 case DRM_MODE_SCALE_FULLSCREEN:
6174                         rmx_type = RMX_FULL;
6175                         break;
6176                 case DRM_MODE_SCALE_NONE:
6177                 default:
6178                         rmx_type = RMX_OFF;
6179                         break;
6180                 }
6181
6182                 if (dm_old_state->scaling == rmx_type)
6183                         return 0;
6184
6185                 dm_new_state->scaling = rmx_type;
6186                 ret = 0;
6187         } else if (property == adev->mode_info.underscan_hborder_property) {
6188                 dm_new_state->underscan_hborder = val;
6189                 ret = 0;
6190         } else if (property == adev->mode_info.underscan_vborder_property) {
6191                 dm_new_state->underscan_vborder = val;
6192                 ret = 0;
6193         } else if (property == adev->mode_info.underscan_property) {
6194                 dm_new_state->underscan_enable = val;
6195                 ret = 0;
6196         } else if (property == adev->mode_info.abm_level_property) {
6197                 dm_new_state->abm_level = val;
6198                 ret = 0;
6199         }
6200
6201         return ret;
6202 }
6203
6204 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6205                                             const struct drm_connector_state *state,
6206                                             struct drm_property *property,
6207                                             uint64_t *val)
6208 {
6209         struct drm_device *dev = connector->dev;
6210         struct amdgpu_device *adev = drm_to_adev(dev);
6211         struct dm_connector_state *dm_state =
6212                 to_dm_connector_state(state);
6213         int ret = -EINVAL;
6214
6215         if (property == dev->mode_config.scaling_mode_property) {
6216                 switch (dm_state->scaling) {
6217                 case RMX_CENTER:
6218                         *val = DRM_MODE_SCALE_CENTER;
6219                         break;
6220                 case RMX_ASPECT:
6221                         *val = DRM_MODE_SCALE_ASPECT;
6222                         break;
6223                 case RMX_FULL:
6224                         *val = DRM_MODE_SCALE_FULLSCREEN;
6225                         break;
6226                 case RMX_OFF:
6227                 default:
6228                         *val = DRM_MODE_SCALE_NONE;
6229                         break;
6230                 }
6231                 ret = 0;
6232         } else if (property == adev->mode_info.underscan_hborder_property) {
6233                 *val = dm_state->underscan_hborder;
6234                 ret = 0;
6235         } else if (property == adev->mode_info.underscan_vborder_property) {
6236                 *val = dm_state->underscan_vborder;
6237                 ret = 0;
6238         } else if (property == adev->mode_info.underscan_property) {
6239                 *val = dm_state->underscan_enable;
6240                 ret = 0;
6241         } else if (property == adev->mode_info.abm_level_property) {
6242                 *val = dm_state->abm_level;
6243                 ret = 0;
6244         }
6245
6246         return ret;
6247 }
6248
6249 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6250 {
6251         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6252
6253         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6254 }
6255
6256 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6257 {
6258         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6259         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6260         struct amdgpu_display_manager *dm = &adev->dm;
6261
6262         /*
6263          * Call only if mst_mgr was initialized before since it's not done
6264          * for all connector types.
6265          */
6266         if (aconnector->mst_mgr.dev)
6267                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6268
6269         if (aconnector->bl_idx != -1) {
6270                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6271                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6272         }
6273
6274         if (aconnector->dc_em_sink)
6275                 dc_sink_release(aconnector->dc_em_sink);
6276         aconnector->dc_em_sink = NULL;
6277         if (aconnector->dc_sink)
6278                 dc_sink_release(aconnector->dc_sink);
6279         aconnector->dc_sink = NULL;
6280
6281         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6282         drm_connector_unregister(connector);
6283         drm_connector_cleanup(connector);
6284         if (aconnector->i2c) {
6285                 i2c_del_adapter(&aconnector->i2c->base);
6286                 kfree(aconnector->i2c);
6287         }
6288         kfree(aconnector->dm_dp_aux.aux.name);
6289
6290         kfree(connector);
6291 }
6292
6293 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6294 {
6295         struct dm_connector_state *state =
6296                 to_dm_connector_state(connector->state);
6297
6298         if (connector->state)
6299                 __drm_atomic_helper_connector_destroy_state(connector->state);
6300
6301         kfree(state);
6302
6303         state = kzalloc(sizeof(*state), GFP_KERNEL);
6304
6305         if (state) {
6306                 state->scaling = RMX_OFF;
6307                 state->underscan_enable = false;
6308                 state->underscan_hborder = 0;
6309                 state->underscan_vborder = 0;
6310                 state->base.max_requested_bpc = 8;
6311                 state->vcpi_slots = 0;
6312                 state->pbn = 0;
6313
6314                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6315                         state->abm_level = amdgpu_dm_abm_level;
6316
6317                 __drm_atomic_helper_connector_reset(connector, &state->base);
6318         }
6319 }
6320
6321 struct drm_connector_state *
6322 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6323 {
6324         struct dm_connector_state *state =
6325                 to_dm_connector_state(connector->state);
6326
6327         struct dm_connector_state *new_state =
6328                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6329
6330         if (!new_state)
6331                 return NULL;
6332
6333         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6334
6335         new_state->freesync_capable = state->freesync_capable;
6336         new_state->abm_level = state->abm_level;
6337         new_state->scaling = state->scaling;
6338         new_state->underscan_enable = state->underscan_enable;
6339         new_state->underscan_hborder = state->underscan_hborder;
6340         new_state->underscan_vborder = state->underscan_vborder;
6341         new_state->vcpi_slots = state->vcpi_slots;
6342         new_state->pbn = state->pbn;
6343         return &new_state->base;
6344 }
6345
6346 static int
6347 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6348 {
6349         struct amdgpu_dm_connector *amdgpu_dm_connector =
6350                 to_amdgpu_dm_connector(connector);
6351         int r;
6352
6353         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6354
6355         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6356             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6357                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6358                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6359                 if (r)
6360                         return r;
6361         }
6362
6363 #if defined(CONFIG_DEBUG_FS)
6364         connector_debugfs_init(amdgpu_dm_connector);
6365 #endif
6366
6367         return 0;
6368 }
6369
6370 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6371 {
6372         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6373         struct dc_link *dc_link = aconnector->dc_link;
6374         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6375         struct edid *edid;
6376
6377         if (!connector->edid_override)
6378                 return;
6379
6380         drm_edid_override_connector_update(&aconnector->base);
6381         edid = aconnector->base.edid_blob_ptr->data;
6382         aconnector->edid = edid;
6383
6384         /* Update emulated (virtual) sink's EDID */
6385         if (dc_em_sink && dc_link) {
6386                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6387                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6388                 dm_helpers_parse_edid_caps(
6389                         dc_link,
6390                         &dc_em_sink->dc_edid,
6391                         &dc_em_sink->edid_caps);
6392         }
6393 }
6394
6395 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6396         .reset = amdgpu_dm_connector_funcs_reset,
6397         .detect = amdgpu_dm_connector_detect,
6398         .fill_modes = drm_helper_probe_single_connector_modes,
6399         .destroy = amdgpu_dm_connector_destroy,
6400         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6401         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6402         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6403         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6404         .late_register = amdgpu_dm_connector_late_register,
6405         .early_unregister = amdgpu_dm_connector_unregister,
6406         .force = amdgpu_dm_connector_funcs_force
6407 };
6408
6409 static int get_modes(struct drm_connector *connector)
6410 {
6411         return amdgpu_dm_connector_get_modes(connector);
6412 }
6413
6414 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6415 {
6416         struct dc_sink_init_data init_params = {
6417                         .link = aconnector->dc_link,
6418                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6419         };
6420         struct edid *edid;
6421
6422         if (!aconnector->base.edid_blob_ptr) {
6423                 /* if connector->edid_override valid, pass
6424                  * it to edid_override to edid_blob_ptr
6425                  */
6426
6427                 drm_edid_override_connector_update(&aconnector->base);
6428
6429                 if (!aconnector->base.edid_blob_ptr) {
6430                         DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6431                                         aconnector->base.name);
6432
6433                         aconnector->base.force = DRM_FORCE_OFF;
6434                         return;
6435                 }
6436         }
6437
6438         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6439
6440         aconnector->edid = edid;
6441
6442         aconnector->dc_em_sink = dc_link_add_remote_sink(
6443                 aconnector->dc_link,
6444                 (uint8_t *)edid,
6445                 (edid->extensions + 1) * EDID_LENGTH,
6446                 &init_params);
6447
6448         if (aconnector->base.force == DRM_FORCE_ON) {
6449                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6450                 aconnector->dc_link->local_sink :
6451                 aconnector->dc_em_sink;
6452                 dc_sink_retain(aconnector->dc_sink);
6453         }
6454 }
6455
6456 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6457 {
6458         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6459
6460         /*
6461          * In case of headless boot with force on for DP managed connector
6462          * Those settings have to be != 0 to get initial modeset
6463          */
6464         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6465                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6466                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6467         }
6468
6469         create_eml_sink(aconnector);
6470 }
6471
6472 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6473                                                 struct dc_stream_state *stream)
6474 {
6475         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6476         struct dc_plane_state *dc_plane_state = NULL;
6477         struct dc_state *dc_state = NULL;
6478
6479         if (!stream)
6480                 goto cleanup;
6481
6482         dc_plane_state = dc_create_plane_state(dc);
6483         if (!dc_plane_state)
6484                 goto cleanup;
6485
6486         dc_state = dc_create_state(dc);
6487         if (!dc_state)
6488                 goto cleanup;
6489
6490         /* populate stream to plane */
6491         dc_plane_state->src_rect.height  = stream->src.height;
6492         dc_plane_state->src_rect.width   = stream->src.width;
6493         dc_plane_state->dst_rect.height  = stream->src.height;
6494         dc_plane_state->dst_rect.width   = stream->src.width;
6495         dc_plane_state->clip_rect.height = stream->src.height;
6496         dc_plane_state->clip_rect.width  = stream->src.width;
6497         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6498         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6499         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6500         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6501         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6502         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6503         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6504         dc_plane_state->rotation = ROTATION_ANGLE_0;
6505         dc_plane_state->is_tiling_rotated = false;
6506         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6507
6508         dc_result = dc_validate_stream(dc, stream);
6509         if (dc_result == DC_OK)
6510                 dc_result = dc_validate_plane(dc, dc_plane_state);
6511
6512         if (dc_result == DC_OK)
6513                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6514
6515         if (dc_result == DC_OK && !dc_add_plane_to_context(
6516                                                 dc,
6517                                                 stream,
6518                                                 dc_plane_state,
6519                                                 dc_state))
6520                 dc_result = DC_FAIL_ATTACH_SURFACES;
6521
6522         if (dc_result == DC_OK)
6523                 dc_result = dc_validate_global_state(dc, dc_state, true);
6524
6525 cleanup:
6526         if (dc_state)
6527                 dc_release_state(dc_state);
6528
6529         if (dc_plane_state)
6530                 dc_plane_state_release(dc_plane_state);
6531
6532         return dc_result;
6533 }
6534
6535 struct dc_stream_state *
6536 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6537                                 const struct drm_display_mode *drm_mode,
6538                                 const struct dm_connector_state *dm_state,
6539                                 const struct dc_stream_state *old_stream)
6540 {
6541         struct drm_connector *connector = &aconnector->base;
6542         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6543         struct dc_stream_state *stream;
6544         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6545         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6546         enum dc_status dc_result = DC_OK;
6547
6548         do {
6549                 stream = create_stream_for_sink(aconnector, drm_mode,
6550                                                 dm_state, old_stream,
6551                                                 requested_bpc);
6552                 if (stream == NULL) {
6553                         DRM_ERROR("Failed to create stream for sink!\n");
6554                         break;
6555                 }
6556
6557                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6558                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6559                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6560
6561                 if (dc_result == DC_OK)
6562                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6563
6564                 if (dc_result != DC_OK) {
6565                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6566                                       drm_mode->hdisplay,
6567                                       drm_mode->vdisplay,
6568                                       drm_mode->clock,
6569                                       dc_result,
6570                                       dc_status_to_str(dc_result));
6571
6572                         dc_stream_release(stream);
6573                         stream = NULL;
6574                         requested_bpc -= 2; /* lower bpc to retry validation */
6575                 }
6576
6577         } while (stream == NULL && requested_bpc >= 6);
6578
6579         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6580                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6581
6582                 aconnector->force_yuv420_output = true;
6583                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6584                                                 dm_state, old_stream);
6585                 aconnector->force_yuv420_output = false;
6586         }
6587
6588         return stream;
6589 }
6590
6591 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6592                                    struct drm_display_mode *mode)
6593 {
6594         int result = MODE_ERROR;
6595         struct dc_sink *dc_sink;
6596         /* TODO: Unhardcode stream count */
6597         struct dc_stream_state *stream;
6598         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6599
6600         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6601                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6602                 return result;
6603
6604         /*
6605          * Only run this the first time mode_valid is called to initilialize
6606          * EDID mgmt
6607          */
6608         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6609                 !aconnector->dc_em_sink)
6610                 handle_edid_mgmt(aconnector);
6611
6612         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6613
6614         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6615                                 aconnector->base.force != DRM_FORCE_ON) {
6616                 DRM_ERROR("dc_sink is NULL!\n");
6617                 goto fail;
6618         }
6619
6620         stream = create_validate_stream_for_sink(aconnector, mode,
6621                                                  to_dm_connector_state(connector->state),
6622                                                  NULL);
6623         if (stream) {
6624                 dc_stream_release(stream);
6625                 result = MODE_OK;
6626         }
6627
6628 fail:
6629         /* TODO: error handling*/
6630         return result;
6631 }
6632
6633 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6634                                 struct dc_info_packet *out)
6635 {
6636         struct hdmi_drm_infoframe frame;
6637         unsigned char buf[30]; /* 26 + 4 */
6638         ssize_t len;
6639         int ret, i;
6640
6641         memset(out, 0, sizeof(*out));
6642
6643         if (!state->hdr_output_metadata)
6644                 return 0;
6645
6646         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6647         if (ret)
6648                 return ret;
6649
6650         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6651         if (len < 0)
6652                 return (int)len;
6653
6654         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6655         if (len != 30)
6656                 return -EINVAL;
6657
6658         /* Prepare the infopacket for DC. */
6659         switch (state->connector->connector_type) {
6660         case DRM_MODE_CONNECTOR_HDMIA:
6661                 out->hb0 = 0x87; /* type */
6662                 out->hb1 = 0x01; /* version */
6663                 out->hb2 = 0x1A; /* length */
6664                 out->sb[0] = buf[3]; /* checksum */
6665                 i = 1;
6666                 break;
6667
6668         case DRM_MODE_CONNECTOR_DisplayPort:
6669         case DRM_MODE_CONNECTOR_eDP:
6670                 out->hb0 = 0x00; /* sdp id, zero */
6671                 out->hb1 = 0x87; /* type */
6672                 out->hb2 = 0x1D; /* payload len - 1 */
6673                 out->hb3 = (0x13 << 2); /* sdp version */
6674                 out->sb[0] = 0x01; /* version */
6675                 out->sb[1] = 0x1A; /* length */
6676                 i = 2;
6677                 break;
6678
6679         default:
6680                 return -EINVAL;
6681         }
6682
6683         memcpy(&out->sb[i], &buf[4], 26);
6684         out->valid = true;
6685
6686         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6687                        sizeof(out->sb), false);
6688
6689         return 0;
6690 }
6691
6692 static int
6693 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6694                                  struct drm_atomic_state *state)
6695 {
6696         struct drm_connector_state *new_con_state =
6697                 drm_atomic_get_new_connector_state(state, conn);
6698         struct drm_connector_state *old_con_state =
6699                 drm_atomic_get_old_connector_state(state, conn);
6700         struct drm_crtc *crtc = new_con_state->crtc;
6701         struct drm_crtc_state *new_crtc_state;
6702         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6703         int ret;
6704
6705         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6706
6707         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6708                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6709                 if (ret < 0)
6710                         return ret;
6711         }
6712
6713         if (!crtc)
6714                 return 0;
6715
6716         if (new_con_state->colorspace != old_con_state->colorspace) {
6717                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6718                 if (IS_ERR(new_crtc_state))
6719                         return PTR_ERR(new_crtc_state);
6720
6721                 new_crtc_state->mode_changed = true;
6722         }
6723
6724         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6725                 struct dc_info_packet hdr_infopacket;
6726
6727                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6728                 if (ret)
6729                         return ret;
6730
6731                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6732                 if (IS_ERR(new_crtc_state))
6733                         return PTR_ERR(new_crtc_state);
6734
6735                 /*
6736                  * DC considers the stream backends changed if the
6737                  * static metadata changes. Forcing the modeset also
6738                  * gives a simple way for userspace to switch from
6739                  * 8bpc to 10bpc when setting the metadata to enter
6740                  * or exit HDR.
6741                  *
6742                  * Changing the static metadata after it's been
6743                  * set is permissible, however. So only force a
6744                  * modeset if we're entering or exiting HDR.
6745                  */
6746                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6747                         !old_con_state->hdr_output_metadata ||
6748                         !new_con_state->hdr_output_metadata;
6749         }
6750
6751         return 0;
6752 }
6753
6754 static const struct drm_connector_helper_funcs
6755 amdgpu_dm_connector_helper_funcs = {
6756         /*
6757          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6758          * modes will be filtered by drm_mode_validate_size(), and those modes
6759          * are missing after user start lightdm. So we need to renew modes list.
6760          * in get_modes call back, not just return the modes count
6761          */
6762         .get_modes = get_modes,
6763         .mode_valid = amdgpu_dm_connector_mode_valid,
6764         .atomic_check = amdgpu_dm_connector_atomic_check,
6765 };
6766
6767 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6768 {
6769
6770 }
6771
6772 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6773 {
6774         switch (display_color_depth) {
6775         case COLOR_DEPTH_666:
6776                 return 6;
6777         case COLOR_DEPTH_888:
6778                 return 8;
6779         case COLOR_DEPTH_101010:
6780                 return 10;
6781         case COLOR_DEPTH_121212:
6782                 return 12;
6783         case COLOR_DEPTH_141414:
6784                 return 14;
6785         case COLOR_DEPTH_161616:
6786                 return 16;
6787         default:
6788                 break;
6789         }
6790         return 0;
6791 }
6792
6793 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6794                                           struct drm_crtc_state *crtc_state,
6795                                           struct drm_connector_state *conn_state)
6796 {
6797         struct drm_atomic_state *state = crtc_state->state;
6798         struct drm_connector *connector = conn_state->connector;
6799         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6800         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6801         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6802         struct drm_dp_mst_topology_mgr *mst_mgr;
6803         struct drm_dp_mst_port *mst_port;
6804         struct drm_dp_mst_topology_state *mst_state;
6805         enum dc_color_depth color_depth;
6806         int clock, bpp = 0;
6807         bool is_y420 = false;
6808
6809         if (!aconnector->mst_output_port)
6810                 return 0;
6811
6812         mst_port = aconnector->mst_output_port;
6813         mst_mgr = &aconnector->mst_root->mst_mgr;
6814
6815         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6816                 return 0;
6817
6818         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6819         if (IS_ERR(mst_state))
6820                 return PTR_ERR(mst_state);
6821
6822         if (!mst_state->pbn_div)
6823                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6824
6825         if (!state->duplicated) {
6826                 int max_bpc = conn_state->max_requested_bpc;
6827                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6828                           aconnector->force_yuv420_output;
6829                 color_depth = convert_color_depth_from_display_info(connector,
6830                                                                     is_y420,
6831                                                                     max_bpc);
6832                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6833                 clock = adjusted_mode->clock;
6834                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6835         }
6836
6837         dm_new_connector_state->vcpi_slots =
6838                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6839                                               dm_new_connector_state->pbn);
6840         if (dm_new_connector_state->vcpi_slots < 0) {
6841                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6842                 return dm_new_connector_state->vcpi_slots;
6843         }
6844         return 0;
6845 }
6846
6847 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6848         .disable = dm_encoder_helper_disable,
6849         .atomic_check = dm_encoder_helper_atomic_check
6850 };
6851
6852 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6853                                             struct dc_state *dc_state,
6854                                             struct dsc_mst_fairness_vars *vars)
6855 {
6856         struct dc_stream_state *stream = NULL;
6857         struct drm_connector *connector;
6858         struct drm_connector_state *new_con_state;
6859         struct amdgpu_dm_connector *aconnector;
6860         struct dm_connector_state *dm_conn_state;
6861         int i, j, ret;
6862         int vcpi, pbn_div, pbn, slot_num = 0;
6863
6864         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6865
6866                 aconnector = to_amdgpu_dm_connector(connector);
6867
6868                 if (!aconnector->mst_output_port)
6869                         continue;
6870
6871                 if (!new_con_state || !new_con_state->crtc)
6872                         continue;
6873
6874                 dm_conn_state = to_dm_connector_state(new_con_state);
6875
6876                 for (j = 0; j < dc_state->stream_count; j++) {
6877                         stream = dc_state->streams[j];
6878                         if (!stream)
6879                                 continue;
6880
6881                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6882                                 break;
6883
6884                         stream = NULL;
6885                 }
6886
6887                 if (!stream)
6888                         continue;
6889
6890                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6891                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6892                 for (j = 0; j < dc_state->stream_count; j++) {
6893                         if (vars[j].aconnector == aconnector) {
6894                                 pbn = vars[j].pbn;
6895                                 break;
6896                         }
6897                 }
6898
6899                 if (j == dc_state->stream_count)
6900                         continue;
6901
6902                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6903
6904                 if (stream->timing.flags.DSC != 1) {
6905                         dm_conn_state->pbn = pbn;
6906                         dm_conn_state->vcpi_slots = slot_num;
6907
6908                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6909                                                            dm_conn_state->pbn, false);
6910                         if (ret < 0)
6911                                 return ret;
6912
6913                         continue;
6914                 }
6915
6916                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6917                 if (vcpi < 0)
6918                         return vcpi;
6919
6920                 dm_conn_state->pbn = pbn;
6921                 dm_conn_state->vcpi_slots = vcpi;
6922         }
6923         return 0;
6924 }
6925
6926 static int to_drm_connector_type(enum signal_type st)
6927 {
6928         switch (st) {
6929         case SIGNAL_TYPE_HDMI_TYPE_A:
6930                 return DRM_MODE_CONNECTOR_HDMIA;
6931         case SIGNAL_TYPE_EDP:
6932                 return DRM_MODE_CONNECTOR_eDP;
6933         case SIGNAL_TYPE_LVDS:
6934                 return DRM_MODE_CONNECTOR_LVDS;
6935         case SIGNAL_TYPE_RGB:
6936                 return DRM_MODE_CONNECTOR_VGA;
6937         case SIGNAL_TYPE_DISPLAY_PORT:
6938         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6939                 return DRM_MODE_CONNECTOR_DisplayPort;
6940         case SIGNAL_TYPE_DVI_DUAL_LINK:
6941         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6942                 return DRM_MODE_CONNECTOR_DVID;
6943         case SIGNAL_TYPE_VIRTUAL:
6944                 return DRM_MODE_CONNECTOR_VIRTUAL;
6945
6946         default:
6947                 return DRM_MODE_CONNECTOR_Unknown;
6948         }
6949 }
6950
6951 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6952 {
6953         struct drm_encoder *encoder;
6954
6955         /* There is only one encoder per connector */
6956         drm_connector_for_each_possible_encoder(connector, encoder)
6957                 return encoder;
6958
6959         return NULL;
6960 }
6961
6962 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6963 {
6964         struct drm_encoder *encoder;
6965         struct amdgpu_encoder *amdgpu_encoder;
6966
6967         encoder = amdgpu_dm_connector_to_encoder(connector);
6968
6969         if (encoder == NULL)
6970                 return;
6971
6972         amdgpu_encoder = to_amdgpu_encoder(encoder);
6973
6974         amdgpu_encoder->native_mode.clock = 0;
6975
6976         if (!list_empty(&connector->probed_modes)) {
6977                 struct drm_display_mode *preferred_mode = NULL;
6978
6979                 list_for_each_entry(preferred_mode,
6980                                     &connector->probed_modes,
6981                                     head) {
6982                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6983                                 amdgpu_encoder->native_mode = *preferred_mode;
6984
6985                         break;
6986                 }
6987
6988         }
6989 }
6990
6991 static struct drm_display_mode *
6992 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6993                              char *name,
6994                              int hdisplay, int vdisplay)
6995 {
6996         struct drm_device *dev = encoder->dev;
6997         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6998         struct drm_display_mode *mode = NULL;
6999         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7000
7001         mode = drm_mode_duplicate(dev, native_mode);
7002
7003         if (mode == NULL)
7004                 return NULL;
7005
7006         mode->hdisplay = hdisplay;
7007         mode->vdisplay = vdisplay;
7008         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7009         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7010
7011         return mode;
7012
7013 }
7014
7015 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7016                                                  struct drm_connector *connector)
7017 {
7018         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7019         struct drm_display_mode *mode = NULL;
7020         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7021         struct amdgpu_dm_connector *amdgpu_dm_connector =
7022                                 to_amdgpu_dm_connector(connector);
7023         int i;
7024         int n;
7025         struct mode_size {
7026                 char name[DRM_DISPLAY_MODE_LEN];
7027                 int w;
7028                 int h;
7029         } common_modes[] = {
7030                 {  "640x480",  640,  480},
7031                 {  "800x600",  800,  600},
7032                 { "1024x768", 1024,  768},
7033                 { "1280x720", 1280,  720},
7034                 { "1280x800", 1280,  800},
7035                 {"1280x1024", 1280, 1024},
7036                 { "1440x900", 1440,  900},
7037                 {"1680x1050", 1680, 1050},
7038                 {"1600x1200", 1600, 1200},
7039                 {"1920x1080", 1920, 1080},
7040                 {"1920x1200", 1920, 1200}
7041         };
7042
7043         n = ARRAY_SIZE(common_modes);
7044
7045         for (i = 0; i < n; i++) {
7046                 struct drm_display_mode *curmode = NULL;
7047                 bool mode_existed = false;
7048
7049                 if (common_modes[i].w > native_mode->hdisplay ||
7050                     common_modes[i].h > native_mode->vdisplay ||
7051                    (common_modes[i].w == native_mode->hdisplay &&
7052                     common_modes[i].h == native_mode->vdisplay))
7053                         continue;
7054
7055                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7056                         if (common_modes[i].w == curmode->hdisplay &&
7057                             common_modes[i].h == curmode->vdisplay) {
7058                                 mode_existed = true;
7059                                 break;
7060                         }
7061                 }
7062
7063                 if (mode_existed)
7064                         continue;
7065
7066                 mode = amdgpu_dm_create_common_mode(encoder,
7067                                 common_modes[i].name, common_modes[i].w,
7068                                 common_modes[i].h);
7069                 if (!mode)
7070                         continue;
7071
7072                 drm_mode_probed_add(connector, mode);
7073                 amdgpu_dm_connector->num_modes++;
7074         }
7075 }
7076
7077 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7078 {
7079         struct drm_encoder *encoder;
7080         struct amdgpu_encoder *amdgpu_encoder;
7081         const struct drm_display_mode *native_mode;
7082
7083         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7084             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7085                 return;
7086
7087         mutex_lock(&connector->dev->mode_config.mutex);
7088         amdgpu_dm_connector_get_modes(connector);
7089         mutex_unlock(&connector->dev->mode_config.mutex);
7090
7091         encoder = amdgpu_dm_connector_to_encoder(connector);
7092         if (!encoder)
7093                 return;
7094
7095         amdgpu_encoder = to_amdgpu_encoder(encoder);
7096
7097         native_mode = &amdgpu_encoder->native_mode;
7098         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7099                 return;
7100
7101         drm_connector_set_panel_orientation_with_quirk(connector,
7102                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7103                                                        native_mode->hdisplay,
7104                                                        native_mode->vdisplay);
7105 }
7106
7107 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7108                                               struct edid *edid)
7109 {
7110         struct amdgpu_dm_connector *amdgpu_dm_connector =
7111                         to_amdgpu_dm_connector(connector);
7112
7113         if (edid) {
7114                 /* empty probed_modes */
7115                 INIT_LIST_HEAD(&connector->probed_modes);
7116                 amdgpu_dm_connector->num_modes =
7117                                 drm_add_edid_modes(connector, edid);
7118
7119                 /* sorting the probed modes before calling function
7120                  * amdgpu_dm_get_native_mode() since EDID can have
7121                  * more than one preferred mode. The modes that are
7122                  * later in the probed mode list could be of higher
7123                  * and preferred resolution. For example, 3840x2160
7124                  * resolution in base EDID preferred timing and 4096x2160
7125                  * preferred resolution in DID extension block later.
7126                  */
7127                 drm_mode_sort(&connector->probed_modes);
7128                 amdgpu_dm_get_native_mode(connector);
7129
7130                 /* Freesync capabilities are reset by calling
7131                  * drm_add_edid_modes() and need to be
7132                  * restored here.
7133                  */
7134                 amdgpu_dm_update_freesync_caps(connector, edid);
7135         } else {
7136                 amdgpu_dm_connector->num_modes = 0;
7137         }
7138 }
7139
7140 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7141                               struct drm_display_mode *mode)
7142 {
7143         struct drm_display_mode *m;
7144
7145         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7146                 if (drm_mode_equal(m, mode))
7147                         return true;
7148         }
7149
7150         return false;
7151 }
7152
7153 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7154 {
7155         const struct drm_display_mode *m;
7156         struct drm_display_mode *new_mode;
7157         uint i;
7158         u32 new_modes_count = 0;
7159
7160         /* Standard FPS values
7161          *
7162          * 23.976       - TV/NTSC
7163          * 24           - Cinema
7164          * 25           - TV/PAL
7165          * 29.97        - TV/NTSC
7166          * 30           - TV/NTSC
7167          * 48           - Cinema HFR
7168          * 50           - TV/PAL
7169          * 60           - Commonly used
7170          * 48,72,96,120 - Multiples of 24
7171          */
7172         static const u32 common_rates[] = {
7173                 23976, 24000, 25000, 29970, 30000,
7174                 48000, 50000, 60000, 72000, 96000, 120000
7175         };
7176
7177         /*
7178          * Find mode with highest refresh rate with the same resolution
7179          * as the preferred mode. Some monitors report a preferred mode
7180          * with lower resolution than the highest refresh rate supported.
7181          */
7182
7183         m = get_highest_refresh_rate_mode(aconnector, true);
7184         if (!m)
7185                 return 0;
7186
7187         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7188                 u64 target_vtotal, target_vtotal_diff;
7189                 u64 num, den;
7190
7191                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7192                         continue;
7193
7194                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7195                     common_rates[i] > aconnector->max_vfreq * 1000)
7196                         continue;
7197
7198                 num = (unsigned long long)m->clock * 1000 * 1000;
7199                 den = common_rates[i] * (unsigned long long)m->htotal;
7200                 target_vtotal = div_u64(num, den);
7201                 target_vtotal_diff = target_vtotal - m->vtotal;
7202
7203                 /* Check for illegal modes */
7204                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7205                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7206                     m->vtotal + target_vtotal_diff < m->vsync_end)
7207                         continue;
7208
7209                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7210                 if (!new_mode)
7211                         goto out;
7212
7213                 new_mode->vtotal += (u16)target_vtotal_diff;
7214                 new_mode->vsync_start += (u16)target_vtotal_diff;
7215                 new_mode->vsync_end += (u16)target_vtotal_diff;
7216                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7217                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7218
7219                 if (!is_duplicate_mode(aconnector, new_mode)) {
7220                         drm_mode_probed_add(&aconnector->base, new_mode);
7221                         new_modes_count += 1;
7222                 } else
7223                         drm_mode_destroy(aconnector->base.dev, new_mode);
7224         }
7225  out:
7226         return new_modes_count;
7227 }
7228
7229 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7230                                                    struct edid *edid)
7231 {
7232         struct amdgpu_dm_connector *amdgpu_dm_connector =
7233                 to_amdgpu_dm_connector(connector);
7234
7235         if (!edid)
7236                 return;
7237
7238         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7239                 amdgpu_dm_connector->num_modes +=
7240                         add_fs_modes(amdgpu_dm_connector);
7241 }
7242
7243 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7244 {
7245         struct amdgpu_dm_connector *amdgpu_dm_connector =
7246                         to_amdgpu_dm_connector(connector);
7247         struct drm_encoder *encoder;
7248         struct edid *edid = amdgpu_dm_connector->edid;
7249         struct dc_link_settings *verified_link_cap =
7250                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7251         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7252
7253         encoder = amdgpu_dm_connector_to_encoder(connector);
7254
7255         if (!drm_edid_is_valid(edid)) {
7256                 amdgpu_dm_connector->num_modes =
7257                                 drm_add_modes_noedid(connector, 640, 480);
7258                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7259                         amdgpu_dm_connector->num_modes +=
7260                                 drm_add_modes_noedid(connector, 1920, 1080);
7261         } else {
7262                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7263                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7264                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7265         }
7266         amdgpu_dm_fbc_init(connector);
7267
7268         return amdgpu_dm_connector->num_modes;
7269 }
7270
7271 static const u32 supported_colorspaces =
7272         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7273         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7274         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7275         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7276
7277 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7278                                      struct amdgpu_dm_connector *aconnector,
7279                                      int connector_type,
7280                                      struct dc_link *link,
7281                                      int link_index)
7282 {
7283         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7284
7285         /*
7286          * Some of the properties below require access to state, like bpc.
7287          * Allocate some default initial connector state with our reset helper.
7288          */
7289         if (aconnector->base.funcs->reset)
7290                 aconnector->base.funcs->reset(&aconnector->base);
7291
7292         aconnector->connector_id = link_index;
7293         aconnector->bl_idx = -1;
7294         aconnector->dc_link = link;
7295         aconnector->base.interlace_allowed = false;
7296         aconnector->base.doublescan_allowed = false;
7297         aconnector->base.stereo_allowed = false;
7298         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7299         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7300         aconnector->audio_inst = -1;
7301         aconnector->pack_sdp_v1_3 = false;
7302         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7303         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7304         mutex_init(&aconnector->hpd_lock);
7305
7306         /*
7307          * configure support HPD hot plug connector_>polled default value is 0
7308          * which means HPD hot plug not supported
7309          */
7310         switch (connector_type) {
7311         case DRM_MODE_CONNECTOR_HDMIA:
7312                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7313                 aconnector->base.ycbcr_420_allowed =
7314                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7315                 break;
7316         case DRM_MODE_CONNECTOR_DisplayPort:
7317                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7318                 link->link_enc = link_enc_cfg_get_link_enc(link);
7319                 ASSERT(link->link_enc);
7320                 if (link->link_enc)
7321                         aconnector->base.ycbcr_420_allowed =
7322                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7323                 break;
7324         case DRM_MODE_CONNECTOR_DVID:
7325                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7326                 break;
7327         default:
7328                 break;
7329         }
7330
7331         drm_object_attach_property(&aconnector->base.base,
7332                                 dm->ddev->mode_config.scaling_mode_property,
7333                                 DRM_MODE_SCALE_NONE);
7334
7335         drm_object_attach_property(&aconnector->base.base,
7336                                 adev->mode_info.underscan_property,
7337                                 UNDERSCAN_OFF);
7338         drm_object_attach_property(&aconnector->base.base,
7339                                 adev->mode_info.underscan_hborder_property,
7340                                 0);
7341         drm_object_attach_property(&aconnector->base.base,
7342                                 adev->mode_info.underscan_vborder_property,
7343                                 0);
7344
7345         if (!aconnector->mst_root)
7346                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7347
7348         aconnector->base.state->max_bpc = 16;
7349         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7350
7351         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7352             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7353                 drm_object_attach_property(&aconnector->base.base,
7354                                 adev->mode_info.abm_level_property, 0);
7355         }
7356
7357         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7358                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7359                         drm_connector_attach_colorspace_property(&aconnector->base);
7360         } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7361                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7362                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7363                         drm_connector_attach_colorspace_property(&aconnector->base);
7364         }
7365
7366         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7367             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7368             connector_type == DRM_MODE_CONNECTOR_eDP) {
7369                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7370
7371                 if (!aconnector->mst_root)
7372                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7373
7374                 if (adev->dm.hdcp_workqueue)
7375                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7376         }
7377 }
7378
7379 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7380                               struct i2c_msg *msgs, int num)
7381 {
7382         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7383         struct ddc_service *ddc_service = i2c->ddc_service;
7384         struct i2c_command cmd;
7385         int i;
7386         int result = -EIO;
7387
7388         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7389
7390         if (!cmd.payloads)
7391                 return result;
7392
7393         cmd.number_of_payloads = num;
7394         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7395         cmd.speed = 100;
7396
7397         for (i = 0; i < num; i++) {
7398                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7399                 cmd.payloads[i].address = msgs[i].addr;
7400                 cmd.payloads[i].length = msgs[i].len;
7401                 cmd.payloads[i].data = msgs[i].buf;
7402         }
7403
7404         if (dc_submit_i2c(
7405                         ddc_service->ctx->dc,
7406                         ddc_service->link->link_index,
7407                         &cmd))
7408                 result = num;
7409
7410         kfree(cmd.payloads);
7411         return result;
7412 }
7413
7414 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7415 {
7416         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7417 }
7418
7419 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7420         .master_xfer = amdgpu_dm_i2c_xfer,
7421         .functionality = amdgpu_dm_i2c_func,
7422 };
7423
7424 static struct amdgpu_i2c_adapter *
7425 create_i2c(struct ddc_service *ddc_service,
7426            int link_index,
7427            int *res)
7428 {
7429         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7430         struct amdgpu_i2c_adapter *i2c;
7431
7432         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7433         if (!i2c)
7434                 return NULL;
7435         i2c->base.owner = THIS_MODULE;
7436         i2c->base.class = I2C_CLASS_DDC;
7437         i2c->base.dev.parent = &adev->pdev->dev;
7438         i2c->base.algo = &amdgpu_dm_i2c_algo;
7439         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7440         i2c_set_adapdata(&i2c->base, i2c);
7441         i2c->ddc_service = ddc_service;
7442
7443         return i2c;
7444 }
7445
7446
7447 /*
7448  * Note: this function assumes that dc_link_detect() was called for the
7449  * dc_link which will be represented by this aconnector.
7450  */
7451 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7452                                     struct amdgpu_dm_connector *aconnector,
7453                                     u32 link_index,
7454                                     struct amdgpu_encoder *aencoder)
7455 {
7456         int res = 0;
7457         int connector_type;
7458         struct dc *dc = dm->dc;
7459         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7460         struct amdgpu_i2c_adapter *i2c;
7461
7462         link->priv = aconnector;
7463
7464         DRM_DEBUG_DRIVER("%s()\n", __func__);
7465
7466         i2c = create_i2c(link->ddc, link->link_index, &res);
7467         if (!i2c) {
7468                 DRM_ERROR("Failed to create i2c adapter data\n");
7469                 return -ENOMEM;
7470         }
7471
7472         aconnector->i2c = i2c;
7473         res = i2c_add_adapter(&i2c->base);
7474
7475         if (res) {
7476                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7477                 goto out_free;
7478         }
7479
7480         connector_type = to_drm_connector_type(link->connector_signal);
7481
7482         res = drm_connector_init_with_ddc(
7483                         dm->ddev,
7484                         &aconnector->base,
7485                         &amdgpu_dm_connector_funcs,
7486                         connector_type,
7487                         &i2c->base);
7488
7489         if (res) {
7490                 DRM_ERROR("connector_init failed\n");
7491                 aconnector->connector_id = -1;
7492                 goto out_free;
7493         }
7494
7495         drm_connector_helper_add(
7496                         &aconnector->base,
7497                         &amdgpu_dm_connector_helper_funcs);
7498
7499         amdgpu_dm_connector_init_helper(
7500                 dm,
7501                 aconnector,
7502                 connector_type,
7503                 link,
7504                 link_index);
7505
7506         drm_connector_attach_encoder(
7507                 &aconnector->base, &aencoder->base);
7508
7509         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7510                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7511                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7512
7513 out_free:
7514         if (res) {
7515                 kfree(i2c);
7516                 aconnector->i2c = NULL;
7517         }
7518         return res;
7519 }
7520
7521 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7522 {
7523         switch (adev->mode_info.num_crtc) {
7524         case 1:
7525                 return 0x1;
7526         case 2:
7527                 return 0x3;
7528         case 3:
7529                 return 0x7;
7530         case 4:
7531                 return 0xf;
7532         case 5:
7533                 return 0x1f;
7534         case 6:
7535         default:
7536                 return 0x3f;
7537         }
7538 }
7539
7540 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7541                                   struct amdgpu_encoder *aencoder,
7542                                   uint32_t link_index)
7543 {
7544         struct amdgpu_device *adev = drm_to_adev(dev);
7545
7546         int res = drm_encoder_init(dev,
7547                                    &aencoder->base,
7548                                    &amdgpu_dm_encoder_funcs,
7549                                    DRM_MODE_ENCODER_TMDS,
7550                                    NULL);
7551
7552         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7553
7554         if (!res)
7555                 aencoder->encoder_id = link_index;
7556         else
7557                 aencoder->encoder_id = -1;
7558
7559         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7560
7561         return res;
7562 }
7563
7564 static void manage_dm_interrupts(struct amdgpu_device *adev,
7565                                  struct amdgpu_crtc *acrtc,
7566                                  bool enable)
7567 {
7568         /*
7569          * We have no guarantee that the frontend index maps to the same
7570          * backend index - some even map to more than one.
7571          *
7572          * TODO: Use a different interrupt or check DC itself for the mapping.
7573          */
7574         int irq_type =
7575                 amdgpu_display_crtc_idx_to_irq_type(
7576                         adev,
7577                         acrtc->crtc_id);
7578
7579         if (enable) {
7580                 drm_crtc_vblank_on(&acrtc->base);
7581                 amdgpu_irq_get(
7582                         adev,
7583                         &adev->pageflip_irq,
7584                         irq_type);
7585 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7586                 amdgpu_irq_get(
7587                         adev,
7588                         &adev->vline0_irq,
7589                         irq_type);
7590 #endif
7591         } else {
7592 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7593                 amdgpu_irq_put(
7594                         adev,
7595                         &adev->vline0_irq,
7596                         irq_type);
7597 #endif
7598                 amdgpu_irq_put(
7599                         adev,
7600                         &adev->pageflip_irq,
7601                         irq_type);
7602                 drm_crtc_vblank_off(&acrtc->base);
7603         }
7604 }
7605
7606 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7607                                       struct amdgpu_crtc *acrtc)
7608 {
7609         int irq_type =
7610                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7611
7612         /**
7613          * This reads the current state for the IRQ and force reapplies
7614          * the setting to hardware.
7615          */
7616         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7617 }
7618
7619 static bool
7620 is_scaling_state_different(const struct dm_connector_state *dm_state,
7621                            const struct dm_connector_state *old_dm_state)
7622 {
7623         if (dm_state->scaling != old_dm_state->scaling)
7624                 return true;
7625         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7626                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7627                         return true;
7628         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7629                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7630                         return true;
7631         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7632                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7633                 return true;
7634         return false;
7635 }
7636
7637 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7638                                             struct drm_crtc_state *old_crtc_state,
7639                                             struct drm_connector_state *new_conn_state,
7640                                             struct drm_connector_state *old_conn_state,
7641                                             const struct drm_connector *connector,
7642                                             struct hdcp_workqueue *hdcp_w)
7643 {
7644         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7645         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7646
7647         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7648                 connector->index, connector->status, connector->dpms);
7649         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7650                 old_conn_state->content_protection, new_conn_state->content_protection);
7651
7652         if (old_crtc_state)
7653                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7654                 old_crtc_state->enable,
7655                 old_crtc_state->active,
7656                 old_crtc_state->mode_changed,
7657                 old_crtc_state->active_changed,
7658                 old_crtc_state->connectors_changed);
7659
7660         if (new_crtc_state)
7661                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7662                 new_crtc_state->enable,
7663                 new_crtc_state->active,
7664                 new_crtc_state->mode_changed,
7665                 new_crtc_state->active_changed,
7666                 new_crtc_state->connectors_changed);
7667
7668         /* hdcp content type change */
7669         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7670             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7671                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7672                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7673                 return true;
7674         }
7675
7676         /* CP is being re enabled, ignore this */
7677         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7678             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7679                 if (new_crtc_state && new_crtc_state->mode_changed) {
7680                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7681                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7682                         return true;
7683                 }
7684                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7685                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7686                 return false;
7687         }
7688
7689         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7690          *
7691          * Handles:     UNDESIRED -> ENABLED
7692          */
7693         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7694             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7695                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7696
7697         /* Stream removed and re-enabled
7698          *
7699          * Can sometimes overlap with the HPD case,
7700          * thus set update_hdcp to false to avoid
7701          * setting HDCP multiple times.
7702          *
7703          * Handles:     DESIRED -> DESIRED (Special case)
7704          */
7705         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7706                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7707                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7708                 dm_con_state->update_hdcp = false;
7709                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7710                         __func__);
7711                 return true;
7712         }
7713
7714         /* Hot-plug, headless s3, dpms
7715          *
7716          * Only start HDCP if the display is connected/enabled.
7717          * update_hdcp flag will be set to false until the next
7718          * HPD comes in.
7719          *
7720          * Handles:     DESIRED -> DESIRED (Special case)
7721          */
7722         if (dm_con_state->update_hdcp &&
7723         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7724         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7725                 dm_con_state->update_hdcp = false;
7726                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7727                         __func__);
7728                 return true;
7729         }
7730
7731         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7732                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7733                         if (new_crtc_state && new_crtc_state->mode_changed) {
7734                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7735                                         __func__);
7736                                 return true;
7737                         }
7738                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7739                                 __func__);
7740                         return false;
7741                 }
7742
7743                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7744                 return false;
7745         }
7746
7747         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7748                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7749                         __func__);
7750                 return true;
7751         }
7752
7753         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7754         return false;
7755 }
7756
7757 static void remove_stream(struct amdgpu_device *adev,
7758                           struct amdgpu_crtc *acrtc,
7759                           struct dc_stream_state *stream)
7760 {
7761         /* this is the update mode case */
7762
7763         acrtc->otg_inst = -1;
7764         acrtc->enabled = false;
7765 }
7766
7767 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7768 {
7769
7770         assert_spin_locked(&acrtc->base.dev->event_lock);
7771         WARN_ON(acrtc->event);
7772
7773         acrtc->event = acrtc->base.state->event;
7774
7775         /* Set the flip status */
7776         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7777
7778         /* Mark this event as consumed */
7779         acrtc->base.state->event = NULL;
7780
7781         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7782                      acrtc->crtc_id);
7783 }
7784
7785 static void update_freesync_state_on_stream(
7786         struct amdgpu_display_manager *dm,
7787         struct dm_crtc_state *new_crtc_state,
7788         struct dc_stream_state *new_stream,
7789         struct dc_plane_state *surface,
7790         u32 flip_timestamp_in_us)
7791 {
7792         struct mod_vrr_params vrr_params;
7793         struct dc_info_packet vrr_infopacket = {0};
7794         struct amdgpu_device *adev = dm->adev;
7795         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7796         unsigned long flags;
7797         bool pack_sdp_v1_3 = false;
7798         struct amdgpu_dm_connector *aconn;
7799         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7800
7801         if (!new_stream)
7802                 return;
7803
7804         /*
7805          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7806          * For now it's sufficient to just guard against these conditions.
7807          */
7808
7809         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7810                 return;
7811
7812         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7813         vrr_params = acrtc->dm_irq_params.vrr_params;
7814
7815         if (surface) {
7816                 mod_freesync_handle_preflip(
7817                         dm->freesync_module,
7818                         surface,
7819                         new_stream,
7820                         flip_timestamp_in_us,
7821                         &vrr_params);
7822
7823                 if (adev->family < AMDGPU_FAMILY_AI &&
7824                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7825                         mod_freesync_handle_v_update(dm->freesync_module,
7826                                                      new_stream, &vrr_params);
7827
7828                         /* Need to call this before the frame ends. */
7829                         dc_stream_adjust_vmin_vmax(dm->dc,
7830                                                    new_crtc_state->stream,
7831                                                    &vrr_params.adjust);
7832                 }
7833         }
7834
7835         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7836
7837         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7838                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7839
7840                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7841                         packet_type = PACKET_TYPE_FS_V1;
7842                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7843                         packet_type = PACKET_TYPE_FS_V2;
7844                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7845                         packet_type = PACKET_TYPE_FS_V3;
7846
7847                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7848                                         &new_stream->adaptive_sync_infopacket);
7849         }
7850
7851         mod_freesync_build_vrr_infopacket(
7852                 dm->freesync_module,
7853                 new_stream,
7854                 &vrr_params,
7855                 packet_type,
7856                 TRANSFER_FUNC_UNKNOWN,
7857                 &vrr_infopacket,
7858                 pack_sdp_v1_3);
7859
7860         new_crtc_state->freesync_vrr_info_changed |=
7861                 (memcmp(&new_crtc_state->vrr_infopacket,
7862                         &vrr_infopacket,
7863                         sizeof(vrr_infopacket)) != 0);
7864
7865         acrtc->dm_irq_params.vrr_params = vrr_params;
7866         new_crtc_state->vrr_infopacket = vrr_infopacket;
7867
7868         new_stream->vrr_infopacket = vrr_infopacket;
7869         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7870
7871         if (new_crtc_state->freesync_vrr_info_changed)
7872                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7873                               new_crtc_state->base.crtc->base.id,
7874                               (int)new_crtc_state->base.vrr_enabled,
7875                               (int)vrr_params.state);
7876
7877         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7878 }
7879
7880 static void update_stream_irq_parameters(
7881         struct amdgpu_display_manager *dm,
7882         struct dm_crtc_state *new_crtc_state)
7883 {
7884         struct dc_stream_state *new_stream = new_crtc_state->stream;
7885         struct mod_vrr_params vrr_params;
7886         struct mod_freesync_config config = new_crtc_state->freesync_config;
7887         struct amdgpu_device *adev = dm->adev;
7888         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7889         unsigned long flags;
7890
7891         if (!new_stream)
7892                 return;
7893
7894         /*
7895          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7896          * For now it's sufficient to just guard against these conditions.
7897          */
7898         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7899                 return;
7900
7901         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7902         vrr_params = acrtc->dm_irq_params.vrr_params;
7903
7904         if (new_crtc_state->vrr_supported &&
7905             config.min_refresh_in_uhz &&
7906             config.max_refresh_in_uhz) {
7907                 /*
7908                  * if freesync compatible mode was set, config.state will be set
7909                  * in atomic check
7910                  */
7911                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7912                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7913                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7914                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7915                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7916                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7917                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7918                 } else {
7919                         config.state = new_crtc_state->base.vrr_enabled ?
7920                                                      VRR_STATE_ACTIVE_VARIABLE :
7921                                                      VRR_STATE_INACTIVE;
7922                 }
7923         } else {
7924                 config.state = VRR_STATE_UNSUPPORTED;
7925         }
7926
7927         mod_freesync_build_vrr_params(dm->freesync_module,
7928                                       new_stream,
7929                                       &config, &vrr_params);
7930
7931         new_crtc_state->freesync_config = config;
7932         /* Copy state for access from DM IRQ handler */
7933         acrtc->dm_irq_params.freesync_config = config;
7934         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7935         acrtc->dm_irq_params.vrr_params = vrr_params;
7936         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7937 }
7938
7939 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7940                                             struct dm_crtc_state *new_state)
7941 {
7942         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7943         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7944
7945         if (!old_vrr_active && new_vrr_active) {
7946                 /* Transition VRR inactive -> active:
7947                  * While VRR is active, we must not disable vblank irq, as a
7948                  * reenable after disable would compute bogus vblank/pflip
7949                  * timestamps if it likely happened inside display front-porch.
7950                  *
7951                  * We also need vupdate irq for the actual core vblank handling
7952                  * at end of vblank.
7953                  */
7954                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7955                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7956                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7957                                  __func__, new_state->base.crtc->base.id);
7958         } else if (old_vrr_active && !new_vrr_active) {
7959                 /* Transition VRR active -> inactive:
7960                  * Allow vblank irq disable again for fixed refresh rate.
7961                  */
7962                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7963                 drm_crtc_vblank_put(new_state->base.crtc);
7964                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7965                                  __func__, new_state->base.crtc->base.id);
7966         }
7967 }
7968
7969 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7970 {
7971         struct drm_plane *plane;
7972         struct drm_plane_state *old_plane_state;
7973         int i;
7974
7975         /*
7976          * TODO: Make this per-stream so we don't issue redundant updates for
7977          * commits with multiple streams.
7978          */
7979         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7980                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7981                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7982 }
7983
7984 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7985 {
7986         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7987
7988         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7989 }
7990
7991 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7992                                     struct dc_state *dc_state,
7993                                     struct drm_device *dev,
7994                                     struct amdgpu_display_manager *dm,
7995                                     struct drm_crtc *pcrtc,
7996                                     bool wait_for_vblank)
7997 {
7998         u32 i;
7999         u64 timestamp_ns = ktime_get_ns();
8000         struct drm_plane *plane;
8001         struct drm_plane_state *old_plane_state, *new_plane_state;
8002         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8003         struct drm_crtc_state *new_pcrtc_state =
8004                         drm_atomic_get_new_crtc_state(state, pcrtc);
8005         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8006         struct dm_crtc_state *dm_old_crtc_state =
8007                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8008         int planes_count = 0, vpos, hpos;
8009         unsigned long flags;
8010         u32 target_vblank, last_flip_vblank;
8011         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8012         bool cursor_update = false;
8013         bool pflip_present = false;
8014         bool dirty_rects_changed = false;
8015         struct {
8016                 struct dc_surface_update surface_updates[MAX_SURFACES];
8017                 struct dc_plane_info plane_infos[MAX_SURFACES];
8018                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8019                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8020                 struct dc_stream_update stream_update;
8021         } *bundle;
8022
8023         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8024
8025         if (!bundle) {
8026                 dm_error("Failed to allocate update bundle\n");
8027                 goto cleanup;
8028         }
8029
8030         /*
8031          * Disable the cursor first if we're disabling all the planes.
8032          * It'll remain on the screen after the planes are re-enabled
8033          * if we don't.
8034          */
8035         if (acrtc_state->active_planes == 0)
8036                 amdgpu_dm_commit_cursors(state);
8037
8038         /* update planes when needed */
8039         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8040                 struct drm_crtc *crtc = new_plane_state->crtc;
8041                 struct drm_crtc_state *new_crtc_state;
8042                 struct drm_framebuffer *fb = new_plane_state->fb;
8043                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8044                 bool plane_needs_flip;
8045                 struct dc_plane_state *dc_plane;
8046                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8047
8048                 /* Cursor plane is handled after stream updates */
8049                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8050                         if ((fb && crtc == pcrtc) ||
8051                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8052                                 cursor_update = true;
8053
8054                         continue;
8055                 }
8056
8057                 if (!fb || !crtc || pcrtc != crtc)
8058                         continue;
8059
8060                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8061                 if (!new_crtc_state->active)
8062                         continue;
8063
8064                 dc_plane = dm_new_plane_state->dc_state;
8065                 if (!dc_plane)
8066                         continue;
8067
8068                 bundle->surface_updates[planes_count].surface = dc_plane;
8069                 if (new_pcrtc_state->color_mgmt_changed) {
8070                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8071                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8072                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8073                 }
8074
8075                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8076                                      &bundle->scaling_infos[planes_count]);
8077
8078                 bundle->surface_updates[planes_count].scaling_info =
8079                         &bundle->scaling_infos[planes_count];
8080
8081                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8082
8083                 pflip_present = pflip_present || plane_needs_flip;
8084
8085                 if (!plane_needs_flip) {
8086                         planes_count += 1;
8087                         continue;
8088                 }
8089
8090                 fill_dc_plane_info_and_addr(
8091                         dm->adev, new_plane_state,
8092                         afb->tiling_flags,
8093                         &bundle->plane_infos[planes_count],
8094                         &bundle->flip_addrs[planes_count].address,
8095                         afb->tmz_surface, false);
8096
8097                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8098                                  new_plane_state->plane->index,
8099                                  bundle->plane_infos[planes_count].dcc.enable);
8100
8101                 bundle->surface_updates[planes_count].plane_info =
8102                         &bundle->plane_infos[planes_count];
8103
8104                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8105                         fill_dc_dirty_rects(plane, old_plane_state,
8106                                             new_plane_state, new_crtc_state,
8107                                             &bundle->flip_addrs[planes_count],
8108                                             &dirty_rects_changed);
8109
8110                         /*
8111                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8112                          * and enabled it again after dirty regions are stable to avoid video glitch.
8113                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8114                          * during the PSR-SU was disabled.
8115                          */
8116                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8117                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8118 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8119                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8120 #endif
8121                             dirty_rects_changed) {
8122                                 mutex_lock(&dm->dc_lock);
8123                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8124                                 timestamp_ns;
8125                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8126                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8127                                 mutex_unlock(&dm->dc_lock);
8128                         }
8129                 }
8130
8131                 /*
8132                  * Only allow immediate flips for fast updates that don't
8133                  * change memory domain, FB pitch, DCC state, rotation or
8134                  * mirroring.
8135                  */
8136                 bundle->flip_addrs[planes_count].flip_immediate =
8137                         crtc->state->async_flip &&
8138                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8139                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8140
8141                 timestamp_ns = ktime_get_ns();
8142                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8143                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8144                 bundle->surface_updates[planes_count].surface = dc_plane;
8145
8146                 if (!bundle->surface_updates[planes_count].surface) {
8147                         DRM_ERROR("No surface for CRTC: id=%d\n",
8148                                         acrtc_attach->crtc_id);
8149                         continue;
8150                 }
8151
8152                 if (plane == pcrtc->primary)
8153                         update_freesync_state_on_stream(
8154                                 dm,
8155                                 acrtc_state,
8156                                 acrtc_state->stream,
8157                                 dc_plane,
8158                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8159
8160                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8161                                  __func__,
8162                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8163                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8164
8165                 planes_count += 1;
8166
8167         }
8168
8169         if (pflip_present) {
8170                 if (!vrr_active) {
8171                         /* Use old throttling in non-vrr fixed refresh rate mode
8172                          * to keep flip scheduling based on target vblank counts
8173                          * working in a backwards compatible way, e.g., for
8174                          * clients using the GLX_OML_sync_control extension or
8175                          * DRI3/Present extension with defined target_msc.
8176                          */
8177                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8178                 }
8179                 else {
8180                         /* For variable refresh rate mode only:
8181                          * Get vblank of last completed flip to avoid > 1 vrr
8182                          * flips per video frame by use of throttling, but allow
8183                          * flip programming anywhere in the possibly large
8184                          * variable vrr vblank interval for fine-grained flip
8185                          * timing control and more opportunity to avoid stutter
8186                          * on late submission of flips.
8187                          */
8188                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8189                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8190                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8191                 }
8192
8193                 target_vblank = last_flip_vblank + wait_for_vblank;
8194
8195                 /*
8196                  * Wait until we're out of the vertical blank period before the one
8197                  * targeted by the flip
8198                  */
8199                 while ((acrtc_attach->enabled &&
8200                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8201                                                             0, &vpos, &hpos, NULL,
8202                                                             NULL, &pcrtc->hwmode)
8203                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8204                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8205                         (int)(target_vblank -
8206                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8207                         usleep_range(1000, 1100);
8208                 }
8209
8210                 /**
8211                  * Prepare the flip event for the pageflip interrupt to handle.
8212                  *
8213                  * This only works in the case where we've already turned on the
8214                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8215                  * from 0 -> n planes we have to skip a hardware generated event
8216                  * and rely on sending it from software.
8217                  */
8218                 if (acrtc_attach->base.state->event &&
8219                     acrtc_state->active_planes > 0) {
8220                         drm_crtc_vblank_get(pcrtc);
8221
8222                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8223
8224                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8225                         prepare_flip_isr(acrtc_attach);
8226
8227                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8228                 }
8229
8230                 if (acrtc_state->stream) {
8231                         if (acrtc_state->freesync_vrr_info_changed)
8232                                 bundle->stream_update.vrr_infopacket =
8233                                         &acrtc_state->stream->vrr_infopacket;
8234                 }
8235         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8236                    acrtc_attach->base.state->event) {
8237                 drm_crtc_vblank_get(pcrtc);
8238
8239                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8240
8241                 acrtc_attach->event = acrtc_attach->base.state->event;
8242                 acrtc_attach->base.state->event = NULL;
8243
8244                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8245         }
8246
8247         /* Update the planes if changed or disable if we don't have any. */
8248         if ((planes_count || acrtc_state->active_planes == 0) &&
8249                 acrtc_state->stream) {
8250                 /*
8251                  * If PSR or idle optimizations are enabled then flush out
8252                  * any pending work before hardware programming.
8253                  */
8254                 if (dm->vblank_control_workqueue)
8255                         flush_workqueue(dm->vblank_control_workqueue);
8256
8257                 bundle->stream_update.stream = acrtc_state->stream;
8258                 if (new_pcrtc_state->mode_changed) {
8259                         bundle->stream_update.src = acrtc_state->stream->src;
8260                         bundle->stream_update.dst = acrtc_state->stream->dst;
8261                 }
8262
8263                 if (new_pcrtc_state->color_mgmt_changed) {
8264                         /*
8265                          * TODO: This isn't fully correct since we've actually
8266                          * already modified the stream in place.
8267                          */
8268                         bundle->stream_update.gamut_remap =
8269                                 &acrtc_state->stream->gamut_remap_matrix;
8270                         bundle->stream_update.output_csc_transform =
8271                                 &acrtc_state->stream->csc_color_matrix;
8272                         bundle->stream_update.out_transfer_func =
8273                                 acrtc_state->stream->out_transfer_func;
8274                 }
8275
8276                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8277                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8278                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8279
8280                 /*
8281                  * If FreeSync state on the stream has changed then we need to
8282                  * re-adjust the min/max bounds now that DC doesn't handle this
8283                  * as part of commit.
8284                  */
8285                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8286                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8287                         dc_stream_adjust_vmin_vmax(
8288                                 dm->dc, acrtc_state->stream,
8289                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8290                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8291                 }
8292                 mutex_lock(&dm->dc_lock);
8293                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8294                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8295                         amdgpu_dm_psr_disable(acrtc_state->stream);
8296
8297                 update_planes_and_stream_adapter(dm->dc,
8298                                          acrtc_state->update_type,
8299                                          planes_count,
8300                                          acrtc_state->stream,
8301                                          &bundle->stream_update,
8302                                          bundle->surface_updates);
8303
8304                 /**
8305                  * Enable or disable the interrupts on the backend.
8306                  *
8307                  * Most pipes are put into power gating when unused.
8308                  *
8309                  * When power gating is enabled on a pipe we lose the
8310                  * interrupt enablement state when power gating is disabled.
8311                  *
8312                  * So we need to update the IRQ control state in hardware
8313                  * whenever the pipe turns on (since it could be previously
8314                  * power gated) or off (since some pipes can't be power gated
8315                  * on some ASICs).
8316                  */
8317                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8318                         dm_update_pflip_irq_state(drm_to_adev(dev),
8319                                                   acrtc_attach);
8320
8321                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8322                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8323                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8324                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8325
8326                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8327                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8328                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8329                         struct amdgpu_dm_connector *aconn =
8330                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8331
8332                         if (aconn->psr_skip_count > 0)
8333                                 aconn->psr_skip_count--;
8334
8335                         /* Allow PSR when skip count is 0. */
8336                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8337
8338                         /*
8339                          * If sink supports PSR SU, there is no need to rely on
8340                          * a vblank event disable request to enable PSR. PSR SU
8341                          * can be enabled immediately once OS demonstrates an
8342                          * adequate number of fast atomic commits to notify KMD
8343                          * of update events. See `vblank_control_worker()`.
8344                          */
8345                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8346                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8347 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8348                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8349 #endif
8350                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8351                             (timestamp_ns -
8352                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8353                             500000000)
8354                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8355                 } else {
8356                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8357                 }
8358
8359                 mutex_unlock(&dm->dc_lock);
8360         }
8361
8362         /*
8363          * Update cursor state *after* programming all the planes.
8364          * This avoids redundant programming in the case where we're going
8365          * to be disabling a single plane - those pipes are being disabled.
8366          */
8367         if (acrtc_state->active_planes)
8368                 amdgpu_dm_commit_cursors(state);
8369
8370 cleanup:
8371         kfree(bundle);
8372 }
8373
8374 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8375                                    struct drm_atomic_state *state)
8376 {
8377         struct amdgpu_device *adev = drm_to_adev(dev);
8378         struct amdgpu_dm_connector *aconnector;
8379         struct drm_connector *connector;
8380         struct drm_connector_state *old_con_state, *new_con_state;
8381         struct drm_crtc_state *new_crtc_state;
8382         struct dm_crtc_state *new_dm_crtc_state;
8383         const struct dc_stream_status *status;
8384         int i, inst;
8385
8386         /* Notify device removals. */
8387         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8388                 if (old_con_state->crtc != new_con_state->crtc) {
8389                         /* CRTC changes require notification. */
8390                         goto notify;
8391                 }
8392
8393                 if (!new_con_state->crtc)
8394                         continue;
8395
8396                 new_crtc_state = drm_atomic_get_new_crtc_state(
8397                         state, new_con_state->crtc);
8398
8399                 if (!new_crtc_state)
8400                         continue;
8401
8402                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8403                         continue;
8404
8405 notify:
8406                 aconnector = to_amdgpu_dm_connector(connector);
8407
8408                 mutex_lock(&adev->dm.audio_lock);
8409                 inst = aconnector->audio_inst;
8410                 aconnector->audio_inst = -1;
8411                 mutex_unlock(&adev->dm.audio_lock);
8412
8413                 amdgpu_dm_audio_eld_notify(adev, inst);
8414         }
8415
8416         /* Notify audio device additions. */
8417         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8418                 if (!new_con_state->crtc)
8419                         continue;
8420
8421                 new_crtc_state = drm_atomic_get_new_crtc_state(
8422                         state, new_con_state->crtc);
8423
8424                 if (!new_crtc_state)
8425                         continue;
8426
8427                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8428                         continue;
8429
8430                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8431                 if (!new_dm_crtc_state->stream)
8432                         continue;
8433
8434                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8435                 if (!status)
8436                         continue;
8437
8438                 aconnector = to_amdgpu_dm_connector(connector);
8439
8440                 mutex_lock(&adev->dm.audio_lock);
8441                 inst = status->audio_inst;
8442                 aconnector->audio_inst = inst;
8443                 mutex_unlock(&adev->dm.audio_lock);
8444
8445                 amdgpu_dm_audio_eld_notify(adev, inst);
8446         }
8447 }
8448
8449 /*
8450  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8451  * @crtc_state: the DRM CRTC state
8452  * @stream_state: the DC stream state.
8453  *
8454  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8455  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8456  */
8457 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8458                                                 struct dc_stream_state *stream_state)
8459 {
8460         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8461 }
8462
8463 /**
8464  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8465  * @state: The atomic state to commit
8466  *
8467  * This will tell DC to commit the constructed DC state from atomic_check,
8468  * programming the hardware. Any failures here implies a hardware failure, since
8469  * atomic check should have filtered anything non-kosher.
8470  */
8471 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8472 {
8473         struct drm_device *dev = state->dev;
8474         struct amdgpu_device *adev = drm_to_adev(dev);
8475         struct amdgpu_display_manager *dm = &adev->dm;
8476         struct dm_atomic_state *dm_state;
8477         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8478         u32 i, j;
8479         struct drm_crtc *crtc;
8480         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8481         unsigned long flags;
8482         bool wait_for_vblank = true;
8483         struct drm_connector *connector;
8484         struct drm_connector_state *old_con_state, *new_con_state;
8485         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8486         int crtc_disable_count = 0;
8487         bool mode_set_reset_required = false;
8488         int r;
8489
8490         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8491
8492         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8493         if (unlikely(r))
8494                 DRM_ERROR("Waiting for fences timed out!");
8495
8496         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8497         drm_dp_mst_atomic_wait_for_dependencies(state);
8498
8499         dm_state = dm_atomic_get_new_state(state);
8500         if (dm_state && dm_state->context) {
8501                 dc_state = dm_state->context;
8502         } else {
8503                 /* No state changes, retain current state. */
8504                 dc_state_temp = dc_create_state(dm->dc);
8505                 ASSERT(dc_state_temp);
8506                 dc_state = dc_state_temp;
8507                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8508         }
8509
8510         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8511                                        new_crtc_state, i) {
8512                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8513
8514                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8515
8516                 if (old_crtc_state->active &&
8517                     (!new_crtc_state->active ||
8518                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8519                         manage_dm_interrupts(adev, acrtc, false);
8520                         dc_stream_release(dm_old_crtc_state->stream);
8521                 }
8522         }
8523
8524         drm_atomic_helper_calc_timestamping_constants(state);
8525
8526         /* update changed items */
8527         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8528                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8529
8530                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8531                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8532
8533                 drm_dbg_state(state->dev,
8534                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8535                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8536                         "connectors_changed:%d\n",
8537                         acrtc->crtc_id,
8538                         new_crtc_state->enable,
8539                         new_crtc_state->active,
8540                         new_crtc_state->planes_changed,
8541                         new_crtc_state->mode_changed,
8542                         new_crtc_state->active_changed,
8543                         new_crtc_state->connectors_changed);
8544
8545                 /* Disable cursor if disabling crtc */
8546                 if (old_crtc_state->active && !new_crtc_state->active) {
8547                         struct dc_cursor_position position;
8548
8549                         memset(&position, 0, sizeof(position));
8550                         mutex_lock(&dm->dc_lock);
8551                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8552                         mutex_unlock(&dm->dc_lock);
8553                 }
8554
8555                 /* Copy all transient state flags into dc state */
8556                 if (dm_new_crtc_state->stream) {
8557                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8558                                                             dm_new_crtc_state->stream);
8559                 }
8560
8561                 /* handles headless hotplug case, updating new_state and
8562                  * aconnector as needed
8563                  */
8564
8565                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8566
8567                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8568
8569                         if (!dm_new_crtc_state->stream) {
8570                                 /*
8571                                  * this could happen because of issues with
8572                                  * userspace notifications delivery.
8573                                  * In this case userspace tries to set mode on
8574                                  * display which is disconnected in fact.
8575                                  * dc_sink is NULL in this case on aconnector.
8576                                  * We expect reset mode will come soon.
8577                                  *
8578                                  * This can also happen when unplug is done
8579                                  * during resume sequence ended
8580                                  *
8581                                  * In this case, we want to pretend we still
8582                                  * have a sink to keep the pipe running so that
8583                                  * hw state is consistent with the sw state
8584                                  */
8585                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8586                                                 __func__, acrtc->base.base.id);
8587                                 continue;
8588                         }
8589
8590                         if (dm_old_crtc_state->stream)
8591                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8592
8593                         pm_runtime_get_noresume(dev->dev);
8594
8595                         acrtc->enabled = true;
8596                         acrtc->hw_mode = new_crtc_state->mode;
8597                         crtc->hwmode = new_crtc_state->mode;
8598                         mode_set_reset_required = true;
8599                 } else if (modereset_required(new_crtc_state)) {
8600                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8601                         /* i.e. reset mode */
8602                         if (dm_old_crtc_state->stream)
8603                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8604
8605                         mode_set_reset_required = true;
8606                 }
8607         } /* for_each_crtc_in_state() */
8608
8609         if (dc_state) {
8610                 /* if there mode set or reset, disable eDP PSR */
8611                 if (mode_set_reset_required) {
8612                         if (dm->vblank_control_workqueue)
8613                                 flush_workqueue(dm->vblank_control_workqueue);
8614
8615                         amdgpu_dm_psr_disable_all(dm);
8616                 }
8617
8618                 dm_enable_per_frame_crtc_master_sync(dc_state);
8619                 mutex_lock(&dm->dc_lock);
8620                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8621
8622                 /* Allow idle optimization when vblank count is 0 for display off */
8623                 if (dm->active_vblank_irq_count == 0)
8624                         dc_allow_idle_optimizations(dm->dc, true);
8625                 mutex_unlock(&dm->dc_lock);
8626         }
8627
8628         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8629                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8630
8631                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8632
8633                 if (dm_new_crtc_state->stream != NULL) {
8634                         const struct dc_stream_status *status =
8635                                         dc_stream_get_status(dm_new_crtc_state->stream);
8636
8637                         if (!status)
8638                                 status = dc_stream_get_status_from_state(dc_state,
8639                                                                          dm_new_crtc_state->stream);
8640                         if (!status)
8641                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8642                         else
8643                                 acrtc->otg_inst = status->primary_otg_inst;
8644                 }
8645         }
8646         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8647                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8648                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8649                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8650
8651                 if (!adev->dm.hdcp_workqueue)
8652                         continue;
8653
8654                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8655
8656                 if (!connector)
8657                         continue;
8658
8659                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8660                         connector->index, connector->status, connector->dpms);
8661                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8662                         old_con_state->content_protection, new_con_state->content_protection);
8663
8664                 if (aconnector->dc_sink) {
8665                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8666                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8667                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8668                                 aconnector->dc_sink->edid_caps.display_name);
8669                         }
8670                 }
8671
8672                 new_crtc_state = NULL;
8673                 old_crtc_state = NULL;
8674
8675                 if (acrtc) {
8676                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8677                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8678                 }
8679
8680                 if (old_crtc_state)
8681                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8682                         old_crtc_state->enable,
8683                         old_crtc_state->active,
8684                         old_crtc_state->mode_changed,
8685                         old_crtc_state->active_changed,
8686                         old_crtc_state->connectors_changed);
8687
8688                 if (new_crtc_state)
8689                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8690                         new_crtc_state->enable,
8691                         new_crtc_state->active,
8692                         new_crtc_state->mode_changed,
8693                         new_crtc_state->active_changed,
8694                         new_crtc_state->connectors_changed);
8695         }
8696
8697         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8698                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8699                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8700                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8701
8702                 if (!adev->dm.hdcp_workqueue)
8703                         continue;
8704
8705                 new_crtc_state = NULL;
8706                 old_crtc_state = NULL;
8707
8708                 if (acrtc) {
8709                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8710                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8711                 }
8712
8713                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8714
8715                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8716                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8717                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8718                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8719                         dm_new_con_state->update_hdcp = true;
8720                         continue;
8721                 }
8722
8723                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8724                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8725                         /* when display is unplugged from mst hub, connctor will
8726                          * be destroyed within dm_dp_mst_connector_destroy. connector
8727                          * hdcp perperties, like type, undesired, desired, enabled,
8728                          * will be lost. So, save hdcp properties into hdcp_work within
8729                          * amdgpu_dm_atomic_commit_tail. if the same display is
8730                          * plugged back with same display index, its hdcp properties
8731                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8732                          */
8733
8734                         bool enable_encryption = false;
8735
8736                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8737                                 enable_encryption = true;
8738
8739                         if (aconnector->dc_link && aconnector->dc_sink &&
8740                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8741                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8742                                 struct hdcp_workqueue *hdcp_w =
8743                                         &hdcp_work[aconnector->dc_link->link_index];
8744
8745                                 hdcp_w->hdcp_content_type[connector->index] =
8746                                         new_con_state->hdcp_content_type;
8747                                 hdcp_w->content_protection[connector->index] =
8748                                         new_con_state->content_protection;
8749                         }
8750
8751                         if (new_crtc_state && new_crtc_state->mode_changed &&
8752                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8753                                 enable_encryption = true;
8754
8755                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8756
8757                         hdcp_update_display(
8758                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8759                                 new_con_state->hdcp_content_type, enable_encryption);
8760                 }
8761         }
8762
8763         /* Handle connector state changes */
8764         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8765                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8766                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8767                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8768                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8769                 struct dc_stream_update stream_update;
8770                 struct dc_info_packet hdr_packet;
8771                 struct dc_stream_status *status = NULL;
8772                 bool abm_changed, hdr_changed, scaling_changed;
8773
8774                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8775                 memset(&stream_update, 0, sizeof(stream_update));
8776
8777                 if (acrtc) {
8778                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8779                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8780                 }
8781
8782                 /* Skip any modesets/resets */
8783                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8784                         continue;
8785
8786                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8787                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8788
8789                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8790                                                              dm_old_con_state);
8791
8792                 abm_changed = dm_new_crtc_state->abm_level !=
8793                               dm_old_crtc_state->abm_level;
8794
8795                 hdr_changed =
8796                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8797
8798                 if (!scaling_changed && !abm_changed && !hdr_changed)
8799                         continue;
8800
8801                 stream_update.stream = dm_new_crtc_state->stream;
8802                 if (scaling_changed) {
8803                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8804                                         dm_new_con_state, dm_new_crtc_state->stream);
8805
8806                         stream_update.src = dm_new_crtc_state->stream->src;
8807                         stream_update.dst = dm_new_crtc_state->stream->dst;
8808                 }
8809
8810                 if (abm_changed) {
8811                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8812
8813                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8814                 }
8815
8816                 if (hdr_changed) {
8817                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8818                         stream_update.hdr_static_metadata = &hdr_packet;
8819                 }
8820
8821                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8822
8823                 if (WARN_ON(!status))
8824                         continue;
8825
8826                 WARN_ON(!status->plane_count);
8827
8828                 /*
8829                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8830                  * Here we create an empty update on each plane.
8831                  * To fix this, DC should permit updating only stream properties.
8832                  */
8833                 for (j = 0; j < status->plane_count; j++)
8834                         dummy_updates[j].surface = status->plane_states[0];
8835
8836
8837                 mutex_lock(&dm->dc_lock);
8838                 dc_update_planes_and_stream(dm->dc,
8839                                             dummy_updates,
8840                                             status->plane_count,
8841                                             dm_new_crtc_state->stream,
8842                                             &stream_update);
8843                 mutex_unlock(&dm->dc_lock);
8844         }
8845
8846         /**
8847          * Enable interrupts for CRTCs that are newly enabled or went through
8848          * a modeset. It was intentionally deferred until after the front end
8849          * state was modified to wait until the OTG was on and so the IRQ
8850          * handlers didn't access stale or invalid state.
8851          */
8852         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8853                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8854 #ifdef CONFIG_DEBUG_FS
8855                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8856 #endif
8857                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8858                 if (old_crtc_state->active && !new_crtc_state->active)
8859                         crtc_disable_count++;
8860
8861                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8862                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8863
8864                 /* For freesync config update on crtc state and params for irq */
8865                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8866
8867 #ifdef CONFIG_DEBUG_FS
8868                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8869                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8870                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8871 #endif
8872
8873                 if (new_crtc_state->active &&
8874                     (!old_crtc_state->active ||
8875                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8876                         dc_stream_retain(dm_new_crtc_state->stream);
8877                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8878                         manage_dm_interrupts(adev, acrtc, true);
8879                 }
8880                 /* Handle vrr on->off / off->on transitions */
8881                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8882
8883 #ifdef CONFIG_DEBUG_FS
8884                 if (new_crtc_state->active &&
8885                     (!old_crtc_state->active ||
8886                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8887                         /**
8888                          * Frontend may have changed so reapply the CRC capture
8889                          * settings for the stream.
8890                          */
8891                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8892 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8893                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8894                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8895                                         acrtc->dm_irq_params.window_param.update_win = true;
8896
8897                                         /**
8898                                          * It takes 2 frames for HW to stably generate CRC when
8899                                          * resuming from suspend, so we set skip_frame_cnt 2.
8900                                          */
8901                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8902                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8903                                 }
8904 #endif
8905                                 if (amdgpu_dm_crtc_configure_crc_source(
8906                                         crtc, dm_new_crtc_state, cur_crc_src))
8907                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8908                         }
8909                 }
8910 #endif
8911         }
8912
8913         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8914                 if (new_crtc_state->async_flip)
8915                         wait_for_vblank = false;
8916
8917         /* update planes when needed per crtc*/
8918         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8919                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8920
8921                 if (dm_new_crtc_state->stream)
8922                         amdgpu_dm_commit_planes(state, dc_state, dev,
8923                                                 dm, crtc, wait_for_vblank);
8924         }
8925
8926         /* Update audio instances for each connector. */
8927         amdgpu_dm_commit_audio(dev, state);
8928
8929         /* restore the backlight level */
8930         for (i = 0; i < dm->num_of_edps; i++) {
8931                 if (dm->backlight_dev[i] &&
8932                     (dm->actual_brightness[i] != dm->brightness[i]))
8933                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8934         }
8935
8936         /*
8937          * send vblank event on all events not handled in flip and
8938          * mark consumed event for drm_atomic_helper_commit_hw_done
8939          */
8940         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8941         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8942
8943                 if (new_crtc_state->event)
8944                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8945
8946                 new_crtc_state->event = NULL;
8947         }
8948         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8949
8950         /* Signal HW programming completion */
8951         drm_atomic_helper_commit_hw_done(state);
8952
8953         if (wait_for_vblank)
8954                 drm_atomic_helper_wait_for_flip_done(dev, state);
8955
8956         drm_atomic_helper_cleanup_planes(dev, state);
8957
8958         /* return the stolen vga memory back to VRAM */
8959         if (!adev->mman.keep_stolen_vga_memory)
8960                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8961         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8962
8963         /*
8964          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8965          * so we can put the GPU into runtime suspend if we're not driving any
8966          * displays anymore
8967          */
8968         for (i = 0; i < crtc_disable_count; i++)
8969                 pm_runtime_put_autosuspend(dev->dev);
8970         pm_runtime_mark_last_busy(dev->dev);
8971
8972         if (dc_state_temp)
8973                 dc_release_state(dc_state_temp);
8974 }
8975
8976 static int dm_force_atomic_commit(struct drm_connector *connector)
8977 {
8978         int ret = 0;
8979         struct drm_device *ddev = connector->dev;
8980         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8981         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8982         struct drm_plane *plane = disconnected_acrtc->base.primary;
8983         struct drm_connector_state *conn_state;
8984         struct drm_crtc_state *crtc_state;
8985         struct drm_plane_state *plane_state;
8986
8987         if (!state)
8988                 return -ENOMEM;
8989
8990         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8991
8992         /* Construct an atomic state to restore previous display setting */
8993
8994         /*
8995          * Attach connectors to drm_atomic_state
8996          */
8997         conn_state = drm_atomic_get_connector_state(state, connector);
8998
8999         ret = PTR_ERR_OR_ZERO(conn_state);
9000         if (ret)
9001                 goto out;
9002
9003         /* Attach crtc to drm_atomic_state*/
9004         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9005
9006         ret = PTR_ERR_OR_ZERO(crtc_state);
9007         if (ret)
9008                 goto out;
9009
9010         /* force a restore */
9011         crtc_state->mode_changed = true;
9012
9013         /* Attach plane to drm_atomic_state */
9014         plane_state = drm_atomic_get_plane_state(state, plane);
9015
9016         ret = PTR_ERR_OR_ZERO(plane_state);
9017         if (ret)
9018                 goto out;
9019
9020         /* Call commit internally with the state we just constructed */
9021         ret = drm_atomic_commit(state);
9022
9023 out:
9024         drm_atomic_state_put(state);
9025         if (ret)
9026                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9027
9028         return ret;
9029 }
9030
9031 /*
9032  * This function handles all cases when set mode does not come upon hotplug.
9033  * This includes when a display is unplugged then plugged back into the
9034  * same port and when running without usermode desktop manager supprot
9035  */
9036 void dm_restore_drm_connector_state(struct drm_device *dev,
9037                                     struct drm_connector *connector)
9038 {
9039         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9040         struct amdgpu_crtc *disconnected_acrtc;
9041         struct dm_crtc_state *acrtc_state;
9042
9043         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9044                 return;
9045
9046         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9047         if (!disconnected_acrtc)
9048                 return;
9049
9050         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9051         if (!acrtc_state->stream)
9052                 return;
9053
9054         /*
9055          * If the previous sink is not released and different from the current,
9056          * we deduce we are in a state where we can not rely on usermode call
9057          * to turn on the display, so we do it here
9058          */
9059         if (acrtc_state->stream->sink != aconnector->dc_sink)
9060                 dm_force_atomic_commit(&aconnector->base);
9061 }
9062
9063 /*
9064  * Grabs all modesetting locks to serialize against any blocking commits,
9065  * Waits for completion of all non blocking commits.
9066  */
9067 static int do_aquire_global_lock(struct drm_device *dev,
9068                                  struct drm_atomic_state *state)
9069 {
9070         struct drm_crtc *crtc;
9071         struct drm_crtc_commit *commit;
9072         long ret;
9073
9074         /*
9075          * Adding all modeset locks to aquire_ctx will
9076          * ensure that when the framework release it the
9077          * extra locks we are locking here will get released to
9078          */
9079         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9080         if (ret)
9081                 return ret;
9082
9083         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9084                 spin_lock(&crtc->commit_lock);
9085                 commit = list_first_entry_or_null(&crtc->commit_list,
9086                                 struct drm_crtc_commit, commit_entry);
9087                 if (commit)
9088                         drm_crtc_commit_get(commit);
9089                 spin_unlock(&crtc->commit_lock);
9090
9091                 if (!commit)
9092                         continue;
9093
9094                 /*
9095                  * Make sure all pending HW programming completed and
9096                  * page flips done
9097                  */
9098                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9099
9100                 if (ret > 0)
9101                         ret = wait_for_completion_interruptible_timeout(
9102                                         &commit->flip_done, 10*HZ);
9103
9104                 if (ret == 0)
9105                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9106                                   "timed out\n", crtc->base.id, crtc->name);
9107
9108                 drm_crtc_commit_put(commit);
9109         }
9110
9111         return ret < 0 ? ret : 0;
9112 }
9113
9114 static void get_freesync_config_for_crtc(
9115         struct dm_crtc_state *new_crtc_state,
9116         struct dm_connector_state *new_con_state)
9117 {
9118         struct mod_freesync_config config = {0};
9119         struct amdgpu_dm_connector *aconnector =
9120                         to_amdgpu_dm_connector(new_con_state->base.connector);
9121         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9122         int vrefresh = drm_mode_vrefresh(mode);
9123         bool fs_vid_mode = false;
9124
9125         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9126                                         vrefresh >= aconnector->min_vfreq &&
9127                                         vrefresh <= aconnector->max_vfreq;
9128
9129         if (new_crtc_state->vrr_supported) {
9130                 new_crtc_state->stream->ignore_msa_timing_param = true;
9131                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9132
9133                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9134                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9135                 config.vsif_supported = true;
9136                 config.btr = true;
9137
9138                 if (fs_vid_mode) {
9139                         config.state = VRR_STATE_ACTIVE_FIXED;
9140                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9141                         goto out;
9142                 } else if (new_crtc_state->base.vrr_enabled) {
9143                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9144                 } else {
9145                         config.state = VRR_STATE_INACTIVE;
9146                 }
9147         }
9148 out:
9149         new_crtc_state->freesync_config = config;
9150 }
9151
9152 static void reset_freesync_config_for_crtc(
9153         struct dm_crtc_state *new_crtc_state)
9154 {
9155         new_crtc_state->vrr_supported = false;
9156
9157         memset(&new_crtc_state->vrr_infopacket, 0,
9158                sizeof(new_crtc_state->vrr_infopacket));
9159 }
9160
9161 static bool
9162 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9163                                  struct drm_crtc_state *new_crtc_state)
9164 {
9165         const struct drm_display_mode *old_mode, *new_mode;
9166
9167         if (!old_crtc_state || !new_crtc_state)
9168                 return false;
9169
9170         old_mode = &old_crtc_state->mode;
9171         new_mode = &new_crtc_state->mode;
9172
9173         if (old_mode->clock       == new_mode->clock &&
9174             old_mode->hdisplay    == new_mode->hdisplay &&
9175             old_mode->vdisplay    == new_mode->vdisplay &&
9176             old_mode->htotal      == new_mode->htotal &&
9177             old_mode->vtotal      != new_mode->vtotal &&
9178             old_mode->hsync_start == new_mode->hsync_start &&
9179             old_mode->vsync_start != new_mode->vsync_start &&
9180             old_mode->hsync_end   == new_mode->hsync_end &&
9181             old_mode->vsync_end   != new_mode->vsync_end &&
9182             old_mode->hskew       == new_mode->hskew &&
9183             old_mode->vscan       == new_mode->vscan &&
9184             (old_mode->vsync_end - old_mode->vsync_start) ==
9185             (new_mode->vsync_end - new_mode->vsync_start))
9186                 return true;
9187
9188         return false;
9189 }
9190
9191 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9192         u64 num, den, res;
9193         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9194
9195         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9196
9197         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9198         den = (unsigned long long)new_crtc_state->mode.htotal *
9199               (unsigned long long)new_crtc_state->mode.vtotal;
9200
9201         res = div_u64(num, den);
9202         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9203 }
9204
9205 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9206                          struct drm_atomic_state *state,
9207                          struct drm_crtc *crtc,
9208                          struct drm_crtc_state *old_crtc_state,
9209                          struct drm_crtc_state *new_crtc_state,
9210                          bool enable,
9211                          bool *lock_and_validation_needed)
9212 {
9213         struct dm_atomic_state *dm_state = NULL;
9214         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9215         struct dc_stream_state *new_stream;
9216         int ret = 0;
9217
9218         /*
9219          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9220          * update changed items
9221          */
9222         struct amdgpu_crtc *acrtc = NULL;
9223         struct amdgpu_dm_connector *aconnector = NULL;
9224         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9225         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9226
9227         new_stream = NULL;
9228
9229         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9230         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9231         acrtc = to_amdgpu_crtc(crtc);
9232         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9233
9234         /* TODO This hack should go away */
9235         if (aconnector && enable) {
9236                 /* Make sure fake sink is created in plug-in scenario */
9237                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9238                                                             &aconnector->base);
9239                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9240                                                             &aconnector->base);
9241
9242                 if (IS_ERR(drm_new_conn_state)) {
9243                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9244                         goto fail;
9245                 }
9246
9247                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9248                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9249
9250                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9251                         goto skip_modeset;
9252
9253                 new_stream = create_validate_stream_for_sink(aconnector,
9254                                                              &new_crtc_state->mode,
9255                                                              dm_new_conn_state,
9256                                                              dm_old_crtc_state->stream);
9257
9258                 /*
9259                  * we can have no stream on ACTION_SET if a display
9260                  * was disconnected during S3, in this case it is not an
9261                  * error, the OS will be updated after detection, and
9262                  * will do the right thing on next atomic commit
9263                  */
9264
9265                 if (!new_stream) {
9266                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9267                                         __func__, acrtc->base.base.id);
9268                         ret = -ENOMEM;
9269                         goto fail;
9270                 }
9271
9272                 /*
9273                  * TODO: Check VSDB bits to decide whether this should
9274                  * be enabled or not.
9275                  */
9276                 new_stream->triggered_crtc_reset.enabled =
9277                         dm->force_timing_sync;
9278
9279                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9280
9281                 ret = fill_hdr_info_packet(drm_new_conn_state,
9282                                            &new_stream->hdr_static_metadata);
9283                 if (ret)
9284                         goto fail;
9285
9286                 /*
9287                  * If we already removed the old stream from the context
9288                  * (and set the new stream to NULL) then we can't reuse
9289                  * the old stream even if the stream and scaling are unchanged.
9290                  * We'll hit the BUG_ON and black screen.
9291                  *
9292                  * TODO: Refactor this function to allow this check to work
9293                  * in all conditions.
9294                  */
9295                 if (dm_new_crtc_state->stream &&
9296                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9297                         goto skip_modeset;
9298
9299                 if (dm_new_crtc_state->stream &&
9300                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9301                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9302                         new_crtc_state->mode_changed = false;
9303                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9304                                          new_crtc_state->mode_changed);
9305                 }
9306         }
9307
9308         /* mode_changed flag may get updated above, need to check again */
9309         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9310                 goto skip_modeset;
9311
9312         drm_dbg_state(state->dev,
9313                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9314                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9315                 "connectors_changed:%d\n",
9316                 acrtc->crtc_id,
9317                 new_crtc_state->enable,
9318                 new_crtc_state->active,
9319                 new_crtc_state->planes_changed,
9320                 new_crtc_state->mode_changed,
9321                 new_crtc_state->active_changed,
9322                 new_crtc_state->connectors_changed);
9323
9324         /* Remove stream for any changed/disabled CRTC */
9325         if (!enable) {
9326
9327                 if (!dm_old_crtc_state->stream)
9328                         goto skip_modeset;
9329
9330                 /* Unset freesync video if it was active before */
9331                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9332                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9333                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9334                 }
9335
9336                 /* Now check if we should set freesync video mode */
9337                 if (dm_new_crtc_state->stream &&
9338                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9339                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9340                     is_timing_unchanged_for_freesync(new_crtc_state,
9341                                                      old_crtc_state)) {
9342                         new_crtc_state->mode_changed = false;
9343                         DRM_DEBUG_DRIVER(
9344                                 "Mode change not required for front porch change, "
9345                                 "setting mode_changed to %d",
9346                                 new_crtc_state->mode_changed);
9347
9348                         set_freesync_fixed_config(dm_new_crtc_state);
9349
9350                         goto skip_modeset;
9351                 } else if (aconnector &&
9352                            is_freesync_video_mode(&new_crtc_state->mode,
9353                                                   aconnector)) {
9354                         struct drm_display_mode *high_mode;
9355
9356                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9357                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9358                                 set_freesync_fixed_config(dm_new_crtc_state);
9359                         }
9360                 }
9361
9362                 ret = dm_atomic_get_state(state, &dm_state);
9363                 if (ret)
9364                         goto fail;
9365
9366                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9367                                 crtc->base.id);
9368
9369                 /* i.e. reset mode */
9370                 if (dc_remove_stream_from_ctx(
9371                                 dm->dc,
9372                                 dm_state->context,
9373                                 dm_old_crtc_state->stream) != DC_OK) {
9374                         ret = -EINVAL;
9375                         goto fail;
9376                 }
9377
9378                 dc_stream_release(dm_old_crtc_state->stream);
9379                 dm_new_crtc_state->stream = NULL;
9380
9381                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9382
9383                 *lock_and_validation_needed = true;
9384
9385         } else {/* Add stream for any updated/enabled CRTC */
9386                 /*
9387                  * Quick fix to prevent NULL pointer on new_stream when
9388                  * added MST connectors not found in existing crtc_state in the chained mode
9389                  * TODO: need to dig out the root cause of that
9390                  */
9391                 if (!aconnector)
9392                         goto skip_modeset;
9393
9394                 if (modereset_required(new_crtc_state))
9395                         goto skip_modeset;
9396
9397                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9398                                      dm_old_crtc_state->stream)) {
9399
9400                         WARN_ON(dm_new_crtc_state->stream);
9401
9402                         ret = dm_atomic_get_state(state, &dm_state);
9403                         if (ret)
9404                                 goto fail;
9405
9406                         dm_new_crtc_state->stream = new_stream;
9407
9408                         dc_stream_retain(new_stream);
9409
9410                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9411                                          crtc->base.id);
9412
9413                         if (dc_add_stream_to_ctx(
9414                                         dm->dc,
9415                                         dm_state->context,
9416                                         dm_new_crtc_state->stream) != DC_OK) {
9417                                 ret = -EINVAL;
9418                                 goto fail;
9419                         }
9420
9421                         *lock_and_validation_needed = true;
9422                 }
9423         }
9424
9425 skip_modeset:
9426         /* Release extra reference */
9427         if (new_stream)
9428                 dc_stream_release(new_stream);
9429
9430         /*
9431          * We want to do dc stream updates that do not require a
9432          * full modeset below.
9433          */
9434         if (!(enable && aconnector && new_crtc_state->active))
9435                 return 0;
9436         /*
9437          * Given above conditions, the dc state cannot be NULL because:
9438          * 1. We're in the process of enabling CRTCs (just been added
9439          *    to the dc context, or already is on the context)
9440          * 2. Has a valid connector attached, and
9441          * 3. Is currently active and enabled.
9442          * => The dc stream state currently exists.
9443          */
9444         BUG_ON(dm_new_crtc_state->stream == NULL);
9445
9446         /* Scaling or underscan settings */
9447         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9448                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9449                 update_stream_scaling_settings(
9450                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9451
9452         /* ABM settings */
9453         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9454
9455         /*
9456          * Color management settings. We also update color properties
9457          * when a modeset is needed, to ensure it gets reprogrammed.
9458          */
9459         if (dm_new_crtc_state->base.color_mgmt_changed ||
9460             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9461                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9462                 if (ret)
9463                         goto fail;
9464         }
9465
9466         /* Update Freesync settings. */
9467         get_freesync_config_for_crtc(dm_new_crtc_state,
9468                                      dm_new_conn_state);
9469
9470         return ret;
9471
9472 fail:
9473         if (new_stream)
9474                 dc_stream_release(new_stream);
9475         return ret;
9476 }
9477
9478 static bool should_reset_plane(struct drm_atomic_state *state,
9479                                struct drm_plane *plane,
9480                                struct drm_plane_state *old_plane_state,
9481                                struct drm_plane_state *new_plane_state)
9482 {
9483         struct drm_plane *other;
9484         struct drm_plane_state *old_other_state, *new_other_state;
9485         struct drm_crtc_state *new_crtc_state;
9486         int i;
9487
9488         /*
9489          * TODO: Remove this hack once the checks below are sufficient
9490          * enough to determine when we need to reset all the planes on
9491          * the stream.
9492          */
9493         if (state->allow_modeset)
9494                 return true;
9495
9496         /* Exit early if we know that we're adding or removing the plane. */
9497         if (old_plane_state->crtc != new_plane_state->crtc)
9498                 return true;
9499
9500         /* old crtc == new_crtc == NULL, plane not in context. */
9501         if (!new_plane_state->crtc)
9502                 return false;
9503
9504         new_crtc_state =
9505                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9506
9507         if (!new_crtc_state)
9508                 return true;
9509
9510         /* CRTC Degamma changes currently require us to recreate planes. */
9511         if (new_crtc_state->color_mgmt_changed)
9512                 return true;
9513
9514         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9515                 return true;
9516
9517         /*
9518          * If there are any new primary or overlay planes being added or
9519          * removed then the z-order can potentially change. To ensure
9520          * correct z-order and pipe acquisition the current DC architecture
9521          * requires us to remove and recreate all existing planes.
9522          *
9523          * TODO: Come up with a more elegant solution for this.
9524          */
9525         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9526                 struct amdgpu_framebuffer *old_afb, *new_afb;
9527                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9528                         continue;
9529
9530                 if (old_other_state->crtc != new_plane_state->crtc &&
9531                     new_other_state->crtc != new_plane_state->crtc)
9532                         continue;
9533
9534                 if (old_other_state->crtc != new_other_state->crtc)
9535                         return true;
9536
9537                 /* Src/dst size and scaling updates. */
9538                 if (old_other_state->src_w != new_other_state->src_w ||
9539                     old_other_state->src_h != new_other_state->src_h ||
9540                     old_other_state->crtc_w != new_other_state->crtc_w ||
9541                     old_other_state->crtc_h != new_other_state->crtc_h)
9542                         return true;
9543
9544                 /* Rotation / mirroring updates. */
9545                 if (old_other_state->rotation != new_other_state->rotation)
9546                         return true;
9547
9548                 /* Blending updates. */
9549                 if (old_other_state->pixel_blend_mode !=
9550                     new_other_state->pixel_blend_mode)
9551                         return true;
9552
9553                 /* Alpha updates. */
9554                 if (old_other_state->alpha != new_other_state->alpha)
9555                         return true;
9556
9557                 /* Colorspace changes. */
9558                 if (old_other_state->color_range != new_other_state->color_range ||
9559                     old_other_state->color_encoding != new_other_state->color_encoding)
9560                         return true;
9561
9562                 /* Framebuffer checks fall at the end. */
9563                 if (!old_other_state->fb || !new_other_state->fb)
9564                         continue;
9565
9566                 /* Pixel format changes can require bandwidth updates. */
9567                 if (old_other_state->fb->format != new_other_state->fb->format)
9568                         return true;
9569
9570                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9571                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9572
9573                 /* Tiling and DCC changes also require bandwidth updates. */
9574                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9575                     old_afb->base.modifier != new_afb->base.modifier)
9576                         return true;
9577         }
9578
9579         return false;
9580 }
9581
9582 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9583                               struct drm_plane_state *new_plane_state,
9584                               struct drm_framebuffer *fb)
9585 {
9586         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9587         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9588         unsigned int pitch;
9589         bool linear;
9590
9591         if (fb->width > new_acrtc->max_cursor_width ||
9592             fb->height > new_acrtc->max_cursor_height) {
9593                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9594                                  new_plane_state->fb->width,
9595                                  new_plane_state->fb->height);
9596                 return -EINVAL;
9597         }
9598         if (new_plane_state->src_w != fb->width << 16 ||
9599             new_plane_state->src_h != fb->height << 16) {
9600                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9601                 return -EINVAL;
9602         }
9603
9604         /* Pitch in pixels */
9605         pitch = fb->pitches[0] / fb->format->cpp[0];
9606
9607         if (fb->width != pitch) {
9608                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9609                                  fb->width, pitch);
9610                 return -EINVAL;
9611         }
9612
9613         switch (pitch) {
9614         case 64:
9615         case 128:
9616         case 256:
9617                 /* FB pitch is supported by cursor plane */
9618                 break;
9619         default:
9620                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9621                 return -EINVAL;
9622         }
9623
9624         /* Core DRM takes care of checking FB modifiers, so we only need to
9625          * check tiling flags when the FB doesn't have a modifier. */
9626         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9627                 if (adev->family < AMDGPU_FAMILY_AI) {
9628                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9629                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9630                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9631                 } else {
9632                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9633                 }
9634                 if (!linear) {
9635                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9636                         return -EINVAL;
9637                 }
9638         }
9639
9640         return 0;
9641 }
9642
9643 static int dm_update_plane_state(struct dc *dc,
9644                                  struct drm_atomic_state *state,
9645                                  struct drm_plane *plane,
9646                                  struct drm_plane_state *old_plane_state,
9647                                  struct drm_plane_state *new_plane_state,
9648                                  bool enable,
9649                                  bool *lock_and_validation_needed,
9650                                  bool *is_top_most_overlay)
9651 {
9652
9653         struct dm_atomic_state *dm_state = NULL;
9654         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9655         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9656         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9657         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9658         struct amdgpu_crtc *new_acrtc;
9659         bool needs_reset;
9660         int ret = 0;
9661
9662
9663         new_plane_crtc = new_plane_state->crtc;
9664         old_plane_crtc = old_plane_state->crtc;
9665         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9666         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9667
9668         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9669                 if (!enable || !new_plane_crtc ||
9670                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9671                         return 0;
9672
9673                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9674
9675                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9676                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9677                         return -EINVAL;
9678                 }
9679
9680                 if (new_plane_state->fb) {
9681                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9682                                                  new_plane_state->fb);
9683                         if (ret)
9684                                 return ret;
9685                 }
9686
9687                 return 0;
9688         }
9689
9690         needs_reset = should_reset_plane(state, plane, old_plane_state,
9691                                          new_plane_state);
9692
9693         /* Remove any changed/removed planes */
9694         if (!enable) {
9695                 if (!needs_reset)
9696                         return 0;
9697
9698                 if (!old_plane_crtc)
9699                         return 0;
9700
9701                 old_crtc_state = drm_atomic_get_old_crtc_state(
9702                                 state, old_plane_crtc);
9703                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9704
9705                 if (!dm_old_crtc_state->stream)
9706                         return 0;
9707
9708                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9709                                 plane->base.id, old_plane_crtc->base.id);
9710
9711                 ret = dm_atomic_get_state(state, &dm_state);
9712                 if (ret)
9713                         return ret;
9714
9715                 if (!dc_remove_plane_from_context(
9716                                 dc,
9717                                 dm_old_crtc_state->stream,
9718                                 dm_old_plane_state->dc_state,
9719                                 dm_state->context)) {
9720
9721                         return -EINVAL;
9722                 }
9723
9724                 if (dm_old_plane_state->dc_state)
9725                         dc_plane_state_release(dm_old_plane_state->dc_state);
9726
9727                 dm_new_plane_state->dc_state = NULL;
9728
9729                 *lock_and_validation_needed = true;
9730
9731         } else { /* Add new planes */
9732                 struct dc_plane_state *dc_new_plane_state;
9733
9734                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9735                         return 0;
9736
9737                 if (!new_plane_crtc)
9738                         return 0;
9739
9740                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9741                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9742
9743                 if (!dm_new_crtc_state->stream)
9744                         return 0;
9745
9746                 if (!needs_reset)
9747                         return 0;
9748
9749                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9750                 if (ret)
9751                         return ret;
9752
9753                 WARN_ON(dm_new_plane_state->dc_state);
9754
9755                 dc_new_plane_state = dc_create_plane_state(dc);
9756                 if (!dc_new_plane_state)
9757                         return -ENOMEM;
9758
9759                 /* Block top most plane from being a video plane */
9760                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9761                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9762                                 return -EINVAL;
9763                         else
9764                                 *is_top_most_overlay = false;
9765                 }
9766
9767                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9768                                  plane->base.id, new_plane_crtc->base.id);
9769
9770                 ret = fill_dc_plane_attributes(
9771                         drm_to_adev(new_plane_crtc->dev),
9772                         dc_new_plane_state,
9773                         new_plane_state,
9774                         new_crtc_state);
9775                 if (ret) {
9776                         dc_plane_state_release(dc_new_plane_state);
9777                         return ret;
9778                 }
9779
9780                 ret = dm_atomic_get_state(state, &dm_state);
9781                 if (ret) {
9782                         dc_plane_state_release(dc_new_plane_state);
9783                         return ret;
9784                 }
9785
9786                 /*
9787                  * Any atomic check errors that occur after this will
9788                  * not need a release. The plane state will be attached
9789                  * to the stream, and therefore part of the atomic
9790                  * state. It'll be released when the atomic state is
9791                  * cleaned.
9792                  */
9793                 if (!dc_add_plane_to_context(
9794                                 dc,
9795                                 dm_new_crtc_state->stream,
9796                                 dc_new_plane_state,
9797                                 dm_state->context)) {
9798
9799                         dc_plane_state_release(dc_new_plane_state);
9800                         return -EINVAL;
9801                 }
9802
9803                 dm_new_plane_state->dc_state = dc_new_plane_state;
9804
9805                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9806
9807                 /* Tell DC to do a full surface update every time there
9808                  * is a plane change. Inefficient, but works for now.
9809                  */
9810                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9811
9812                 *lock_and_validation_needed = true;
9813         }
9814
9815
9816         return ret;
9817 }
9818
9819 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9820                                        int *src_w, int *src_h)
9821 {
9822         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9823         case DRM_MODE_ROTATE_90:
9824         case DRM_MODE_ROTATE_270:
9825                 *src_w = plane_state->src_h >> 16;
9826                 *src_h = plane_state->src_w >> 16;
9827                 break;
9828         case DRM_MODE_ROTATE_0:
9829         case DRM_MODE_ROTATE_180:
9830         default:
9831                 *src_w = plane_state->src_w >> 16;
9832                 *src_h = plane_state->src_h >> 16;
9833                 break;
9834         }
9835 }
9836
9837 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9838                                 struct drm_crtc *crtc,
9839                                 struct drm_crtc_state *new_crtc_state)
9840 {
9841         struct drm_plane *cursor = crtc->cursor, *underlying;
9842         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9843         int i;
9844         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9845         int cursor_src_w, cursor_src_h;
9846         int underlying_src_w, underlying_src_h;
9847
9848         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9849          * cursor per pipe but it's going to inherit the scaling and
9850          * positioning from the underlying pipe. Check the cursor plane's
9851          * blending properties match the underlying planes'. */
9852
9853         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9854         if (!new_cursor_state || !new_cursor_state->fb) {
9855                 return 0;
9856         }
9857
9858         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9859         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9860         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9861
9862         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9863                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9864                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9865                         continue;
9866
9867                 /* Ignore disabled planes */
9868                 if (!new_underlying_state->fb)
9869                         continue;
9870
9871                 dm_get_oriented_plane_size(new_underlying_state,
9872                                            &underlying_src_w, &underlying_src_h);
9873                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9874                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9875
9876                 if (cursor_scale_w != underlying_scale_w ||
9877                     cursor_scale_h != underlying_scale_h) {
9878                         drm_dbg_atomic(crtc->dev,
9879                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9880                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9881                         return -EINVAL;
9882                 }
9883
9884                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9885                 if (new_underlying_state->crtc_x <= 0 &&
9886                     new_underlying_state->crtc_y <= 0 &&
9887                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9888                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9889                         break;
9890         }
9891
9892         return 0;
9893 }
9894
9895 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9896 {
9897         struct drm_connector *connector;
9898         struct drm_connector_state *conn_state, *old_conn_state;
9899         struct amdgpu_dm_connector *aconnector = NULL;
9900         int i;
9901         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9902                 if (!conn_state->crtc)
9903                         conn_state = old_conn_state;
9904
9905                 if (conn_state->crtc != crtc)
9906                         continue;
9907
9908                 aconnector = to_amdgpu_dm_connector(connector);
9909                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9910                         aconnector = NULL;
9911                 else
9912                         break;
9913         }
9914
9915         if (!aconnector)
9916                 return 0;
9917
9918         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9919 }
9920
9921 /**
9922  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9923  *
9924  * @dev: The DRM device
9925  * @state: The atomic state to commit
9926  *
9927  * Validate that the given atomic state is programmable by DC into hardware.
9928  * This involves constructing a &struct dc_state reflecting the new hardware
9929  * state we wish to commit, then querying DC to see if it is programmable. It's
9930  * important not to modify the existing DC state. Otherwise, atomic_check
9931  * may unexpectedly commit hardware changes.
9932  *
9933  * When validating the DC state, it's important that the right locks are
9934  * acquired. For full updates case which removes/adds/updates streams on one
9935  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9936  * that any such full update commit will wait for completion of any outstanding
9937  * flip using DRMs synchronization events.
9938  *
9939  * Note that DM adds the affected connectors for all CRTCs in state, when that
9940  * might not seem necessary. This is because DC stream creation requires the
9941  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9942  * be possible but non-trivial - a possible TODO item.
9943  *
9944  * Return: -Error code if validation failed.
9945  */
9946 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9947                                   struct drm_atomic_state *state)
9948 {
9949         struct amdgpu_device *adev = drm_to_adev(dev);
9950         struct dm_atomic_state *dm_state = NULL;
9951         struct dc *dc = adev->dm.dc;
9952         struct drm_connector *connector;
9953         struct drm_connector_state *old_con_state, *new_con_state;
9954         struct drm_crtc *crtc;
9955         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9956         struct drm_plane *plane;
9957         struct drm_plane_state *old_plane_state, *new_plane_state;
9958         enum dc_status status;
9959         int ret, i;
9960         bool lock_and_validation_needed = false;
9961         bool is_top_most_overlay = true;
9962         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9963         struct drm_dp_mst_topology_mgr *mgr;
9964         struct drm_dp_mst_topology_state *mst_state;
9965         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9966
9967         trace_amdgpu_dm_atomic_check_begin(state);
9968
9969         ret = drm_atomic_helper_check_modeset(dev, state);
9970         if (ret) {
9971                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9972                 goto fail;
9973         }
9974
9975         /* Check connector changes */
9976         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9977                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9978                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9979
9980                 /* Skip connectors that are disabled or part of modeset already. */
9981                 if (!new_con_state->crtc)
9982                         continue;
9983
9984                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9985                 if (IS_ERR(new_crtc_state)) {
9986                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9987                         ret = PTR_ERR(new_crtc_state);
9988                         goto fail;
9989                 }
9990
9991                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9992                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9993                         new_crtc_state->connectors_changed = true;
9994         }
9995
9996         if (dc_resource_is_dsc_encoding_supported(dc)) {
9997                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9998                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9999                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10000                                 if (ret) {
10001                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10002                                         goto fail;
10003                                 }
10004                         }
10005                 }
10006         }
10007         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10008                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10009
10010                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10011                     !new_crtc_state->color_mgmt_changed &&
10012                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10013                         dm_old_crtc_state->dsc_force_changed == false)
10014                         continue;
10015
10016                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10017                 if (ret) {
10018                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10019                         goto fail;
10020                 }
10021
10022                 if (!new_crtc_state->enable)
10023                         continue;
10024
10025                 ret = drm_atomic_add_affected_connectors(state, crtc);
10026                 if (ret) {
10027                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10028                         goto fail;
10029                 }
10030
10031                 ret = drm_atomic_add_affected_planes(state, crtc);
10032                 if (ret) {
10033                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10034                         goto fail;
10035                 }
10036
10037                 if (dm_old_crtc_state->dsc_force_changed)
10038                         new_crtc_state->mode_changed = true;
10039         }
10040
10041         /*
10042          * Add all primary and overlay planes on the CRTC to the state
10043          * whenever a plane is enabled to maintain correct z-ordering
10044          * and to enable fast surface updates.
10045          */
10046         drm_for_each_crtc(crtc, dev) {
10047                 bool modified = false;
10048
10049                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10050                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10051                                 continue;
10052
10053                         if (new_plane_state->crtc == crtc ||
10054                             old_plane_state->crtc == crtc) {
10055                                 modified = true;
10056                                 break;
10057                         }
10058                 }
10059
10060                 if (!modified)
10061                         continue;
10062
10063                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10064                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10065                                 continue;
10066
10067                         new_plane_state =
10068                                 drm_atomic_get_plane_state(state, plane);
10069
10070                         if (IS_ERR(new_plane_state)) {
10071                                 ret = PTR_ERR(new_plane_state);
10072                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10073                                 goto fail;
10074                         }
10075                 }
10076         }
10077
10078         /*
10079          * DC consults the zpos (layer_index in DC terminology) to determine the
10080          * hw plane on which to enable the hw cursor (see
10081          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10082          * atomic state, so call drm helper to normalize zpos.
10083          */
10084         ret = drm_atomic_normalize_zpos(dev, state);
10085         if (ret) {
10086                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10087                 goto fail;
10088         }
10089
10090         /* Remove exiting planes if they are modified */
10091         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10092                 ret = dm_update_plane_state(dc, state, plane,
10093                                             old_plane_state,
10094                                             new_plane_state,
10095                                             false,
10096                                             &lock_and_validation_needed,
10097                                             &is_top_most_overlay);
10098                 if (ret) {
10099                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10100                         goto fail;
10101                 }
10102         }
10103
10104         /* Disable all crtcs which require disable */
10105         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10106                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10107                                            old_crtc_state,
10108                                            new_crtc_state,
10109                                            false,
10110                                            &lock_and_validation_needed);
10111                 if (ret) {
10112                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10113                         goto fail;
10114                 }
10115         }
10116
10117         /* Enable all crtcs which require enable */
10118         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10119                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10120                                            old_crtc_state,
10121                                            new_crtc_state,
10122                                            true,
10123                                            &lock_and_validation_needed);
10124                 if (ret) {
10125                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10126                         goto fail;
10127                 }
10128         }
10129
10130         /* Add new/modified planes */
10131         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10132                 ret = dm_update_plane_state(dc, state, plane,
10133                                             old_plane_state,
10134                                             new_plane_state,
10135                                             true,
10136                                             &lock_and_validation_needed,
10137                                             &is_top_most_overlay);
10138                 if (ret) {
10139                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10140                         goto fail;
10141                 }
10142         }
10143
10144         if (dc_resource_is_dsc_encoding_supported(dc)) {
10145                 ret = pre_validate_dsc(state, &dm_state, vars);
10146                 if (ret != 0)
10147                         goto fail;
10148         }
10149
10150         /* Run this here since we want to validate the streams we created */
10151         ret = drm_atomic_helper_check_planes(dev, state);
10152         if (ret) {
10153                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10154                 goto fail;
10155         }
10156
10157         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10158                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10159                 if (dm_new_crtc_state->mpo_requested)
10160                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10161         }
10162
10163         /* Check cursor planes scaling */
10164         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10165                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10166                 if (ret) {
10167                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10168                         goto fail;
10169                 }
10170         }
10171
10172         if (state->legacy_cursor_update) {
10173                 /*
10174                  * This is a fast cursor update coming from the plane update
10175                  * helper, check if it can be done asynchronously for better
10176                  * performance.
10177                  */
10178                 state->async_update =
10179                         !drm_atomic_helper_async_check(dev, state);
10180
10181                 /*
10182                  * Skip the remaining global validation if this is an async
10183                  * update. Cursor updates can be done without affecting
10184                  * state or bandwidth calcs and this avoids the performance
10185                  * penalty of locking the private state object and
10186                  * allocating a new dc_state.
10187                  */
10188                 if (state->async_update)
10189                         return 0;
10190         }
10191
10192         /* Check scaling and underscan changes*/
10193         /* TODO Removed scaling changes validation due to inability to commit
10194          * new stream into context w\o causing full reset. Need to
10195          * decide how to handle.
10196          */
10197         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10198                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10199                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10200                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10201
10202                 /* Skip any modesets/resets */
10203                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10204                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10205                         continue;
10206
10207                 /* Skip any thing not scale or underscan changes */
10208                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10209                         continue;
10210
10211                 lock_and_validation_needed = true;
10212         }
10213
10214         /* set the slot info for each mst_state based on the link encoding format */
10215         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10216                 struct amdgpu_dm_connector *aconnector;
10217                 struct drm_connector *connector;
10218                 struct drm_connector_list_iter iter;
10219                 u8 link_coding_cap;
10220
10221                 drm_connector_list_iter_begin(dev, &iter);
10222                 drm_for_each_connector_iter(connector, &iter) {
10223                         if (connector->index == mst_state->mgr->conn_base_id) {
10224                                 aconnector = to_amdgpu_dm_connector(connector);
10225                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10226                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10227
10228                                 break;
10229                         }
10230                 }
10231                 drm_connector_list_iter_end(&iter);
10232         }
10233
10234         /**
10235          * Streams and planes are reset when there are changes that affect
10236          * bandwidth. Anything that affects bandwidth needs to go through
10237          * DC global validation to ensure that the configuration can be applied
10238          * to hardware.
10239          *
10240          * We have to currently stall out here in atomic_check for outstanding
10241          * commits to finish in this case because our IRQ handlers reference
10242          * DRM state directly - we can end up disabling interrupts too early
10243          * if we don't.
10244          *
10245          * TODO: Remove this stall and drop DM state private objects.
10246          */
10247         if (lock_and_validation_needed) {
10248                 ret = dm_atomic_get_state(state, &dm_state);
10249                 if (ret) {
10250                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10251                         goto fail;
10252                 }
10253
10254                 ret = do_aquire_global_lock(dev, state);
10255                 if (ret) {
10256                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10257                         goto fail;
10258                 }
10259
10260                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10261                 if (ret) {
10262                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10263                         ret = -EINVAL;
10264                         goto fail;
10265                 }
10266
10267                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10268                 if (ret) {
10269                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10270                         goto fail;
10271                 }
10272
10273                 /*
10274                  * Perform validation of MST topology in the state:
10275                  * We need to perform MST atomic check before calling
10276                  * dc_validate_global_state(), or there is a chance
10277                  * to get stuck in an infinite loop and hang eventually.
10278                  */
10279                 ret = drm_dp_mst_atomic_check(state);
10280                 if (ret) {
10281                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10282                         goto fail;
10283                 }
10284                 status = dc_validate_global_state(dc, dm_state->context, true);
10285                 if (status != DC_OK) {
10286                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10287                                        dc_status_to_str(status), status);
10288                         ret = -EINVAL;
10289                         goto fail;
10290                 }
10291         } else {
10292                 /*
10293                  * The commit is a fast update. Fast updates shouldn't change
10294                  * the DC context, affect global validation, and can have their
10295                  * commit work done in parallel with other commits not touching
10296                  * the same resource. If we have a new DC context as part of
10297                  * the DM atomic state from validation we need to free it and
10298                  * retain the existing one instead.
10299                  *
10300                  * Furthermore, since the DM atomic state only contains the DC
10301                  * context and can safely be annulled, we can free the state
10302                  * and clear the associated private object now to free
10303                  * some memory and avoid a possible use-after-free later.
10304                  */
10305
10306                 for (i = 0; i < state->num_private_objs; i++) {
10307                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10308
10309                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10310                                 int j = state->num_private_objs-1;
10311
10312                                 dm_atomic_destroy_state(obj,
10313                                                 state->private_objs[i].state);
10314
10315                                 /* If i is not at the end of the array then the
10316                                  * last element needs to be moved to where i was
10317                                  * before the array can safely be truncated.
10318                                  */
10319                                 if (i != j)
10320                                         state->private_objs[i] =
10321                                                 state->private_objs[j];
10322
10323                                 state->private_objs[j].ptr = NULL;
10324                                 state->private_objs[j].state = NULL;
10325                                 state->private_objs[j].old_state = NULL;
10326                                 state->private_objs[j].new_state = NULL;
10327
10328                                 state->num_private_objs = j;
10329                                 break;
10330                         }
10331                 }
10332         }
10333
10334         /* Store the overall update type for use later in atomic check. */
10335         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10336                 struct dm_crtc_state *dm_new_crtc_state =
10337                         to_dm_crtc_state(new_crtc_state);
10338
10339                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10340                                                          UPDATE_TYPE_FULL :
10341                                                          UPDATE_TYPE_FAST;
10342         }
10343
10344         /* Must be success */
10345         WARN_ON(ret);
10346
10347         trace_amdgpu_dm_atomic_check_finish(state, ret);
10348
10349         return ret;
10350
10351 fail:
10352         if (ret == -EDEADLK)
10353                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10354         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10355                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10356         else
10357                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10358
10359         trace_amdgpu_dm_atomic_check_finish(state, ret);
10360
10361         return ret;
10362 }
10363
10364 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10365                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10366 {
10367         u8 dpcd_data;
10368         bool capable = false;
10369
10370         if (amdgpu_dm_connector->dc_link &&
10371                 dm_helpers_dp_read_dpcd(
10372                                 NULL,
10373                                 amdgpu_dm_connector->dc_link,
10374                                 DP_DOWN_STREAM_PORT_COUNT,
10375                                 &dpcd_data,
10376                                 sizeof(dpcd_data))) {
10377                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10378         }
10379
10380         return capable;
10381 }
10382
10383 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10384                 unsigned int offset,
10385                 unsigned int total_length,
10386                 u8 *data,
10387                 unsigned int length,
10388                 struct amdgpu_hdmi_vsdb_info *vsdb)
10389 {
10390         bool res;
10391         union dmub_rb_cmd cmd;
10392         struct dmub_cmd_send_edid_cea *input;
10393         struct dmub_cmd_edid_cea_output *output;
10394
10395         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10396                 return false;
10397
10398         memset(&cmd, 0, sizeof(cmd));
10399
10400         input = &cmd.edid_cea.data.input;
10401
10402         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10403         cmd.edid_cea.header.sub_type = 0;
10404         cmd.edid_cea.header.payload_bytes =
10405                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10406         input->offset = offset;
10407         input->length = length;
10408         input->cea_total_length = total_length;
10409         memcpy(input->payload, data, length);
10410
10411         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10412         if (!res) {
10413                 DRM_ERROR("EDID CEA parser failed\n");
10414                 return false;
10415         }
10416
10417         output = &cmd.edid_cea.data.output;
10418
10419         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10420                 if (!output->ack.success) {
10421                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10422                                         output->ack.offset);
10423                 }
10424         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10425                 if (!output->amd_vsdb.vsdb_found)
10426                         return false;
10427
10428                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10429                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10430                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10431                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10432         } else {
10433                 DRM_WARN("Unknown EDID CEA parser results\n");
10434                 return false;
10435         }
10436
10437         return true;
10438 }
10439
10440 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10441                 u8 *edid_ext, int len,
10442                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10443 {
10444         int i;
10445
10446         /* send extension block to DMCU for parsing */
10447         for (i = 0; i < len; i += 8) {
10448                 bool res;
10449                 int offset;
10450
10451                 /* send 8 bytes a time */
10452                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10453                         return false;
10454
10455                 if (i+8 == len) {
10456                         /* EDID block sent completed, expect result */
10457                         int version, min_rate, max_rate;
10458
10459                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10460                         if (res) {
10461                                 /* amd vsdb found */
10462                                 vsdb_info->freesync_supported = 1;
10463                                 vsdb_info->amd_vsdb_version = version;
10464                                 vsdb_info->min_refresh_rate_hz = min_rate;
10465                                 vsdb_info->max_refresh_rate_hz = max_rate;
10466                                 return true;
10467                         }
10468                         /* not amd vsdb */
10469                         return false;
10470                 }
10471
10472                 /* check for ack*/
10473                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10474                 if (!res)
10475                         return false;
10476         }
10477
10478         return false;
10479 }
10480
10481 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10482                 u8 *edid_ext, int len,
10483                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10484 {
10485         int i;
10486
10487         /* send extension block to DMCU for parsing */
10488         for (i = 0; i < len; i += 8) {
10489                 /* send 8 bytes a time */
10490                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10491                         return false;
10492         }
10493
10494         return vsdb_info->freesync_supported;
10495 }
10496
10497 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10498                 u8 *edid_ext, int len,
10499                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10500 {
10501         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10502         bool ret;
10503
10504         mutex_lock(&adev->dm.dc_lock);
10505         if (adev->dm.dmub_srv)
10506                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10507         else
10508                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10509         mutex_unlock(&adev->dm.dc_lock);
10510         return ret;
10511 }
10512
10513 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10514                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10515 {
10516         u8 *edid_ext = NULL;
10517         int i;
10518         bool valid_vsdb_found = false;
10519
10520         /*----- drm_find_cea_extension() -----*/
10521         /* No EDID or EDID extensions */
10522         if (edid == NULL || edid->extensions == 0)
10523                 return -ENODEV;
10524
10525         /* Find CEA extension */
10526         for (i = 0; i < edid->extensions; i++) {
10527                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10528                 if (edid_ext[0] == CEA_EXT)
10529                         break;
10530         }
10531
10532         if (i == edid->extensions)
10533                 return -ENODEV;
10534
10535         /*----- cea_db_offsets() -----*/
10536         if (edid_ext[0] != CEA_EXT)
10537                 return -ENODEV;
10538
10539         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10540
10541         return valid_vsdb_found ? i : -ENODEV;
10542 }
10543
10544 /**
10545  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10546  *
10547  * @connector: Connector to query.
10548  * @edid: EDID from monitor
10549  *
10550  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10551  * track of some of the display information in the internal data struct used by
10552  * amdgpu_dm. This function checks which type of connector we need to set the
10553  * FreeSync parameters.
10554  */
10555 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10556                                     struct edid *edid)
10557 {
10558         int i = 0;
10559         struct detailed_timing *timing;
10560         struct detailed_non_pixel *data;
10561         struct detailed_data_monitor_range *range;
10562         struct amdgpu_dm_connector *amdgpu_dm_connector =
10563                         to_amdgpu_dm_connector(connector);
10564         struct dm_connector_state *dm_con_state = NULL;
10565         struct dc_sink *sink;
10566
10567         struct drm_device *dev = connector->dev;
10568         struct amdgpu_device *adev = drm_to_adev(dev);
10569         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10570         bool freesync_capable = false;
10571         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10572
10573         if (!connector->state) {
10574                 DRM_ERROR("%s - Connector has no state", __func__);
10575                 goto update;
10576         }
10577
10578         sink = amdgpu_dm_connector->dc_sink ?
10579                 amdgpu_dm_connector->dc_sink :
10580                 amdgpu_dm_connector->dc_em_sink;
10581
10582         if (!edid || !sink) {
10583                 dm_con_state = to_dm_connector_state(connector->state);
10584
10585                 amdgpu_dm_connector->min_vfreq = 0;
10586                 amdgpu_dm_connector->max_vfreq = 0;
10587                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10588                 connector->display_info.monitor_range.min_vfreq = 0;
10589                 connector->display_info.monitor_range.max_vfreq = 0;
10590                 freesync_capable = false;
10591
10592                 goto update;
10593         }
10594
10595         dm_con_state = to_dm_connector_state(connector->state);
10596
10597         if (!adev->dm.freesync_module)
10598                 goto update;
10599
10600         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10601                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10602                 bool edid_check_required = false;
10603
10604                 if (edid) {
10605                         edid_check_required = is_dp_capable_without_timing_msa(
10606                                                 adev->dm.dc,
10607                                                 amdgpu_dm_connector);
10608                 }
10609
10610                 if (edid_check_required == true && (edid->version > 1 ||
10611                    (edid->version == 1 && edid->revision > 1))) {
10612                         for (i = 0; i < 4; i++) {
10613
10614                                 timing  = &edid->detailed_timings[i];
10615                                 data    = &timing->data.other_data;
10616                                 range   = &data->data.range;
10617                                 /*
10618                                  * Check if monitor has continuous frequency mode
10619                                  */
10620                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10621                                         continue;
10622                                 /*
10623                                  * Check for flag range limits only. If flag == 1 then
10624                                  * no additional timing information provided.
10625                                  * Default GTF, GTF Secondary curve and CVT are not
10626                                  * supported
10627                                  */
10628                                 if (range->flags != 1)
10629                                         continue;
10630
10631                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10632                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10633                                 amdgpu_dm_connector->pixel_clock_mhz =
10634                                         range->pixel_clock_mhz * 10;
10635
10636                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10637                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10638
10639                                 break;
10640                         }
10641
10642                         if (amdgpu_dm_connector->max_vfreq -
10643                             amdgpu_dm_connector->min_vfreq > 10) {
10644
10645                                 freesync_capable = true;
10646                         }
10647                 }
10648         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10649                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10650                 if (i >= 0 && vsdb_info.freesync_supported) {
10651                         timing  = &edid->detailed_timings[i];
10652                         data    = &timing->data.other_data;
10653
10654                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10655                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10656                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10657                                 freesync_capable = true;
10658
10659                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10660                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10661                 }
10662         }
10663
10664         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10665
10666         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10667                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10668                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10669
10670                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10671                         amdgpu_dm_connector->as_type = as_type;
10672                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10673
10674                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10675                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10676                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10677                                 freesync_capable = true;
10678
10679                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10680                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10681                 }
10682         }
10683
10684 update:
10685         if (dm_con_state)
10686                 dm_con_state->freesync_capable = freesync_capable;
10687
10688         if (connector->vrr_capable_property)
10689                 drm_connector_set_vrr_capable_property(connector,
10690                                                        freesync_capable);
10691 }
10692
10693 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10694 {
10695         struct amdgpu_device *adev = drm_to_adev(dev);
10696         struct dc *dc = adev->dm.dc;
10697         int i;
10698
10699         mutex_lock(&adev->dm.dc_lock);
10700         if (dc->current_state) {
10701                 for (i = 0; i < dc->current_state->stream_count; ++i)
10702                         dc->current_state->streams[i]
10703                                 ->triggered_crtc_reset.enabled =
10704                                 adev->dm.force_timing_sync;
10705
10706                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10707                 dc_trigger_sync(dc, dc->current_state);
10708         }
10709         mutex_unlock(&adev->dm.dc_lock);
10710 }
10711
10712 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10713                        u32 value, const char *func_name)
10714 {
10715 #ifdef DM_CHECK_ADDR_0
10716         if (address == 0) {
10717                 DC_ERR("invalid register write. address = 0");
10718                 return;
10719         }
10720 #endif
10721         cgs_write_register(ctx->cgs_device, address, value);
10722         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10723 }
10724
10725 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10726                           const char *func_name)
10727 {
10728         u32 value;
10729 #ifdef DM_CHECK_ADDR_0
10730         if (address == 0) {
10731                 DC_ERR("invalid register read; address = 0\n");
10732                 return 0;
10733         }
10734 #endif
10735
10736         if (ctx->dmub_srv &&
10737             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10738             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10739                 ASSERT(false);
10740                 return 0;
10741         }
10742
10743         value = cgs_read_register(ctx->cgs_device, address);
10744
10745         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10746
10747         return value;
10748 }
10749
10750 int amdgpu_dm_process_dmub_aux_transfer_sync(
10751                 struct dc_context *ctx,
10752                 unsigned int link_index,
10753                 struct aux_payload *payload,
10754                 enum aux_return_code_type *operation_result)
10755 {
10756         struct amdgpu_device *adev = ctx->driver_context;
10757         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10758         int ret = -1;
10759
10760         mutex_lock(&adev->dm.dpia_aux_lock);
10761         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10762                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10763                 goto out;
10764         }
10765
10766         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10767                 DRM_ERROR("wait_for_completion_timeout timeout!");
10768                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10769                 goto out;
10770         }
10771
10772         if (p_notify->result != AUX_RET_SUCCESS) {
10773                 /*
10774                  * Transient states before tunneling is enabled could
10775                  * lead to this error. We can ignore this for now.
10776                  */
10777                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10778                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10779                                         payload->address, payload->length,
10780                                         p_notify->result);
10781                 }
10782                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10783                 goto out;
10784         }
10785
10786
10787         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10788         if (!payload->write && p_notify->aux_reply.length &&
10789                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10790
10791                 if (payload->length != p_notify->aux_reply.length) {
10792                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10793                                 p_notify->aux_reply.length,
10794                                         payload->address, payload->length);
10795                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10796                         goto out;
10797                 }
10798
10799                 memcpy(payload->data, p_notify->aux_reply.data,
10800                                 p_notify->aux_reply.length);
10801         }
10802
10803         /* success */
10804         ret = p_notify->aux_reply.length;
10805         *operation_result = p_notify->result;
10806 out:
10807         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10808         mutex_unlock(&adev->dm.dpia_aux_lock);
10809         return ret;
10810 }
10811
10812 int amdgpu_dm_process_dmub_set_config_sync(
10813                 struct dc_context *ctx,
10814                 unsigned int link_index,
10815                 struct set_config_cmd_payload *payload,
10816                 enum set_config_status *operation_result)
10817 {
10818         struct amdgpu_device *adev = ctx->driver_context;
10819         bool is_cmd_complete;
10820         int ret;
10821
10822         mutex_lock(&adev->dm.dpia_aux_lock);
10823         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10824                         link_index, payload, adev->dm.dmub_notify);
10825
10826         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10827                 ret = 0;
10828                 *operation_result = adev->dm.dmub_notify->sc_status;
10829         } else {
10830                 DRM_ERROR("wait_for_completion_timeout timeout!");
10831                 ret = -1;
10832                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10833         }
10834
10835         if (!is_cmd_complete)
10836                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10837         mutex_unlock(&adev->dm.dpia_aux_lock);
10838         return ret;
10839 }
10840
10841 /*
10842  * Check whether seamless boot is supported.
10843  *
10844  * So far we only support seamless boot on CHIP_VANGOGH.
10845  * If everything goes well, we may consider expanding
10846  * seamless boot to other ASICs.
10847  */
10848 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10849 {
10850         switch (adev->ip_versions[DCE_HWIP][0]) {
10851         case IP_VERSION(3, 0, 1):
10852                 if (!adev->mman.keep_stolen_vga_memory)
10853                         return true;
10854                 break;
10855         default:
10856                 break;
10857         }
10858
10859         return false;
10860 }
10861
10862 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10863 {
10864         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
10865 }
10866
10867 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10868 {
10869         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
10870 }