drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "bif/bif_4_1_d.h"
  50
  51 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  52
  53 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  54                              struct ttm_mem_reg *mem, unsigned num_pages,
  55                              uint64_t offset, unsigned window,
  56                              struct amdgpu_ring *ring,
  57                              uint64_t *addr);
  58
  59 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  60 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  61
  62 /*
  63  * Global memory.
  64  */
  65 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  66 {
  67         return ttm_mem_global_init(ref->object);
  68 }
  69
  70 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  71 {
  72         ttm_mem_global_release(ref->object);
  73 }
  74
  75 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  76 {
  77         struct drm_global_reference *global_ref;
  78         struct amdgpu_ring *ring;
  79         struct amd_sched_rq *rq;
  80         int r;
  81
  82         adev->mman.mem_global_referenced = false;
  83         global_ref = &adev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &amdgpu_ttm_mem_global_init;
  87         global_ref->release = &amdgpu_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 goto error_mem;
  93         }
  94
  95         adev->mman.bo_global_ref.mem_glob =
  96                 adev->mman.mem_global_ref.object;
  97         global_ref = &adev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 goto error_bo;
 106         }
 107
 108         mutex_init(&adev->mman.gtt_window_lock);
 109
 110         ring = adev->mman.buffer_funcs_ring;
 111         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 112         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 113                                   rq, amdgpu_sched_jobs);
 114         if (r) {
 115                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 116                 goto error_entity;
 117         }
 118
 119         adev->mman.mem_global_referenced = true;
 120
 121         return 0;
 122
 123 error_entity:
 124         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 125 error_bo:
 126         drm_global_item_unref(&adev->mman.mem_global_ref);
 127 error_mem:
 128         return r;
 129 }
 130
 131 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 132 {
 133         if (adev->mman.mem_global_referenced) {
 134                 amd_sched_entity_fini(adev->mman.entity.sched,
 135                                       &adev->mman.entity);
 136                 mutex_destroy(&adev->mman.gtt_window_lock);
 137                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 138                 drm_global_item_unref(&adev->mman.mem_global_ref);
 139                 adev->mman.mem_global_referenced = false;
 140         }
 141 }
 142
 143 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 144 {
 145         return 0;
 146 }
 147
 148 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 149                                 struct ttm_mem_type_manager *man)
 150 {
 151         struct amdgpu_device *adev;
 152
 153         adev = amdgpu_ttm_adev(bdev);
 154
 155         switch (type) {
 156         case TTM_PL_SYSTEM:
 157                 /* System memory */
 158                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 159                 man->available_caching = TTM_PL_MASK_CACHING;
 160                 man->default_caching = TTM_PL_FLAG_CACHED;
 161                 break;
 162         case TTM_PL_TT:
 163                 man->func = &amdgpu_gtt_mgr_func;
 164                 man->gpu_offset = adev->mc.gart_start;
 165                 man->available_caching = TTM_PL_MASK_CACHING;
 166                 man->default_caching = TTM_PL_FLAG_CACHED;
 167                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 168                 break;
 169         case TTM_PL_VRAM:
 170                 /* "On-card" video ram */
 171                 man->func = &amdgpu_vram_mgr_func;
 172                 man->gpu_offset = adev->mc.vram_start;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 174                              TTM_MEMTYPE_FLAG_MAPPABLE;
 175                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 176                 man->default_caching = TTM_PL_FLAG_WC;
 177                 break;
 178         case AMDGPU_PL_GDS:
 179         case AMDGPU_PL_GWS:
 180         case AMDGPU_PL_OA:
 181                 /* On-chip GDS memory*/
 182                 man->func = &ttm_bo_manager_func;
 183                 man->gpu_offset = 0;
 184                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 185                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 186                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 187                 break;
 188         default:
 189                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 190                 return -EINVAL;
 191         }
 192         return 0;
 193 }
 194
 195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 196                                 struct ttm_placement *placement)
 197 {
 198         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 199         struct amdgpu_bo *abo;
 200         static const struct ttm_place placements = {
 201                 .fpfn = 0,
 202                 .lpfn = 0,
 203                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 204         };
 205
 206         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 207                 placement->placement = &placements;
 208                 placement->busy_placement = &placements;
 209                 placement->num_placement = 1;
 210                 placement->num_busy_placement = 1;
 211                 return;
 212         }
 213         abo = ttm_to_amdgpu_bo(bo);
 214         switch (bo->mem.mem_type) {
 215         case TTM_PL_VRAM:
 216                 if (adev->mman.buffer_funcs &&
 217                     adev->mman.buffer_funcs_ring &&
 218                     adev->mman.buffer_funcs_ring->ready == false) {
 219                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 220                 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 221                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 222                         unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 223                         struct drm_mm_node *node = bo->mem.mm_node;
 224                         unsigned long pages_left;
 225
 226                         for (pages_left = bo->mem.num_pages;
 227                              pages_left;
 228                              pages_left -= node->size, node++) {
 229                                 if (node->start < fpfn)
 230                                         break;
 231                         }
 232
 233                         if (!pages_left)
 234                                 goto gtt;
 235
 236                         /* Try evicting to the CPU inaccessible part of VRAM
 237                          * first, but only set GTT as busy placement, so this
 238                          * BO will be evicted to GTT rather than causing other
 239                          * BOs to be evicted from VRAM
 240                          */
 241                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 242                                                          AMDGPU_GEM_DOMAIN_GTT);
 243                         abo->placements[0].fpfn = fpfn;
 244                         abo->placements[0].lpfn = 0;
 245                         abo->placement.busy_placement = &abo->placements[1];
 246                         abo->placement.num_busy_placement = 1;
 247                 } else {
 248 gtt:
 249                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 250                 }
 251                 break;
 252         case TTM_PL_TT:
 253         default:
 254                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 255         }
 256         *placement = abo->placement;
 257 }
 258
 259 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 260 {
 261         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 262
 263         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 264                 return -EPERM;
 265         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 266                                           filp->private_data);
 267 }
 268
 269 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 270                              struct ttm_mem_reg *new_mem)
 271 {
 272         struct ttm_mem_reg *old_mem = &bo->mem;
 273
 274         BUG_ON(old_mem->mm_node != NULL);
 275         *old_mem = *new_mem;
 276         new_mem->mm_node = NULL;
 277 }
 278
 279 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 280                                     struct drm_mm_node *mm_node,
 281                                     struct ttm_mem_reg *mem)
 282 {
 283         uint64_t addr = 0;
 284
 285         if (mem->mem_type != TTM_PL_TT ||
 286             amdgpu_gtt_mgr_is_allocated(mem)) {
 287                 addr = mm_node->start << PAGE_SHIFT;
 288                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 289         }
 290         return addr;
 291 }
 292
 293 /**
 294  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
 295  *  corresponding to @offset. It also modifies the offset to be
 296  *  within the drm_mm_node returned
 297  */
 298 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 299                                                unsigned long *offset)
 300 {
 301         struct drm_mm_node *mm_node = mem->mm_node;
 302
 303         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 304                 *offset -= (mm_node->size << PAGE_SHIFT);
 305                 ++mm_node;
 306         }
 307         return mm_node;
 308 }
 309
 310 /**
 311  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 312  *
 313  * The function copies @size bytes from {src->mem + src->offset} to
 314  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 315  * move and different for a BO to BO copy.
 316  *
 317  * @f: Returns the last fence if multiple jobs are submitted.
 318  */
 319 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 320                                struct amdgpu_copy_mem *src,
 321                                struct amdgpu_copy_mem *dst,
 322                                uint64_t size,
 323                                struct reservation_object *resv,
 324                                struct dma_fence **f)
 325 {
 326         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 327         struct drm_mm_node *src_mm, *dst_mm;
 328         uint64_t src_node_start, dst_node_start, src_node_size,
 329                  dst_node_size, src_page_offset, dst_page_offset;
 330         struct dma_fence *fence = NULL;
 331         int r = 0;
 332         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 333                                         AMDGPU_GPU_PAGE_SIZE);
 334
 335         if (!ring->ready) {
 336                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 337                 return -EINVAL;
 338         }
 339
 340         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 341         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 342                                              src->offset;
 343         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 344         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 345
 346         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 347         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 348                                              dst->offset;
 349         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 350         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 351
 352         mutex_lock(&adev->mman.gtt_window_lock);
 353
 354         while (size) {
 355                 unsigned long cur_size;
 356                 uint64_t from = src_node_start, to = dst_node_start;
 357                 struct dma_fence *next;
 358
 359                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 360                  * begins at an offset, then adjust the size accordingly
 361                  */
 362                 cur_size = min3(min(src_node_size, dst_node_size), size,
 363                                 GTT_MAX_BYTES);
 364                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 365                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 366                         cur_size -= max(src_page_offset, dst_page_offset);
 367
 368                 /* Map only what needs to be accessed. Map src to window 0 and
 369                  * dst to window 1
 370                  */
 371                 if (src->mem->mem_type == TTM_PL_TT &&
 372                     !amdgpu_gtt_mgr_is_allocated(src->mem)) {
 373                         r = amdgpu_map_buffer(src->bo, src->mem,
 374                                         PFN_UP(cur_size + src_page_offset),
 375                                         src_node_start, 0, ring,
 376                                         &from);
 377                         if (r)
 378                                 goto error;
 379                         /* Adjust the offset because amdgpu_map_buffer returns
 380                          * start of mapped page
 381                          */
 382                         from += src_page_offset;
 383                 }
 384
 385                 if (dst->mem->mem_type == TTM_PL_TT &&
 386                     !amdgpu_gtt_mgr_is_allocated(dst->mem)) {
 387                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 388                                         PFN_UP(cur_size + dst_page_offset),
 389                                         dst_node_start, 1, ring,
 390                                         &to);
 391                         if (r)
 392                                 goto error;
 393                         to += dst_page_offset;
 394                 }
 395
 396                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 397                                        resv, &next, false, true);
 398                 if (r)
 399                         goto error;
 400
 401                 dma_fence_put(fence);
 402                 fence = next;
 403
 404                 size -= cur_size;
 405                 if (!size)
 406                         break;
 407
 408                 src_node_size -= cur_size;
 409                 if (!src_node_size) {
 410                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 411                                                              src->mem);
 412                         src_node_size = (src_mm->size << PAGE_SHIFT);
 413                 } else {
 414                         src_node_start += cur_size;
 415                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 416                 }
 417                 dst_node_size -= cur_size;
 418                 if (!dst_node_size) {
 419                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 420                                                              dst->mem);
 421                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 422                 } else {
 423                         dst_node_start += cur_size;
 424                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 425                 }
 426         }
 427 error:
 428         mutex_unlock(&adev->mman.gtt_window_lock);
 429         if (f)
 430                 *f = dma_fence_get(fence);
 431         dma_fence_put(fence);
 432         return r;
 433 }
 434
 435
 436 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 437                             bool evict, bool no_wait_gpu,
 438                             struct ttm_mem_reg *new_mem,
 439                             struct ttm_mem_reg *old_mem)
 440 {
 441         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 442         struct amdgpu_copy_mem src, dst;
 443         struct dma_fence *fence = NULL;
 444         int r;
 445
 446         src.bo = bo;
 447         dst.bo = bo;
 448         src.mem = old_mem;
 449         dst.mem = new_mem;
 450         src.offset = 0;
 451         dst.offset = 0;
 452
 453         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 454                                        new_mem->num_pages << PAGE_SHIFT,
 455                                        bo->resv, &fence);
 456         if (r)
 457                 goto error;
 458
 459         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 460         dma_fence_put(fence);
 461         return r;
 462
 463 error:
 464         if (fence)
 465                 dma_fence_wait(fence, false);
 466         dma_fence_put(fence);
 467         return r;
 468 }
 469
 470 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 471                                 bool evict, bool interruptible,
 472                                 bool no_wait_gpu,
 473                                 struct ttm_mem_reg *new_mem)
 474 {
 475         struct amdgpu_device *adev;
 476         struct ttm_mem_reg *old_mem = &bo->mem;
 477         struct ttm_mem_reg tmp_mem;
 478         struct ttm_place placements;
 479         struct ttm_placement placement;
 480         int r;
 481
 482         adev = amdgpu_ttm_adev(bo->bdev);
 483         tmp_mem = *new_mem;
 484         tmp_mem.mm_node = NULL;
 485         placement.num_placement = 1;
 486         placement.placement = &placements;
 487         placement.num_busy_placement = 1;
 488         placement.busy_placement = &placements;
 489         placements.fpfn = 0;
 490         placements.lpfn = 0;
 491         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 492         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 493                              interruptible, no_wait_gpu);
 494         if (unlikely(r)) {
 495                 return r;
 496         }
 497
 498         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 499         if (unlikely(r)) {
 500                 goto out_cleanup;
 501         }
 502
 503         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 504         if (unlikely(r)) {
 505                 goto out_cleanup;
 506         }
 507         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 508         if (unlikely(r)) {
 509                 goto out_cleanup;
 510         }
 511         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 512 out_cleanup:
 513         ttm_bo_mem_put(bo, &tmp_mem);
 514         return r;
 515 }
 516
 517 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 518                                 bool evict, bool interruptible,
 519                                 bool no_wait_gpu,
 520                                 struct ttm_mem_reg *new_mem)
 521 {
 522         struct amdgpu_device *adev;
 523         struct ttm_mem_reg *old_mem = &bo->mem;
 524         struct ttm_mem_reg tmp_mem;
 525         struct ttm_placement placement;
 526         struct ttm_place placements;
 527         int r;
 528
 529         adev = amdgpu_ttm_adev(bo->bdev);
 530         tmp_mem = *new_mem;
 531         tmp_mem.mm_node = NULL;
 532         placement.num_placement = 1;
 533         placement.placement = &placements;
 534         placement.num_busy_placement = 1;
 535         placement.busy_placement = &placements;
 536         placements.fpfn = 0;
 537         placements.lpfn = 0;
 538         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 539         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 540                              interruptible, no_wait_gpu);
 541         if (unlikely(r)) {
 542                 return r;
 543         }
 544         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 545         if (unlikely(r)) {
 546                 goto out_cleanup;
 547         }
 548         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 549         if (unlikely(r)) {
 550                 goto out_cleanup;
 551         }
 552 out_cleanup:
 553         ttm_bo_mem_put(bo, &tmp_mem);
 554         return r;
 555 }
 556
 557 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 558                         bool evict, bool interruptible,
 559                         bool no_wait_gpu,
 560                         struct ttm_mem_reg *new_mem)
 561 {
 562         struct amdgpu_device *adev;
 563         struct amdgpu_bo *abo;
 564         struct ttm_mem_reg *old_mem = &bo->mem;
 565         int r;
 566
 567         /* Can't move a pinned BO */
 568         abo = ttm_to_amdgpu_bo(bo);
 569         if (WARN_ON_ONCE(abo->pin_count > 0))
 570                 return -EINVAL;
 571
 572         adev = amdgpu_ttm_adev(bo->bdev);
 573
 574         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 575                 amdgpu_move_null(bo, new_mem);
 576                 return 0;
 577         }
 578         if ((old_mem->mem_type == TTM_PL_TT &&
 579              new_mem->mem_type == TTM_PL_SYSTEM) ||
 580             (old_mem->mem_type == TTM_PL_SYSTEM &&
 581              new_mem->mem_type == TTM_PL_TT)) {
 582                 /* bind is enough */
 583                 amdgpu_move_null(bo, new_mem);
 584                 return 0;
 585         }
 586         if (adev->mman.buffer_funcs == NULL ||
 587             adev->mman.buffer_funcs_ring == NULL ||
 588             !adev->mman.buffer_funcs_ring->ready) {
 589                 /* use memcpy */
 590                 goto memcpy;
 591         }
 592
 593         if (old_mem->mem_type == TTM_PL_VRAM &&
 594             new_mem->mem_type == TTM_PL_SYSTEM) {
 595                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 596                                         no_wait_gpu, new_mem);
 597         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 598                    new_mem->mem_type == TTM_PL_VRAM) {
 599                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 600                                             no_wait_gpu, new_mem);
 601         } else {
 602                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 603         }
 604
 605         if (r) {
 606 memcpy:
 607                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 608                 if (r) {
 609                         return r;
 610                 }
 611         }
 612
 613         if (bo->type == ttm_bo_type_device &&
 614             new_mem->mem_type == TTM_PL_VRAM &&
 615             old_mem->mem_type != TTM_PL_VRAM) {
 616                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 617                  * accesses the BO after it's moved.
 618                  */
 619                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 620         }
 621
 622         /* update statistics */
 623         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 624         return 0;
 625 }
 626
 627 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 628 {
 629         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 630         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 631
 632         mem->bus.addr = NULL;
 633         mem->bus.offset = 0;
 634         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 635         mem->bus.base = 0;
 636         mem->bus.is_iomem = false;
 637         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 638                 return -EINVAL;
 639         switch (mem->mem_type) {
 640         case TTM_PL_SYSTEM:
 641                 /* system memory */
 642                 return 0;
 643         case TTM_PL_TT:
 644                 break;
 645         case TTM_PL_VRAM:
 646                 mem->bus.offset = mem->start << PAGE_SHIFT;
 647                 /* check if it's visible */
 648                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 649                         return -EINVAL;
 650                 mem->bus.base = adev->mc.aper_base;
 651                 mem->bus.is_iomem = true;
 652                 break;
 653         default:
 654                 return -EINVAL;
 655         }
 656         return 0;
 657 }
 658
 659 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 660 {
 661 }
 662
 663 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 664                                            unsigned long page_offset)
 665 {
 666         struct drm_mm_node *mm;
 667         unsigned long offset = (page_offset << PAGE_SHIFT);
 668
 669         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 670         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 671                 (offset >> PAGE_SHIFT);
 672 }
 673
 674 /*
 675  * TTM backend functions.
 676  */
 677 struct amdgpu_ttm_gup_task_list {
 678         struct list_head        list;
 679         struct task_struct      *task;
 680 };
 681
 682 struct amdgpu_ttm_tt {
 683         struct ttm_dma_tt       ttm;
 684         struct amdgpu_device    *adev;
 685         u64                     offset;
 686         uint64_t                userptr;
 687         struct mm_struct        *usermm;
 688         uint32_t                userflags;
 689         spinlock_t              guptasklock;
 690         struct list_head        guptasks;
 691         atomic_t                mmu_invalidations;
 692         uint32_t                last_set_pages;
 693         struct list_head        list;
 694 };
 695
 696 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 697 {
 698         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 699         unsigned int flags = 0;
 700         unsigned pinned = 0;
 701         int r;
 702
 703         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 704                 flags |= FOLL_WRITE;
 705
 706         down_read(&current->mm->mmap_sem);
 707
 708         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 709                 /* check that we only use anonymous memory
 710                    to prevent problems with writeback */
 711                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 712                 struct vm_area_struct *vma;
 713
 714                 vma = find_vma(gtt->usermm, gtt->userptr);
 715                 if (!vma || vma->vm_file || vma->vm_end < end) {
 716                         up_read(&current->mm->mmap_sem);
 717                         return -EPERM;
 718                 }
 719         }
 720
 721         do {
 722                 unsigned num_pages = ttm->num_pages - pinned;
 723                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 724                 struct page **p = pages + pinned;
 725                 struct amdgpu_ttm_gup_task_list guptask;
 726
 727                 guptask.task = current;
 728                 spin_lock(&gtt->guptasklock);
 729                 list_add(&guptask.list, &gtt->guptasks);
 730                 spin_unlock(&gtt->guptasklock);
 731
 732                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 733
 734                 spin_lock(&gtt->guptasklock);
 735                 list_del(&guptask.list);
 736                 spin_unlock(&gtt->guptasklock);
 737
 738                 if (r < 0)
 739                         goto release_pages;
 740
 741                 pinned += r;
 742
 743         } while (pinned < ttm->num_pages);
 744
 745         up_read(&current->mm->mmap_sem);
 746         return 0;
 747
 748 release_pages:
 749         release_pages(pages, pinned, 0);
 750         up_read(&current->mm->mmap_sem);
 751         return r;
 752 }
 753
 754 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 755 {
 756         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 757         unsigned i;
 758
 759         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 760         for (i = 0; i < ttm->num_pages; ++i) {
 761                 if (ttm->pages[i])
 762                         put_page(ttm->pages[i]);
 763
 764                 ttm->pages[i] = pages ? pages[i] : NULL;
 765         }
 766 }
 767
 768 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 769 {
 770         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 771         unsigned i;
 772
 773         for (i = 0; i < ttm->num_pages; ++i) {
 774                 struct page *page = ttm->pages[i];
 775
 776                 if (!page)
 777                         continue;
 778
 779                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 780                         set_page_dirty(page);
 781
 782                 mark_page_accessed(page);
 783         }
 784 }
 785
 786 /* prepare the sg table with the user pages */
 787 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 788 {
 789         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 790         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 791         unsigned nents;
 792         int r;
 793
 794         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 795         enum dma_data_direction direction = write ?
 796                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 797
 798         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 799                                       ttm->num_pages << PAGE_SHIFT,
 800                                       GFP_KERNEL);
 801         if (r)
 802                 goto release_sg;
 803
 804         r = -ENOMEM;
 805         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 806         if (nents != ttm->sg->nents)
 807                 goto release_sg;
 808
 809         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 810                                          gtt->ttm.dma_address, ttm->num_pages);
 811
 812         return 0;
 813
 814 release_sg:
 815         kfree(ttm->sg);
 816         return r;
 817 }
 818
 819 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 820 {
 821         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 822         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 823
 824         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 825         enum dma_data_direction direction = write ?
 826                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 827
 828         /* double check that we don't free the table twice */
 829         if (!ttm->sg->sgl)
 830                 return;
 831
 832         /* free the sg table and pages again */
 833         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 834
 835         amdgpu_ttm_tt_mark_user_pages(ttm);
 836
 837         sg_free_table(ttm->sg);
 838 }
 839
 840 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 841                                    struct ttm_mem_reg *bo_mem)
 842 {
 843         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 844         uint64_t flags;
 845         int r = 0;
 846
 847         if (gtt->userptr) {
 848                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 849                 if (r) {
 850                         DRM_ERROR("failed to pin userptr\n");
 851                         return r;
 852                 }
 853         }
 854         if (!ttm->num_pages) {
 855                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 856                      ttm->num_pages, bo_mem, ttm);
 857         }
 858
 859         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 860             bo_mem->mem_type == AMDGPU_PL_GWS ||
 861             bo_mem->mem_type == AMDGPU_PL_OA)
 862                 return -EINVAL;
 863
 864         if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
 865                 return 0;
 866
 867         spin_lock(&gtt->adev->gtt_list_lock);
 868         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 869         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 870         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 871                 ttm->pages, gtt->ttm.dma_address, flags);
 872
 873         if (r) {
 874                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 875                           ttm->num_pages, gtt->offset);
 876                 goto error_gart_bind;
 877         }
 878
 879         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 880 error_gart_bind:
 881         spin_unlock(&gtt->adev->gtt_list_lock);
 882         return r;
 883 }
 884
 885 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 886 {
 887         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 888
 889         return gtt && !list_empty(&gtt->list);
 890 }
 891
 892 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 893 {
 894         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 895         struct ttm_tt *ttm = bo->ttm;
 896         struct ttm_mem_reg tmp;
 897         struct ttm_placement placement;
 898         struct ttm_place placements;
 899         int r;
 900
 901         if (!ttm || amdgpu_ttm_is_bound(ttm))
 902                 return 0;
 903
 904         tmp = bo->mem;
 905         tmp.mm_node = NULL;
 906         placement.num_placement = 1;
 907         placement.placement = &placements;
 908         placement.num_busy_placement = 1;
 909         placement.busy_placement = &placements;
 910         placements.fpfn = 0;
 911         placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
 912         placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
 913
 914         r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
 915         if (unlikely(r))
 916                 return r;
 917
 918         r = ttm_bo_move_ttm(bo, true, false, &tmp);
 919         if (unlikely(r))
 920                 ttm_bo_mem_put(bo, &tmp);
 921         else
 922                 bo->offset = (bo->mem.start << PAGE_SHIFT) +
 923                         bo->bdev->man[bo->mem.mem_type].gpu_offset;
 924
 925         return r;
 926 }
 927
 928 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 929 {
 930         struct amdgpu_ttm_tt *gtt, *tmp;
 931         struct ttm_mem_reg bo_mem;
 932         uint64_t flags;
 933         int r;
 934
 935         bo_mem.mem_type = TTM_PL_TT;
 936         spin_lock(&adev->gtt_list_lock);
 937         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 938                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 939                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 940                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 941                                      flags);
 942                 if (r) {
 943                         spin_unlock(&adev->gtt_list_lock);
 944                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 945                                   gtt->ttm.ttm.num_pages, gtt->offset);
 946                         return r;
 947                 }
 948         }
 949         spin_unlock(&adev->gtt_list_lock);
 950         return 0;
 951 }
 952
 953 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 954 {
 955         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 956         int r;
 957
 958         if (gtt->userptr)
 959                 amdgpu_ttm_tt_unpin_userptr(ttm);
 960
 961         if (!amdgpu_ttm_is_bound(ttm))
 962                 return 0;
 963
 964         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 965         spin_lock(&gtt->adev->gtt_list_lock);
 966         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 967         if (r) {
 968                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 969                           gtt->ttm.ttm.num_pages, gtt->offset);
 970                 goto error_unbind;
 971         }
 972         list_del_init(&gtt->list);
 973 error_unbind:
 974         spin_unlock(&gtt->adev->gtt_list_lock);
 975         return r;
 976 }
 977
 978 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 979 {
 980         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 981
 982         ttm_dma_tt_fini(&gtt->ttm);
 983         kfree(gtt);
 984 }
 985
 986 static struct ttm_backend_func amdgpu_backend_func = {
 987         .bind = &amdgpu_ttm_backend_bind,
 988         .unbind = &amdgpu_ttm_backend_unbind,
 989         .destroy = &amdgpu_ttm_backend_destroy,
 990 };
 991
 992 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 993                                     unsigned long size, uint32_t page_flags,
 994                                     struct page *dummy_read_page)
 995 {
 996         struct amdgpu_device *adev;
 997         struct amdgpu_ttm_tt *gtt;
 998
 999         adev = amdgpu_ttm_adev(bdev);
1000
1001         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1002         if (gtt == NULL) {
1003                 return NULL;
1004         }
1005         gtt->ttm.ttm.func = &amdgpu_backend_func;
1006         gtt->adev = adev;
1007         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
1008                 kfree(gtt);
1009                 return NULL;
1010         }
1011         INIT_LIST_HEAD(&gtt->list);
1012         return &gtt->ttm.ttm;
1013 }
1014
1015 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
1016 {
1017         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1018         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1019         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1020
1021         if (ttm->state != tt_unpopulated)
1022                 return 0;
1023
1024         if (gtt && gtt->userptr) {
1025                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1026                 if (!ttm->sg)
1027                         return -ENOMEM;
1028
1029                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1030                 ttm->state = tt_unbound;
1031                 return 0;
1032         }
1033
1034         if (slave && ttm->sg) {
1035                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1036                                                  gtt->ttm.dma_address, ttm->num_pages);
1037                 ttm->state = tt_unbound;
1038                 return 0;
1039         }
1040
1041 #ifdef CONFIG_SWIOTLB
1042         if (swiotlb_nr_tbl()) {
1043                 return ttm_dma_populate(&gtt->ttm, adev->dev);
1044         }
1045 #endif
1046
1047         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
1048 }
1049
1050 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1051 {
1052         struct amdgpu_device *adev;
1053         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1054         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1055
1056         if (gtt && gtt->userptr) {
1057                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1058                 kfree(ttm->sg);
1059                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1060                 return;
1061         }
1062
1063         if (slave)
1064                 return;
1065
1066         adev = amdgpu_ttm_adev(ttm->bdev);
1067
1068 #ifdef CONFIG_SWIOTLB
1069         if (swiotlb_nr_tbl()) {
1070                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1071                 return;
1072         }
1073 #endif
1074
1075         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1076 }
1077
1078 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1079                               uint32_t flags)
1080 {
1081         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1082
1083         if (gtt == NULL)
1084                 return -EINVAL;
1085
1086         gtt->userptr = addr;
1087         gtt->usermm = current->mm;
1088         gtt->userflags = flags;
1089         spin_lock_init(&gtt->guptasklock);
1090         INIT_LIST_HEAD(&gtt->guptasks);
1091         atomic_set(&gtt->mmu_invalidations, 0);
1092         gtt->last_set_pages = 0;
1093
1094         return 0;
1095 }
1096
1097 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1098 {
1099         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1100
1101         if (gtt == NULL)
1102                 return NULL;
1103
1104         return gtt->usermm;
1105 }
1106
1107 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1108                                   unsigned long end)
1109 {
1110         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1111         struct amdgpu_ttm_gup_task_list *entry;
1112         unsigned long size;
1113
1114         if (gtt == NULL || !gtt->userptr)
1115                 return false;
1116
1117         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1118         if (gtt->userptr > end || gtt->userptr + size <= start)
1119                 return false;
1120
1121         spin_lock(&gtt->guptasklock);
1122         list_for_each_entry(entry, &gtt->guptasks, list) {
1123                 if (entry->task == current) {
1124                         spin_unlock(&gtt->guptasklock);
1125                         return false;
1126                 }
1127         }
1128         spin_unlock(&gtt->guptasklock);
1129
1130         atomic_inc(&gtt->mmu_invalidations);
1131
1132         return true;
1133 }
1134
1135 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1136                                        int *last_invalidated)
1137 {
1138         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1139         int prev_invalidated = *last_invalidated;
1140
1141         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1142         return prev_invalidated != *last_invalidated;
1143 }
1144
1145 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1146 {
1147         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1148
1149         if (gtt == NULL || !gtt->userptr)
1150                 return false;
1151
1152         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1153 }
1154
1155 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1156 {
1157         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1158
1159         if (gtt == NULL)
1160                 return false;
1161
1162         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1163 }
1164
1165 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1166                                  struct ttm_mem_reg *mem)
1167 {
1168         uint64_t flags = 0;
1169
1170         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1171                 flags |= AMDGPU_PTE_VALID;
1172
1173         if (mem && mem->mem_type == TTM_PL_TT) {
1174                 flags |= AMDGPU_PTE_SYSTEM;
1175
1176                 if (ttm->caching_state == tt_cached)
1177                         flags |= AMDGPU_PTE_SNOOPED;
1178         }
1179
1180         flags |= adev->gart.gart_pte_flags;
1181         flags |= AMDGPU_PTE_READABLE;
1182
1183         if (!amdgpu_ttm_tt_is_readonly(ttm))
1184                 flags |= AMDGPU_PTE_WRITEABLE;
1185
1186         return flags;
1187 }
1188
1189 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1190                                             const struct ttm_place *place)
1191 {
1192         unsigned long num_pages = bo->mem.num_pages;
1193         struct drm_mm_node *node = bo->mem.mm_node;
1194
1195         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1196                 return ttm_bo_eviction_valuable(bo, place);
1197
1198         switch (bo->mem.mem_type) {
1199         case TTM_PL_TT:
1200                 return true;
1201
1202         case TTM_PL_VRAM:
1203                 /* Check each drm MM node individually */
1204                 while (num_pages) {
1205                         if (place->fpfn < (node->start + node->size) &&
1206                             !(place->lpfn && place->lpfn <= node->start))
1207                                 return true;
1208
1209                         num_pages -= node->size;
1210                         ++node;
1211                 }
1212                 break;
1213
1214         default:
1215                 break;
1216         }
1217
1218         return ttm_bo_eviction_valuable(bo, place);
1219 }
1220
1221 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1222                                     unsigned long offset,
1223                                     void *buf, int len, int write)
1224 {
1225         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1226         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1227         struct drm_mm_node *nodes;
1228         uint32_t value = 0;
1229         int ret = 0;
1230         uint64_t pos;
1231         unsigned long flags;
1232
1233         if (bo->mem.mem_type != TTM_PL_VRAM)
1234                 return -EIO;
1235
1236         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1237         pos = (nodes->start << PAGE_SHIFT) + offset;
1238
1239         while (len && pos < adev->mc.mc_vram_size) {
1240                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1241                 uint32_t bytes = 4 - (pos & 3);
1242                 uint32_t shift = (pos & 3) * 8;
1243                 uint32_t mask = 0xffffffff << shift;
1244
1245                 if (len < bytes) {
1246                         mask &= 0xffffffff >> (bytes - len) * 8;
1247                         bytes = len;
1248                 }
1249
1250                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1251                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1252                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1253                 if (!write || mask != 0xffffffff)
1254                         value = RREG32_NO_KIQ(mmMM_DATA);
1255                 if (write) {
1256                         value &= ~mask;
1257                         value |= (*(uint32_t *)buf << shift) & mask;
1258                         WREG32_NO_KIQ(mmMM_DATA, value);
1259                 }
1260                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1261                 if (!write) {
1262                         value = (value & mask) >> shift;
1263                         memcpy(buf, &value, bytes);
1264                 }
1265
1266                 ret += bytes;
1267                 buf = (uint8_t *)buf + bytes;
1268                 pos += bytes;
1269                 len -= bytes;
1270                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1271                         ++nodes;
1272                         pos = (nodes->start << PAGE_SHIFT);
1273                 }
1274         }
1275
1276         return ret;
1277 }
1278
1279 static struct ttm_bo_driver amdgpu_bo_driver = {
1280         .ttm_tt_create = &amdgpu_ttm_tt_create,
1281         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1282         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1283         .invalidate_caches = &amdgpu_invalidate_caches,
1284         .init_mem_type = &amdgpu_init_mem_type,
1285         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1286         .evict_flags = &amdgpu_evict_flags,
1287         .move = &amdgpu_bo_move,
1288         .verify_access = &amdgpu_verify_access,
1289         .move_notify = &amdgpu_bo_move_notify,
1290         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1291         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1292         .io_mem_free = &amdgpu_ttm_io_mem_free,
1293         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1294         .access_memory = &amdgpu_ttm_access_memory
1295 };
1296
1297 int amdgpu_ttm_init(struct amdgpu_device *adev)
1298 {
1299         uint64_t gtt_size;
1300         int r;
1301         u64 vis_vram_limit;
1302
1303         r = amdgpu_ttm_global_init(adev);
1304         if (r) {
1305                 return r;
1306         }
1307         /* No others user of address space so set it to 0 */
1308         r = ttm_bo_device_init(&adev->mman.bdev,
1309                                adev->mman.bo_global_ref.ref.object,
1310                                &amdgpu_bo_driver,
1311                                adev->ddev->anon_inode->i_mapping,
1312                                DRM_FILE_PAGE_OFFSET,
1313                                adev->need_dma32);
1314         if (r) {
1315                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1316                 return r;
1317         }
1318         adev->mman.initialized = true;
1319         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1320                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1321         if (r) {
1322                 DRM_ERROR("Failed initializing VRAM heap.\n");
1323                 return r;
1324         }
1325
1326         /* Reduce size of CPU-visible VRAM if requested */
1327         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1328         if (amdgpu_vis_vram_limit > 0 &&
1329             vis_vram_limit <= adev->mc.visible_vram_size)
1330                 adev->mc.visible_vram_size = vis_vram_limit;
1331
1332         /* Change the size here instead of the init above so only lpfn is affected */
1333         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1334
1335         /*
1336          *The reserved vram for firmware must be pinned to the specified
1337          *place on the VRAM, so reserve it early.
1338          */
1339         r = amdgpu_fw_reserve_vram_init(adev);
1340         if (r) {
1341                 return r;
1342         }
1343
1344         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1345                                     AMDGPU_GEM_DOMAIN_VRAM,
1346                                     &adev->stolen_vga_memory,
1347                                     NULL, NULL);
1348         if (r)
1349                 return r;
1350         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1351                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1352
1353         if (amdgpu_gtt_size == -1)
1354                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1355                                adev->mc.mc_vram_size);
1356         else
1357                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1358         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1359         if (r) {
1360                 DRM_ERROR("Failed initializing GTT heap.\n");
1361                 return r;
1362         }
1363         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1364                  (unsigned)(gtt_size / (1024 * 1024)));
1365
1366         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1367         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1368         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1369         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1370         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1371         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1372         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1373         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1374         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1375         /* GDS Memory */
1376         if (adev->gds.mem.total_size) {
1377                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1378                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1379                 if (r) {
1380                         DRM_ERROR("Failed initializing GDS heap.\n");
1381                         return r;
1382                 }
1383         }
1384
1385         /* GWS */
1386         if (adev->gds.gws.total_size) {
1387                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1388                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1389                 if (r) {
1390                         DRM_ERROR("Failed initializing gws heap.\n");
1391                         return r;
1392                 }
1393         }
1394
1395         /* OA */
1396         if (adev->gds.oa.total_size) {
1397                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1398                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1399                 if (r) {
1400                         DRM_ERROR("Failed initializing oa heap.\n");
1401                         return r;
1402                 }
1403         }
1404
1405         r = amdgpu_ttm_debugfs_init(adev);
1406         if (r) {
1407                 DRM_ERROR("Failed to init debugfs\n");
1408                 return r;
1409         }
1410         return 0;
1411 }
1412
1413 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1414 {
1415         int r;
1416
1417         if (!adev->mman.initialized)
1418                 return;
1419         amdgpu_ttm_debugfs_fini(adev);
1420         if (adev->stolen_vga_memory) {
1421                 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1422                 if (r == 0) {
1423                         amdgpu_bo_unpin(adev->stolen_vga_memory);
1424                         amdgpu_bo_unreserve(adev->stolen_vga_memory);
1425                 }
1426                 amdgpu_bo_unref(&adev->stolen_vga_memory);
1427         }
1428         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1429         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1430         if (adev->gds.mem.total_size)
1431                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1432         if (adev->gds.gws.total_size)
1433                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1434         if (adev->gds.oa.total_size)
1435                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1436         ttm_bo_device_release(&adev->mman.bdev);
1437         amdgpu_gart_fini(adev);
1438         amdgpu_ttm_global_fini(adev);
1439         adev->mman.initialized = false;
1440         DRM_INFO("amdgpu: ttm finalized\n");
1441 }
1442
1443 /* this should only be called at bootup or when userspace
1444  * isn't running */
1445 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1446 {
1447         struct ttm_mem_type_manager *man;
1448
1449         if (!adev->mman.initialized)
1450                 return;
1451
1452         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1453         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1454         man->size = size >> PAGE_SHIFT;
1455 }
1456
1457 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1458 {
1459         struct drm_file *file_priv;
1460         struct amdgpu_device *adev;
1461
1462         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1463                 return -EINVAL;
1464
1465         file_priv = filp->private_data;
1466         adev = file_priv->minor->dev->dev_private;
1467         if (adev == NULL)
1468                 return -EINVAL;
1469
1470         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1471 }
1472
1473 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1474                              struct ttm_mem_reg *mem, unsigned num_pages,
1475                              uint64_t offset, unsigned window,
1476                              struct amdgpu_ring *ring,
1477                              uint64_t *addr)
1478 {
1479         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1480         struct amdgpu_device *adev = ring->adev;
1481         struct ttm_tt *ttm = bo->ttm;
1482         struct amdgpu_job *job;
1483         unsigned num_dw, num_bytes;
1484         dma_addr_t *dma_address;
1485         struct dma_fence *fence;
1486         uint64_t src_addr, dst_addr;
1487         uint64_t flags;
1488         int r;
1489
1490         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1491                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1492
1493         *addr = adev->mc.gart_start;
1494         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1495                 AMDGPU_GPU_PAGE_SIZE;
1496
1497         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1498         while (num_dw & 0x7)
1499                 num_dw++;
1500
1501         num_bytes = num_pages * 8;
1502
1503         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1504         if (r)
1505                 return r;
1506
1507         src_addr = num_dw * 4;
1508         src_addr += job->ibs[0].gpu_addr;
1509
1510         dst_addr = adev->gart.table_addr;
1511         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1512         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1513                                 dst_addr, num_bytes);
1514
1515         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1516         WARN_ON(job->ibs[0].length_dw > num_dw);
1517
1518         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1519         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1520         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1521                             &job->ibs[0].ptr[num_dw]);
1522         if (r)
1523                 goto error_free;
1524
1525         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1526                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1527         if (r)
1528                 goto error_free;
1529
1530         dma_fence_put(fence);
1531
1532         return r;
1533
1534 error_free:
1535         amdgpu_job_free(job);
1536         return r;
1537 }
1538
1539 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1540                        uint64_t dst_offset, uint32_t byte_count,
1541                        struct reservation_object *resv,
1542                        struct dma_fence **fence, bool direct_submit,
1543                        bool vm_needs_flush)
1544 {
1545         struct amdgpu_device *adev = ring->adev;
1546         struct amdgpu_job *job;
1547
1548         uint32_t max_bytes;
1549         unsigned num_loops, num_dw;
1550         unsigned i;
1551         int r;
1552
1553         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1554         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1555         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1556
1557         /* for IB padding */
1558         while (num_dw & 0x7)
1559                 num_dw++;
1560
1561         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1562         if (r)
1563                 return r;
1564
1565         job->vm_needs_flush = vm_needs_flush;
1566         if (resv) {
1567                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1568                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1569                                      false);
1570                 if (r) {
1571                         DRM_ERROR("sync failed (%d).\n", r);
1572                         goto error_free;
1573                 }
1574         }
1575
1576         for (i = 0; i < num_loops; i++) {
1577                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1578
1579                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1580                                         dst_offset, cur_size_in_bytes);
1581
1582                 src_offset += cur_size_in_bytes;
1583                 dst_offset += cur_size_in_bytes;
1584                 byte_count -= cur_size_in_bytes;
1585         }
1586
1587         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1588         WARN_ON(job->ibs[0].length_dw > num_dw);
1589         if (direct_submit) {
1590                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1591                                        NULL, fence);
1592                 job->fence = dma_fence_get(*fence);
1593                 if (r)
1594                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1595                 amdgpu_job_free(job);
1596         } else {
1597                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1598                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1599                 if (r)
1600                         goto error_free;
1601         }
1602
1603         return r;
1604
1605 error_free:
1606         amdgpu_job_free(job);
1607         return r;
1608 }
1609
1610 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1611                        uint64_t src_data,
1612                        struct reservation_object *resv,
1613                        struct dma_fence **fence)
1614 {
1615         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1616         uint32_t max_bytes = 8 *
1617                         adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
1618         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1619
1620         struct drm_mm_node *mm_node;
1621         unsigned long num_pages;
1622         unsigned int num_loops, num_dw;
1623
1624         struct amdgpu_job *job;
1625         int r;
1626
1627         if (!ring->ready) {
1628                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1629                 return -EINVAL;
1630         }
1631
1632         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1633                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1634                 if (r)
1635                         return r;
1636         }
1637
1638         num_pages = bo->tbo.num_pages;
1639         mm_node = bo->tbo.mem.mm_node;
1640         num_loops = 0;
1641         while (num_pages) {
1642                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1643
1644                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1645                 num_pages -= mm_node->size;
1646                 ++mm_node;
1647         }
1648
1649         /* num of dwords for each SDMA_OP_PTEPDE cmd */
1650         num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1651
1652         /* for IB padding */
1653         num_dw += 64;
1654
1655         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1656         if (r)
1657                 return r;
1658
1659         if (resv) {
1660                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1661                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1662                 if (r) {
1663                         DRM_ERROR("sync failed (%d).\n", r);
1664                         goto error_free;
1665                 }
1666         }
1667
1668         num_pages = bo->tbo.num_pages;
1669         mm_node = bo->tbo.mem.mm_node;
1670
1671         while (num_pages) {
1672                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1673                 uint64_t dst_addr;
1674
1675                 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1676
1677                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1678                 while (byte_count) {
1679                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1680
1681                         amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1682                                         dst_addr, 0,
1683                                         cur_size_in_bytes >> 3, 0,
1684                                         src_data);
1685
1686                         dst_addr += cur_size_in_bytes;
1687                         byte_count -= cur_size_in_bytes;
1688                 }
1689
1690                 num_pages -= mm_node->size;
1691                 ++mm_node;
1692         }
1693
1694         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1695         WARN_ON(job->ibs[0].length_dw > num_dw);
1696         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1697                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1698         if (r)
1699                 goto error_free;
1700
1701         return 0;
1702
1703 error_free:
1704         amdgpu_job_free(job);
1705         return r;
1706 }
1707
1708 #if defined(CONFIG_DEBUG_FS)
1709
1710 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1711 {
1712         struct drm_info_node *node = (struct drm_info_node *)m->private;
1713         unsigned ttm_pl = *(int *)node->info_ent->data;
1714         struct drm_device *dev = node->minor->dev;
1715         struct amdgpu_device *adev = dev->dev_private;
1716         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1717         struct drm_printer p = drm_seq_file_printer(m);
1718
1719         man->func->debug(man, &p);
1720         return 0;
1721 }
1722
1723 static int ttm_pl_vram = TTM_PL_VRAM;
1724 static int ttm_pl_tt = TTM_PL_TT;
1725
1726 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1727         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1728         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1729         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1730 #ifdef CONFIG_SWIOTLB
1731         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1732 #endif
1733 };
1734
1735 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1736                                     size_t size, loff_t *pos)
1737 {
1738         struct amdgpu_device *adev = file_inode(f)->i_private;
1739         ssize_t result = 0;
1740         int r;
1741
1742         if (size & 0x3 || *pos & 0x3)
1743                 return -EINVAL;
1744
1745         if (*pos >= adev->mc.mc_vram_size)
1746                 return -ENXIO;
1747
1748         while (size) {
1749                 unsigned long flags;
1750                 uint32_t value;
1751
1752                 if (*pos >= adev->mc.mc_vram_size)
1753                         return result;
1754
1755                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1756                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1757                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1758                 value = RREG32_NO_KIQ(mmMM_DATA);
1759                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1760
1761                 r = put_user(value, (uint32_t *)buf);
1762                 if (r)
1763                         return r;
1764
1765                 result += 4;
1766                 buf += 4;
1767                 *pos += 4;
1768                 size -= 4;
1769         }
1770
1771         return result;
1772 }
1773
1774 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1775                                     size_t size, loff_t *pos)
1776 {
1777         struct amdgpu_device *adev = file_inode(f)->i_private;
1778         ssize_t result = 0;
1779         int r;
1780
1781         if (size & 0x3 || *pos & 0x3)
1782                 return -EINVAL;
1783
1784         if (*pos >= adev->mc.mc_vram_size)
1785                 return -ENXIO;
1786
1787         while (size) {
1788                 unsigned long flags;
1789                 uint32_t value;
1790
1791                 if (*pos >= adev->mc.mc_vram_size)
1792                         return result;
1793
1794                 r = get_user(value, (uint32_t *)buf);
1795                 if (r)
1796                         return r;
1797
1798                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1799                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1800                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1801                 WREG32_NO_KIQ(mmMM_DATA, value);
1802                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1803
1804                 result += 4;
1805                 buf += 4;
1806                 *pos += 4;
1807                 size -= 4;
1808         }
1809
1810         return result;
1811 }
1812
1813 static const struct file_operations amdgpu_ttm_vram_fops = {
1814         .owner = THIS_MODULE,
1815         .read = amdgpu_ttm_vram_read,
1816         .write = amdgpu_ttm_vram_write,
1817         .llseek = default_llseek,
1818 };
1819
1820 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1821
1822 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1823                                    size_t size, loff_t *pos)
1824 {
1825         struct amdgpu_device *adev = file_inode(f)->i_private;
1826         ssize_t result = 0;
1827         int r;
1828
1829         while (size) {
1830                 loff_t p = *pos / PAGE_SIZE;
1831                 unsigned off = *pos & ~PAGE_MASK;
1832                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1833                 struct page *page;
1834                 void *ptr;
1835
1836                 if (p >= adev->gart.num_cpu_pages)
1837                         return result;
1838
1839                 page = adev->gart.pages[p];
1840                 if (page) {
1841                         ptr = kmap(page);
1842                         ptr += off;
1843
1844                         r = copy_to_user(buf, ptr, cur_size);
1845                         kunmap(adev->gart.pages[p]);
1846                 } else
1847                         r = clear_user(buf, cur_size);
1848
1849                 if (r)
1850                         return -EFAULT;
1851
1852                 result += cur_size;
1853                 buf += cur_size;
1854                 *pos += cur_size;
1855                 size -= cur_size;
1856         }
1857
1858         return result;
1859 }
1860
1861 static const struct file_operations amdgpu_ttm_gtt_fops = {
1862         .owner = THIS_MODULE,
1863         .read = amdgpu_ttm_gtt_read,
1864         .llseek = default_llseek
1865 };
1866
1867 #endif
1868
1869 static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
1870                                    size_t size, loff_t *pos)
1871 {
1872         struct amdgpu_device *adev = file_inode(f)->i_private;
1873         int r;
1874         uint64_t phys;
1875         struct iommu_domain *dom;
1876
1877         // always return 8 bytes
1878         if (size != 8)
1879                 return -EINVAL;
1880
1881         // only accept page addresses
1882         if (*pos & 0xFFF)
1883                 return -EINVAL;
1884
1885         dom = iommu_get_domain_for_dev(adev->dev);
1886         if (dom)
1887                 phys = iommu_iova_to_phys(dom, *pos);
1888         else
1889                 phys = *pos;
1890
1891         r = copy_to_user(buf, &phys, 8);
1892         if (r)
1893                 return -EFAULT;
1894
1895         return 8;
1896 }
1897
1898 static const struct file_operations amdgpu_ttm_iova_fops = {
1899         .owner = THIS_MODULE,
1900         .read = amdgpu_iova_to_phys_read,
1901         .llseek = default_llseek
1902 };
1903
1904 static const struct {
1905         char *name;
1906         const struct file_operations *fops;
1907         int domain;
1908 } ttm_debugfs_entries[] = {
1909         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
1910 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1911         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
1912 #endif
1913         { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
1914 };
1915
1916 #endif
1917
1918 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1919 {
1920 #if defined(CONFIG_DEBUG_FS)
1921         unsigned count;
1922
1923         struct drm_minor *minor = adev->ddev->primary;
1924         struct dentry *ent, *root = minor->debugfs_root;
1925
1926         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
1927                 ent = debugfs_create_file(
1928                                 ttm_debugfs_entries[count].name,
1929                                 S_IFREG | S_IRUGO, root,
1930                                 adev,
1931                                 ttm_debugfs_entries[count].fops);
1932                 if (IS_ERR(ent))
1933                         return PTR_ERR(ent);
1934                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
1935                         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1936                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
1937                         i_size_write(ent->d_inode, adev->mc.gart_size);
1938                 adev->mman.debugfs_entries[count] = ent;
1939         }
1940
1941         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1942
1943 #ifdef CONFIG_SWIOTLB
1944         if (!swiotlb_nr_tbl())
1945                 --count;
1946 #endif
1947
1948         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1949 #else
1950         return 0;
1951 #endif
1952 }
1953
1954 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1955 {
1956 #if defined(CONFIG_DEBUG_FS)
1957         unsigned i;
1958
1959         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
1960                 debugfs_remove(adev->mman.debugfs_entries[i]);
1961 #endif
1962 }