drivers/net/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <[email protected]>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/clk.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/crc32.h>
  28 #include <linux/err.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/if_vlan.h>
  32
  33 #include <bcm63xx_dev_enet.h>
  34 #include "bcm63xx_enet.h"
  35
  36 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  37 static char bcm_enet_driver_version[] = "1.0";
  38
  39 static int copybreak __read_mostly = 128;
  40 module_param(copybreak, int, 0);
  41 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  42
  43 /* io memory shared between all devices */
  44 static void __iomem *bcm_enet_shared_base;
  45
  46 /*
  47  * io helpers to access mac registers
  48  */
  49 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  50 {
  51         return bcm_readl(priv->base + off);
  52 }
  53
  54 static inline void enet_writel(struct bcm_enet_priv *priv,
  55                                u32 val, u32 off)
  56 {
  57         bcm_writel(val, priv->base + off);
  58 }
  59
  60 /*
  61  * io helpers to access shared registers
  62  */
  63 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
  64 {
  65         return bcm_readl(bcm_enet_shared_base + off);
  66 }
  67
  68 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
  69                                        u32 val, u32 off)
  70 {
  71         bcm_writel(val, bcm_enet_shared_base + off);
  72 }
  73
  74 /*
  75  * write given data into mii register and wait for transfer to end
  76  * with timeout (average measured transfer time is 25us)
  77  */
  78 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
  79 {
  80         int limit;
  81
  82         /* make sure mii interrupt status is cleared */
  83         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
  84
  85         enet_writel(priv, data, ENET_MIIDATA_REG);
  86         wmb();
  87
  88         /* busy wait on mii interrupt bit, with timeout */
  89         limit = 1000;
  90         do {
  91                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
  92                         break;
  93                 udelay(1);
  94         } while (limit-- > 0);
  95
  96         return (limit < 0) ? 1 : 0;
  97 }
  98
  99 /*
 100  * MII internal read callback
 101  */
 102 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 103                               int regnum)
 104 {
 105         u32 tmp, val;
 106
 107         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 108         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 109         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 110         tmp |= ENET_MIIDATA_OP_READ_MASK;
 111
 112         if (do_mdio_op(priv, tmp))
 113                 return -1;
 114
 115         val = enet_readl(priv, ENET_MIIDATA_REG);
 116         val &= 0xffff;
 117         return val;
 118 }
 119
 120 /*
 121  * MII internal write callback
 122  */
 123 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 124                                int regnum, u16 value)
 125 {
 126         u32 tmp;
 127
 128         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 129         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 130         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 131         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 132         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 133
 134         (void)do_mdio_op(priv, tmp);
 135         return 0;
 136 }
 137
 138 /*
 139  * MII read callback from phylib
 140  */
 141 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 142                                      int regnum)
 143 {
 144         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 145 }
 146
 147 /*
 148  * MII write callback from phylib
 149  */
 150 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 151                                       int regnum, u16 value)
 152 {
 153         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 154 }
 155
 156 /*
 157  * MII read callback from mii core
 158  */
 159 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 160                                   int regnum)
 161 {
 162         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 163 }
 164
 165 /*
 166  * MII write callback from mii core
 167  */
 168 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 169                                     int regnum, int value)
 170 {
 171         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 172 }
 173
 174 /*
 175  * refill rx queue
 176  */
 177 static int bcm_enet_refill_rx(struct net_device *dev)
 178 {
 179         struct bcm_enet_priv *priv;
 180
 181         priv = netdev_priv(dev);
 182
 183         while (priv->rx_desc_count < priv->rx_ring_size) {
 184                 struct bcm_enet_desc *desc;
 185                 struct sk_buff *skb;
 186                 dma_addr_t p;
 187                 int desc_idx;
 188                 u32 len_stat;
 189
 190                 desc_idx = priv->rx_dirty_desc;
 191                 desc = &priv->rx_desc_cpu[desc_idx];
 192
 193                 if (!priv->rx_skb[desc_idx]) {
 194                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 195                         if (!skb)
 196                                 break;
 197                         priv->rx_skb[desc_idx] = skb;
 198
 199                         p = dma_map_single(&priv->pdev->dev, skb->data,
 200                                            priv->rx_skb_size,
 201                                            DMA_FROM_DEVICE);
 202                         desc->address = p;
 203                 }
 204
 205                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 206                 len_stat |= DMADESC_OWNER_MASK;
 207                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 208                         len_stat |= DMADESC_WRAP_MASK;
 209                         priv->rx_dirty_desc = 0;
 210                 } else {
 211                         priv->rx_dirty_desc++;
 212                 }
 213                 wmb();
 214                 desc->len_stat = len_stat;
 215
 216                 priv->rx_desc_count++;
 217
 218                 /* tell dma engine we allocated one buffer */
 219                 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 220         }
 221
 222         /* If rx ring is still empty, set a timer to try allocating
 223          * again at a later time. */
 224         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 225                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 226                 priv->rx_timeout.expires = jiffies + HZ;
 227                 add_timer(&priv->rx_timeout);
 228         }
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * timer callback to defer refill rx queue in case we're OOM
 235  */
 236 static void bcm_enet_refill_rx_timer(unsigned long data)
 237 {
 238         struct net_device *dev;
 239         struct bcm_enet_priv *priv;
 240
 241         dev = (struct net_device *)data;
 242         priv = netdev_priv(dev);
 243
 244         spin_lock(&priv->rx_lock);
 245         bcm_enet_refill_rx((struct net_device *)data);
 246         spin_unlock(&priv->rx_lock);
 247 }
 248
 249 /*
 250  * extract packet from rx queue
 251  */
 252 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 253 {
 254         struct bcm_enet_priv *priv;
 255         struct device *kdev;
 256         int processed;
 257
 258         priv = netdev_priv(dev);
 259         kdev = &priv->pdev->dev;
 260         processed = 0;
 261
 262         /* don't scan ring further than number of refilled
 263          * descriptor */
 264         if (budget > priv->rx_desc_count)
 265                 budget = priv->rx_desc_count;
 266
 267         do {
 268                 struct bcm_enet_desc *desc;
 269                 struct sk_buff *skb;
 270                 int desc_idx;
 271                 u32 len_stat;
 272                 unsigned int len;
 273
 274                 desc_idx = priv->rx_curr_desc;
 275                 desc = &priv->rx_desc_cpu[desc_idx];
 276
 277                 /* make sure we actually read the descriptor status at
 278                  * each loop */
 279                 rmb();
 280
 281                 len_stat = desc->len_stat;
 282
 283                 /* break if dma ownership belongs to hw */
 284                 if (len_stat & DMADESC_OWNER_MASK)
 285                         break;
 286
 287                 processed++;
 288                 priv->rx_curr_desc++;
 289                 if (priv->rx_curr_desc == priv->rx_ring_size)
 290                         priv->rx_curr_desc = 0;
 291                 priv->rx_desc_count--;
 292
 293                 /* if the packet does not have start of packet _and_
 294                  * end of packet flag set, then just recycle it */
 295                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 296                         priv->stats.rx_dropped++;
 297                         continue;
 298                 }
 299
 300                 /* recycle packet if it's marked as bad */
 301                 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
 302                         priv->stats.rx_errors++;
 303
 304                         if (len_stat & DMADESC_OVSIZE_MASK)
 305                                 priv->stats.rx_length_errors++;
 306                         if (len_stat & DMADESC_CRC_MASK)
 307                                 priv->stats.rx_crc_errors++;
 308                         if (len_stat & DMADESC_UNDER_MASK)
 309                                 priv->stats.rx_frame_errors++;
 310                         if (len_stat & DMADESC_OV_MASK)
 311                                 priv->stats.rx_fifo_errors++;
 312                         continue;
 313                 }
 314
 315                 /* valid packet */
 316                 skb = priv->rx_skb[desc_idx];
 317                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 318                 /* don't include FCS */
 319                 len -= 4;
 320
 321                 if (len < copybreak) {
 322                         struct sk_buff *nskb;
 323
 324                         nskb = netdev_alloc_skb_ip_align(dev, len);
 325                         if (!nskb) {
 326                                 /* forget packet, just rearm desc */
 327                                 priv->stats.rx_dropped++;
 328                                 continue;
 329                         }
 330
 331                         dma_sync_single_for_cpu(kdev, desc->address,
 332                                                 len, DMA_FROM_DEVICE);
 333                         memcpy(nskb->data, skb->data, len);
 334                         dma_sync_single_for_device(kdev, desc->address,
 335                                                    len, DMA_FROM_DEVICE);
 336                         skb = nskb;
 337                 } else {
 338                         dma_unmap_single(&priv->pdev->dev, desc->address,
 339                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 340                         priv->rx_skb[desc_idx] = NULL;
 341                 }
 342
 343                 skb_put(skb, len);
 344                 skb->protocol = eth_type_trans(skb, dev);
 345                 priv->stats.rx_packets++;
 346                 priv->stats.rx_bytes += len;
 347                 netif_receive_skb(skb);
 348
 349         } while (--budget > 0);
 350
 351         if (processed || !priv->rx_desc_count) {
 352                 bcm_enet_refill_rx(dev);
 353
 354                 /* kick rx dma */
 355                 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 356                                 ENETDMA_CHANCFG_REG(priv->rx_chan));
 357         }
 358
 359         return processed;
 360 }
 361
 362
 363 /*
 364  * try to or force reclaim of transmitted buffers
 365  */
 366 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 367 {
 368         struct bcm_enet_priv *priv;
 369         int released;
 370
 371         priv = netdev_priv(dev);
 372         released = 0;
 373
 374         while (priv->tx_desc_count < priv->tx_ring_size) {
 375                 struct bcm_enet_desc *desc;
 376                 struct sk_buff *skb;
 377
 378                 /* We run in a bh and fight against start_xmit, which
 379                  * is called with bh disabled  */
 380                 spin_lock(&priv->tx_lock);
 381
 382                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 383
 384                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 385                         spin_unlock(&priv->tx_lock);
 386                         break;
 387                 }
 388
 389                 /* ensure other field of the descriptor were not read
 390                  * before we checked ownership */
 391                 rmb();
 392
 393                 skb = priv->tx_skb[priv->tx_dirty_desc];
 394                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 395                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 396                                  DMA_TO_DEVICE);
 397
 398                 priv->tx_dirty_desc++;
 399                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 400                         priv->tx_dirty_desc = 0;
 401                 priv->tx_desc_count++;
 402
 403                 spin_unlock(&priv->tx_lock);
 404
 405                 if (desc->len_stat & DMADESC_UNDER_MASK)
 406                         priv->stats.tx_errors++;
 407
 408                 dev_kfree_skb(skb);
 409                 released++;
 410         }
 411
 412         if (netif_queue_stopped(dev) && released)
 413                 netif_wake_queue(dev);
 414
 415         return released;
 416 }
 417
 418 /*
 419  * poll func, called by network core
 420  */
 421 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 422 {
 423         struct bcm_enet_priv *priv;
 424         struct net_device *dev;
 425         int tx_work_done, rx_work_done;
 426
 427         priv = container_of(napi, struct bcm_enet_priv, napi);
 428         dev = priv->net_dev;
 429
 430         /* ack interrupts */
 431         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 432                         ENETDMA_IR_REG(priv->rx_chan));
 433         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 434                         ENETDMA_IR_REG(priv->tx_chan));
 435
 436         /* reclaim sent skb */
 437         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 438
 439         spin_lock(&priv->rx_lock);
 440         rx_work_done = bcm_enet_receive_queue(dev, budget);
 441         spin_unlock(&priv->rx_lock);
 442
 443         if (rx_work_done >= budget || tx_work_done > 0) {
 444                 /* rx/tx queue is not yet empty/clean */
 445                 return rx_work_done;
 446         }
 447
 448         /* no more packet in rx/tx queue, remove device from poll
 449          * queue */
 450         napi_complete(napi);
 451
 452         /* restore rx/tx interrupt */
 453         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 454                         ENETDMA_IRMASK_REG(priv->rx_chan));
 455         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 456                         ENETDMA_IRMASK_REG(priv->tx_chan));
 457
 458         return rx_work_done;
 459 }
 460
 461 /*
 462  * mac interrupt handler
 463  */
 464 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 465 {
 466         struct net_device *dev;
 467         struct bcm_enet_priv *priv;
 468         u32 stat;
 469
 470         dev = dev_id;
 471         priv = netdev_priv(dev);
 472
 473         stat = enet_readl(priv, ENET_IR_REG);
 474         if (!(stat & ENET_IR_MIB))
 475                 return IRQ_NONE;
 476
 477         /* clear & mask interrupt */
 478         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 479         enet_writel(priv, 0, ENET_IRMASK_REG);
 480
 481         /* read mib registers in workqueue */
 482         schedule_work(&priv->mib_update_task);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 /*
 488  * rx/tx dma interrupt handler
 489  */
 490 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 491 {
 492         struct net_device *dev;
 493         struct bcm_enet_priv *priv;
 494
 495         dev = dev_id;
 496         priv = netdev_priv(dev);
 497
 498         /* mask rx/tx interrupts */
 499         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 500         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 501
 502         napi_schedule(&priv->napi);
 503
 504         return IRQ_HANDLED;
 505 }
 506
 507 /*
 508  * tx request callback
 509  */
 510 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 511 {
 512         struct bcm_enet_priv *priv;
 513         struct bcm_enet_desc *desc;
 514         u32 len_stat;
 515         int ret;
 516
 517         priv = netdev_priv(dev);
 518
 519         /* lock against tx reclaim */
 520         spin_lock(&priv->tx_lock);
 521
 522         /* make sure  the tx hw queue  is not full,  should not happen
 523          * since we stop queue before it's the case */
 524         if (unlikely(!priv->tx_desc_count)) {
 525                 netif_stop_queue(dev);
 526                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 527                         "available?\n");
 528                 ret = NETDEV_TX_BUSY;
 529                 goto out_unlock;
 530         }
 531
 532         /* point to the next available desc */
 533         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 534         priv->tx_skb[priv->tx_curr_desc] = skb;
 535
 536         /* fill descriptor */
 537         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 538                                        DMA_TO_DEVICE);
 539
 540         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 541         len_stat |= DMADESC_ESOP_MASK |
 542                 DMADESC_APPEND_CRC |
 543                 DMADESC_OWNER_MASK;
 544
 545         priv->tx_curr_desc++;
 546         if (priv->tx_curr_desc == priv->tx_ring_size) {
 547                 priv->tx_curr_desc = 0;
 548                 len_stat |= DMADESC_WRAP_MASK;
 549         }
 550         priv->tx_desc_count--;
 551
 552         /* dma might be already polling, make sure we update desc
 553          * fields in correct order */
 554         wmb();
 555         desc->len_stat = len_stat;
 556         wmb();
 557
 558         /* kick tx dma */
 559         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 560                         ENETDMA_CHANCFG_REG(priv->tx_chan));
 561
 562         /* stop queue if no more desc available */
 563         if (!priv->tx_desc_count)
 564                 netif_stop_queue(dev);
 565
 566         priv->stats.tx_bytes += skb->len;
 567         priv->stats.tx_packets++;
 568         dev->trans_start = jiffies;
 569         ret = NETDEV_TX_OK;
 570
 571 out_unlock:
 572         spin_unlock(&priv->tx_lock);
 573         return ret;
 574 }
 575
 576 /*
 577  * Change the interface's mac address.
 578  */
 579 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 580 {
 581         struct bcm_enet_priv *priv;
 582         struct sockaddr *addr = p;
 583         u32 val;
 584
 585         priv = netdev_priv(dev);
 586         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 587
 588         /* use perfect match register 0 to store my mac address */
 589         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 590                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 591         enet_writel(priv, val, ENET_PML_REG(0));
 592
 593         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 594         val |= ENET_PMH_DATAVALID_MASK;
 595         enet_writel(priv, val, ENET_PMH_REG(0));
 596
 597         return 0;
 598 }
 599
 600 /*
 601  * Change rx mode (promiscous/allmulti) and update multicast list
 602  */
 603 static void bcm_enet_set_multicast_list(struct net_device *dev)
 604 {
 605         struct bcm_enet_priv *priv;
 606         struct netdev_hw_addr *ha;
 607         u32 val;
 608         int i;
 609
 610         priv = netdev_priv(dev);
 611
 612         val = enet_readl(priv, ENET_RXCFG_REG);
 613
 614         if (dev->flags & IFF_PROMISC)
 615                 val |= ENET_RXCFG_PROMISC_MASK;
 616         else
 617                 val &= ~ENET_RXCFG_PROMISC_MASK;
 618
 619         /* only 3 perfect match registers left, first one is used for
 620          * own mac address */
 621         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 622                 val |= ENET_RXCFG_ALLMCAST_MASK;
 623         else
 624                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 625
 626         /* no need to set perfect match registers if we catch all
 627          * multicast */
 628         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 629                 enet_writel(priv, val, ENET_RXCFG_REG);
 630                 return;
 631         }
 632
 633         i = 0;
 634         netdev_for_each_mc_addr(ha, dev) {
 635                 u8 *dmi_addr;
 636                 u32 tmp;
 637
 638                 if (i == 3)
 639                         break;
 640                 /* update perfect match registers */
 641                 dmi_addr = ha->addr;
 642                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 643                         (dmi_addr[4] << 8) | dmi_addr[5];
 644                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 645
 646                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 647                 tmp |= ENET_PMH_DATAVALID_MASK;
 648                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 649         }
 650
 651         for (; i < 3; i++) {
 652                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 653                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 654         }
 655
 656         enet_writel(priv, val, ENET_RXCFG_REG);
 657 }
 658
 659 /*
 660  * set mac duplex parameters
 661  */
 662 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 663 {
 664         u32 val;
 665
 666         val = enet_readl(priv, ENET_TXCTL_REG);
 667         if (fullduplex)
 668                 val |= ENET_TXCTL_FD_MASK;
 669         else
 670                 val &= ~ENET_TXCTL_FD_MASK;
 671         enet_writel(priv, val, ENET_TXCTL_REG);
 672 }
 673
 674 /*
 675  * set mac flow control parameters
 676  */
 677 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 678 {
 679         u32 val;
 680
 681         /* rx flow control (pause frame handling) */
 682         val = enet_readl(priv, ENET_RXCFG_REG);
 683         if (rx_en)
 684                 val |= ENET_RXCFG_ENFLOW_MASK;
 685         else
 686                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 687         enet_writel(priv, val, ENET_RXCFG_REG);
 688
 689         /* tx flow control (pause frame generation) */
 690         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 691         if (tx_en)
 692                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 693         else
 694                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 695         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 696 }
 697
 698 /*
 699  * link changed callback (from phylib)
 700  */
 701 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 702 {
 703         struct bcm_enet_priv *priv;
 704         struct phy_device *phydev;
 705         int status_changed;
 706
 707         priv = netdev_priv(dev);
 708         phydev = priv->phydev;
 709         status_changed = 0;
 710
 711         if (priv->old_link != phydev->link) {
 712                 status_changed = 1;
 713                 priv->old_link = phydev->link;
 714         }
 715
 716         /* reflect duplex change in mac configuration */
 717         if (phydev->link && phydev->duplex != priv->old_duplex) {
 718                 bcm_enet_set_duplex(priv,
 719                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 720                 status_changed = 1;
 721                 priv->old_duplex = phydev->duplex;
 722         }
 723
 724         /* enable flow control if remote advertise it (trust phylib to
 725          * check that duplex is full */
 726         if (phydev->link && phydev->pause != priv->old_pause) {
 727                 int rx_pause_en, tx_pause_en;
 728
 729                 if (phydev->pause) {
 730                         /* pause was advertised by lpa and us */
 731                         rx_pause_en = 1;
 732                         tx_pause_en = 1;
 733                 } else if (!priv->pause_auto) {
 734                         /* pause setting overrided by user */
 735                         rx_pause_en = priv->pause_rx;
 736                         tx_pause_en = priv->pause_tx;
 737                 } else {
 738                         rx_pause_en = 0;
 739                         tx_pause_en = 0;
 740                 }
 741
 742                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 743                 status_changed = 1;
 744                 priv->old_pause = phydev->pause;
 745         }
 746
 747         if (status_changed) {
 748                 pr_info("%s: link %s", dev->name, phydev->link ?
 749                         "UP" : "DOWN");
 750                 if (phydev->link)
 751                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 752                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 753                                phydev->pause == 1 ? "rx&tx" : "off");
 754
 755                 pr_cont("\n");
 756         }
 757 }
 758
 759 /*
 760  * link changed callback (if phylib is not used)
 761  */
 762 static void bcm_enet_adjust_link(struct net_device *dev)
 763 {
 764         struct bcm_enet_priv *priv;
 765
 766         priv = netdev_priv(dev);
 767         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 768         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 769         netif_carrier_on(dev);
 770
 771         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 772                 dev->name,
 773                 priv->force_speed_100 ? 100 : 10,
 774                 priv->force_duplex_full ? "full" : "half",
 775                 priv->pause_rx ? "rx" : "off",
 776                 priv->pause_tx ? "tx" : "off");
 777 }
 778
 779 /*
 780  * open callback, allocate dma rings & buffers and start rx operation
 781  */
 782 static int bcm_enet_open(struct net_device *dev)
 783 {
 784         struct bcm_enet_priv *priv;
 785         struct sockaddr addr;
 786         struct device *kdev;
 787         struct phy_device *phydev;
 788         int i, ret;
 789         unsigned int size;
 790         char phy_id[MII_BUS_ID_SIZE + 3];
 791         void *p;
 792         u32 val;
 793
 794         priv = netdev_priv(dev);
 795         kdev = &priv->pdev->dev;
 796
 797         if (priv->has_phy) {
 798                 /* connect to PHY */
 799                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 800                          priv->mac_id ? "1" : "0", priv->phy_id);
 801
 802                 phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0,
 803                                      PHY_INTERFACE_MODE_MII);
 804
 805                 if (IS_ERR(phydev)) {
 806                         dev_err(kdev, "could not attach to PHY\n");
 807                         return PTR_ERR(phydev);
 808                 }
 809
 810                 /* mask with MAC supported features */
 811                 phydev->supported &= (SUPPORTED_10baseT_Half |
 812                                       SUPPORTED_10baseT_Full |
 813                                       SUPPORTED_100baseT_Half |
 814                                       SUPPORTED_100baseT_Full |
 815                                       SUPPORTED_Autoneg |
 816                                       SUPPORTED_Pause |
 817                                       SUPPORTED_MII);
 818                 phydev->advertising = phydev->supported;
 819
 820                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 821                         phydev->advertising |= SUPPORTED_Pause;
 822                 else
 823                         phydev->advertising &= ~SUPPORTED_Pause;
 824
 825                 dev_info(kdev, "attached PHY at address %d [%s]\n",
 826                          phydev->addr, phydev->drv->name);
 827
 828                 priv->old_link = 0;
 829                 priv->old_duplex = -1;
 830                 priv->old_pause = -1;
 831                 priv->phydev = phydev;
 832         }
 833
 834         /* mask all interrupts and request them */
 835         enet_writel(priv, 0, ENET_IRMASK_REG);
 836         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 837         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 838
 839         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 840         if (ret)
 841                 goto out_phy_disconnect;
 842
 843         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 844                           IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev);
 845         if (ret)
 846                 goto out_freeirq;
 847
 848         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 849                           IRQF_DISABLED, dev->name, dev);
 850         if (ret)
 851                 goto out_freeirq_rx;
 852
 853         /* initialize perfect match registers */
 854         for (i = 0; i < 4; i++) {
 855                 enet_writel(priv, 0, ENET_PML_REG(i));
 856                 enet_writel(priv, 0, ENET_PMH_REG(i));
 857         }
 858
 859         /* write device mac address */
 860         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 861         bcm_enet_set_mac_address(dev, &addr);
 862
 863         /* allocate rx dma ring */
 864         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 865         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 866         if (!p) {
 867                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 868                 ret = -ENOMEM;
 869                 goto out_freeirq_tx;
 870         }
 871
 872         memset(p, 0, size);
 873         priv->rx_desc_alloc_size = size;
 874         priv->rx_desc_cpu = p;
 875
 876         /* allocate tx dma ring */
 877         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 878         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 879         if (!p) {
 880                 dev_err(kdev, "cannot allocate tx ring\n");
 881                 ret = -ENOMEM;
 882                 goto out_free_rx_ring;
 883         }
 884
 885         memset(p, 0, size);
 886         priv->tx_desc_alloc_size = size;
 887         priv->tx_desc_cpu = p;
 888
 889         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 890                                GFP_KERNEL);
 891         if (!priv->tx_skb) {
 892                 dev_err(kdev, "cannot allocate rx skb queue\n");
 893                 ret = -ENOMEM;
 894                 goto out_free_tx_ring;
 895         }
 896
 897         priv->tx_desc_count = priv->tx_ring_size;
 898         priv->tx_dirty_desc = 0;
 899         priv->tx_curr_desc = 0;
 900         spin_lock_init(&priv->tx_lock);
 901
 902         /* init & fill rx ring with skbs */
 903         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
 904                                GFP_KERNEL);
 905         if (!priv->rx_skb) {
 906                 dev_err(kdev, "cannot allocate rx skb queue\n");
 907                 ret = -ENOMEM;
 908                 goto out_free_tx_skb;
 909         }
 910
 911         priv->rx_desc_count = 0;
 912         priv->rx_dirty_desc = 0;
 913         priv->rx_curr_desc = 0;
 914
 915         /* initialize flow control buffer allocation */
 916         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 917                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
 918
 919         if (bcm_enet_refill_rx(dev)) {
 920                 dev_err(kdev, "cannot allocate rx skb queue\n");
 921                 ret = -ENOMEM;
 922                 goto out;
 923         }
 924
 925         /* write rx & tx ring addresses */
 926         enet_dma_writel(priv, priv->rx_desc_dma,
 927                         ENETDMA_RSTART_REG(priv->rx_chan));
 928         enet_dma_writel(priv, priv->tx_desc_dma,
 929                         ENETDMA_RSTART_REG(priv->tx_chan));
 930
 931         /* clear remaining state ram for rx & tx channel */
 932         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
 933         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
 934         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
 935         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
 936         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
 937         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
 938
 939         /* set max rx/tx length */
 940         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 941         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
 942
 943         /* set dma maximum burst len */
 944         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 945                         ENETDMA_MAXBURST_REG(priv->rx_chan));
 946         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 947                         ENETDMA_MAXBURST_REG(priv->tx_chan));
 948
 949         /* set correct transmit fifo watermark */
 950         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 951
 952         /* set flow control low/high threshold to 1/3 / 2/3 */
 953         val = priv->rx_ring_size / 3;
 954         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 955         val = (priv->rx_ring_size * 2) / 3;
 956         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 957
 958         /* all set, enable mac and interrupts, start dma engine and
 959          * kick rx dma channel */
 960         wmb();
 961         val = enet_readl(priv, ENET_CTL_REG);
 962         val |= ENET_CTL_ENABLE_MASK;
 963         enet_writel(priv, val, ENET_CTL_REG);
 964         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 965         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 966                         ENETDMA_CHANCFG_REG(priv->rx_chan));
 967
 968         /* watch "mib counters about to overflow" interrupt */
 969         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 970         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 971
 972         /* watch "packet transferred" interrupt in rx and tx */
 973         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 974                         ENETDMA_IR_REG(priv->rx_chan));
 975         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 976                         ENETDMA_IR_REG(priv->tx_chan));
 977
 978         /* make sure we enable napi before rx interrupt  */
 979         napi_enable(&priv->napi);
 980
 981         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 982                         ENETDMA_IRMASK_REG(priv->rx_chan));
 983         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 984                         ENETDMA_IRMASK_REG(priv->tx_chan));
 985
 986         if (priv->has_phy)
 987                 phy_start(priv->phydev);
 988         else
 989                 bcm_enet_adjust_link(dev);
 990
 991         netif_start_queue(dev);
 992         return 0;
 993
 994 out:
 995         for (i = 0; i < priv->rx_ring_size; i++) {
 996                 struct bcm_enet_desc *desc;
 997
 998                 if (!priv->rx_skb[i])
 999                         continue;
1000
1001                 desc = &priv->rx_desc_cpu[i];
1002                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1003                                  DMA_FROM_DEVICE);
1004                 kfree_skb(priv->rx_skb[i]);
1005         }
1006         kfree(priv->rx_skb);
1007
1008 out_free_tx_skb:
1009         kfree(priv->tx_skb);
1010
1011 out_free_tx_ring:
1012         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1013                           priv->tx_desc_cpu, priv->tx_desc_dma);
1014
1015 out_free_rx_ring:
1016         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1017                           priv->rx_desc_cpu, priv->rx_desc_dma);
1018
1019 out_freeirq_tx:
1020         free_irq(priv->irq_tx, dev);
1021
1022 out_freeirq_rx:
1023         free_irq(priv->irq_rx, dev);
1024
1025 out_freeirq:
1026         free_irq(dev->irq, dev);
1027
1028 out_phy_disconnect:
1029         phy_disconnect(priv->phydev);
1030
1031         return ret;
1032 }
1033
1034 /*
1035  * disable mac
1036  */
1037 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1038 {
1039         int limit;
1040         u32 val;
1041
1042         val = enet_readl(priv, ENET_CTL_REG);
1043         val |= ENET_CTL_DISABLE_MASK;
1044         enet_writel(priv, val, ENET_CTL_REG);
1045
1046         limit = 1000;
1047         do {
1048                 u32 val;
1049
1050                 val = enet_readl(priv, ENET_CTL_REG);
1051                 if (!(val & ENET_CTL_DISABLE_MASK))
1052                         break;
1053                 udelay(1);
1054         } while (limit--);
1055 }
1056
1057 /*
1058  * disable dma in given channel
1059  */
1060 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1061 {
1062         int limit;
1063
1064         enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1065
1066         limit = 1000;
1067         do {
1068                 u32 val;
1069
1070                 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1071                 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1072                         break;
1073                 udelay(1);
1074         } while (limit--);
1075 }
1076
1077 /*
1078  * stop callback
1079  */
1080 static int bcm_enet_stop(struct net_device *dev)
1081 {
1082         struct bcm_enet_priv *priv;
1083         struct device *kdev;
1084         int i;
1085
1086         priv = netdev_priv(dev);
1087         kdev = &priv->pdev->dev;
1088
1089         netif_stop_queue(dev);
1090         napi_disable(&priv->napi);
1091         if (priv->has_phy)
1092                 phy_stop(priv->phydev);
1093         del_timer_sync(&priv->rx_timeout);
1094
1095         /* mask all interrupts */
1096         enet_writel(priv, 0, ENET_IRMASK_REG);
1097         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1098         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1099
1100         /* make sure no mib update is scheduled */
1101         flush_scheduled_work();
1102
1103         /* disable dma & mac */
1104         bcm_enet_disable_dma(priv, priv->tx_chan);
1105         bcm_enet_disable_dma(priv, priv->rx_chan);
1106         bcm_enet_disable_mac(priv);
1107
1108         /* force reclaim of all tx buffers */
1109         bcm_enet_tx_reclaim(dev, 1);
1110
1111         /* free the rx skb ring */
1112         for (i = 0; i < priv->rx_ring_size; i++) {
1113                 struct bcm_enet_desc *desc;
1114
1115                 if (!priv->rx_skb[i])
1116                         continue;
1117
1118                 desc = &priv->rx_desc_cpu[i];
1119                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1120                                  DMA_FROM_DEVICE);
1121                 kfree_skb(priv->rx_skb[i]);
1122         }
1123
1124         /* free remaining allocated memory */
1125         kfree(priv->rx_skb);
1126         kfree(priv->tx_skb);
1127         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1128                           priv->rx_desc_cpu, priv->rx_desc_dma);
1129         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1130                           priv->tx_desc_cpu, priv->tx_desc_dma);
1131         free_irq(priv->irq_tx, dev);
1132         free_irq(priv->irq_rx, dev);
1133         free_irq(dev->irq, dev);
1134
1135         /* release phy */
1136         if (priv->has_phy) {
1137                 phy_disconnect(priv->phydev);
1138                 priv->phydev = NULL;
1139         }
1140
1141         return 0;
1142 }
1143
1144 /*
1145  * core request to return device rx/tx stats
1146  */
1147 static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev)
1148 {
1149         struct bcm_enet_priv *priv;
1150
1151         priv = netdev_priv(dev);
1152         return &priv->stats;
1153 }
1154
1155 /*
1156  * ethtool callbacks
1157  */
1158 struct bcm_enet_stats {
1159         char stat_string[ETH_GSTRING_LEN];
1160         int sizeof_stat;
1161         int stat_offset;
1162         int mib_reg;
1163 };
1164
1165 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1166                      offsetof(struct bcm_enet_priv, m)
1167
1168 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1169         { "rx_packets", GEN_STAT(stats.rx_packets), -1 },
1170         { "tx_packets", GEN_STAT(stats.tx_packets), -1 },
1171         { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 },
1172         { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 },
1173         { "rx_errors", GEN_STAT(stats.rx_errors), -1 },
1174         { "tx_errors", GEN_STAT(stats.tx_errors), -1 },
1175         { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 },
1176         { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 },
1177
1178         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1179         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1180         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1181         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1182         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1183         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1184         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1185         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1186         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1187         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1188         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1189         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1190         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1191         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1192         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1193         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1194         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1195         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1196         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1197         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1198         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1199
1200         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1201         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1202         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1203         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1204         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1205         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1206         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1207         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1208         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1209         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1210         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1211         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1212         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1213         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1214         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1215         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1216         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1217         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1218         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1219         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1220         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1221         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1222
1223 };
1224
1225 #define BCM_ENET_STATS_LEN      \
1226         (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1227
1228 static const u32 unused_mib_regs[] = {
1229         ETH_MIB_TX_ALL_OCTETS,
1230         ETH_MIB_TX_ALL_PKTS,
1231         ETH_MIB_RX_ALL_OCTETS,
1232         ETH_MIB_RX_ALL_PKTS,
1233 };
1234
1235
1236 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1237                                  struct ethtool_drvinfo *drvinfo)
1238 {
1239         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
1240         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
1241         strncpy(drvinfo->fw_version, "N/A", 32);
1242         strncpy(drvinfo->bus_info, "bcm63xx", 32);
1243         drvinfo->n_stats = BCM_ENET_STATS_LEN;
1244 }
1245
1246 static int bcm_enet_get_sset_count(struct net_device *netdev,
1247                                         int string_set)
1248 {
1249         switch (string_set) {
1250         case ETH_SS_STATS:
1251                 return BCM_ENET_STATS_LEN;
1252         default:
1253                 return -EINVAL;
1254         }
1255 }
1256
1257 static void bcm_enet_get_strings(struct net_device *netdev,
1258                                  u32 stringset, u8 *data)
1259 {
1260         int i;
1261
1262         switch (stringset) {
1263         case ETH_SS_STATS:
1264                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1265                         memcpy(data + i * ETH_GSTRING_LEN,
1266                                bcm_enet_gstrings_stats[i].stat_string,
1267                                ETH_GSTRING_LEN);
1268                 }
1269                 break;
1270         }
1271 }
1272
1273 static void update_mib_counters(struct bcm_enet_priv *priv)
1274 {
1275         int i;
1276
1277         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1278                 const struct bcm_enet_stats *s;
1279                 u32 val;
1280                 char *p;
1281
1282                 s = &bcm_enet_gstrings_stats[i];
1283                 if (s->mib_reg == -1)
1284                         continue;
1285
1286                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1287                 p = (char *)priv + s->stat_offset;
1288
1289                 if (s->sizeof_stat == sizeof(u64))
1290                         *(u64 *)p += val;
1291                 else
1292                         *(u32 *)p += val;
1293         }
1294
1295         /* also empty unused mib counters to make sure mib counter
1296          * overflow interrupt is cleared */
1297         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1298                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1299 }
1300
1301 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1302 {
1303         struct bcm_enet_priv *priv;
1304
1305         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1306         mutex_lock(&priv->mib_update_lock);
1307         update_mib_counters(priv);
1308         mutex_unlock(&priv->mib_update_lock);
1309
1310         /* reenable mib interrupt */
1311         if (netif_running(priv->net_dev))
1312                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1313 }
1314
1315 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1316                                        struct ethtool_stats *stats,
1317                                        u64 *data)
1318 {
1319         struct bcm_enet_priv *priv;
1320         int i;
1321
1322         priv = netdev_priv(netdev);
1323
1324         mutex_lock(&priv->mib_update_lock);
1325         update_mib_counters(priv);
1326
1327         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1328                 const struct bcm_enet_stats *s;
1329                 char *p;
1330
1331                 s = &bcm_enet_gstrings_stats[i];
1332                 p = (char *)priv + s->stat_offset;
1333                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1334                         *(u64 *)p : *(u32 *)p;
1335         }
1336         mutex_unlock(&priv->mib_update_lock);
1337 }
1338
1339 static int bcm_enet_get_settings(struct net_device *dev,
1340                                  struct ethtool_cmd *cmd)
1341 {
1342         struct bcm_enet_priv *priv;
1343
1344         priv = netdev_priv(dev);
1345
1346         cmd->maxrxpkt = 0;
1347         cmd->maxtxpkt = 0;
1348
1349         if (priv->has_phy) {
1350                 if (!priv->phydev)
1351                         return -ENODEV;
1352                 return phy_ethtool_gset(priv->phydev, cmd);
1353         } else {
1354                 cmd->autoneg = 0;
1355                 cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10;
1356                 cmd->duplex = (priv->force_duplex_full) ?
1357                         DUPLEX_FULL : DUPLEX_HALF;
1358                 cmd->supported = ADVERTISED_10baseT_Half  |
1359                         ADVERTISED_10baseT_Full |
1360                         ADVERTISED_100baseT_Half |
1361                         ADVERTISED_100baseT_Full;
1362                 cmd->advertising = 0;
1363                 cmd->port = PORT_MII;
1364                 cmd->transceiver = XCVR_EXTERNAL;
1365         }
1366         return 0;
1367 }
1368
1369 static int bcm_enet_set_settings(struct net_device *dev,
1370                                  struct ethtool_cmd *cmd)
1371 {
1372         struct bcm_enet_priv *priv;
1373
1374         priv = netdev_priv(dev);
1375         if (priv->has_phy) {
1376                 if (!priv->phydev)
1377                         return -ENODEV;
1378                 return phy_ethtool_sset(priv->phydev, cmd);
1379         } else {
1380
1381                 if (cmd->autoneg ||
1382                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1383                     cmd->port != PORT_MII)
1384                         return -EINVAL;
1385
1386                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1387                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1388
1389                 if (netif_running(dev))
1390                         bcm_enet_adjust_link(dev);
1391                 return 0;
1392         }
1393 }
1394
1395 static void bcm_enet_get_ringparam(struct net_device *dev,
1396                                    struct ethtool_ringparam *ering)
1397 {
1398         struct bcm_enet_priv *priv;
1399
1400         priv = netdev_priv(dev);
1401
1402         /* rx/tx ring is actually only limited by memory */
1403         ering->rx_max_pending = 8192;
1404         ering->tx_max_pending = 8192;
1405         ering->rx_mini_max_pending = 0;
1406         ering->rx_jumbo_max_pending = 0;
1407         ering->rx_pending = priv->rx_ring_size;
1408         ering->tx_pending = priv->tx_ring_size;
1409 }
1410
1411 static int bcm_enet_set_ringparam(struct net_device *dev,
1412                                   struct ethtool_ringparam *ering)
1413 {
1414         struct bcm_enet_priv *priv;
1415         int was_running;
1416
1417         priv = netdev_priv(dev);
1418
1419         was_running = 0;
1420         if (netif_running(dev)) {
1421                 bcm_enet_stop(dev);
1422                 was_running = 1;
1423         }
1424
1425         priv->rx_ring_size = ering->rx_pending;
1426         priv->tx_ring_size = ering->tx_pending;
1427
1428         if (was_running) {
1429                 int err;
1430
1431                 err = bcm_enet_open(dev);
1432                 if (err)
1433                         dev_close(dev);
1434                 else
1435                         bcm_enet_set_multicast_list(dev);
1436         }
1437         return 0;
1438 }
1439
1440 static void bcm_enet_get_pauseparam(struct net_device *dev,
1441                                     struct ethtool_pauseparam *ecmd)
1442 {
1443         struct bcm_enet_priv *priv;
1444
1445         priv = netdev_priv(dev);
1446         ecmd->autoneg = priv->pause_auto;
1447         ecmd->rx_pause = priv->pause_rx;
1448         ecmd->tx_pause = priv->pause_tx;
1449 }
1450
1451 static int bcm_enet_set_pauseparam(struct net_device *dev,
1452                                    struct ethtool_pauseparam *ecmd)
1453 {
1454         struct bcm_enet_priv *priv;
1455
1456         priv = netdev_priv(dev);
1457
1458         if (priv->has_phy) {
1459                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1460                         /* asymetric pause mode not supported,
1461                          * actually possible but integrated PHY has RO
1462                          * asym_pause bit */
1463                         return -EINVAL;
1464                 }
1465         } else {
1466                 /* no pause autoneg on direct mii connection */
1467                 if (ecmd->autoneg)
1468                         return -EINVAL;
1469         }
1470
1471         priv->pause_auto = ecmd->autoneg;
1472         priv->pause_rx = ecmd->rx_pause;
1473         priv->pause_tx = ecmd->tx_pause;
1474
1475         return 0;
1476 }
1477
1478 static struct ethtool_ops bcm_enet_ethtool_ops = {
1479         .get_strings            = bcm_enet_get_strings,
1480         .get_sset_count         = bcm_enet_get_sset_count,
1481         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1482         .get_settings           = bcm_enet_get_settings,
1483         .set_settings           = bcm_enet_set_settings,
1484         .get_drvinfo            = bcm_enet_get_drvinfo,
1485         .get_link               = ethtool_op_get_link,
1486         .get_ringparam          = bcm_enet_get_ringparam,
1487         .set_ringparam          = bcm_enet_set_ringparam,
1488         .get_pauseparam         = bcm_enet_get_pauseparam,
1489         .set_pauseparam         = bcm_enet_set_pauseparam,
1490 };
1491
1492 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1493 {
1494         struct bcm_enet_priv *priv;
1495
1496         priv = netdev_priv(dev);
1497         if (priv->has_phy) {
1498                 if (!priv->phydev)
1499                         return -ENODEV;
1500                 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1501         } else {
1502                 struct mii_if_info mii;
1503
1504                 mii.dev = dev;
1505                 mii.mdio_read = bcm_enet_mdio_read_mii;
1506                 mii.mdio_write = bcm_enet_mdio_write_mii;
1507                 mii.phy_id = 0;
1508                 mii.phy_id_mask = 0x3f;
1509                 mii.reg_num_mask = 0x1f;
1510                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1511         }
1512 }
1513
1514 /*
1515  * calculate actual hardware mtu
1516  */
1517 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1518 {
1519         int actual_mtu;
1520
1521         actual_mtu = mtu;
1522
1523         /* add ethernet header + vlan tag size */
1524         actual_mtu += VLAN_ETH_HLEN;
1525
1526         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1527                 return -EINVAL;
1528
1529         /*
1530          * setup maximum size before we get overflow mark in
1531          * descriptor, note that this will not prevent reception of
1532          * big frames, they will be split into multiple buffers
1533          * anyway
1534          */
1535         priv->hw_mtu = actual_mtu;
1536
1537         /*
1538          * align rx buffer size to dma burst len, account FCS since
1539          * it's appended
1540          */
1541         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1542                                   BCMENET_DMA_MAXBURST * 4);
1543         return 0;
1544 }
1545
1546 /*
1547  * adjust mtu, can't be called while device is running
1548  */
1549 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1550 {
1551         int ret;
1552
1553         if (netif_running(dev))
1554                 return -EBUSY;
1555
1556         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1557         if (ret)
1558                 return ret;
1559         dev->mtu = new_mtu;
1560         return 0;
1561 }
1562
1563 /*
1564  * preinit hardware to allow mii operation while device is down
1565  */
1566 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1567 {
1568         u32 val;
1569         int limit;
1570
1571         /* make sure mac is disabled */
1572         bcm_enet_disable_mac(priv);
1573
1574         /* soft reset mac */
1575         val = ENET_CTL_SRESET_MASK;
1576         enet_writel(priv, val, ENET_CTL_REG);
1577         wmb();
1578
1579         limit = 1000;
1580         do {
1581                 val = enet_readl(priv, ENET_CTL_REG);
1582                 if (!(val & ENET_CTL_SRESET_MASK))
1583                         break;
1584                 udelay(1);
1585         } while (limit--);
1586
1587         /* select correct mii interface */
1588         val = enet_readl(priv, ENET_CTL_REG);
1589         if (priv->use_external_mii)
1590                 val |= ENET_CTL_EPHYSEL_MASK;
1591         else
1592                 val &= ~ENET_CTL_EPHYSEL_MASK;
1593         enet_writel(priv, val, ENET_CTL_REG);
1594
1595         /* turn on mdc clock */
1596         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1597                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1598
1599         /* set mib counters to self-clear when read */
1600         val = enet_readl(priv, ENET_MIBCTL_REG);
1601         val |= ENET_MIBCTL_RDCLEAR_MASK;
1602         enet_writel(priv, val, ENET_MIBCTL_REG);
1603 }
1604
1605 static const struct net_device_ops bcm_enet_ops = {
1606         .ndo_open               = bcm_enet_open,
1607         .ndo_stop               = bcm_enet_stop,
1608         .ndo_start_xmit         = bcm_enet_start_xmit,
1609         .ndo_get_stats          = bcm_enet_get_stats,
1610         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1611         .ndo_set_multicast_list = bcm_enet_set_multicast_list,
1612         .ndo_do_ioctl           = bcm_enet_ioctl,
1613         .ndo_change_mtu         = bcm_enet_change_mtu,
1614 #ifdef CONFIG_NET_POLL_CONTROLLER
1615         .ndo_poll_controller = bcm_enet_netpoll,
1616 #endif
1617 };
1618
1619 /*
1620  * allocate netdevice, request register memory and register device.
1621  */
1622 static int __devinit bcm_enet_probe(struct platform_device *pdev)
1623 {
1624         struct bcm_enet_priv *priv;
1625         struct net_device *dev;
1626         struct bcm63xx_enet_platform_data *pd;
1627         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1628         struct mii_bus *bus;
1629         const char *clk_name;
1630         unsigned int iomem_size;
1631         int i, ret;
1632
1633         /* stop if shared driver failed, assume driver->probe will be
1634          * called in the same order we register devices (correct ?) */
1635         if (!bcm_enet_shared_base)
1636                 return -ENODEV;
1637
1638         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1639         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1640         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1641         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1642         if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1643                 return -ENODEV;
1644
1645         ret = 0;
1646         dev = alloc_etherdev(sizeof(*priv));
1647         if (!dev)
1648                 return -ENOMEM;
1649         priv = netdev_priv(dev);
1650         memset(priv, 0, sizeof(*priv));
1651
1652         ret = compute_hw_mtu(priv, dev->mtu);
1653         if (ret)
1654                 goto out;
1655
1656         iomem_size = res_mem->end - res_mem->start + 1;
1657         if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1658                 ret = -EBUSY;
1659                 goto out;
1660         }
1661
1662         priv->base = ioremap(res_mem->start, iomem_size);
1663         if (priv->base == NULL) {
1664                 ret = -ENOMEM;
1665                 goto out_release_mem;
1666         }
1667         dev->irq = priv->irq = res_irq->start;
1668         priv->irq_rx = res_irq_rx->start;
1669         priv->irq_tx = res_irq_tx->start;
1670         priv->mac_id = pdev->id;
1671
1672         /* get rx & tx dma channel id for this mac */
1673         if (priv->mac_id == 0) {
1674                 priv->rx_chan = 0;
1675                 priv->tx_chan = 1;
1676                 clk_name = "enet0";
1677         } else {
1678                 priv->rx_chan = 2;
1679                 priv->tx_chan = 3;
1680                 clk_name = "enet1";
1681         }
1682
1683         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1684         if (IS_ERR(priv->mac_clk)) {
1685                 ret = PTR_ERR(priv->mac_clk);
1686                 goto out_unmap;
1687         }
1688         clk_enable(priv->mac_clk);
1689
1690         /* initialize default and fetch platform data */
1691         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1692         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1693
1694         pd = pdev->dev.platform_data;
1695         if (pd) {
1696                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1697                 priv->has_phy = pd->has_phy;
1698                 priv->phy_id = pd->phy_id;
1699                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1700                 priv->phy_interrupt = pd->phy_interrupt;
1701                 priv->use_external_mii = !pd->use_internal_phy;
1702                 priv->pause_auto = pd->pause_auto;
1703                 priv->pause_rx = pd->pause_rx;
1704                 priv->pause_tx = pd->pause_tx;
1705                 priv->force_duplex_full = pd->force_duplex_full;
1706                 priv->force_speed_100 = pd->force_speed_100;
1707         }
1708
1709         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1710                 /* using internal PHY, enable clock */
1711                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1712                 if (IS_ERR(priv->phy_clk)) {
1713                         ret = PTR_ERR(priv->phy_clk);
1714                         priv->phy_clk = NULL;
1715                         goto out_put_clk_mac;
1716                 }
1717                 clk_enable(priv->phy_clk);
1718         }
1719
1720         /* do minimal hardware init to be able to probe mii bus */
1721         bcm_enet_hw_preinit(priv);
1722
1723         /* MII bus registration */
1724         if (priv->has_phy) {
1725
1726                 priv->mii_bus = mdiobus_alloc();
1727                 if (!priv->mii_bus) {
1728                         ret = -ENOMEM;
1729                         goto out_uninit_hw;
1730                 }
1731
1732                 bus = priv->mii_bus;
1733                 bus->name = "bcm63xx_enet MII bus";
1734                 bus->parent = &pdev->dev;
1735                 bus->priv = priv;
1736                 bus->read = bcm_enet_mdio_read_phylib;
1737                 bus->write = bcm_enet_mdio_write_phylib;
1738                 sprintf(bus->id, "%d", priv->mac_id);
1739
1740                 /* only probe bus where we think the PHY is, because
1741                  * the mdio read operation return 0 instead of 0xffff
1742                  * if a slave is not present on hw */
1743                 bus->phy_mask = ~(1 << priv->phy_id);
1744
1745                 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1746                 if (!bus->irq) {
1747                         ret = -ENOMEM;
1748                         goto out_free_mdio;
1749                 }
1750
1751                 if (priv->has_phy_interrupt)
1752                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1753                 else
1754                         bus->irq[priv->phy_id] = PHY_POLL;
1755
1756                 ret = mdiobus_register(bus);
1757                 if (ret) {
1758                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1759                         goto out_free_mdio;
1760                 }
1761         } else {
1762
1763                 /* run platform code to initialize PHY device */
1764                 if (pd->mii_config &&
1765                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1766                                    bcm_enet_mdio_write_mii)) {
1767                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1768                         goto out_uninit_hw;
1769                 }
1770         }
1771
1772         spin_lock_init(&priv->rx_lock);
1773
1774         /* init rx timeout (used for oom) */
1775         init_timer(&priv->rx_timeout);
1776         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1777         priv->rx_timeout.data = (unsigned long)dev;
1778
1779         /* init the mib update lock&work */
1780         mutex_init(&priv->mib_update_lock);
1781         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1782
1783         /* zero mib counters */
1784         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1785                 enet_writel(priv, 0, ENET_MIB_REG(i));
1786
1787         /* register netdevice */
1788         dev->netdev_ops = &bcm_enet_ops;
1789         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1790
1791         SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1792         SET_NETDEV_DEV(dev, &pdev->dev);
1793
1794         ret = register_netdev(dev);
1795         if (ret)
1796                 goto out_unregister_mdio;
1797
1798         netif_carrier_off(dev);
1799         platform_set_drvdata(pdev, dev);
1800         priv->pdev = pdev;
1801         priv->net_dev = dev;
1802
1803         return 0;
1804
1805 out_unregister_mdio:
1806         if (priv->mii_bus) {
1807                 mdiobus_unregister(priv->mii_bus);
1808                 kfree(priv->mii_bus->irq);
1809         }
1810
1811 out_free_mdio:
1812         if (priv->mii_bus)
1813                 mdiobus_free(priv->mii_bus);
1814
1815 out_uninit_hw:
1816         /* turn off mdc clock */
1817         enet_writel(priv, 0, ENET_MIISC_REG);
1818         if (priv->phy_clk) {
1819                 clk_disable(priv->phy_clk);
1820                 clk_put(priv->phy_clk);
1821         }
1822
1823 out_put_clk_mac:
1824         clk_disable(priv->mac_clk);
1825         clk_put(priv->mac_clk);
1826
1827 out_unmap:
1828         iounmap(priv->base);
1829
1830 out_release_mem:
1831         release_mem_region(res_mem->start, iomem_size);
1832 out:
1833         free_netdev(dev);
1834         return ret;
1835 }
1836
1837
1838 /*
1839  * exit func, stops hardware and unregisters netdevice
1840  */
1841 static int __devexit bcm_enet_remove(struct platform_device *pdev)
1842 {
1843         struct bcm_enet_priv *priv;
1844         struct net_device *dev;
1845         struct resource *res;
1846
1847         /* stop netdevice */
1848         dev = platform_get_drvdata(pdev);
1849         priv = netdev_priv(dev);
1850         unregister_netdev(dev);
1851
1852         /* turn off mdc clock */
1853         enet_writel(priv, 0, ENET_MIISC_REG);
1854
1855         if (priv->has_phy) {
1856                 mdiobus_unregister(priv->mii_bus);
1857                 kfree(priv->mii_bus->irq);
1858                 mdiobus_free(priv->mii_bus);
1859         } else {
1860                 struct bcm63xx_enet_platform_data *pd;
1861
1862                 pd = pdev->dev.platform_data;
1863                 if (pd && pd->mii_config)
1864                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1865                                        bcm_enet_mdio_write_mii);
1866         }
1867
1868         /* release device resources */
1869         iounmap(priv->base);
1870         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1871         release_mem_region(res->start, res->end - res->start + 1);
1872
1873         /* disable hw block clocks */
1874         if (priv->phy_clk) {
1875                 clk_disable(priv->phy_clk);
1876                 clk_put(priv->phy_clk);
1877         }
1878         clk_disable(priv->mac_clk);
1879         clk_put(priv->mac_clk);
1880
1881         platform_set_drvdata(pdev, NULL);
1882         free_netdev(dev);
1883         return 0;
1884 }
1885
1886 struct platform_driver bcm63xx_enet_driver = {
1887         .probe  = bcm_enet_probe,
1888         .remove = __devexit_p(bcm_enet_remove),
1889         .driver = {
1890                 .name   = "bcm63xx_enet",
1891                 .owner  = THIS_MODULE,
1892         },
1893 };
1894
1895 /*
1896  * reserve & remap memory space shared between all macs
1897  */
1898 static int __devinit bcm_enet_shared_probe(struct platform_device *pdev)
1899 {
1900         struct resource *res;
1901         unsigned int iomem_size;
1902
1903         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1904         if (!res)
1905                 return -ENODEV;
1906
1907         iomem_size = res->end - res->start + 1;
1908         if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1909                 return -EBUSY;
1910
1911         bcm_enet_shared_base = ioremap(res->start, iomem_size);
1912         if (!bcm_enet_shared_base) {
1913                 release_mem_region(res->start, iomem_size);
1914                 return -ENOMEM;
1915         }
1916         return 0;
1917 }
1918
1919 static int __devexit bcm_enet_shared_remove(struct platform_device *pdev)
1920 {
1921         struct resource *res;
1922
1923         iounmap(bcm_enet_shared_base);
1924         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1925         release_mem_region(res->start, res->end - res->start + 1);
1926         return 0;
1927 }
1928
1929 /*
1930  * this "shared" driver is needed because both macs share a single
1931  * address space
1932  */
1933 struct platform_driver bcm63xx_enet_shared_driver = {
1934         .probe  = bcm_enet_shared_probe,
1935         .remove = __devexit_p(bcm_enet_shared_remove),
1936         .driver = {
1937                 .name   = "bcm63xx_enet_shared",
1938                 .owner  = THIS_MODULE,
1939         },
1940 };
1941
1942 /*
1943  * entry point
1944  */
1945 static int __init bcm_enet_init(void)
1946 {
1947         int ret;
1948
1949         ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1950         if (ret)
1951                 return ret;
1952
1953         ret = platform_driver_register(&bcm63xx_enet_driver);
1954         if (ret)
1955                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1956
1957         return ret;
1958 }
1959
1960 static void __exit bcm_enet_exit(void)
1961 {
1962         platform_driver_unregister(&bcm63xx_enet_driver);
1963         platform_driver_unregister(&bcm63xx_enet_shared_driver);
1964 }
1965
1966
1967 module_init(bcm_enet_init);
1968 module_exit(bcm_enet_exit);
1969
1970 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1971 MODULE_AUTHOR("Maxime Bizon <[email protected]>");
1972 MODULE_LICENSE("GPL");