drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "hdp_v4_0.h"
  26 #include "amdgpu_ras.h"
  27
  28 #include "hdp/hdp_4_0_offset.h"
  29 #include "hdp/hdp_4_0_sh_mask.h"
  30 #include <uapi/linux/kfd_ioctl.h>
  31
  32 /* for Vega20 register name change */
  33 #define mmHDP_MEM_POWER_CTRL    0x00d4
  34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L
  38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  39
  40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
  41                                 struct amdgpu_ring *ring)
  42 {
  43         if (!ring || !ring->funcs->emit_wreg)
  44                 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  45         else
  46                 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  47 }
  48
  49 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
  50                                     struct amdgpu_ring *ring)
  51 {
  52         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) ||
  53             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
  54             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
  55                 return;
  56
  57         if (!ring || !ring->funcs->emit_wreg)
  58                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
  59         else
  60                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  61                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
  62 }
  63
  64 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
  65                                            void *ras_error_status)
  66 {
  67         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
  68
  69         err_data->ue_count = 0;
  70         err_data->ce_count = 0;
  71
  72         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
  73                 return;
  74
  75         /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
  76         err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
  77 };
  78
  79 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
  80 {
  81         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
  82                 return;
  83
  84         if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0))
  85                 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
  86         else
  87                 /*read back hdp ras counter to reset it to 0 */
  88                 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
  89 }
  90
  91 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
  92                                          bool enable)
  93 {
  94         uint32_t def, data;
  95
  96         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) ||
  97             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) ||
  98             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) ||
  99             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) {
 100                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 101
 102                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 103                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 104                 else
 105                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 106
 107                 if (def != data)
 108                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 109         } else {
 110                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
 111
 112                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 113                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
 114                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
 115                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
 116                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
 117                 else
 118                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
 119                                   HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
 120                                   HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
 121                                   HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
 122
 123                 if (def != data)
 124                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
 125         }
 126 }
 127
 128 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
 129                                             u64 *flags)
 130 {
 131         int data;
 132
 133         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
 134             amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) {
 135                 /* Default enabled */
 136                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
 137                 return;
 138         }
 139         /* AMD_CG_SUPPORT_HDP_LS */
 140         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 141         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 142                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 143 }
 144
 145 static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
 146 {
 147         switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
 148         case IP_VERSION(4, 2, 1):
 149                 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         /* Do not program registers if VF */
 156         if (amdgpu_sriov_vf(adev))
 157                 return;
 158
 159         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 160
 161         if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
 162                 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
 163
 164         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 165         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
 166 }
 167
 168 struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
 169         .query_ras_error_count = hdp_v4_0_query_ras_error_count,
 170         .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
 171 };
 172
 173 struct amdgpu_hdp_ras hdp_v4_0_ras = {
 174         .ras_block = {
 175                 .hw_ops = &hdp_v4_0_ras_hw_ops,
 176         },
 177 };
 178
 179 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
 180         .flush_hdp = hdp_v4_0_flush_hdp,
 181         .invalidate_hdp = hdp_v4_0_invalidate_hdp,
 182         .update_clock_gating = hdp_v4_0_update_clock_gating,
 183         .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
 184         .init_registers = hdp_v4_0_init_registers,
 185 };