drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v8_0.h"
  28 #include "amdgpu_ucode.h"
  29
  30 #include "gmc/gmc_8_1_d.h"
  31 #include "gmc/gmc_8_1_sh_mask.h"
  32
  33 #include "bif/bif_5_0_d.h"
  34 #include "bif/bif_5_0_sh_mask.h"
  35
  36 #include "oss/oss_3_0_d.h"
  37 #include "oss/oss_3_0_sh_mask.h"
  38
  39 #include "dce/dce_10_0_d.h"
  40 #include "dce/dce_10_0_sh_mask.h"
  41
  42 #include "vid.h"
  43 #include "vi.h"
  44
  45 #include "amdgpu_atombios.h"
  46
  47
  48 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  49 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  50 static int gmc_v8_0_wait_for_idle(void *handle);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  54 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  55 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  56
  57 static const u32 golden_settings_tonga_a11[] =
  58 {
  59         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  60         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  61         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  62         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66 };
  67
  68 static const u32 tonga_mgcg_cgcg_init[] =
  69 {
  70         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  71 };
  72
  73 static const u32 golden_settings_fiji_a10[] =
  74 {
  75         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  76         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  79 };
  80
  81 static const u32 fiji_mgcg_cgcg_init[] =
  82 {
  83         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  84 };
  85
  86 static const u32 golden_settings_polaris11_a11[] =
  87 {
  88         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  92 };
  93
  94 static const u32 golden_settings_polaris10_a11[] =
  95 {
  96         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  97         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  98         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 100         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 101 };
 102
 103 static const u32 cz_mgcg_cgcg_init[] =
 104 {
 105         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 106 };
 107
 108 static const u32 stoney_mgcg_cgcg_init[] =
 109 {
 110         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 111         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 112 };
 113
 114 static const u32 golden_settings_stoney_common[] =
 115 {
 116         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 117         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 118 };
 119
 120 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 121 {
 122         switch (adev->asic_type) {
 123         case CHIP_FIJI:
 124                 amdgpu_device_program_register_sequence(adev,
 125                                                         fiji_mgcg_cgcg_init,
 126                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 127                 amdgpu_device_program_register_sequence(adev,
 128                                                         golden_settings_fiji_a10,
 129                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 130                 break;
 131         case CHIP_TONGA:
 132                 amdgpu_device_program_register_sequence(adev,
 133                                                         tonga_mgcg_cgcg_init,
 134                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 135                 amdgpu_device_program_register_sequence(adev,
 136                                                         golden_settings_tonga_a11,
 137                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 138                 break;
 139         case CHIP_POLARIS11:
 140         case CHIP_POLARIS12:
 141         case CHIP_VEGAM:
 142                 amdgpu_device_program_register_sequence(adev,
 143                                                         golden_settings_polaris11_a11,
 144                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 145                 break;
 146         case CHIP_POLARIS10:
 147                 amdgpu_device_program_register_sequence(adev,
 148                                                         golden_settings_polaris10_a11,
 149                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 150                 break;
 151         case CHIP_CARRIZO:
 152                 amdgpu_device_program_register_sequence(adev,
 153                                                         cz_mgcg_cgcg_init,
 154                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 155                 break;
 156         case CHIP_STONEY:
 157                 amdgpu_device_program_register_sequence(adev,
 158                                                         stoney_mgcg_cgcg_init,
 159                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 160                 amdgpu_device_program_register_sequence(adev,
 161                                                         golden_settings_stoney_common,
 162                                                         ARRAY_SIZE(golden_settings_stoney_common));
 163                 break;
 164         default:
 165                 break;
 166         }
 167 }
 168
 169 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 170 {
 171         u32 blackout;
 172
 173         gmc_v8_0_wait_for_idle(adev);
 174
 175         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 176         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 177                 /* Block CPU access */
 178                 WREG32(mmBIF_FB_EN, 0);
 179                 /* blackout the MC */
 180                 blackout = REG_SET_FIELD(blackout,
 181                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 182                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 183         }
 184         /* wait for the MC to settle */
 185         udelay(100);
 186 }
 187
 188 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 189 {
 190         u32 tmp;
 191
 192         /* unblackout the MC */
 193         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 194         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 195         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 196         /* allow CPU access */
 197         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 198         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 199         WREG32(mmBIF_FB_EN, tmp);
 200 }
 201
 202 /**
 203  * gmc_v8_0_init_microcode - load ucode images from disk
 204  *
 205  * @adev: amdgpu_device pointer
 206  *
 207  * Use the firmware interface to load the ucode images into
 208  * the driver (not loaded into hw).
 209  * Returns 0 on success, error on failure.
 210  */
 211 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 212 {
 213         const char *chip_name;
 214         char fw_name[30];
 215         int err;
 216
 217         DRM_DEBUG("\n");
 218
 219         switch (adev->asic_type) {
 220         case CHIP_TONGA:
 221                 chip_name = "tonga";
 222                 break;
 223         case CHIP_POLARIS11:
 224                 chip_name = "polaris11";
 225                 break;
 226         case CHIP_POLARIS10:
 227                 chip_name = "polaris10";
 228                 break;
 229         case CHIP_POLARIS12:
 230                 chip_name = "polaris12";
 231                 break;
 232         case CHIP_FIJI:
 233         case CHIP_CARRIZO:
 234         case CHIP_STONEY:
 235         case CHIP_VEGAM:
 236                 return 0;
 237         default: BUG();
 238         }
 239
 240         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 241         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 242         if (err)
 243                 goto out;
 244         err = amdgpu_ucode_validate(adev->gmc.fw);
 245
 246 out:
 247         if (err) {
 248                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 249                 release_firmware(adev->gmc.fw);
 250                 adev->gmc.fw = NULL;
 251         }
 252         return err;
 253 }
 254
 255 /**
 256  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 257  *
 258  * @adev: amdgpu_device pointer
 259  *
 260  * Load the GDDR MC ucode into the hw (CIK).
 261  * Returns 0 on success, error on failure.
 262  */
 263 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 264 {
 265         const struct mc_firmware_header_v1_0 *hdr;
 266         const __le32 *fw_data = NULL;
 267         const __le32 *io_mc_regs = NULL;
 268         u32 running;
 269         int i, ucode_size, regs_size;
 270
 271         /* Skip MC ucode loading on SR-IOV capable boards.
 272          * vbios does this for us in asic_init in that case.
 273          * Skip MC ucode loading on VF, because hypervisor will do that
 274          * for this adaptor.
 275          */
 276         if (amdgpu_sriov_bios(adev))
 277                 return 0;
 278
 279         if (!adev->gmc.fw)
 280                 return -EINVAL;
 281
 282         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 283         amdgpu_ucode_print_mc_hdr(&hdr->header);
 284
 285         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 286         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 287         io_mc_regs = (const __le32 *)
 288                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 289         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 290         fw_data = (const __le32 *)
 291                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 292
 293         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 294
 295         if (running == 0) {
 296                 /* reset the engine and set to writable */
 297                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 298                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 299
 300                 /* load mc io regs */
 301                 for (i = 0; i < regs_size; i++) {
 302                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 303                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 304                 }
 305                 /* load the MC ucode */
 306                 for (i = 0; i < ucode_size; i++)
 307                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 308
 309                 /* put the engine back into the active state */
 310                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 311                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 312                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 313
 314                 /* wait for training to complete */
 315                 for (i = 0; i < adev->usec_timeout; i++) {
 316                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 317                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 318                                 break;
 319                         udelay(1);
 320                 }
 321                 for (i = 0; i < adev->usec_timeout; i++) {
 322                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 323                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 324                                 break;
 325                         udelay(1);
 326                 }
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 333 {
 334         const struct mc_firmware_header_v1_0 *hdr;
 335         const __le32 *fw_data = NULL;
 336         const __le32 *io_mc_regs = NULL;
 337         u32 data, vbios_version;
 338         int i, ucode_size, regs_size;
 339
 340         /* Skip MC ucode loading on SR-IOV capable boards.
 341          * vbios does this for us in asic_init in that case.
 342          * Skip MC ucode loading on VF, because hypervisor will do that
 343          * for this adaptor.
 344          */
 345         if (amdgpu_sriov_bios(adev))
 346                 return 0;
 347
 348         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 349         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 350         vbios_version = data & 0xf;
 351
 352         if (vbios_version == 0)
 353                 return 0;
 354
 355         if (!adev->gmc.fw)
 356                 return -EINVAL;
 357
 358         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 359         amdgpu_ucode_print_mc_hdr(&hdr->header);
 360
 361         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 362         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 363         io_mc_regs = (const __le32 *)
 364                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 365         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 366         fw_data = (const __le32 *)
 367                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 368
 369         data = RREG32(mmMC_SEQ_MISC0);
 370         data &= ~(0x40);
 371         WREG32(mmMC_SEQ_MISC0, data);
 372
 373         /* load mc io regs */
 374         for (i = 0; i < regs_size; i++) {
 375                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 376                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 377         }
 378
 379         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 380         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 381
 382         /* load the MC ucode */
 383         for (i = 0; i < ucode_size; i++)
 384                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 385
 386         /* put the engine back into the active state */
 387         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 388         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 389         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 390
 391         /* wait for training to complete */
 392         for (i = 0; i < adev->usec_timeout; i++) {
 393                 data = RREG32(mmMC_SEQ_MISC0);
 394                 if (data & 0x80)
 395                         break;
 396                 udelay(1);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 403                                        struct amdgpu_gmc *mc)
 404 {
 405         u64 base = 0;
 406
 407         if (!amdgpu_sriov_vf(adev))
 408                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 409         base <<= 24;
 410
 411         amdgpu_device_vram_location(adev, &adev->gmc, base);
 412         amdgpu_device_gart_location(adev, mc);
 413 }
 414
 415 /**
 416  * gmc_v8_0_mc_program - program the GPU memory controller
 417  *
 418  * @adev: amdgpu_device pointer
 419  *
 420  * Set the location of vram, gart, and AGP in the GPU's
 421  * physical address space (CIK).
 422  */
 423 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 424 {
 425         u32 tmp;
 426         int i, j;
 427
 428         /* Initialize HDP */
 429         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 430                 WREG32((0xb05 + j), 0x00000000);
 431                 WREG32((0xb06 + j), 0x00000000);
 432                 WREG32((0xb07 + j), 0x00000000);
 433                 WREG32((0xb08 + j), 0x00000000);
 434                 WREG32((0xb09 + j), 0x00000000);
 435         }
 436         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 437
 438         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 439                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 440         }
 441         if (adev->mode_info.num_crtc) {
 442                 /* Lockout access through VGA aperture*/
 443                 tmp = RREG32(mmVGA_HDP_CONTROL);
 444                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 445                 WREG32(mmVGA_HDP_CONTROL, tmp);
 446
 447                 /* disable VGA render */
 448                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 449                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 450                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 451         }
 452         /* Update configuration */
 453         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 454                adev->gmc.vram_start >> 12);
 455         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 456                adev->gmc.vram_end >> 12);
 457         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 458                adev->vram_scratch.gpu_addr >> 12);
 459
 460         if (amdgpu_sriov_vf(adev)) {
 461                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 462                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 463                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 464                 /* XXX double check these! */
 465                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 466                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 467                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 468         }
 469
 470         WREG32(mmMC_VM_AGP_BASE, 0);
 471         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 472         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 473         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 474                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 475         }
 476
 477         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 478
 479         tmp = RREG32(mmHDP_MISC_CNTL);
 480         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 481         WREG32(mmHDP_MISC_CNTL, tmp);
 482
 483         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 484         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 485 }
 486
 487 /**
 488  * gmc_v8_0_mc_init - initialize the memory controller driver params
 489  *
 490  * @adev: amdgpu_device pointer
 491  *
 492  * Look up the amount of vram, vram width, and decide how to place
 493  * vram and gart within the GPU's physical address space (CIK).
 494  * Returns 0 for success.
 495  */
 496 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 497 {
 498         int r;
 499
 500         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 501         if (!adev->gmc.vram_width) {
 502                 u32 tmp;
 503                 int chansize, numchan;
 504
 505                 /* Get VRAM informations */
 506                 tmp = RREG32(mmMC_ARB_RAMCFG);
 507                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 508                         chansize = 64;
 509                 } else {
 510                         chansize = 32;
 511                 }
 512                 tmp = RREG32(mmMC_SHARED_CHMAP);
 513                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 514                 case 0:
 515                 default:
 516                         numchan = 1;
 517                         break;
 518                 case 1:
 519                         numchan = 2;
 520                         break;
 521                 case 2:
 522                         numchan = 4;
 523                         break;
 524                 case 3:
 525                         numchan = 8;
 526                         break;
 527                 case 4:
 528                         numchan = 3;
 529                         break;
 530                 case 5:
 531                         numchan = 6;
 532                         break;
 533                 case 6:
 534                         numchan = 10;
 535                         break;
 536                 case 7:
 537                         numchan = 12;
 538                         break;
 539                 case 8:
 540                         numchan = 16;
 541                         break;
 542                 }
 543                 adev->gmc.vram_width = numchan * chansize;
 544         }
 545         /* size in MB on si */
 546         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 547         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 548
 549         if (!(adev->flags & AMD_IS_APU)) {
 550                 r = amdgpu_device_resize_fb_bar(adev);
 551                 if (r)
 552                         return r;
 553         }
 554         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 555         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 556
 557 #ifdef CONFIG_X86_64
 558         if (adev->flags & AMD_IS_APU) {
 559                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 560                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 561         }
 562 #endif
 563
 564         /* In case the PCI BAR is larger than the actual amount of vram */
 565         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 566         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 567                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 568
 569         /* set the gart size */
 570         if (amdgpu_gart_size == -1) {
 571                 switch (adev->asic_type) {
 572                 case CHIP_POLARIS10: /* all engines support GPUVM */
 573                 case CHIP_POLARIS11: /* all engines support GPUVM */
 574                 case CHIP_POLARIS12: /* all engines support GPUVM */
 575                 case CHIP_VEGAM:     /* all engines support GPUVM */
 576                 default:
 577                         adev->gmc.gart_size = 256ULL << 20;
 578                         break;
 579                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 580                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 581                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 582                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 583                         adev->gmc.gart_size = 1024ULL << 20;
 584                         break;
 585                 }
 586         } else {
 587                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 588         }
 589
 590         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 591
 592         return 0;
 593 }
 594
 595 /*
 596  * GART
 597  * VMID 0 is the physical GPU addresses as used by the kernel.
 598  * VMIDs 1-15 are used for userspace clients and are handled
 599  * by the amdgpu vm/hsa code.
 600  */
 601
 602 /**
 603  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 604  *
 605  * @adev: amdgpu_device pointer
 606  * @vmid: vm instance to flush
 607  *
 608  * Flush the TLB for the requested page table (CIK).
 609  */
 610 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 611                                         uint32_t vmid)
 612 {
 613         /* bits 0-15 are the VM contexts0-15 */
 614         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 615 }
 616
 617 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 618                                             unsigned vmid, uint64_t pd_addr)
 619 {
 620         uint32_t reg;
 621
 622         if (vmid < 8)
 623                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 624         else
 625                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 626         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 627
 628         /* bits 0-15 are the VM contexts0-15 */
 629         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 630
 631         return pd_addr;
 632 }
 633
 634 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 635                                         unsigned pasid)
 636 {
 637         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 638 }
 639
 640 /**
 641  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
 642  *
 643  * @adev: amdgpu_device pointer
 644  * @cpu_pt_addr: cpu address of the page table
 645  * @gpu_page_idx: entry in the page table to update
 646  * @addr: dst addr to write into pte/pde
 647  * @flags: access flags
 648  *
 649  * Update the page tables using the CPU.
 650  */
 651 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 652                                 uint32_t gpu_page_idx, uint64_t addr,
 653                                 uint64_t flags)
 654 {
 655         void __iomem *ptr = (void *)cpu_pt_addr;
 656         uint64_t value;
 657
 658         /*
 659          * PTE format on VI:
 660          * 63:40 reserved
 661          * 39:12 4k physical page base address
 662          * 11:7 fragment
 663          * 6 write
 664          * 5 read
 665          * 4 exe
 666          * 3 reserved
 667          * 2 snooped
 668          * 1 system
 669          * 0 valid
 670          *
 671          * PDE format on VI:
 672          * 63:59 block fragment size
 673          * 58:40 reserved
 674          * 39:1 physical base address of PTE
 675          * bits 5:1 must be 0.
 676          * 0 valid
 677          */
 678         value = addr & 0x000000FFFFFFF000ULL;
 679         value |= flags;
 680         writeq(value, ptr + (gpu_page_idx * 8));
 681
 682         return 0;
 683 }
 684
 685 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 686                                           uint32_t flags)
 687 {
 688         uint64_t pte_flag = 0;
 689
 690         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 691                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 692         if (flags & AMDGPU_VM_PAGE_READABLE)
 693                 pte_flag |= AMDGPU_PTE_READABLE;
 694         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 695                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 696         if (flags & AMDGPU_VM_PAGE_PRT)
 697                 pte_flag |= AMDGPU_PTE_PRT;
 698
 699         return pte_flag;
 700 }
 701
 702 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 703                                 uint64_t *addr, uint64_t *flags)
 704 {
 705         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 706 }
 707
 708 /**
 709  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 710  *
 711  * @adev: amdgpu_device pointer
 712  * @value: true redirects VM faults to the default page
 713  */
 714 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 715                                               bool value)
 716 {
 717         u32 tmp;
 718
 719         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 720         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 721                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 722         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 723                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 724         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 725                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 726         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 727                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 728         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 729                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 730         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 731                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 732         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 733                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 734         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 735 }
 736
 737 /**
 738  * gmc_v8_0_set_prt - set PRT VM fault
 739  *
 740  * @adev: amdgpu_device pointer
 741  * @enable: enable/disable VM fault handling for PRT
 742 */
 743 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 744 {
 745         u32 tmp;
 746
 747         if (enable && !adev->gmc.prt_warning) {
 748                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 749                 adev->gmc.prt_warning = true;
 750         }
 751
 752         tmp = RREG32(mmVM_PRT_CNTL);
 753         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 754                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 755         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 756                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 757         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 758                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 759         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 760                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 761         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 762                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 763         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 764                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 765         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 766                             MASK_PDE0_FAULT, enable);
 767         WREG32(mmVM_PRT_CNTL, tmp);
 768
 769         if (enable) {
 770                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 771                 uint32_t high = adev->vm_manager.max_pfn -
 772                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 773
 774                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 775                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 776                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 777                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 778                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 779                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 780                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 781                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 782         } else {
 783                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 784                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 785                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 786                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 787                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 788                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 789                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 790                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 791         }
 792 }
 793
 794 /**
 795  * gmc_v8_0_gart_enable - gart enable
 796  *
 797  * @adev: amdgpu_device pointer
 798  *
 799  * This sets up the TLBs, programs the page tables for VMID0,
 800  * sets up the hw for VMIDs 1-15 which are allocated on
 801  * demand, and sets up the global locations for the LDS, GDS,
 802  * and GPUVM for FSA64 clients (CIK).
 803  * Returns 0 for success, errors for failure.
 804  */
 805 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 806 {
 807         int r, i;
 808         u32 tmp, field;
 809
 810         if (adev->gart.robj == NULL) {
 811                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 812                 return -EINVAL;
 813         }
 814         r = amdgpu_gart_table_vram_pin(adev);
 815         if (r)
 816                 return r;
 817         /* Setup TLB control */
 818         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 819         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 820         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 821         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 822         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 823         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 824         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 825         /* Setup L2 cache */
 826         tmp = RREG32(mmVM_L2_CNTL);
 827         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 828         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 834         WREG32(mmVM_L2_CNTL, tmp);
 835         tmp = RREG32(mmVM_L2_CNTL2);
 836         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 837         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 838         WREG32(mmVM_L2_CNTL2, tmp);
 839
 840         field = adev->vm_manager.fragment_size;
 841         tmp = RREG32(mmVM_L2_CNTL3);
 842         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 843         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 844         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 845         WREG32(mmVM_L2_CNTL3, tmp);
 846         /* XXX: set to enable PTE/PDE in system memory */
 847         tmp = RREG32(mmVM_L2_CNTL4);
 848         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 849         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 850         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 851         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 860         WREG32(mmVM_L2_CNTL4, tmp);
 861         /* setup context0 */
 862         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 863         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 864         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 865         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 866                         (u32)(adev->dummy_page_addr >> 12));
 867         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 868         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 869         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 870         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 871         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 872         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 873
 874         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 875         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 876         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 877
 878         /* empty context1-15 */
 879         /* FIXME start with 4G, once using 2 level pt switch to full
 880          * vm size space
 881          */
 882         /* set vm size, must be a multiple of 4 */
 883         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 884         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 885         for (i = 1; i < 16; i++) {
 886                 if (i < 8)
 887                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 888                                adev->gart.table_addr >> 12);
 889                 else
 890                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 891                                adev->gart.table_addr >> 12);
 892         }
 893
 894         /* enable context1-15 */
 895         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 896                (u32)(adev->dummy_page_addr >> 12));
 897         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 898         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 899         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 900         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 901         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 902         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 903         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 904         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 905         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 906         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 907         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 908         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 909                             adev->vm_manager.block_size - 9);
 910         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 911         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 912                 gmc_v8_0_set_fault_enable_default(adev, false);
 913         else
 914                 gmc_v8_0_set_fault_enable_default(adev, true);
 915
 916         gmc_v8_0_flush_gpu_tlb(adev, 0);
 917         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 918                  (unsigned)(adev->gmc.gart_size >> 20),
 919                  (unsigned long long)adev->gart.table_addr);
 920         adev->gart.ready = true;
 921         return 0;
 922 }
 923
 924 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 925 {
 926         int r;
 927
 928         if (adev->gart.robj) {
 929                 WARN(1, "R600 PCIE GART already initialized\n");
 930                 return 0;
 931         }
 932         /* Initialize common gart structure */
 933         r = amdgpu_gart_init(adev);
 934         if (r)
 935                 return r;
 936         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 937         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 938         return amdgpu_gart_table_vram_alloc(adev);
 939 }
 940
 941 /**
 942  * gmc_v8_0_gart_disable - gart disable
 943  *
 944  * @adev: amdgpu_device pointer
 945  *
 946  * This disables all VM page table (CIK).
 947  */
 948 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 949 {
 950         u32 tmp;
 951
 952         /* Disable all tables */
 953         WREG32(mmVM_CONTEXT0_CNTL, 0);
 954         WREG32(mmVM_CONTEXT1_CNTL, 0);
 955         /* Setup TLB control */
 956         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 957         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 958         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 959         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 960         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 961         /* Setup L2 cache */
 962         tmp = RREG32(mmVM_L2_CNTL);
 963         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 964         WREG32(mmVM_L2_CNTL, tmp);
 965         WREG32(mmVM_L2_CNTL2, 0);
 966         amdgpu_gart_table_vram_unpin(adev);
 967 }
 968
 969 /**
 970  * gmc_v8_0_gart_fini - vm fini callback
 971  *
 972  * @adev: amdgpu_device pointer
 973  *
 974  * Tears down the driver GART/VM setup (CIK).
 975  */
 976 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 977 {
 978         amdgpu_gart_table_vram_free(adev);
 979         amdgpu_gart_fini(adev);
 980 }
 981
 982 /**
 983  * gmc_v8_0_vm_decode_fault - print human readable fault info
 984  *
 985  * @adev: amdgpu_device pointer
 986  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 987  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 988  *
 989  * Print human readable fault information (CIK).
 990  */
 991 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 992                                      u32 addr, u32 mc_client, unsigned pasid)
 993 {
 994         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 995         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 996                                         PROTECTIONS);
 997         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 998                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 999         u32 mc_id;
1000
1001         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1002                               MEMORY_CLIENT_ID);
1003
1004         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1005                protections, vmid, pasid, addr,
1006                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1007                              MEMORY_CLIENT_RW) ?
1008                "write" : "read", block, mc_client, mc_id);
1009 }
1010
1011 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1012 {
1013         switch (mc_seq_vram_type) {
1014         case MC_SEQ_MISC0__MT__GDDR1:
1015                 return AMDGPU_VRAM_TYPE_GDDR1;
1016         case MC_SEQ_MISC0__MT__DDR2:
1017                 return AMDGPU_VRAM_TYPE_DDR2;
1018         case MC_SEQ_MISC0__MT__GDDR3:
1019                 return AMDGPU_VRAM_TYPE_GDDR3;
1020         case MC_SEQ_MISC0__MT__GDDR4:
1021                 return AMDGPU_VRAM_TYPE_GDDR4;
1022         case MC_SEQ_MISC0__MT__GDDR5:
1023                 return AMDGPU_VRAM_TYPE_GDDR5;
1024         case MC_SEQ_MISC0__MT__HBM:
1025                 return AMDGPU_VRAM_TYPE_HBM;
1026         case MC_SEQ_MISC0__MT__DDR3:
1027                 return AMDGPU_VRAM_TYPE_DDR3;
1028         default:
1029                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1030         }
1031 }
1032
1033 static int gmc_v8_0_early_init(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         gmc_v8_0_set_gmc_funcs(adev);
1038         gmc_v8_0_set_irq_funcs(adev);
1039
1040         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1041         adev->gmc.shared_aperture_end =
1042                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1043         adev->gmc.private_aperture_start =
1044                 adev->gmc.shared_aperture_end + 1;
1045         adev->gmc.private_aperture_end =
1046                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1047
1048         return 0;
1049 }
1050
1051 static int gmc_v8_0_late_init(void *handle)
1052 {
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055         amdgpu_bo_late_init(adev);
1056
1057         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1058                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1059         else
1060                 return 0;
1061 }
1062
1063 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1064 {
1065         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1066         unsigned size;
1067
1068         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1069                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1070         } else {
1071                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1072                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1073                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1074                         4);
1075         }
1076         /* return 0 if the pre-OS buffer uses up most of vram */
1077         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1078                 return 0;
1079         return size;
1080 }
1081
1082 #define mmMC_SEQ_MISC0_FIJI 0xA71
1083
1084 static int gmc_v8_0_sw_init(void *handle)
1085 {
1086         int r;
1087         int dma_bits;
1088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089
1090         if (adev->flags & AMD_IS_APU) {
1091                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1092         } else {
1093                 u32 tmp;
1094
1095                 if ((adev->asic_type == CHIP_FIJI) ||
1096                     (adev->asic_type == CHIP_VEGAM))
1097                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1098                 else
1099                         tmp = RREG32(mmMC_SEQ_MISC0);
1100                 tmp &= MC_SEQ_MISC0__MT__MASK;
1101                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1102         }
1103
1104         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
1105         if (r)
1106                 return r;
1107
1108         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
1109         if (r)
1110                 return r;
1111
1112         /* Adjust VM size here.
1113          * Currently set to 4GB ((1 << 20) 4k pages).
1114          * Max GPUVM size for cayman and SI is 40 bits.
1115          */
1116         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1117
1118         /* Set the internal MC address mask
1119          * This is the max address of the GPU's
1120          * internal address space.
1121          */
1122         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1123
1124         /* set DMA mask + need_dma32 flags.
1125          * PCIE - can handle 40-bits.
1126          * IGP - can handle 40-bits
1127          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1128          */
1129         adev->need_dma32 = false;
1130         dma_bits = adev->need_dma32 ? 32 : 40;
1131         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1132         if (r) {
1133                 adev->need_dma32 = true;
1134                 dma_bits = 32;
1135                 pr_warn("amdgpu: No suitable DMA available\n");
1136         }
1137         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1138         if (r) {
1139                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1140                 pr_warn("amdgpu: No coherent DMA available\n");
1141         }
1142         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1143
1144         r = gmc_v8_0_init_microcode(adev);
1145         if (r) {
1146                 DRM_ERROR("Failed to load mc firmware!\n");
1147                 return r;
1148         }
1149
1150         r = gmc_v8_0_mc_init(adev);
1151         if (r)
1152                 return r;
1153
1154         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1155
1156         /* Memory manager */
1157         r = amdgpu_bo_init(adev);
1158         if (r)
1159                 return r;
1160
1161         r = gmc_v8_0_gart_init(adev);
1162         if (r)
1163                 return r;
1164
1165         /*
1166          * number of VMs
1167          * VMID 0 is reserved for System
1168          * amdgpu graphics/compute will use VMIDs 1-7
1169          * amdkfd will use VMIDs 8-15
1170          */
1171         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1172         amdgpu_vm_manager_init(adev);
1173
1174         /* base offset of vram pages */
1175         if (adev->flags & AMD_IS_APU) {
1176                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1177
1178                 tmp <<= 22;
1179                 adev->vm_manager.vram_base_offset = tmp;
1180         } else {
1181                 adev->vm_manager.vram_base_offset = 0;
1182         }
1183
1184         return 0;
1185 }
1186
1187 static int gmc_v8_0_sw_fini(void *handle)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190
1191         amdgpu_gem_force_release(adev);
1192         amdgpu_vm_manager_fini(adev);
1193         gmc_v8_0_gart_fini(adev);
1194         amdgpu_bo_fini(adev);
1195         release_firmware(adev->gmc.fw);
1196         adev->gmc.fw = NULL;
1197
1198         return 0;
1199 }
1200
1201 static int gmc_v8_0_hw_init(void *handle)
1202 {
1203         int r;
1204         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1205
1206         gmc_v8_0_init_golden_registers(adev);
1207
1208         gmc_v8_0_mc_program(adev);
1209
1210         if (adev->asic_type == CHIP_TONGA) {
1211                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1212                 if (r) {
1213                         DRM_ERROR("Failed to load MC firmware!\n");
1214                         return r;
1215                 }
1216         } else if (adev->asic_type == CHIP_POLARIS11 ||
1217                         adev->asic_type == CHIP_POLARIS10 ||
1218                         adev->asic_type == CHIP_POLARIS12) {
1219                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1220                 if (r) {
1221                         DRM_ERROR("Failed to load MC firmware!\n");
1222                         return r;
1223                 }
1224         }
1225
1226         r = gmc_v8_0_gart_enable(adev);
1227         if (r)
1228                 return r;
1229
1230         return r;
1231 }
1232
1233 static int gmc_v8_0_hw_fini(void *handle)
1234 {
1235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1236
1237         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1238         gmc_v8_0_gart_disable(adev);
1239
1240         return 0;
1241 }
1242
1243 static int gmc_v8_0_suspend(void *handle)
1244 {
1245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246
1247         gmc_v8_0_hw_fini(adev);
1248
1249         return 0;
1250 }
1251
1252 static int gmc_v8_0_resume(void *handle)
1253 {
1254         int r;
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256
1257         r = gmc_v8_0_hw_init(adev);
1258         if (r)
1259                 return r;
1260
1261         amdgpu_vmid_reset_all(adev);
1262
1263         return 0;
1264 }
1265
1266 static bool gmc_v8_0_is_idle(void *handle)
1267 {
1268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1269         u32 tmp = RREG32(mmSRBM_STATUS);
1270
1271         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1272                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1273                 return false;
1274
1275         return true;
1276 }
1277
1278 static int gmc_v8_0_wait_for_idle(void *handle)
1279 {
1280         unsigned i;
1281         u32 tmp;
1282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283
1284         for (i = 0; i < adev->usec_timeout; i++) {
1285                 /* read MC_STATUS */
1286                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1287                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1288                                                SRBM_STATUS__MCC_BUSY_MASK |
1289                                                SRBM_STATUS__MCD_BUSY_MASK |
1290                                                SRBM_STATUS__VMC_BUSY_MASK |
1291                                                SRBM_STATUS__VMC1_BUSY_MASK);
1292                 if (!tmp)
1293                         return 0;
1294                 udelay(1);
1295         }
1296         return -ETIMEDOUT;
1297
1298 }
1299
1300 static bool gmc_v8_0_check_soft_reset(void *handle)
1301 {
1302         u32 srbm_soft_reset = 0;
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304         u32 tmp = RREG32(mmSRBM_STATUS);
1305
1306         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1307                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1308                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1309
1310         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1311                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1312                 if (!(adev->flags & AMD_IS_APU))
1313                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1314                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1315         }
1316         if (srbm_soft_reset) {
1317                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1318                 return true;
1319         } else {
1320                 adev->gmc.srbm_soft_reset = 0;
1321                 return false;
1322         }
1323 }
1324
1325 static int gmc_v8_0_pre_soft_reset(void *handle)
1326 {
1327         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329         if (!adev->gmc.srbm_soft_reset)
1330                 return 0;
1331
1332         gmc_v8_0_mc_stop(adev);
1333         if (gmc_v8_0_wait_for_idle(adev)) {
1334                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int gmc_v8_0_soft_reset(void *handle)
1341 {
1342         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343         u32 srbm_soft_reset;
1344
1345         if (!adev->gmc.srbm_soft_reset)
1346                 return 0;
1347         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1348
1349         if (srbm_soft_reset) {
1350                 u32 tmp;
1351
1352                 tmp = RREG32(mmSRBM_SOFT_RESET);
1353                 tmp |= srbm_soft_reset;
1354                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1355                 WREG32(mmSRBM_SOFT_RESET, tmp);
1356                 tmp = RREG32(mmSRBM_SOFT_RESET);
1357
1358                 udelay(50);
1359
1360                 tmp &= ~srbm_soft_reset;
1361                 WREG32(mmSRBM_SOFT_RESET, tmp);
1362                 tmp = RREG32(mmSRBM_SOFT_RESET);
1363
1364                 /* Wait a little for things to settle down */
1365                 udelay(50);
1366         }
1367
1368         return 0;
1369 }
1370
1371 static int gmc_v8_0_post_soft_reset(void *handle)
1372 {
1373         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374
1375         if (!adev->gmc.srbm_soft_reset)
1376                 return 0;
1377
1378         gmc_v8_0_mc_resume(adev);
1379         return 0;
1380 }
1381
1382 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1383                                              struct amdgpu_irq_src *src,
1384                                              unsigned type,
1385                                              enum amdgpu_interrupt_state state)
1386 {
1387         u32 tmp;
1388         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1389                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1390                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1391                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1392                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1393                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1394                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1395
1396         switch (state) {
1397         case AMDGPU_IRQ_STATE_DISABLE:
1398                 /* system context */
1399                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1400                 tmp &= ~bits;
1401                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1402                 /* VMs */
1403                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1404                 tmp &= ~bits;
1405                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1406                 break;
1407         case AMDGPU_IRQ_STATE_ENABLE:
1408                 /* system context */
1409                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1410                 tmp |= bits;
1411                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1412                 /* VMs */
1413                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1414                 tmp |= bits;
1415                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1416                 break;
1417         default:
1418                 break;
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1425                                       struct amdgpu_irq_src *source,
1426                                       struct amdgpu_iv_entry *entry)
1427 {
1428         u32 addr, status, mc_client;
1429
1430         if (amdgpu_sriov_vf(adev)) {
1431                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1432                         entry->src_id, entry->src_data[0]);
1433                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1434                 return 0;
1435         }
1436
1437         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1438         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1439         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1440         /* reset addr and status */
1441         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1442
1443         if (!addr && !status)
1444                 return 0;
1445
1446         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1447                 gmc_v8_0_set_fault_enable_default(adev, false);
1448
1449         if (printk_ratelimit()) {
1450                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1451                         entry->src_id, entry->src_data[0]);
1452                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1453                         addr);
1454                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1455                         status);
1456                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1457                                          entry->pasid);
1458         }
1459
1460         return 0;
1461 }
1462
1463 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1464                                                      bool enable)
1465 {
1466         uint32_t data;
1467
1468         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1469                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1470                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1471                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1472
1473                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1474                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1475                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1476
1477                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1478                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1479                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1480
1481                 data = RREG32(mmMC_XPB_CLK_GAT);
1482                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1483                 WREG32(mmMC_XPB_CLK_GAT, data);
1484
1485                 data = RREG32(mmATC_MISC_CG);
1486                 data |= ATC_MISC_CG__ENABLE_MASK;
1487                 WREG32(mmATC_MISC_CG, data);
1488
1489                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1490                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1491                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1492
1493                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1494                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1495                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1496
1497                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1498                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1499                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1500
1501                 data = RREG32(mmVM_L2_CG);
1502                 data |= VM_L2_CG__ENABLE_MASK;
1503                 WREG32(mmVM_L2_CG, data);
1504         } else {
1505                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1506                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1507                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1508
1509                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1510                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1511                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1512
1513                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1514                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1515                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1516
1517                 data = RREG32(mmMC_XPB_CLK_GAT);
1518                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1519                 WREG32(mmMC_XPB_CLK_GAT, data);
1520
1521                 data = RREG32(mmATC_MISC_CG);
1522                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1523                 WREG32(mmATC_MISC_CG, data);
1524
1525                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1526                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1527                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1528
1529                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1530                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1531                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1532
1533                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1534                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1535                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1536
1537                 data = RREG32(mmVM_L2_CG);
1538                 data &= ~VM_L2_CG__ENABLE_MASK;
1539                 WREG32(mmVM_L2_CG, data);
1540         }
1541 }
1542
1543 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1544                                        bool enable)
1545 {
1546         uint32_t data;
1547
1548         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1549                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1550                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1551                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1552
1553                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1554                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1555                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1556
1557                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1558                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1559                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1560
1561                 data = RREG32(mmMC_XPB_CLK_GAT);
1562                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1563                 WREG32(mmMC_XPB_CLK_GAT, data);
1564
1565                 data = RREG32(mmATC_MISC_CG);
1566                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1567                 WREG32(mmATC_MISC_CG, data);
1568
1569                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1570                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1571                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1572
1573                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1574                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1575                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1576
1577                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1578                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1579                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1580
1581                 data = RREG32(mmVM_L2_CG);
1582                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1583                 WREG32(mmVM_L2_CG, data);
1584         } else {
1585                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1586                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1587                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1588
1589                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1590                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1591                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1592
1593                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1594                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1595                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1596
1597                 data = RREG32(mmMC_XPB_CLK_GAT);
1598                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1599                 WREG32(mmMC_XPB_CLK_GAT, data);
1600
1601                 data = RREG32(mmATC_MISC_CG);
1602                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1603                 WREG32(mmATC_MISC_CG, data);
1604
1605                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1606                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1607                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1608
1609                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1610                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1611                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1612
1613                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1614                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1615                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1616
1617                 data = RREG32(mmVM_L2_CG);
1618                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1619                 WREG32(mmVM_L2_CG, data);
1620         }
1621 }
1622
1623 static int gmc_v8_0_set_clockgating_state(void *handle,
1624                                           enum amd_clockgating_state state)
1625 {
1626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1627
1628         if (amdgpu_sriov_vf(adev))
1629                 return 0;
1630
1631         switch (adev->asic_type) {
1632         case CHIP_FIJI:
1633                 fiji_update_mc_medium_grain_clock_gating(adev,
1634                                 state == AMD_CG_STATE_GATE);
1635                 fiji_update_mc_light_sleep(adev,
1636                                 state == AMD_CG_STATE_GATE);
1637                 break;
1638         default:
1639                 break;
1640         }
1641         return 0;
1642 }
1643
1644 static int gmc_v8_0_set_powergating_state(void *handle,
1645                                           enum amd_powergating_state state)
1646 {
1647         return 0;
1648 }
1649
1650 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1651 {
1652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1653         int data;
1654
1655         if (amdgpu_sriov_vf(adev))
1656                 *flags = 0;
1657
1658         /* AMD_CG_SUPPORT_MC_MGCG */
1659         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1660         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1661                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1662
1663         /* AMD_CG_SUPPORT_MC_LS */
1664         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1665                 *flags |= AMD_CG_SUPPORT_MC_LS;
1666 }
1667
1668 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1669         .name = "gmc_v8_0",
1670         .early_init = gmc_v8_0_early_init,
1671         .late_init = gmc_v8_0_late_init,
1672         .sw_init = gmc_v8_0_sw_init,
1673         .sw_fini = gmc_v8_0_sw_fini,
1674         .hw_init = gmc_v8_0_hw_init,
1675         .hw_fini = gmc_v8_0_hw_fini,
1676         .suspend = gmc_v8_0_suspend,
1677         .resume = gmc_v8_0_resume,
1678         .is_idle = gmc_v8_0_is_idle,
1679         .wait_for_idle = gmc_v8_0_wait_for_idle,
1680         .check_soft_reset = gmc_v8_0_check_soft_reset,
1681         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1682         .soft_reset = gmc_v8_0_soft_reset,
1683         .post_soft_reset = gmc_v8_0_post_soft_reset,
1684         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1685         .set_powergating_state = gmc_v8_0_set_powergating_state,
1686         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1687 };
1688
1689 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1690         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1691         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1692         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1693         .set_pte_pde = gmc_v8_0_set_pte_pde,
1694         .set_prt = gmc_v8_0_set_prt,
1695         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1696         .get_vm_pde = gmc_v8_0_get_vm_pde
1697 };
1698
1699 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1700         .set = gmc_v8_0_vm_fault_interrupt_state,
1701         .process = gmc_v8_0_process_interrupt,
1702 };
1703
1704 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1705 {
1706         if (adev->gmc.gmc_funcs == NULL)
1707                 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1708 }
1709
1710 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1711 {
1712         adev->gmc.vm_fault.num_types = 1;
1713         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1714 }
1715
1716 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1717 {
1718         .type = AMD_IP_BLOCK_TYPE_GMC,
1719         .major = 8,
1720         .minor = 0,
1721         .rev = 0,
1722         .funcs = &gmc_v8_0_ip_funcs,
1723 };
1724
1725 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1726 {
1727         .type = AMD_IP_BLOCK_TYPE_GMC,
1728         .major = 8,
1729         .minor = 1,
1730         .rev = 0,
1731         .funcs = &gmc_v8_0_ip_funcs,
1732 };
1733
1734 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1735 {
1736         .type = AMD_IP_BLOCK_TYPE_GMC,
1737         .major = 8,
1738         .minor = 5,
1739         .rev = 0,
1740         .funcs = &gmc_v8_0_ip_funcs,
1741 };